1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_ll_rcc.c
4 * @author MCD Application Team
5 * @version $VERSION$
6 * @date $DATE$
7 * @brief RCC LL module driver.
8 ******************************************************************************
9 * @attention
10 *
11 * Copyright (c) 2019 STMicroelectronics.
12 * All rights reserved.
13 *
14 * This software is licensed under terms that can be found in the LICENSE file
15 * in the root directory of this software component.
16 * If no LICENSE file comes with this software, it is provided AS-IS.
17 *
18 ******************************************************************************
19 */
20 #if defined(USE_FULL_LL_DRIVER)
21
22 /* Includes ------------------------------------------------------------------*/
23 #include "stm32mp1xx_ll_rcc.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32MP1xx_LL_Driver
31 * @{
32 */
33
34 #if defined(RCC)
35 /** @addtogroup RCC_LL
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private constants ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43 /** @addtogroup RCC_LL_Private_Macros
44 * @{
45 */
46
47 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C12_CLKSOURCE) \
48 || ((__VALUE__) == LL_RCC_I2C35_CLKSOURCE) \
49 || ((__VALUE__) == LL_RCC_I2C46_CLKSOURCE))
50
51 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
52 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE) \
53 || ((__VALUE__) == LL_RCC_SAI3_CLKSOURCE) \
54 || ((__VALUE__) == LL_RCC_SAI4_CLKSOURCE))
55
56 #define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI1_CLKSOURCE) \
57 || ((__VALUE__) == LL_RCC_SPI23_CLKSOURCE) \
58 || ((__VALUE__) == LL_RCC_SPI45_CLKSOURCE) \
59 || ((__VALUE__) == LL_RCC_SPI6_CLKSOURCE))
60
61 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
62 || ((__VALUE__) == LL_RCC_UART24_CLKSOURCE) \
63 || ((__VALUE__) == LL_RCC_UART35_CLKSOURCE) \
64 || ((__VALUE__) == LL_RCC_USART6_CLKSOURCE) \
65 || ((__VALUE__) == LL_RCC_UART78_CLKSOURCE))
66
67 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC12_CLKSOURCE) \
68 || ((__VALUE__) == LL_RCC_SDMMC3_CLKSOURCE))
69
70 #define IS_LL_RCC_ETH_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ETH_CLKSOURCE))
71
72 #define IS_LL_RCC_QSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_QSPI_CLKSOURCE))
73
74 #define IS_LL_RCC_FMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_FMC_CLKSOURCE))
75
76 #if defined(FDCAN1)
77 #define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE))
78 #endif /*FDCAN1*/
79
80 #define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX_CLKSOURCE))
81
82 #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
83
84 #define IS_LL_RCC_USBPHY_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USBPHY_CLKSOURCE))
85
86 #define IS_LL_RCC_USBO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USBO_CLKSOURCE))
87
88 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG1_CLKSOURCE) \
89 || ((__VALUE__) == LL_RCC_RNG2_CLKSOURCE))
90
91 #define IS_LL_RCC_CKPER_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CKPER_CLKSOURCE))
92
93 #define IS_LL_RCC_STGEN_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_STGEN_CLKSOURCE))
94
95 #if defined(DSI)
96 #define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
97 #endif /*DSI*/
98
99 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
100
101 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
102 || ((__VALUE__) == LL_RCC_LPTIM23_CLKSOURCE) \
103 || ((__VALUE__) == LL_RCC_LPTIM45_CLKSOURCE))
104
105 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM_CLKSOURCE))
106
107 #define IS_LL_RCC_TIMGPRES(__VALUE__) (((__VALUE__) == LL_RCC_TIMG1PRES) \
108 || ((__VALUE__) == LL_RCC_TIMG2PRES))
109
110 /**
111 * @}
112 */
113
114 /* Private function prototypes -----------------------------------------------*/
115 /** @defgroup RCC_LL_Private_Functions RCC Private functions
116 * @{
117 */
118 uint32_t RCC_GetMPUSSClockFreq(void);
119 uint32_t RCC_GetAXISSClockFreq(void);
120 uint32_t RCC_GetMCUSSClockFreq(void);
121 uint32_t RCC_GetACLKClockFreq(uint32_t AXISS_Frequency);
122 uint32_t RCC_GetMLHCLKClockFreq(uint32_t MCUSS_Frequency);
123 uint32_t RCC_GetPCLK1ClockFreq(uint32_t MLHCLK_Frequency);
124 uint32_t RCC_GetPCLK2ClockFreq(uint32_t MLHCLK_Frequency);
125 uint32_t RCC_GetPCLK3ClockFreq(uint32_t MLHCLK_Frequency);
126 uint32_t RCC_GetPCLK4ClockFreq(uint32_t ACLK_Frequency);
127 uint32_t RCC_GetPCLK5ClockFreq(uint32_t ACLK_Frequency);
128
129 /**
130 * @}
131 */
132
133 /* Exported functions --------------------------------------------------------*/
134 /** @addtogroup RCC_LL_Exported_Functions
135 * @{
136 */
137
138 /** @addtogroup RCC_LL_EF_Init
139 * @{
140 */
141
142 /**
143 * @brief Reset the RCC clock configuration to the default reset state.
144 * @note The default reset state of the clock configuration is given below:
145 * - HSI ON and used as system clock source
146 * - HSE, CSI, PLL1, PLL2, PLL3 and PLL4 OFF
147 * - AHBs and APBs bus pre-scalers set to 1.
148 * - MCO1 and MCO2 OFF
149 * - All interrupts disabled (except Wake-up from CSTOP Interrupt Enable)
150 * @note This function doesn't modify the configuration of the
151 * - Peripheral clocks
152 * - LSI, LSE and RTC clocks
153 * - HSECSS and LSECSS
154 * @retval An ErrorStatus enumeration value:
155 * - SUCCESS: RCC registers are de-initialized
156 * - ERROR: not applicable
157 */
LL_RCC_DeInit(void)158 ErrorStatus LL_RCC_DeInit(void)
159 {
160 /* Set HSION bit */
161 LL_RCC_HSI_Enable();
162
163 /* Insure HSIRDY bit is set before writing default MSIRANGE value */
164 while (LL_RCC_HSI_IsReady() == 0U)
165 {}
166
167 /* Reset MPU Clock Selection */
168 LL_RCC_SetMPUClkSource(LL_RCC_MPU_CLKSOURCE_HSI);
169
170 /* Reset AXI Sub-System Clock Selection */
171 LL_RCC_SetAXISSClkSource(LL_RCC_AXISS_CLKSOURCE_HSI);
172
173 /* Reset MCU Sub-System Clock Selection */
174 LL_RCC_SetMCUSSClkSource(LL_RCC_MCUSS_CLKSOURCE_HSI);
175
176 /* Reset RCC MPU Clock Divider */
177 LL_RCC_SetMPUPrescaler(LL_RCC_MPU_DIV_2);
178
179 /* Reset RCC ACLK (ACLK, HCLK5 and HCLK6) Clock Divider */
180 LL_RCC_SetACLKPrescaler(LL_RCC_AXI_DIV_1);
181
182 /* Reset RCC APB4 Clock Divider */
183 LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_1);
184
185 /* Reset RCC APB5 Clock Divider */
186 LL_RCC_SetAPB5Prescaler(LL_RCC_APB5_DIV_1);
187
188 /* Reset RCC MLHCLK (MLHCLK, MCU, FCLK, HCLK4, HCLK3, HCLK2 and HCLK1) Clock Divider */
189 LL_RCC_SetMLHCLKPrescaler(LL_RCC_MCU_DIV_1);
190
191 /* Reset RCC APB1 Clock Divider */
192 LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
193
194 /* Reset RCC APB2 Clock Divider */
195 LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
196
197 /* Reset RCC APB3 Clock Divider */
198 LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_1);
199
200 /* Reset MCO1 Configuration */
201 CLEAR_BIT(RCC->MCO1CFGR, RCC_MCO1CFGR_MCO1ON);
202 LL_RCC_ConfigMCO(LL_RCC_MCO1SOURCE_HSI, LL_RCC_MCO1_DIV_1);
203
204 /* Reset MCO2 Configuration */
205 CLEAR_BIT(RCC->MCO2CFGR, RCC_MCO2CFGR_MCO2ON);
206 LL_RCC_ConfigMCO(LL_RCC_MCO2SOURCE_MPU, LL_RCC_MCO2_DIV_1);
207
208 /* Disable PLL1 outputs */
209 CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN | RCC_PLL1CR_DIVQEN |
210 RCC_PLL1CR_DIVREN);
211
212 /* Disable PLL1 */
213 CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_PLLON);
214
215 /* Wait for PLL1 READY bit to be reset */
216 while (LL_RCC_PLL1_IsReady() != 0U)
217 {}
218
219 /* Clear remaining SSCG_CTRL bit */
220 LL_RCC_PLL1CSG_Disable();
221
222 /* Disable PLL2 outputs */
223 CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_DIVPEN | RCC_PLL2CR_DIVQEN |
224 RCC_PLL2CR_DIVREN);
225
226 /* Disable PLL2 */
227 CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_PLLON);
228
229 /* Wait for PLL2 READY bit to be reset */
230 while (LL_RCC_PLL2_IsReady() != 0U)
231 {}
232
233 /* Clear remaining SSCG_CTRL bit */
234 LL_RCC_PLL2CSG_Disable();
235
236 /* Disable PLL3 outputs */
237 CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_DIVPEN | RCC_PLL3CR_DIVQEN |
238 RCC_PLL3CR_DIVREN);
239
240 /* Disable PLL3 */
241 CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_PLLON);
242
243 /* Wait for PLL3 READY bit to be reset */
244 while (LL_RCC_PLL3_IsReady() != 0U)
245 {}
246
247 /* Clear remaining SSCG_CTRL bit */
248 LL_RCC_PLL3CSG_Disable();
249
250 /* Disable PLL4 outputs */
251 CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_DIVPEN | RCC_PLL4CR_DIVQEN |
252 RCC_PLL4CR_DIVREN);
253
254 /* Disable PLL4 */
255 CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_PLLON);
256
257 /* Wait for PLL4 READY bit to be reset */
258 while (LL_RCC_PLL4_IsReady() != 0U)
259 {}
260
261 /* Clear remaining SSCG_CTRL bit */
262 LL_RCC_PLL4CSG_Disable();
263
264 /* Clear remaining SSCG_CTRL bit */
265 CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_SSCG_CTRL);
266
267 /* Reset PLL 1 and 2 Ref. Clock Selection Register */
268 MODIFY_REG(RCC->RCK12SELR, (RCC_RCK12SELR_PLL12SRC), RCC_RCK12SELR_PLL12SRC_0);
269
270 /* Reset RCC PLL 3 Ref. Clock Selection Register */
271 MODIFY_REG(RCC->RCK3SELR, (RCC_RCK3SELR_PLL3SRC), RCC_RCK3SELR_PLL3SRC_0);
272
273 /* Reset PLL4 Ref. Clock Selection Register */
274 MODIFY_REG(RCC->RCK4SELR, (RCC_RCK4SELR_PLL4SRC), RCC_RCK4SELR_PLL4SRC_0);
275
276 /* Reset RCC PLL1 Configuration Register 1 */
277 WRITE_REG(RCC->PLL1CFGR1, 0x00010031U);
278
279 /* Reset RCC PLL1 Configuration Register 2 */
280 WRITE_REG(RCC->PLL1CFGR2, 0x00010100U);
281
282 /* Reset RCC PLL1 Fractional Register */
283 CLEAR_REG(RCC->PLL1FRACR);
284
285 /* Reset RCC PLL1 Clock Spreading Generator Register */
286 CLEAR_REG(RCC->PLL1CSGR);
287
288 /* Reset RCC PLL2 Configuration Register 1 */
289 WRITE_REG(RCC->PLL2CFGR1, 0x00010063U);
290
291 /* Reset RCC PLL2 Configuration Register 2 */
292 WRITE_REG(RCC->PLL2CFGR2, 0x00010101U);
293
294 /* Reset RCC PLL2 Fractional Register */
295 CLEAR_REG(RCC->PLL2FRACR);
296
297 /* Reset RCC PLL2 Clock Spreading Generator Register */
298 CLEAR_REG(RCC->PLL2CSGR);
299
300 /* Reset RCC PLL3 Configuration Register 1 */
301 WRITE_REG(RCC->PLL3CFGR1, 0x00010031U);
302
303 /* Reset RCC PLL3 Configuration Register 2 */
304 WRITE_REG(RCC->PLL3CFGR2, 0x00010101U);
305
306 /* Reset RCC PLL3 Fractional Register */
307 CLEAR_REG(RCC->PLL3FRACR);
308
309 /* Reset RCC PLL3 Clock Spreading Generator Register */
310 CLEAR_REG(RCC->PLL3CSGR);
311
312 /* Reset RCC PLL4 Configuration Register 1 */
313 WRITE_REG(RCC->PLL4CFGR1, 0x00010031U);
314
315 /* Reset RCC PLL4 Configuration Register 2 */
316 WRITE_REG(RCC->PLL4CFGR2, 0x00000000U);
317
318 /* Reset RCC PLL4 Fractional Register */
319 CLEAR_REG(RCC->PLL4FRACR);
320
321 /* Reset RCC PLL4 Clock Spreading Generator Register */
322 CLEAR_REG(RCC->PLL4CSGR);
323
324 /* Reset HSIDIV once PLLs are off */
325 LL_RCC_HSI_SetDivider(LL_RCC_HSI_DIV_1);
326
327 /* Wait for HSIDIV READY bit to set */
328 while (LL_RCC_HSI_IsDividerReady() != 1U)
329 {}
330
331 /* Set HSITRIM bits to the reset value*/
332 LL_RCC_HSI_SetCalibTrimming(0x0U);
333
334 /* Reset the Oscillator Enable Control registers */
335 WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSIKERON | RCC_OCENCLRR_CSION |
336 RCC_OCENCLRR_CSIKERON | RCC_OCENCLRR_DIGBYP | RCC_OCENCLRR_HSEON |
337 RCC_OCENCLRR_HSEKERON | RCC_OCENCLRR_HSEBYP);
338
339 /* Reset CSITRIM value */
340 LL_RCC_CSI_SetCalibTrimming(0x10U);
341
342 #ifdef CORE_CM4
343 /* Reset RCC Clock Source Interrupt Enable Register */
344 CLEAR_BIT(RCC->MC_CIER, (RCC_MC_CIER_LSIRDYIE | RCC_MC_CIER_LSERDYIE |
345 RCC_MC_CIER_HSIRDYIE | RCC_MC_CIER_HSERDYIE | RCC_MC_CIER_CSIRDYIE |
346 RCC_MC_CIER_PLL1DYIE | RCC_MC_CIER_PLL2DYIE | RCC_MC_CIER_PLL3DYIE |
347 RCC_MC_CIER_PLL4DYIE | RCC_MC_CIER_LSECSSIE | RCC_MC_CIER_WKUPIE));
348
349 /* Clear all RCC MCU interrupt flags */
350 SET_BIT(RCC->MC_CIFR, (RCC_MC_CIFR_LSIRDYF | RCC_MC_CIFR_LSERDYF |
351 RCC_MC_CIFR_HSIRDYF | RCC_MC_CIFR_HSERDYF | RCC_MC_CIFR_CSIRDYF |
352 RCC_MC_CIFR_PLL1DYF | RCC_MC_CIFR_PLL2DYF | RCC_MC_CIFR_PLL3DYF |
353 RCC_MC_CIFR_PLL4DYF | RCC_MC_CIFR_LSECSSF));
354
355 /* Clear all RCC MCU Reset Flags */
356 SET_BIT(RCC->MC_RSTSCLRR, RCC_MC_RSTSCLRR_WWDG1RSTF |
357 RCC_MC_RSTSCLRR_IWDG2RSTF | RCC_MC_RSTSCLRR_IWDG1RSTF |
358 RCC_MC_RSTSCLRR_MCSYSRSTF | RCC_MC_RSTSCLRR_MPSYSRSTF |
359 RCC_MC_RSTSCLRR_MCURSTF | RCC_MC_RSTSCLRR_VCORERSTF |
360 RCC_MC_RSTSCLRR_HCSSRSTF | RCC_MC_RSTSCLRR_PADRSTF |
361 RCC_MC_RSTSCLRR_BORRSTF | RCC_MC_RSTSCLRR_PORRSTF);
362 #endif
363
364 return SUCCESS;
365 }
366
367 /**
368 * @}
369 */
370
371 /** @addtogroup RCC_LL_EF_Get_Freq
372 * @brief Return the frequencies of different on chip clocks; MPUSS, AXISS,
373 * MCUSS, ACLK, MLHCLK, APB[5:1] AHB[6:1] and MCU buses clocks and
374 * different peripheral clocks available on the device.
375 * @note If MCUSS source is CSI, function returns values based on CSI_VALUE(*)
376 * @note If MPUSS/AXISS/MCUSS source is HSI, function returns values based on HSI_VALUE(**)
377 * @note If MPUSS/AXISS/MCUSS source is HSE, function returns values based on HSE_VALUE(***)
378 * @note If MPUSS/AXISS/MCUSS source is PLLx, function returns values based
379 * on HSE_VALUE(***), or HSI_VALUE(**) or CSI_VALUE(*) or EXTERNAL_CLOCK_VALUE(****)
380 * multiplied/divided by the PLLx factors where 'PLLx' can be PLL1, PLL2
381 * or PLL3.
382 * @note (*) CSI_VALUE is a constant defined in this file (default value
383 * 4 MHz) but the real value may vary depending on the variations
384 * in voltage and temperature.
385 * @note (**) HSI_VALUE is a constant defined in this file (default value
386 * 64 MHz) but the real value may vary depending on the variations
387 * in voltage and temperature.
388 * @note (***) HSE_VALUE is a constant defined in this file (default value
389 * 24 MHz), user has to ensure that HSE_VALUE is same as the real
390 * frequency of the crystal used. Otherwise, this function may
391 * have wrong result.
392 * @note (****) EXTERNAL_CLOCK_VALUE is a constant defined in this file
393 * (default value 12.288 MHz), user has to ensure that
394 * EXTERNAL_CLOCK_VALUE is same as the real frequency of the
395 * I2S_CKIN external oscillator used. Otherwise, this function may
396 * have wrong result.
397 * @note The result of this function could be incorrect when using fractional
398 * value for HSE crystal.
399 * @note This function can be used by the user application to compute the
400 * baud-rate for the communication peripherals or configure other parameters.
401 * @{
402 */
403
404 /**
405 * @brief Return the frequencies of different on chip clocks; MPUSS, AXISS,
406 * MCUSS, ACLK, MLHCLK, APB[5:1] AHB[6:1] and MCU buses clocks.
407 * @note Each time MPUSS, AXISS, MCUSS, ACLK, MLHCLK, APB[5:1] AHB[6:1] and/or
408 * MCU clock changes, this function must be called to update structure
409 * fields. Otherwise, any configuration based on this function will
410 * be incorrect.
411 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which
412 * will hold the clocks frequencies.
413 * @retval None
414 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)415 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
416 {
417 /*!< MPUSS clock frequency */
418 RCC_Clocks->MPUSS_Frequency = RCC_GetMPUSSClockFreq();
419
420 /*!< AXISS clock frequency */
421 RCC_Clocks->AXISS_Frequency = RCC_GetAXISSClockFreq();
422
423 /*!< MCUSS clock frequency */
424 RCC_Clocks->MCUSS_Frequency = RCC_GetMCUSSClockFreq();
425
426 /*!< ACLK clock frequency */
427 RCC_Clocks->ACLK_Frequency = RCC_GetACLKClockFreq(RCC_Clocks->AXISS_Frequency);
428
429 /*!< MLHCLK clock frequency */
430 RCC_Clocks->MLHCLK_Frequency = RCC_GetMLHCLKClockFreq(RCC_Clocks->MCUSS_Frequency);
431
432 /*!< PCLK1 clock frequency */
433 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->MLHCLK_Frequency);
434
435 /*!< PCLK2 clock frequency */
436 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->MLHCLK_Frequency);
437
438 /*!< PCLK3 clock frequency */
439 RCC_Clocks->PCLK3_Frequency = RCC_GetPCLK3ClockFreq(RCC_Clocks->MLHCLK_Frequency);
440
441 /*!< PCLK4 clock frequency */
442 RCC_Clocks->PCLK4_Frequency = RCC_GetPCLK4ClockFreq(RCC_Clocks->ACLK_Frequency);
443
444 /*!< PCLK5 clock frequency */
445 RCC_Clocks->PCLK5_Frequency = RCC_GetPCLK5ClockFreq(RCC_Clocks->ACLK_Frequency);
446
447 /*!< HCLK1 clock frequency */
448 RCC_Clocks->HCLK1_Frequency = RCC_Clocks->MLHCLK_Frequency;
449
450 /*!< HCLK2 clock frequency */
451 RCC_Clocks->HCLK2_Frequency = RCC_Clocks->MLHCLK_Frequency;
452
453 /*!< HCLK3 clock frequency */
454 RCC_Clocks->HCLK3_Frequency = RCC_Clocks->MLHCLK_Frequency;
455
456 /*!< HCLK4 clock frequency */
457 RCC_Clocks->HCLK4_Frequency = RCC_Clocks->MLHCLK_Frequency;
458
459 /*!< MCU clock frequency */
460 RCC_Clocks->MCU_Frequency = RCC_Clocks->MLHCLK_Frequency;
461
462 /*!< HCLK5 clock frequency */
463 RCC_Clocks->HCLK5_Frequency = RCC_Clocks->ACLK_Frequency;
464
465 /*!< HCLK6 clock frequency */
466 RCC_Clocks->HCLK6_Frequency = RCC_Clocks->ACLK_Frequency;
467 }
468
469 /**
470 * @brief Return PLL1 clocks frequencies
471 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or
472 * oscillator not ready.
473 * For PLL1Q and PLL1R LL_RCC_PERIPH_FREQUENCY_NO is returned as these
474 * outputs are not available.
475 * @retval None
476 */
LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef * PLL_Clocks)477 void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
478 {
479 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
480 uint32_t m, n, fracv = 0U;
481
482 /* Fout1_ck = ((HSE_VALUE or HSI_VALUE/HSIDIV) / PLLM) * (PLLN + (FRACV/(2^13)))
483 * Where Fout1_ck is the PLL1 frequency before PQR post-dividers
484 * PLL_P_Frequency = Fout1_ck/DIVP (if output enabled)
485 */
486
487 pllsource = LL_RCC_PLL12_GetSource();
488
489 switch (pllsource)
490 {
491 case LL_RCC_PLL12SOURCE_HSI:
492 if (LL_RCC_HSI_IsReady() != 0U)
493 {
494 pllinputfreq = HSI_VALUE >> LL_RCC_HSI_GetDivider();
495 }
496 break;
497
498 case LL_RCC_PLL12SOURCE_HSE:
499 if (LL_RCC_HSE_IsReady() != 0U)
500 {
501 pllinputfreq = HSE_VALUE;
502 }
503 break;
504
505 case LL_RCC_PLL12SOURCE_NONE:
506 default:
507 /* PLL12 clock disabled */
508 break;
509 }
510
511 PLL_Clocks->PLL_P_Frequency = 0U;
512 PLL_Clocks->PLL_Q_Frequency = LL_RCC_PERIPH_FREQUENCY_NO;
513 PLL_Clocks->PLL_R_Frequency = LL_RCC_PERIPH_FREQUENCY_NO;
514
515 m = LL_RCC_PLL1_GetM();
516 n = LL_RCC_PLL1_GetN();
517 if (LL_RCC_PLL1FRACV_IsEnabled() != 0U)
518 {
519 fracv = LL_RCC_PLL1_GetFRACV();
520 }
521
522 if (m != 0U)
523 {
524 if (LL_RCC_PLL1P_IsEnabled() != 0U)
525 {
526 PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracv, LL_RCC_PLL1_GetP());
527 }
528 }
529 }
530
531 /**
532 * @brief Return PLL2 clocks frequencies
533 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or
534 * oscillator not ready
535 * @retval None
536 */
LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef * PLL_Clocks)537 void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
538 {
539 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
540 uint32_t m, n, fracv = 0U;
541
542 /* Fout2_ck = ((HSE_VALUE or HSI_VALUE/HSIDIV) / PLLM) * (PLLN + (FRACV/(2^13)))
543 * Where Fout2_ck is the PLL2 frequency before PQR post-dividers
544 * PLL_P_Frequency = Fout2_ck/DIVP (if output enabled)
545 * PLL_Q_Frequency = Fout2_ck/DIVQ (if output enabled)
546 * PLL_R_Frequency = Fout2_ck/DIVR (if output enabled)
547 */
548 pllsource = LL_RCC_PLL12_GetSource();
549
550 switch (pllsource)
551 {
552 case LL_RCC_PLL12SOURCE_HSI:
553 if (LL_RCC_HSI_IsReady() != 0U)
554 {
555 pllinputfreq = HSI_VALUE >> LL_RCC_HSI_GetDivider();
556 }
557 break;
558
559 case LL_RCC_PLL12SOURCE_HSE:
560 if (LL_RCC_HSE_IsReady() != 0U)
561 {
562 pllinputfreq = HSE_VALUE;
563 }
564 break;
565
566 case LL_RCC_PLL12SOURCE_NONE:
567 default:
568 /* PLL12 clock disabled */
569 break;
570 }
571
572 PLL_Clocks->PLL_P_Frequency = 0U;
573 PLL_Clocks->PLL_Q_Frequency = 0U;
574 PLL_Clocks->PLL_R_Frequency = 0U;
575
576 m = LL_RCC_PLL2_GetM();
577 n = LL_RCC_PLL2_GetN();
578 if (LL_RCC_PLL2FRACV_IsEnabled() != 0U)
579 {
580 fracv = LL_RCC_PLL2_GetFRACV();
581 }
582
583 if (m != 0U)
584 {
585 if (LL_RCC_PLL2P_IsEnabled() != 0U)
586 {
587 PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracv, LL_RCC_PLL2_GetP());
588 }
589
590 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
591 {
592 PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracv, LL_RCC_PLL2_GetQ());
593 }
594
595 if (LL_RCC_PLL2R_IsEnabled() != 0U)
596 {
597 PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracv, LL_RCC_PLL2_GetR());
598 }
599 }
600 }
601
602 /**
603 * @brief Return PLL3 clocks frequencies
604 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or
605 * oscillator not ready
606 * @retval None
607 */
LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef * PLL_Clocks)608 void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
609 {
610 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
611 uint32_t m, n, fracv = 0U;
612
613 /* Fout3_ck = ((HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM) * (PLLN + (FRACV/(2^13)))
614 * Where Fout3_ck is the PLL3 frequency before PQR post-dividers
615 * PLL_P_Frequency = Fout3_ck/DIVP (if output enabled)
616 * PLL_Q_Frequency = Fout3_ck/DIVQ (if output enabled)
617 * PLL_R_Frequency = Fout3_ck/DIVR (if output enabled)
618 */
619
620 pllsource = LL_RCC_PLL3_GetSource();
621
622 switch (pllsource)
623 {
624 case LL_RCC_PLL3SOURCE_HSI:
625 if (LL_RCC_HSI_IsReady() != 0U)
626 {
627 pllinputfreq = HSI_VALUE >> LL_RCC_HSI_GetDivider();
628 }
629 break;
630
631 case LL_RCC_PLL3SOURCE_HSE:
632 if (LL_RCC_HSE_IsReady() != 0U)
633 {
634 pllinputfreq = HSE_VALUE;
635 }
636 break;
637
638 case LL_RCC_PLL3SOURCE_CSI:
639 if (LL_RCC_CSI_IsReady() != 0U)
640 {
641 pllinputfreq = CSI_VALUE;
642 }
643 break;
644
645 case LL_RCC_PLL3SOURCE_NONE:
646 default:
647 /* PLL3 clock disabled */
648 break;
649 }
650
651 PLL_Clocks->PLL_P_Frequency = 0U;
652 PLL_Clocks->PLL_Q_Frequency = 0U;
653 PLL_Clocks->PLL_R_Frequency = 0U;
654
655 m = LL_RCC_PLL3_GetM();
656 n = LL_RCC_PLL3_GetN();
657 if (LL_RCC_PLL3FRACV_IsEnabled() != 0U)
658 {
659 fracv = LL_RCC_PLL3_GetFRACV();
660 }
661
662 if (m != 0U)
663 {
664 if (LL_RCC_PLL3P_IsEnabled() != 0U)
665 {
666 PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracv, LL_RCC_PLL3_GetP());
667 }
668
669 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
670 {
671 PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracv, LL_RCC_PLL3_GetQ());
672 }
673
674 if (LL_RCC_PLL3R_IsEnabled() != 0U)
675 {
676 PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracv, LL_RCC_PLL3_GetR());
677 }
678 }
679 }
680
681 /**
682 * @brief Return PLL4 clocks frequencies
683 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or
684 * oscillator not ready
685 * @retval None
686 */
LL_RCC_GetPLL4ClockFreq(LL_PLL_ClocksTypeDef * PLL_Clocks)687 void LL_RCC_GetPLL4ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
688 {
689 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource;
690 uint32_t m, n, fracv = 0U;
691
692 /* Fout4_ck = ((HSE_VALUE, CSI_VALUE, EXTERNAL_CLOCK_VALUE or HSI_VALUE/HSIDIV) / PLLM) * (PLLN + (FRACV/(2^13)))
693 * Where Fout4_ck is the PLL4 frequency before PQR post-dividers
694 * PLL_P_Frequency = Fout4_ck/DIVP (if output enabled)
695 * PLL_Q_Frequency = Fout4_ck/DIVQ (if output enabled)
696 * PLL_R_Frequency = Fout4_ck/DIVR (if output enabled)
697 */
698
699 pllsource = LL_RCC_PLL4_GetSource();
700
701 switch (pllsource)
702 {
703 case LL_RCC_PLL4SOURCE_HSI:
704 if (LL_RCC_HSI_IsReady() != 0U)
705 {
706 pllinputfreq = HSI_VALUE >> LL_RCC_HSI_GetDivider();
707 }
708 break;
709
710 case LL_RCC_PLL4SOURCE_HSE:
711 if (LL_RCC_HSE_IsReady() != 0U)
712 {
713 pllinputfreq = HSE_VALUE;
714 }
715 break;
716
717 case LL_RCC_PLL4SOURCE_CSI:
718 if (LL_RCC_HSE_IsReady() != 0U)
719 {
720 pllinputfreq = HSE_VALUE;
721 }
722 break;
723
724 case LL_RCC_PLL4SOURCE_I2SCKIN:
725 pllinputfreq = EXTERNAL_CLOCK_VALUE;
726 break;
727 }
728
729 PLL_Clocks->PLL_P_Frequency = 0U;
730 PLL_Clocks->PLL_Q_Frequency = 0U;
731 PLL_Clocks->PLL_R_Frequency = 0U;
732
733 m = LL_RCC_PLL4_GetM();
734 n = LL_RCC_PLL4_GetN();
735 if (LL_RCC_PLL4FRACV_IsEnabled() != 0U)
736 {
737 fracv = LL_RCC_PLL4_GetFRACV();
738 }
739
740 if (m != 0U)
741 {
742 if (LL_RCC_PLL4P_IsEnabled() != 0U)
743 {
744 PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracv, LL_RCC_PLL4_GetP());
745 }
746
747 if (LL_RCC_PLL4Q_IsEnabled() != 0U)
748 {
749 PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracv, LL_RCC_PLL4_GetQ());
750 }
751
752 if (LL_RCC_PLL4R_IsEnabled() != 0U)
753 {
754 PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracv, LL_RCC_PLL4_GetR());
755 }
756 }
757 }
758
759 /**
760 * @brief Helper function to calculate the PLL frequency output
761 * @note ex: @ref LL_RCC_CalcPLLClockFreq (HSE_VALUE, @ref LL_RCC_PLL1_GetM (),
762 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetFRACV (), @ref LL_RCC_PLL1_GetP ());
763 * @param PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/CSI/I2SCKIN)
764 * @param M Between 1 and 64
765 * @param N Between 4 and 512 on fractional mode (PLL1, PLL2, PLL3 and PLL4).
766 * Between 25 and 100 on integer mode for PLL1 and PLL2.
767 * Between 25 and 200 on integer mode for PLL3 and PLL4.
768 * @param FRACV Between 0 and 0x1FFF
769 * @param PQR VCO output divider (P, Q or R)
770 * Between 1 and 128. For PLL1 and PLL2, only the bypass
771 * (division by 1) and even divisions are allowed. For PLL3,
772 * only the even divisions are allowed. If those conditions are
773 * not respected the behavior of the circuit is not guaranteed.
774 * @retval PLL clock frequency (in Hz)
775 */
LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq,uint32_t M,uint32_t N,uint32_t FRACV,uint32_t PQR)776 uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACV, uint32_t PQR)
777 {
778 float freq;
779
780 freq = ((float)PLLInputFreq / (float)M) * ((float)N + ((float)FRACV / (float)0x2000));
781
782 freq = freq / (float)PQR;
783
784 return (uint32_t)freq;
785 }
786
787 /**
788 * @brief Return I2Cx clock frequency
789 * @param I2CxSource This parameter can be one of the following values:
790 * @arg @ref LL_RCC_I2C12_CLKSOURCE
791 * @arg @ref LL_RCC_I2C35_CLKSOURCE
792 * @arg @ref LL_RCC_I2C46_CLKSOURCE
793 * @retval I2C clock frequency (in Hz)
794 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
795 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)796 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
797 {
798 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
799 LL_PLL_ClocksTypeDef PLL_Clocks;
800
801 /* Check parameter */
802 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
803
804 switch (LL_RCC_GetI2CClockSource(I2CxSource))
805 {
806 case LL_RCC_I2C12_CLKSOURCE_PCLK1:
807 case LL_RCC_I2C35_CLKSOURCE_PCLK1:
808 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetMLHCLKClockFreq(RCC_GetMCUSSClockFreq()));
809 break;
810
811 case LL_RCC_I2C12_CLKSOURCE_PLL4R:
812 case LL_RCC_I2C35_CLKSOURCE_PLL4R:
813 if (LL_RCC_PLL4_IsReady() != 0U)
814 {
815 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
816 i2c_frequency = PLL_Clocks.PLL_R_Frequency;
817 }
818 break;
819
820 case LL_RCC_I2C12_CLKSOURCE_HSI:
821 case LL_RCC_I2C35_CLKSOURCE_HSI:
822 case LL_RCC_I2C46_CLKSOURCE_HSI:
823 if (LL_RCC_HSI_IsReady() != 0U)
824 {
825 i2c_frequency = HSI_VALUE >> LL_RCC_HSI_GetDivider();
826 }
827 break;
828
829 case LL_RCC_I2C12_CLKSOURCE_CSI:
830 case LL_RCC_I2C35_CLKSOURCE_CSI:
831 case LL_RCC_I2C46_CLKSOURCE_CSI:
832 if (LL_RCC_CSI_IsReady() != 0U)
833 {
834 i2c_frequency = CSI_VALUE;
835 }
836 break;
837
838 case LL_RCC_I2C46_CLKSOURCE_PCLK5:
839 i2c_frequency = RCC_GetPCLK5ClockFreq(RCC_GetACLKClockFreq(RCC_GetAXISSClockFreq()));
840 break;
841
842 case LL_RCC_I2C46_CLKSOURCE_PLL3Q:
843 if (LL_RCC_PLL3_IsReady() != 0U)
844 {
845 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
846 i2c_frequency = PLL_Clocks.PLL_Q_Frequency;
847 }
848 break;
849
850 default:
851 /* Nothing to do */
852 break;
853 }
854
855 return i2c_frequency;
856 }
857
858 /**
859 * @brief Return SAIx clock frequency
860 * @param SAIxSource This parameter can be one of the following values:
861 * @arg @ref LL_RCC_SAI1_CLKSOURCE
862 * @arg @ref LL_RCC_SAI2_CLKSOURCE
863 * @arg @ref LL_RCC_SAI3_CLKSOURCE
864 * @arg @ref LL_RCC_SAI4_CLKSOURCE
865 * @retval SAI clock frequency (in Hz)
866 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
867 */
LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)868 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
869 {
870 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
871 LL_PLL_ClocksTypeDef PLL_Clocks;
872
873 /* Check parameter */
874 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
875
876 switch (LL_RCC_GetSAIClockSource(SAIxSource))
877 {
878 case LL_RCC_SAI1_CLKSOURCE_PLL4Q:
879 case LL_RCC_SAI2_CLKSOURCE_PLL4Q:
880 case LL_RCC_SAI3_CLKSOURCE_PLL4Q:
881 case LL_RCC_SAI4_CLKSOURCE_PLL4Q:
882 if (LL_RCC_PLL4_IsReady() != 0U)
883 {
884 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
885 sai_frequency = PLL_Clocks.PLL_Q_Frequency;
886 }
887 break;
888
889 case LL_RCC_SAI1_CLKSOURCE_PLL3Q:
890 case LL_RCC_SAI2_CLKSOURCE_PLL3Q:
891 case LL_RCC_SAI3_CLKSOURCE_PLL3Q:
892 case LL_RCC_SAI4_CLKSOURCE_PLL3Q:
893 if (LL_RCC_PLL3_IsReady() != 0U)
894 {
895 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
896 sai_frequency = PLL_Clocks.PLL_Q_Frequency;
897 }
898 break;
899
900 case LL_RCC_SAI1_CLKSOURCE_I2SCKIN:
901 case LL_RCC_SAI2_CLKSOURCE_I2SCKIN:
902 case LL_RCC_SAI3_CLKSOURCE_I2SCKIN:
903 case LL_RCC_SAI4_CLKSOURCE_I2SCKIN:
904 sai_frequency = EXTERNAL_CLOCK_VALUE;
905 break;
906
907 case LL_RCC_SAI1_CLKSOURCE_PER:
908 case LL_RCC_SAI2_CLKSOURCE_PER:
909 case LL_RCC_SAI3_CLKSOURCE_PER:
910 case LL_RCC_SAI4_CLKSOURCE_PER:
911 sai_frequency = LL_RCC_GetCKPERClockFreq(LL_RCC_CKPER_CLKSOURCE);
912 break;
913
914 case LL_RCC_SAI1_CLKSOURCE_PLL3R:
915 case LL_RCC_SAI2_CLKSOURCE_PLL3R:
916 case LL_RCC_SAI3_CLKSOURCE_PLL3R:
917 case LL_RCC_SAI4_CLKSOURCE_PLL3R:
918 if (LL_RCC_PLL3_IsReady() != 0U)
919 {
920 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
921 sai_frequency = PLL_Clocks.PLL_R_Frequency;
922 }
923 break;
924
925 case LL_RCC_SAI2_CLKSOURCE_SPDIF: //SAI2 manages this SPDIF_CKSYMB_VALUE
926 default:
927 /* Nothing to do */
928 break;
929 }
930
931 return sai_frequency;
932 }
933
934 /**
935 * @brief Return SPIx clock frequency
936 * @param SPIxSource This parameter can be one of the following values:
937 * @arg @ref LL_RCC_SPI1_CLKSOURCE
938 * @arg @ref LL_RCC_SPI23_CLKSOURCE
939 * @arg @ref LL_RCC_SPI45_CLKSOURCE
940 * @arg @ref LL_RCC_SPI6_CLKSOURCE
941 * @retval SPI clock frequency (in Hz)
942 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
943 */
LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)944 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
945 {
946 uint32_t spi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
947 LL_PLL_ClocksTypeDef PLL_Clocks;
948
949 /* Check parameter */
950 assert_param(IS_LL_RCC_SPI_CLKSOURCE(SPIxSource));
951
952 switch (LL_RCC_GetSPIClockSource(SPIxSource))
953 {
954 case LL_RCC_SPI1_CLKSOURCE_PLL4P:
955 case LL_RCC_SPI23_CLKSOURCE_PLL4P:
956 if (LL_RCC_PLL4_IsReady() != 0U)
957 {
958 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
959 spi_frequency = PLL_Clocks.PLL_P_Frequency;
960 }
961 break;
962
963 case LL_RCC_SPI1_CLKSOURCE_PLL3Q:
964 case LL_RCC_SPI23_CLKSOURCE_PLL3Q:
965 case LL_RCC_SPI6_CLKSOURCE_PLL3Q:
966 if (LL_RCC_PLL3_IsReady() != 0U)
967 {
968 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
969 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
970 }
971 break;
972
973 case LL_RCC_SPI1_CLKSOURCE_I2SCKIN:
974 case LL_RCC_SPI23_CLKSOURCE_I2SCKIN:
975 spi_frequency = EXTERNAL_CLOCK_VALUE;
976 break;
977
978 case LL_RCC_SPI1_CLKSOURCE_PER:
979 case LL_RCC_SPI23_CLKSOURCE_PER:
980 spi_frequency = LL_RCC_GetCKPERClockFreq(LL_RCC_CKPER_CLKSOURCE);
981 break;
982
983 case LL_RCC_SPI1_CLKSOURCE_PLL3R:
984 case LL_RCC_SPI23_CLKSOURCE_PLL3R:
985 if (LL_RCC_PLL3_IsReady() != 0U)
986 {
987 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
988 spi_frequency = PLL_Clocks.PLL_R_Frequency;
989 }
990 break;
991
992 case LL_RCC_SPI45_CLKSOURCE_PCLK2:
993 spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetMLHCLKClockFreq(RCC_GetMCUSSClockFreq()));
994 break;
995
996 case LL_RCC_SPI45_CLKSOURCE_PLL4Q:
997 case LL_RCC_SPI6_CLKSOURCE_PLL4Q:
998 if (LL_RCC_PLL4_IsReady() != 0U)
999 {
1000 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
1001 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1002 }
1003 break;
1004
1005 case LL_RCC_SPI45_CLKSOURCE_HSI:
1006 case LL_RCC_SPI6_CLKSOURCE_HSI:
1007 if (LL_RCC_HSI_IsReady() != 0U)
1008 {
1009 spi_frequency = HSI_VALUE >> LL_RCC_HSI_GetDivider();
1010 }
1011 break;
1012
1013 case LL_RCC_SPI45_CLKSOURCE_CSI:
1014 case LL_RCC_SPI6_CLKSOURCE_CSI:
1015 if (LL_RCC_CSI_IsReady() != 0U)
1016 {
1017 spi_frequency = CSI_VALUE;
1018 }
1019 break;
1020
1021 case LL_RCC_SPI45_CLKSOURCE_HSE:
1022 case LL_RCC_SPI6_CLKSOURCE_HSE:
1023 if (LL_RCC_HSE_IsReady() != 0U)
1024 {
1025 spi_frequency = HSE_VALUE;
1026 }
1027 break;
1028
1029 case LL_RCC_SPI6_CLKSOURCE_PCLK5:
1030 spi_frequency = RCC_GetPCLK5ClockFreq(RCC_GetACLKClockFreq(RCC_GetAXISSClockFreq()));
1031 break;
1032
1033 default:
1034 /* Nothing to do */
1035 break;
1036 }
1037
1038 return spi_frequency;
1039 }
1040
1041 /**
1042 * @brief Return UARTx clock frequency
1043 * @param UARTxSource This parameter can be one of the following values:
1044 * @arg @ref LL_RCC_USART1_CLKSOURCE
1045 * @arg @ref LL_RCC_UART24_CLKSOURCE
1046 * @arg @ref LL_RCC_UART35_CLKSOURCE
1047 * @arg @ref LL_RCC_USART6_CLKSOURCE
1048 * @arg @ref LL_RCC_UART78_CLKSOURCE
1049 * @retval UART clock frequency (in Hz)
1050 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1051 */
LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)1052 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
1053 {
1054 uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1055 LL_PLL_ClocksTypeDef PLL_Clocks;
1056
1057 /* Check parameter */
1058 assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
1059
1060 switch (LL_RCC_GetUARTClockSource(UARTxSource))
1061 {
1062 case LL_RCC_USART1_CLKSOURCE_PCLK5:
1063 uart_frequency = RCC_GetPCLK5ClockFreq(RCC_GetACLKClockFreq(RCC_GetAXISSClockFreq()));
1064 break;
1065
1066 case LL_RCC_USART1_CLKSOURCE_PLL3Q:
1067 if (LL_RCC_PLL3_IsReady() != 0U)
1068 {
1069 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1070 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1071 }
1072 break;
1073
1074 case LL_RCC_USART1_CLKSOURCE_HSI:
1075 case LL_RCC_UART24_CLKSOURCE_HSI:
1076 case LL_RCC_UART35_CLKSOURCE_HSI:
1077 case LL_RCC_USART6_CLKSOURCE_HSI:
1078 case LL_RCC_UART78_CLKSOURCE_HSI:
1079 if (LL_RCC_HSI_IsReady() != 0U)
1080 {
1081 uart_frequency = HSI_VALUE >> LL_RCC_HSI_GetDivider();
1082 }
1083 break;
1084
1085 case LL_RCC_USART1_CLKSOURCE_CSI:
1086 case LL_RCC_UART24_CLKSOURCE_CSI:
1087 case LL_RCC_UART35_CLKSOURCE_CSI:
1088 case LL_RCC_USART6_CLKSOURCE_CSI:
1089 case LL_RCC_UART78_CLKSOURCE_CSI:
1090 if (LL_RCC_CSI_IsReady() != 0U)
1091 {
1092 uart_frequency = CSI_VALUE;
1093 }
1094 break;
1095
1096 case LL_RCC_USART1_CLKSOURCE_PLL4Q:
1097 case LL_RCC_UART24_CLKSOURCE_PLL4Q:
1098 case LL_RCC_UART35_CLKSOURCE_PLL4Q:
1099 case LL_RCC_USART6_CLKSOURCE_PLL4Q:
1100 case LL_RCC_UART78_CLKSOURCE_PLL4Q:
1101 if (LL_RCC_PLL4_IsReady() != 0U)
1102 {
1103 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
1104 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1105 }
1106 break;
1107
1108 case LL_RCC_USART1_CLKSOURCE_HSE:
1109 case LL_RCC_UART24_CLKSOURCE_HSE:
1110 case LL_RCC_UART35_CLKSOURCE_HSE:
1111 case LL_RCC_USART6_CLKSOURCE_HSE:
1112 case LL_RCC_UART78_CLKSOURCE_HSE:
1113 if (LL_RCC_HSE_IsReady() != 0U)
1114 {
1115 uart_frequency = HSE_VALUE;
1116 }
1117 break;
1118
1119 case LL_RCC_UART24_CLKSOURCE_PCLK1:
1120 case LL_RCC_UART35_CLKSOURCE_PCLK1:
1121 case LL_RCC_UART78_CLKSOURCE_PCLK1:
1122 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetMLHCLKClockFreq(RCC_GetMCUSSClockFreq()));
1123 break;
1124
1125 case LL_RCC_USART6_CLKSOURCE_PCLK2:
1126 uart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetMLHCLKClockFreq(RCC_GetMCUSSClockFreq()));
1127 break;
1128
1129 default:
1130 /* Nothing to do */
1131 break;
1132 }
1133
1134 return uart_frequency;
1135 }
1136
1137 /**
1138 * @brief Return SDMMCx clock frequency
1139 * @param SDMMCxSource This parameter can be one of the following values:
1140 * @arg @ref LL_RCC_SDMMC12_CLKSOURCE
1141 * @arg @ref LL_RCC_SDMMC3_CLKSOURCE
1142 * @retval SDMMC clock frequency (in Hz)
1143 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1144 */
LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)1145 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
1146 {
1147 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1148 LL_PLL_ClocksTypeDef PLL_Clocks;
1149
1150 /* Check parameter */
1151 assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
1152
1153 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
1154 {
1155 case LL_RCC_SDMMC12_CLKSOURCE_HCLK6:
1156 sdmmc_frequency = RCC_GetACLKClockFreq(RCC_GetAXISSClockFreq());
1157 break;
1158
1159 case LL_RCC_SDMMC12_CLKSOURCE_PLL3R:
1160 case LL_RCC_SDMMC3_CLKSOURCE_PLL3R:
1161 if (LL_RCC_PLL3_IsReady() != 0U)
1162 {
1163 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1164 sdmmc_frequency = PLL_Clocks.PLL_R_Frequency;
1165 }
1166 break;
1167
1168 case LL_RCC_SDMMC12_CLKSOURCE_PLL4P:
1169 case LL_RCC_SDMMC3_CLKSOURCE_PLL4P:
1170 if (LL_RCC_PLL4_IsReady() != 0U)
1171 {
1172 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
1173 sdmmc_frequency = PLL_Clocks.PLL_P_Frequency;
1174 }
1175 break;
1176
1177 case LL_RCC_SDMMC12_CLKSOURCE_HSI:
1178 case LL_RCC_SDMMC3_CLKSOURCE_HSI:
1179 if (LL_RCC_HSI_IsReady() != 0U)
1180 {
1181 sdmmc_frequency = HSI_VALUE >> LL_RCC_HSI_GetDivider();
1182 }
1183 break;
1184
1185 case LL_RCC_SDMMC3_CLKSOURCE_HCLK2:
1186 sdmmc_frequency = RCC_GetMLHCLKClockFreq(RCC_GetMCUSSClockFreq());
1187 break;
1188
1189 default:
1190 /* Nothing to do */
1191 break;
1192 }
1193
1194 return sdmmc_frequency;
1195 }
1196
1197 /**
1198 * @brief Return ETHx clock frequency
1199 * @param ETHxSource This parameter can be one of the following values:
1200 * @arg @ref LL_RCC_ETH_CLKSOURCE
1201 * @retval ETH clock frequency (in Hz)
1202 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1203 */
LL_RCC_GetETHClockFreq(uint32_t ETHxSource)1204 uint32_t LL_RCC_GetETHClockFreq(uint32_t ETHxSource)
1205 {
1206 uint32_t eth_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1207 LL_PLL_ClocksTypeDef PLL_Clocks;
1208
1209 /* Check parameter */
1210 assert_param(IS_LL_RCC_ETH_CLKSOURCE(ETHxSource));
1211
1212 switch (LL_RCC_GetETHClockSource(ETHxSource))
1213 {
1214 case LL_RCC_ETH_CLKSOURCE_PLL4P:
1215 if (LL_RCC_PLL4_IsReady() != 0U)
1216 {
1217 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
1218 eth_frequency = PLL_Clocks.PLL_P_Frequency;
1219 }
1220 break;
1221
1222 case LL_RCC_ETH_CLKSOURCE_PLL3Q:
1223 if (LL_RCC_PLL3_IsReady() != 0U)
1224 {
1225 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1226 eth_frequency = PLL_Clocks.PLL_Q_Frequency;
1227 }
1228 break;
1229
1230 case LL_RCC_ETH_CLKSOURCE_OFF:
1231 default:
1232 /* Nothing to do */
1233 break;
1234 }
1235
1236 return eth_frequency;
1237 }
1238
1239 /**
1240 * @brief Return QSPIx clock frequency
1241 * @param QSPIxSource This parameter can be one of the following values:
1242 * @arg @ref LL_RCC_QSPI_CLKSOURCE
1243 * @retval QSPI clock frequency (in Hz)
1244 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1245 */
LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource)1246 uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource)
1247 {
1248 uint32_t qspi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1249 LL_PLL_ClocksTypeDef PLL_Clocks;
1250
1251 /* Check parameter */
1252 assert_param(IS_LL_RCC_QSPI_CLKSOURCE(QSPIxSource));
1253
1254 switch (LL_RCC_GetQSPIClockSource(QSPIxSource))
1255 {
1256 case LL_RCC_QSPI_CLKSOURCE_ACLK:
1257 qspi_frequency = RCC_GetACLKClockFreq(RCC_GetACLKClockFreq(RCC_GetAXISSClockFreq()));
1258 break;
1259
1260 case LL_RCC_QSPI_CLKSOURCE_PLL3R:
1261 if (LL_RCC_PLL3_IsReady() != 0U)
1262 {
1263 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1264 qspi_frequency = PLL_Clocks.PLL_R_Frequency;
1265 }
1266 break;
1267
1268 case LL_RCC_QSPI_CLKSOURCE_PLL4P:
1269 if (LL_RCC_PLL4_IsReady() != 0U)
1270 {
1271 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
1272 qspi_frequency = PLL_Clocks.PLL_P_Frequency;
1273 }
1274 break;
1275
1276 case LL_RCC_QSPI_CLKSOURCE_PER:
1277 qspi_frequency = LL_RCC_GetCKPERClockFreq(LL_RCC_CKPER_CLKSOURCE);
1278 break;
1279
1280 default:
1281 /* Nothing to do */
1282 break;
1283 }
1284
1285 return qspi_frequency;
1286 }
1287
1288 /**
1289 * @brief Return FMCx clock frequency
1290 * @param FMCxSource This parameter can be one of the following values:
1291 * @arg @ref LL_RCC_FMC_CLKSOURCE
1292 * @retval FMC clock frequency (in Hz)
1293 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1294 */
LL_RCC_GetFMCClockFreq(uint32_t FMCxSource)1295 uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource)
1296 {
1297 uint32_t fmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1298 LL_PLL_ClocksTypeDef PLL_Clocks;
1299
1300 /* Check parameter */
1301 assert_param(IS_LL_RCC_FMC_CLKSOURCE(FMCxSource));
1302
1303 switch (LL_RCC_GetFMCClockSource(FMCxSource))
1304 {
1305 case LL_RCC_FMC_CLKSOURCE_ACLK:
1306 fmc_frequency = RCC_GetACLKClockFreq(RCC_GetACLKClockFreq(RCC_GetAXISSClockFreq()));
1307 break;
1308
1309 case LL_RCC_FMC_CLKSOURCE_PLL3R:
1310 if (LL_RCC_PLL3_IsReady() != 0U)
1311 {
1312 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1313 fmc_frequency = PLL_Clocks.PLL_R_Frequency;
1314 }
1315 break;
1316
1317 case LL_RCC_FMC_CLKSOURCE_PLL4P:
1318 if (LL_RCC_PLL4_IsReady() != 0U)
1319 {
1320 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
1321 fmc_frequency = PLL_Clocks.PLL_P_Frequency;
1322 }
1323 break;
1324
1325 case LL_RCC_FMC_CLKSOURCE_PER:
1326 fmc_frequency = LL_RCC_GetCKPERClockFreq(LL_RCC_CKPER_CLKSOURCE);
1327 break;
1328
1329 default:
1330 /* Nothing to do */
1331 break;
1332 }
1333
1334 return fmc_frequency;
1335 }
1336
1337 #if defined(FDCAN1)
1338 /**
1339 * @brief Return FDCANx clock frequency
1340 * @param FDCANxSource This parameter can be one of the following values:
1341 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
1342 * @retval FDCAN clock frequency (in Hz)
1343 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1344 */
LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)1345 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
1346 {
1347 uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1348 LL_PLL_ClocksTypeDef PLL_Clocks;
1349
1350 /* Check parameter */
1351 assert_param(IS_LL_RCC_FDCAN_CLKSOURCE(FDCANxSource));
1352
1353 switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
1354 {
1355 case LL_RCC_FDCAN_CLKSOURCE_HSE:
1356 if (LL_RCC_HSE_IsReady() != 0U)
1357 {
1358 fdcan_frequency = HSE_VALUE;
1359 }
1360 break;
1361
1362 case LL_RCC_FDCAN_CLKSOURCE_PLL3Q:
1363 if (LL_RCC_PLL3_IsReady() != 0U)
1364 {
1365 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1366 fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
1367 }
1368 break;
1369
1370 case LL_RCC_FDCAN_CLKSOURCE_PLL4Q:
1371 if (LL_RCC_PLL4_IsReady() != 0U)
1372 {
1373 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
1374 fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
1375 }
1376 break;
1377
1378 case LL_RCC_FDCAN_CLKSOURCE_PLL4R:
1379 if (LL_RCC_PLL4_IsReady() != 0U)
1380 {
1381 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
1382 fdcan_frequency = PLL_Clocks.PLL_R_Frequency;
1383 }
1384 break;
1385
1386 default:
1387 /* Nothing to do */
1388 break;
1389 }
1390
1391 return fdcan_frequency;
1392 }
1393 #endif /*FDCAN1*/
1394
1395 /**
1396 * @brief Return SPDIFRXx clock frequency
1397 * @param SPDIFRXxSource This parameter can be one of the following values:
1398 * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE
1399 * @retval SPDIFRX clock frequency (in Hz)
1400 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1401 */
LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)1402 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
1403 {
1404 uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1405 LL_PLL_ClocksTypeDef PLL_Clocks;
1406
1407 /* Check parameter */
1408 assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
1409
1410 switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource))
1411 {
1412 case LL_RCC_SPDIFRX_CLKSOURCE_PLL4P:
1413 if (LL_RCC_PLL4_IsReady() != 0U)
1414 {
1415 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
1416 spdifrx_frequency = PLL_Clocks.PLL_P_Frequency;
1417 }
1418 break;
1419
1420 case LL_RCC_SPDIFRX_CLKSOURCE_PLL3Q:
1421 if (LL_RCC_PLL3_IsReady() != 0U)
1422 {
1423 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1424 spdifrx_frequency = PLL_Clocks.PLL_Q_Frequency;
1425 }
1426 break;
1427
1428 case LL_RCC_SPDIFRX_CLKSOURCE_HSI:
1429 if (LL_RCC_HSI_IsReady() != 0U)
1430 {
1431 spdifrx_frequency = HSI_VALUE >> LL_RCC_HSI_GetDivider();
1432 }
1433 break;
1434
1435 default:
1436 /* Nothing to do */
1437 break;
1438 }
1439
1440 return spdifrx_frequency;
1441 }
1442
1443 /**
1444 * @brief Return CECx clock frequency
1445 * @param CECxSource This parameter can be one of the following values:
1446 * @arg @ref LL_RCC_CEC_CLKSOURCE
1447 * @retval CEC clock frequency (in Hz)
1448 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1449 */
LL_RCC_GetCECClockFreq(uint32_t CECxSource)1450 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
1451 {
1452 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1453
1454 /* Check parameter */
1455 assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
1456
1457 switch (LL_RCC_GetCECClockSource(CECxSource))
1458 {
1459 case LL_RCC_CEC_CLKSOURCE_LSE:
1460 if (LL_RCC_LSE_IsReady() != 0U)
1461 {
1462 cec_frequency = LSE_VALUE;
1463 }
1464 break;
1465
1466 case LL_RCC_CEC_CLKSOURCE_LSI:
1467 if (LL_RCC_LSI_IsReady() != 0U)
1468 {
1469 cec_frequency = LSI_VALUE;
1470 }
1471 break;
1472
1473 case LL_RCC_CEC_CLKSOURCE_CSI122:
1474 if (LL_RCC_CSI_IsReady() != 0U)
1475 {
1476 cec_frequency = (CSI_VALUE / 122U);
1477 }
1478 break;
1479
1480 default:
1481 /* Nothing to do */
1482 break;
1483 }
1484
1485 return cec_frequency;
1486 }
1487
1488 /**
1489 * @brief Return USBPHYx clock frequency
1490 * @param USBPHYxSource This parameter can be one of the following values:
1491 * @arg @ref LL_RCC_USBPHY_CLKSOURCE
1492 * @retval USBPHY clock frequency (in Hz)
1493 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1494 */
LL_RCC_GetUSBPHYClockFreq(uint32_t USBPHYxSource)1495 uint32_t LL_RCC_GetUSBPHYClockFreq(uint32_t USBPHYxSource)
1496 {
1497 uint32_t usbphy_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1498 LL_PLL_ClocksTypeDef PLL_Clocks;
1499
1500 /* Check parameter */
1501 assert_param(IS_LL_RCC_USBPHY_CLKSOURCE(USBPHYxSource));
1502
1503 switch (LL_RCC_GetUSBPHYClockSource(USBPHYxSource))
1504 {
1505 case LL_RCC_USBPHY_CLKSOURCE_HSE:
1506 if (LL_RCC_HSE_IsReady() != 0U)
1507 {
1508 usbphy_frequency = HSE_VALUE;
1509 }
1510 break;
1511
1512 case LL_RCC_USBPHY_CLKSOURCE_PLL4R:
1513 if (LL_RCC_PLL4_IsReady() != 0U)
1514 {
1515 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
1516 usbphy_frequency = PLL_Clocks.PLL_R_Frequency;
1517 }
1518 break;
1519
1520 case LL_RCC_USBPHY_CLKSOURCE_HSE2:
1521 if (LL_RCC_HSE_IsReady() != 0U)
1522 {
1523 usbphy_frequency = (HSE_VALUE / 2U);
1524 }
1525 break;
1526
1527 default:
1528 /* Nothing to do */
1529 break;
1530 }
1531
1532 return usbphy_frequency;
1533 }
1534
1535 /**
1536 * @brief Return USBOx clock frequency
1537 * @param USBOxSource This parameter can be one of the following values:
1538 * @arg @ref LL_RCC_USBO_CLKSOURCE
1539 * @retval USBO clock frequency (in Hz)
1540 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1541 */
LL_RCC_GetUSBOClockFreq(uint32_t USBOxSource)1542 uint32_t LL_RCC_GetUSBOClockFreq(uint32_t USBOxSource)
1543 {
1544 uint32_t usbo_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1545 LL_PLL_ClocksTypeDef PLL_Clocks;
1546
1547 /* Check parameter */
1548 assert_param(IS_LL_RCC_USBO_CLKSOURCE(USBOxSource));
1549
1550 switch (LL_RCC_GetUSBOClockSource(USBOxSource))
1551 {
1552 case LL_RCC_USBO_CLKSOURCE_PLL4R:
1553 if (LL_RCC_PLL4_IsReady() != 0U)
1554 {
1555 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
1556 usbo_frequency = PLL_Clocks.PLL_R_Frequency;
1557 }
1558 break;
1559
1560 case LL_RCC_USBO_CLKSOURCE_PHY:
1561 usbo_frequency = USBO_48M_VALUE; /* rcc_ck_usbo_48m */
1562 break;
1563
1564 default:
1565 /* Nothing to do */
1566 break;
1567 }
1568
1569 return usbo_frequency;
1570 }
1571
1572 /**
1573 * @brief Return RNGx clock frequency
1574 * @param RNGxSource This parameter can be one of the following values:
1575 * @arg @ref LL_RCC_RNG1_CLKSOURCE
1576 * @arg @ref LL_RCC_RNG2_CLKSOURCE
1577 * @retval RNG clock frequency (in Hz)
1578 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1579 */
LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)1580 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
1581 {
1582 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1583 LL_PLL_ClocksTypeDef PLL_Clocks;
1584
1585 /* Check parameter */
1586 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
1587
1588 switch (LL_RCC_GetRNGClockSource(RNGxSource))
1589 {
1590 case LL_RCC_RNG1_CLKSOURCE_CSI:
1591 case LL_RCC_RNG2_CLKSOURCE_CSI:
1592 if (LL_RCC_CSI_IsReady() != 0U)
1593 {
1594 rng_frequency = CSI_VALUE;
1595 }
1596 break;
1597
1598 case LL_RCC_RNG1_CLKSOURCE_PLL4R:
1599 case LL_RCC_RNG2_CLKSOURCE_PLL4R:
1600 if (LL_RCC_PLL4_IsReady() != 0U)
1601 {
1602 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
1603 rng_frequency = PLL_Clocks.PLL_R_Frequency;
1604 }
1605 break;
1606
1607 case LL_RCC_RNG1_CLKSOURCE_LSE:
1608 case LL_RCC_RNG2_CLKSOURCE_LSE:
1609 if (LL_RCC_LSE_IsReady() != 0U)
1610 {
1611 rng_frequency = LSE_VALUE;
1612 }
1613 break;
1614
1615 case LL_RCC_RNG1_CLKSOURCE_LSI:
1616 case LL_RCC_RNG2_CLKSOURCE_LSI:
1617 if (LL_RCC_LSI_IsReady() != 0U)
1618 {
1619 rng_frequency = LSI_VALUE;
1620 }
1621 break;
1622
1623 default:
1624 /* Nothing to do */
1625 break;
1626 }
1627
1628 return rng_frequency;
1629 }
1630
1631 /**
1632 * @brief Return CKPERx clock frequency
1633 * @param CKPERxSource This parameter can be one of the following values:
1634 * @arg @ref LL_RCC_CKPER_CLKSOURCE
1635 * @retval CKPER clock frequency (in Hz)
1636 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1637 */
LL_RCC_GetCKPERClockFreq(uint32_t CKPERxSource)1638 uint32_t LL_RCC_GetCKPERClockFreq(uint32_t CKPERxSource)
1639 {
1640 uint32_t ckper_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1641
1642 /* Check parameter */
1643 assert_param(IS_LL_RCC_CKPER_CLKSOURCE(CKPERxSource));
1644
1645 switch (LL_RCC_GetCKPERClockSource(CKPERxSource))
1646 {
1647 case LL_RCC_CKPER_CLKSOURCE_HSI:
1648 if (LL_RCC_HSI_IsReady() != 0U)
1649 {
1650 ckper_frequency = HSI_VALUE >> LL_RCC_HSI_GetDivider();
1651 }
1652 break;
1653
1654 case LL_RCC_CKPER_CLKSOURCE_CSI:
1655 if (LL_RCC_CSI_IsReady() != 0U)
1656 {
1657 ckper_frequency = CSI_VALUE;
1658 }
1659 break;
1660
1661 case LL_RCC_CKPER_CLKSOURCE_HSE:
1662 if (LL_RCC_HSE_IsReady() != 0U)
1663 {
1664 ckper_frequency = HSE_VALUE;
1665 }
1666 break;
1667
1668 case LL_RCC_CKPER_CLKSOURCE_OFF:
1669 default:
1670 /* Nothing to do */
1671 break;
1672 }
1673
1674 return ckper_frequency;
1675 }
1676
1677 /**
1678 * @brief Return STGENx clock frequency
1679 * @param STGENxSource This parameter can be one of the following values:
1680 * @arg @ref LL_RCC_STGEN_CLKSOURCE
1681 * @retval STGEN clock frequency (in Hz)
1682 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1683 */
LL_RCC_GetSTGENClockFreq(uint32_t STGENxSource)1684 uint32_t LL_RCC_GetSTGENClockFreq(uint32_t STGENxSource)
1685 {
1686 uint32_t stgen_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1687
1688 /* Check parameter */
1689 assert_param(IS_LL_RCC_STGEN_CLKSOURCE(STGENxSource));
1690
1691 switch (LL_RCC_GetSTGENClockSource(STGENxSource))
1692 {
1693 case LL_RCC_STGEN_CLKSOURCE_HSI:
1694 if (LL_RCC_HSI_IsReady() != 0U)
1695 {
1696 stgen_frequency = HSI_VALUE >> LL_RCC_HSI_GetDivider();
1697 }
1698 break;
1699
1700 case LL_RCC_STGEN_CLKSOURCE_HSE:
1701 if (LL_RCC_HSE_IsReady() != 0U)
1702 {
1703 stgen_frequency = HSE_VALUE;
1704 }
1705 break;
1706
1707 case LL_RCC_STGEN_CLKSOURCE_OFF:
1708 default:
1709 /* Nothing to do */
1710 break;
1711 }
1712
1713 return stgen_frequency;
1714 }
1715
1716 #if defined(DSI)
1717 /**
1718 * @brief Return DSIx clock frequency
1719 * @param DSIxSource This parameter can be one of the following values:
1720 * @arg @ref LL_RCC_DSI_CLKSOURCE
1721 * @retval DSI clock frequency (in Hz)
1722 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1723 */
LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)1724 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
1725 {
1726 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1727 LL_PLL_ClocksTypeDef PLL_Clocks;
1728
1729 /* Check parameter */
1730 assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
1731
1732 switch (LL_RCC_GetDSIClockSource(DSIxSource))
1733 {
1734 case LL_RCC_DSI_CLKSOURCE_PLL4P:
1735 if (LL_RCC_PLL4_IsReady() != 0U)
1736 {
1737 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
1738 dsi_frequency = PLL_Clocks.PLL_P_Frequency;
1739 }
1740 break;
1741
1742 /* It has no sense to ask for DSIPHY frequency because it is generated
1743 * by DSI itself, so send back 0 as kernel frequency
1744 */
1745 case LL_RCC_DSI_CLKSOURCE_PHY:
1746 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1747 break;
1748
1749 default:
1750 /* Nothing to do */
1751 break;
1752 }
1753
1754 return dsi_frequency;
1755 }
1756 #endif /*DSI*/
1757
1758 /**
1759 * @brief Return ADCx clock frequency
1760 * @param ADCxSource This parameter can be one of the following values:
1761 * @arg @ref LL_RCC_ADC_CLKSOURCE
1762 * @retval ADC clock frequency (in Hz)
1763 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1764 */
LL_RCC_GetADCClockFreq(uint32_t ADCxSource)1765 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
1766 {
1767 uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1768 LL_PLL_ClocksTypeDef PLL_Clocks;
1769
1770 /* Check parameter */
1771 assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
1772
1773 switch (LL_RCC_GetADCClockSource(ADCxSource))
1774 {
1775 case LL_RCC_ADC_CLKSOURCE_PLL4R:
1776 if (LL_RCC_PLL4_IsReady() != 0U)
1777 {
1778 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
1779 adc_frequency = PLL_Clocks.PLL_R_Frequency;
1780 }
1781 break;
1782
1783 case LL_RCC_ADC_CLKSOURCE_PER:
1784 adc_frequency = LL_RCC_GetCKPERClockFreq(LL_RCC_CKPER_CLKSOURCE);
1785 break;
1786
1787 case LL_RCC_ADC_CLKSOURCE_PLL3Q:
1788 if (LL_RCC_PLL3_IsReady() != 0U)
1789 {
1790 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1791 adc_frequency = PLL_Clocks.PLL_Q_Frequency;
1792 }
1793 break;
1794
1795 default:
1796 /* Nothing to do */
1797 break;
1798 }
1799
1800 return adc_frequency;
1801 }
1802
1803 /**
1804 * @brief Return LPTIMx clock frequency
1805 * @param LPTIMxSource This parameter can be one of the following values:
1806 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
1807 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE
1808 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE
1809 * @retval LPTIM clock frequency (in Hz)
1810 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1811 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)1812 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
1813 {
1814 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1815 LL_PLL_ClocksTypeDef PLL_Clocks;
1816
1817 /* Check parameter */
1818 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
1819
1820 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
1821 {
1822 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:
1823 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetMLHCLKClockFreq(RCC_GetMCUSSClockFreq()));
1824 break;
1825
1826 case LL_RCC_LPTIM1_CLKSOURCE_PLL4P:
1827 case LL_RCC_LPTIM45_CLKSOURCE_PLL4P:
1828 if (LL_RCC_PLL4_IsReady() != 0U)
1829 {
1830 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
1831 lptim_frequency = PLL_Clocks.PLL_P_Frequency;
1832 }
1833 break;
1834
1835 case LL_RCC_LPTIM1_CLKSOURCE_PLL3Q:
1836 case LL_RCC_LPTIM45_CLKSOURCE_PLL3Q:
1837 if (LL_RCC_PLL3_IsReady() != 0U)
1838 {
1839 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1840 lptim_frequency = PLL_Clocks.PLL_Q_Frequency;
1841 }
1842 break;
1843
1844 case LL_RCC_LPTIM1_CLKSOURCE_LSE:
1845 case LL_RCC_LPTIM23_CLKSOURCE_LSE:
1846 case LL_RCC_LPTIM45_CLKSOURCE_LSE:
1847 if (LL_RCC_LSE_IsReady() != 0U)
1848 {
1849 lptim_frequency = LSE_VALUE;
1850 }
1851 break;
1852
1853 case LL_RCC_LPTIM1_CLKSOURCE_LSI:
1854 case LL_RCC_LPTIM23_CLKSOURCE_LSI:
1855 case LL_RCC_LPTIM45_CLKSOURCE_LSI:
1856 if (LL_RCC_LSI_IsReady() != 0U)
1857 {
1858 lptim_frequency = LSI_VALUE;
1859 }
1860 break;
1861
1862 case LL_RCC_LPTIM1_CLKSOURCE_PER:
1863 case LL_RCC_LPTIM23_CLKSOURCE_PER:
1864 case LL_RCC_LPTIM45_CLKSOURCE_PER:
1865 lptim_frequency = LL_RCC_GetCKPERClockFreq(LL_RCC_CKPER_CLKSOURCE);
1866 break;
1867
1868 case LL_RCC_LPTIM23_CLKSOURCE_PCLK3:
1869 case LL_RCC_LPTIM45_CLKSOURCE_PCLK3:
1870 lptim_frequency = RCC_GetPCLK3ClockFreq(RCC_GetMLHCLKClockFreq(RCC_GetMCUSSClockFreq()));
1871 break;
1872
1873 case LL_RCC_LPTIM23_CLKSOURCE_PLL4Q:
1874 if (LL_RCC_PLL4_IsReady() != 0U)
1875 {
1876 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
1877 lptim_frequency = PLL_Clocks.PLL_Q_Frequency;
1878 }
1879 break;
1880
1881 case LL_RCC_LPTIM1_CLKSOURCE_OFF:
1882 case LL_RCC_LPTIM23_CLKSOURCE_OFF:
1883 case LL_RCC_LPTIM45_CLKSOURCE_OFF:
1884 default:
1885 /* Nothing to do */
1886 break;
1887 }
1888
1889 return lptim_frequency;
1890 }
1891
1892 /**
1893 * @brief Return DFSDM kernel clock frequency
1894 * @param DFSDMxSource This parameter can be one of the following values:
1895 * @arg @ref LL_RCC_DFSDM_CLKSOURCE
1896 * @note DFSM shares with SAI1 the same kernel clock source
1897 * @retval DFSDM clock frequency (in Hz)
1898 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1899 */
LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)1900 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
1901 {
1902 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1903 LL_PLL_ClocksTypeDef PLL_Clocks;
1904
1905 /* Check parameter */
1906 assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
1907
1908 switch (LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE))
1909 {
1910 case LL_RCC_SAI1_CLKSOURCE_PLL4Q:
1911 if (LL_RCC_PLL4_IsReady() != 0U)
1912 {
1913 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
1914 dfsdm_frequency = PLL_Clocks.PLL_Q_Frequency;
1915 }
1916 break;
1917
1918 case LL_RCC_SAI1_CLKSOURCE_PLL3Q:
1919 if (LL_RCC_PLL3_IsReady() != 0U)
1920 {
1921 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1922 dfsdm_frequency = PLL_Clocks.PLL_Q_Frequency;
1923 }
1924 break;
1925
1926 case LL_RCC_SAI1_CLKSOURCE_I2SCKIN:
1927 dfsdm_frequency = EXTERNAL_CLOCK_VALUE;
1928 break;
1929
1930 case LL_RCC_SAI1_CLKSOURCE_PER:
1931 dfsdm_frequency = LL_RCC_GetCKPERClockFreq(LL_RCC_CKPER_CLKSOURCE);
1932 break;
1933
1934 case LL_RCC_SAI1_CLKSOURCE_PLL3R:
1935 if (LL_RCC_PLL3_IsReady() != 0U)
1936 {
1937 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1938 dfsdm_frequency = PLL_Clocks.PLL_R_Frequency;
1939 }
1940 break;
1941
1942 default:
1943 /* Nothing to do */
1944 break;
1945 }
1946
1947 return dfsdm_frequency;
1948 }
1949
1950 /**
1951 * @brief Return LTDC kernel clock frequency
1952 * @retval LTDC clock frequency (in Hz)
1953 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1954 */
LL_RCC_GetLTDCClockFreq(void)1955 uint32_t LL_RCC_GetLTDCClockFreq(void)
1956 {
1957 uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1958 LL_PLL_ClocksTypeDef PLL_Clocks;
1959
1960 if (LL_RCC_PLL4_IsReady() != 0U)
1961 {
1962 LL_RCC_GetPLL4ClockFreq(&PLL_Clocks);
1963 ltdc_frequency = PLL_Clocks.PLL_Q_Frequency;
1964 }
1965
1966 return ltdc_frequency;
1967 }
1968
1969 /**
1970 * @brief Return RTC clock frequency
1971 * @retval RTC clock frequency (in Hz)
1972 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1973 */
LL_RCC_GetRTCClockFreq(void)1974 uint32_t LL_RCC_GetRTCClockFreq(void)
1975 {
1976 uint32_t rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1977
1978 /* RTCCLK clock frequency */
1979 switch (LL_RCC_GetRTCClockSource())
1980 {
1981 case LL_RCC_RTC_CLKSOURCE_LSE: /* LSE clock used as RTC clock source */
1982 if (LL_RCC_LSE_IsReady() != 0U)
1983 {
1984 rtc_frequency = LSE_VALUE;
1985 }
1986 break;
1987
1988 case LL_RCC_RTC_CLKSOURCE_LSI: /* LSI clock used as RTC clock source */
1989 if (LL_RCC_LSI_IsReady() != 0U)
1990 {
1991 rtc_frequency = LSI_VALUE;
1992 }
1993 break;
1994
1995 case LL_RCC_RTC_CLKSOURCE_HSE_DIV: /* HSE clock used as RTC clock source */
1996 rtc_frequency = (HSE_VALUE / (LL_RCC_GetRTC_HSEPrescaler() + 1U));
1997 break;
1998
1999 case LL_RCC_RTC_CLKSOURCE_NONE: /* No clock used as RTC clock source */
2000 default:
2001 /* Nothing to do */
2002 break;
2003 }
2004
2005 return rtc_frequency;
2006 }
2007
2008 /**
2009 * @brief Return TIMGx clock frequency
2010 * @param TIMGxPrescaler This parameter can be one of the following values:
2011 * @arg @ref LL_RCC_TIMG1PRES
2012 * @arg @ref LL_RCC_TIMG2PRES
2013 *@note LL_RCC_TIMG1PRES returns the frequency of the prescaler of timers
2014 * located into APB1 domain. It concerns TIM2, TIM3, TIM4, TIM5, TIM6,
2015 * TIM7, TIM12, TIM13 and TIM14 frequencies.
2016 * LL_RCC_TIMG2PRES returns the frequency of the prescaler of timers
2017 * located into APB2 domain. It concerns TIM1, TIM8, TIM15, TIM16, and
2018 * TIM17.
2019 * @retval TIMGx clock frequency (in Hz)
2020 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
2021 */
LL_RCC_GetTIMGClockFreq(uint32_t TIMGxPrescaler)2022 uint32_t LL_RCC_GetTIMGClockFreq(uint32_t TIMGxPrescaler)
2023 {
2024 uint32_t timg_frequency, apb1_div;
2025
2026 /* Check parameter */
2027 assert_param(IS_LL_RCC_TIMGPRES(TIMGxPrescaler));
2028
2029 timg_frequency = RCC_GetMLHCLKClockFreq(RCC_GetMCUSSClockFreq());
2030 apb1_div = LL_RCC_GetAPB1Prescaler();
2031
2032 switch (LL_RCC_GetTIMGPrescaler(TIMGxPrescaler))
2033 {
2034 case LL_RCC_TIMG1PRES_ACTIVATED:
2035 case LL_RCC_TIMG2PRES_ACTIVATED:
2036 switch (apb1_div)
2037 {
2038 case LL_RCC_APB1_DIV_1:
2039 case LL_RCC_APB1_DIV_2:
2040 case LL_RCC_APB1_DIV_4:
2041 break;
2042 case LL_RCC_APB1_DIV_8:
2043 timg_frequency /= 2U;
2044 break;
2045 case LL_RCC_APB1_DIV_16:
2046 timg_frequency /= 4U;
2047 break;
2048 }
2049 break;
2050
2051 case LL_RCC_TIMG1PRES_DEACTIVATED:
2052 case LL_RCC_TIMG2PRES_DEACTIVATED:
2053 switch (apb1_div)
2054 {
2055 case LL_RCC_APB1_DIV_1:
2056 case LL_RCC_APB1_DIV_2:
2057 break;
2058 case LL_RCC_APB1_DIV_4:
2059 timg_frequency /= 2U;
2060 break;
2061 case LL_RCC_APB1_DIV_8:
2062 timg_frequency /= 4U;
2063 break;
2064 case LL_RCC_APB1_DIV_16:
2065 timg_frequency /= 8U;
2066 break;
2067 }
2068 break;
2069
2070 default:
2071 timg_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2072 break;
2073 }
2074
2075 return timg_frequency;
2076 }
2077
2078 /**
2079 * @}
2080 */
2081
2082 /**
2083 * @}
2084 */
2085
2086 /** @addtogroup RCC_LL_Private_Functions
2087 * @{
2088 */
2089
2090 /**
2091 * @brief Return MPUSS clock frequency
2092 * @retval MPUSS clock frequency (in Hz)
2093 */
RCC_GetMPUSSClockFreq(void)2094 uint32_t RCC_GetMPUSSClockFreq(void)
2095 {
2096 uint32_t frequency = 0U, mpudiv;
2097 LL_PLL_ClocksTypeDef PLL_Clocks;
2098
2099 /* Get MPUSS source -------------------------------------------------------*/
2100 switch (LL_RCC_GetMPUClkSource())
2101 {
2102 case LL_RCC_MPU_CLKSOURCE_HSI:
2103 frequency = (HSI_VALUE >> LL_RCC_HSI_GetDivider());
2104 break;
2105
2106 case LL_RCC_MPU_CLKSOURCE_HSE:
2107 frequency = HSE_VALUE;
2108 break;
2109
2110 case LL_RCC_MPU_CLKSOURCE_PLL1:
2111 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
2112 frequency = PLL_Clocks.PLL_P_Frequency;
2113 break;
2114
2115 case LL_RCC_MPU_CLKSOURCE_MPUDIV:
2116 mpudiv = LL_RCC_GetMPUPrescaler();
2117 if (mpudiv != LL_RCC_MPU_DIV_OFF)
2118 {
2119 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
2120 frequency = (PLL_Clocks.PLL_P_Frequency >> mpudiv);
2121 }
2122 break;
2123
2124 default:
2125 /* Nothing to do */
2126 break;
2127 }
2128
2129 return frequency;
2130 }
2131
2132 /**
2133 * @brief Return AXISS clock frequency
2134 * @retval AXISS clock frequency (in Hz)
2135 */
RCC_GetAXISSClockFreq(void)2136 uint32_t RCC_GetAXISSClockFreq(void)
2137 {
2138 uint32_t frequency = 0U;
2139 LL_PLL_ClocksTypeDef PLL_Clocks;
2140
2141 /* Get AXISS source -------------------------------------------------------*/
2142 switch (LL_RCC_GetAXISSClkSource())
2143 {
2144 case LL_RCC_AXISS_CLKSOURCE_HSI:
2145 frequency = (HSI_VALUE >> LL_RCC_HSI_GetDivider());
2146 break;
2147
2148 case LL_RCC_AXISS_CLKSOURCE_HSE:
2149 frequency = HSE_VALUE;
2150 break;
2151
2152 case LL_RCC_AXISS_CLKSOURCE_PLL2:
2153 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2154 frequency = PLL_Clocks.PLL_P_Frequency;
2155 break;
2156
2157 case LL_RCC_AXISS_CLKSOURCE_OFF:
2158 default:
2159 /* Nothing to do */
2160 break;
2161 }
2162
2163 return frequency;
2164 }
2165
2166 /**
2167 * @brief Return MCUSS clock frequency
2168 * @retval MCUSS clock frequency (in Hz)
2169 */
RCC_GetMCUSSClockFreq()2170 uint32_t RCC_GetMCUSSClockFreq()
2171 {
2172 uint32_t frequency = 0U;
2173 LL_PLL_ClocksTypeDef PLL_Clocks;
2174
2175 /* Get MCUSS source -------------------------------------------------------*/
2176 switch (LL_RCC_GetMCUSSClkSource())
2177 {
2178 case LL_RCC_MCUSS_CLKSOURCE_HSI:
2179 frequency = (HSI_VALUE >> LL_RCC_HSI_GetDivider());
2180 break;
2181
2182 case LL_RCC_MCUSS_CLKSOURCE_HSE:
2183 frequency = HSE_VALUE;
2184 break;
2185
2186 case LL_RCC_MCUSS_CLKSOURCE_CSI:
2187 frequency = CSI_VALUE;
2188 break;
2189
2190 case LL_RCC_MCUSS_CLKSOURCE_PLL3:
2191 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2192 frequency = PLL_Clocks.PLL_P_Frequency;
2193 break;
2194
2195 default:
2196 /* Nothing to do */
2197 break;
2198 }
2199
2200 return frequency;
2201 }
2202
2203 /**
2204 * @brief Return ACLK (ACLK, HCLK5 and HCLK6) clock frequency
2205 * @retval ACLK clock frequency (in Hz)
2206 */
RCC_GetACLKClockFreq(uint32_t AXISS_Frequency)2207 uint32_t RCC_GetACLKClockFreq(uint32_t AXISS_Frequency)
2208 {
2209 return LL_RCC_CALC_ACLK_FREQ(AXISS_Frequency, LL_RCC_GetACLKPrescaler());
2210 }
2211
2212 /**
2213 * @brief Return MLHCLK (MLHCLK, HCLK[4:1], MCU_CK and FCLK_CK) clock frequency
2214 * @retval MLHCLK clock frequency (in Hz)
2215 */
RCC_GetMLHCLKClockFreq(uint32_t MCUSS_Frequency)2216 uint32_t RCC_GetMLHCLKClockFreq(uint32_t MCUSS_Frequency)
2217 {
2218 return LL_RCC_CALC_MLHCLK_FREQ(MCUSS_Frequency, LL_RCC_GetMLHCLKPrescaler());
2219 }
2220
2221 /**
2222 * @brief Return PCLK1 clock frequency
2223 * @param MLHCLK_Frequency MLHCLK clock frequency
2224 * @retval PCLK1 clock frequency (in Hz)
2225 */
RCC_GetPCLK1ClockFreq(uint32_t MLHCLK_Frequency)2226 uint32_t RCC_GetPCLK1ClockFreq(uint32_t MLHCLK_Frequency)
2227 {
2228 /* PCLK1 clock frequency */
2229 return LL_RCC_CALC_PCLK1_FREQ(MLHCLK_Frequency, LL_RCC_GetAPB1Prescaler());
2230 }
2231
2232 /**
2233 * @brief Return PCLK2 clock frequency
2234 * @param MLHCLK_Frequency MLHCLK clock frequency
2235 * @retval PCLK2 clock frequency (in Hz)
2236 */
RCC_GetPCLK2ClockFreq(uint32_t MLHCLK_Frequency)2237 uint32_t RCC_GetPCLK2ClockFreq(uint32_t MLHCLK_Frequency)
2238 {
2239 /* PCLK2 clock frequency */
2240 return LL_RCC_CALC_PCLK2_FREQ(MLHCLK_Frequency, LL_RCC_GetAPB2Prescaler());
2241 }
2242
2243 /**
2244 * @brief Return PCLK3 clock frequency
2245 * @param MLHCLK_Frequency MLHCLK clock frequency
2246 * @retval PCLK3 clock frequency (in Hz)
2247 */
RCC_GetPCLK3ClockFreq(uint32_t MLHCLK_Frequency)2248 uint32_t RCC_GetPCLK3ClockFreq(uint32_t MLHCLK_Frequency)
2249 {
2250 /* PCLK3 clock frequency */
2251 return LL_RCC_CALC_PCLK3_FREQ(MLHCLK_Frequency, LL_RCC_GetAPB3Prescaler());
2252 }
2253
2254 /**
2255 * @brief Return PCLK4 clock frequency
2256 * @param ACLK_Frequency ACLK clock frequency
2257 * @retval PCLK4 clock frequency (in Hz)
2258 */
RCC_GetPCLK4ClockFreq(uint32_t ACLK_Frequency)2259 uint32_t RCC_GetPCLK4ClockFreq(uint32_t ACLK_Frequency)
2260 {
2261 /* PCLK4 clock frequency */
2262 return LL_RCC_CALC_PCLK4_FREQ(ACLK_Frequency, LL_RCC_GetAPB4Prescaler());
2263 }
2264
2265 /**
2266 * @brief Return PCLK5 clock frequency
2267 * @param ACLK_Frequency ACLK clock frequency
2268 * @retval PCLK5 clock frequency (in Hz)
2269 */
RCC_GetPCLK5ClockFreq(uint32_t ACLK_Frequency)2270 uint32_t RCC_GetPCLK5ClockFreq(uint32_t ACLK_Frequency)
2271 {
2272 /* PCLK5 clock frequency */
2273 return LL_RCC_CALC_PCLK5_FREQ(ACLK_Frequency, LL_RCC_GetAPB5Prescaler());
2274 }
2275
2276 /**
2277 * @}
2278 */
2279
2280 /**
2281 * @}
2282 */
2283
2284 #endif /* defined(RCC) */
2285
2286 /**
2287 * @}
2288 */
2289
2290 #endif /* USE_FULL_LL_DRIVER */
2291
