1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_ll_delayblock.c
4 * @author MCD Application Team
5 * @brief DelayBlock Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Delay Block peripheral:
9 * + input clock frequency range 25MHz to 208MHz
10 * + up to 12 oversampling phases
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2019 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### DelayBlock peripheral features #####
26 ==============================================================================
27 [..] The Delay block is used to generate an Output clock which is de-phased from the Input
28 clock. The phase of the Output clock is programmed by FW. The Output clock is then used
29 to clock the receive data in i.e. a SDMMC or QSPI interface.
30 The delay is Voltage and Temperature dependent, which may require FW to do re-tuning
31 and recenter the Output clock phase to the receive data.
32
33 [..] The Delay Block features include the following:
34 (+) Input clock frequency range 25MHz to 208MHz.
35 (+) Up to 12 oversampling phases.
36
37 ##### How to use this driver #####
38 ==============================================================================
39 [..]
40 This driver is a considered as a driver of service for external devices drivers
41 that interfaces with the DELAY peripheral.
42 The DelayBlock_Enable() function, enables the DelayBlock instance, configure the delay line length
43 and configure the Output clock phase.
44 The DelayBlock_Disable() function, disables the DelayBlock instance by setting DEN flag to 0.
45
46
47 @endverbatim
48 ******************************************************************************
49 */
50
51 /* Includes ------------------------------------------------------------------*/
52 #include "stm32mp1xx_hal.h"
53
54 /** @addtogroup STM32MP1xx_HAL_Driver
55 * @{
56 */
57
58 /** @defgroup DELAYBLOCK_LL DELAYBLOCK_LL
59 * @brief Low layer module for Delay Block
60 * @{
61 */
62
63 #if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_QSPI_MODULE_ENABLED)
64
65 /* Private typedef -----------------------------------------------------------*/
66 /* Private define ------------------------------------------------------------*/
67 /* Private macro -------------------------------------------------------------*/
68 /* Private variables ---------------------------------------------------------*/
69 /* Private function prototypes -----------------------------------------------*/
70 /* Exported functions --------------------------------------------------------*/
71
72 /** @defgroup DelayBlock_LL_Exported_Functions Delay Block Low Layer Exported Functions
73 * @{
74 */
75
76 /** @defgroup HAL_DELAY_LL_Group1 Initialization de-initialization functions
77 * @brief Initialization and Configuration functions
78 *
79 @verbatim
80 ===============================================================================
81 ##### Initialization and de-initialization functions #####
82 ===============================================================================
83 [..] This section provides functions allowing to:
84
85 @endverbatim
86 * @{
87 */
88
89
90 /**
91 * @brief Enable the Delay Block instance.
92 * @param DLYBx: Pointer to DLYB instance.
93 * @retval HAL status
94 */
DelayBlock_Enable(DLYB_TypeDef * DLYBx)95 HAL_StatusTypeDef DelayBlock_Enable(DLYB_TypeDef *DLYBx)
96 {
97 uint32_t i=0,N=0, lng=0, tuningOn = 1;
98
99 assert_param(IS_DLYB_ALL_INSTANCE(DLYBx));
100
101 DLYBx->CR = DLYB_CR_DEN | DLYB_CR_SEN;
102
103 while((tuningOn != 0) && (i < DLYB_MAX_UNIT))
104 {
105
106 DLYBx->CFGR = 12 | (i << 8);
107 HAL_Delay(1);
108 if(((DLYBx->CFGR & DLYB_CFGR_LNGF) != 0)
109 && ((DLYBx->CFGR & DLYB_CFGR_LNG) != 0)
110 && ((DLYBx->CFGR & DLYB_CFGR_LNG) != (DLYB_CFGR_LNG_11 | DLYB_CFGR_LNG_10)))
111 {
112 tuningOn = 0;
113 }
114 i++;
115
116 }
117
118 if(DLYB_MAX_UNIT != i)
119 {
120
121 lng = (DLYBx->CFGR & DLYB_CFGR_LNG) >> 16;
122 N = 10;
123 while((N>0) && ((lng >> N) == 0))
124 {
125 N--;
126 }
127 if(0 != N)
128 {
129 MODIFY_REG(DLYBx->CFGR, DLYB_CFGR_SEL, ((N/2)+1));
130
131 /* Disable Selection phase */
132 DLYBx->CR = DLYB_CR_DEN;
133 return HAL_OK;
134 }
135 }
136
137 /* Disable DLYB */
138 DelayBlock_Disable(DLYBx);
139 return HAL_ERROR;
140
141 }
142
143 /**
144 * @brief Disable the Delay Block instance.
145 * @param DLYBx: Pointer to DLYB instance.
146 * @retval HAL status
147 */
DelayBlock_Disable(DLYB_TypeDef * DLYBx)148 HAL_StatusTypeDef DelayBlock_Disable(DLYB_TypeDef *DLYBx)
149 {
150 /* Disable DLYB */
151 DLYBx->CR = 0;
152 return HAL_OK;
153 }
154
155 /**
156 * @}
157 */
158
159 /**
160 * @}
161 */
162
163 #endif /* (HAL_SD_MODULE_ENABLED) & (HAL_QSPI_MODULE_ENABLED)*/
164 /**
165 * @}
166 */
167
168 /**
169 * @}
170 */
171
