1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32mp1xx_ll_adc.h"
22 #include "stm32mp1xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32MP1xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup ADC_LL_Private_Constants
44 * @{
45 */
46
47 /* Definitions of ADC hardware constraints delays */
48 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
49 /* not timeout values: */
50 /* Timeout values for ADC operations are dependent to device clock */
51 /* configuration (system clock versus ADC clock), */
52 /* and therefore must be defined in user application. */
53 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
54 /* values definition. */
55 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
56 /* of device clock setting. */
57 /* In user application, ADC timeout values should be defined with */
58 /* temporal values, in function of device clock settings. */
59 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
60 /* - ADC clock from synchronous clock with AHB prescaler 512, */
61 /* APB prescaler 16, ADC prescaler 4. */
62 /* - ADC clock from asynchronous clock (PLL) with prescaler 1, */
63 /* with highest ratio CPU clock frequency vs HSI clock frequency */
64 /* Unit: CPU cycles. */
65 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
66 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
67 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
68
69 /**
70 * @}
71 */
72
73 /* Private macros ------------------------------------------------------------*/
74
75 /** @addtogroup ADC_LL_Private_Macros
76 * @{
77 */
78
79 /* Check of parameters for configuration of ADC hierarchical scope: */
80 /* common to several ADC instances. */
81 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
82 (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
83 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
84 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
85 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
86 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
87 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
89 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
90 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
93 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
94 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
95 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
96 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
97 )
98
99 /* Check of parameters for configuration of ADC hierarchical scope: */
100 /* ADC instance. */
101 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
102 (((__RESOLUTION__) == LL_ADC_RESOLUTION_16B) \
103 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_14B) \
104 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
105 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
106 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
107 )
108
109 #define IS_LL_ADC_LEFT_BIT_SHIFT(__LEFT_BIT_SHIFT__) \
110 (((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_NONE) \
111 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_1) \
112 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_2) \
113 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_3) \
114 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_4) \
115 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_5) \
116 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_6) \
117 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_7) \
118 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_8) \
119 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_9) \
120 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_10) \
121 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_11) \
122 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_12) \
123 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_13) \
124 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_14) \
125 || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_15) \
126 )
127
128 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
129 (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
130 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
131 )
132
133 /* Check of parameters for configuration of ADC hierarchical scope: */
134 /* ADC group regular */
135 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
136 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
137 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
144 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
145 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
146 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
147 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
148 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
149 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
150 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
151 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
152 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
153 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_OUT) \
154 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_OUT) \
155 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM3_OUT) \
156 )
157
158 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
159 (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
160 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
161 )
162
163 #define IS_LL_ADC_REG_DATA_TRANSFER_MODE(__REG_DATA_TRANSFER_MODE__) \
164 (((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DR_TRANSFER) \
165 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
166 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
167 || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DFSDM_TRANSFER) \
168 )
169
170 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
171 (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
172 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
173 )
174
175 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
176 (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
177 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
178 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
179 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
180 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
181 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
182 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
183 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
184 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
185 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
186 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
187 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
188 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
189 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
190 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
191 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
192 )
193
194 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
195 (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
196 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
197 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
198 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
199 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
200 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
201 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
202 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
203 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
204 )
205
206 /* Check of parameters for configuration of ADC hierarchical scope: */
207 /* ADC group injected */
208 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
209 (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
210 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
211 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
212 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
213 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
214 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
215 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
216 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
217 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
218 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
219 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
220 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
221 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
222 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
223 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
224 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
225 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
226 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) \
227 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) \
228 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) \
229 )
230
231 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
232 (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
233 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
234 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
235 )
236
237 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
238 (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
239 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
240 )
241
242 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
243 (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
244 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
245 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
246 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
247 )
248
249 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
250 (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
251 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
252 )
253
254 #if defined(ADC_MULTIMODE_SUPPORT)
255 /* Check of parameters for configuration of ADC hierarchical scope: */
256 /* multimode. */
257 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
258 (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
259 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
260 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
261 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
262 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
263 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
264 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
265 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
266 )
267
268 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
269 (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
270 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_32_10B) \
271 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_8B) \
272 )
273 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
274 (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) \
275 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5) \
276 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5) \
277 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5) \
278 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS) \
279 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5) \
280 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS) \
281 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5) \
282 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS) \
283 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5) \
284 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5_14_BITS) \
285 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES_5) \
286 )
287 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
288 (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
289 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
290 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
291 )
292
293 #endif /* ADC_MULTIMODE_SUPPORT */
294 /**
295 * @}
296 */
297
298
299 /* Private function prototypes -----------------------------------------------*/
300
301 /* Exported functions --------------------------------------------------------*/
302 /** @addtogroup ADC_LL_Exported_Functions
303 * @{
304 */
305
306 /** @addtogroup ADC_LL_EF_Init
307 * @{
308 */
309
310 /**
311 * @brief De-initialize registers of all ADC instances belonging to
312 * the same ADC common instance to their default reset values.
313 * @note This function is performing a hard reset, using high level
314 * clock source RCC ADC reset.
315 * Caution: On this STM32 series, if several ADC instances are available
316 * on the selected device, RCC ADC reset will reset
317 * all ADC instances belonging to the common ADC instance.
318 * To de-initialize only 1 ADC instance, use
319 * function @ref LL_ADC_DeInit().
320 * @param ADCxy_COMMON ADC common instance
321 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
322 * @retval An ErrorStatus enumeration value:
323 * - SUCCESS: ADC common registers are de-initialized
324 * - ERROR: not applicable
325 */
LL_ADC_CommonDeInit(ADC_Common_TypeDef * ADCxy_COMMON)326 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
327 {
328 /* Check the parameters */
329 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
330
331 /* Force reset of ADC clock (core clock) */
332 LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC12);
333
334 /* Release reset of ADC clock (core clock) */
335 LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC12);
336
337 return SUCCESS;
338 }
339
340 /**
341 * @brief Initialize some features of ADC common parameters
342 * (all ADC instances belonging to the same ADC common instance)
343 * and multimode (for devices with several ADC instances available).
344 * @note The setting of ADC common parameters is conditioned to
345 * ADC instances state:
346 * All ADC instances belonging to the same ADC common instance
347 * must be disabled.
348 * @param ADCxy_COMMON ADC common instance
349 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
350 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
351 * @retval An ErrorStatus enumeration value:
352 * - SUCCESS: ADC common registers are initialized
353 * - ERROR: ADC common registers are not initialized
354 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)355 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
356 {
357 ErrorStatus status = SUCCESS;
358
359 /* Check the parameters */
360 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
361 assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock));
362
363 #if defined(ADC_MULTIMODE_SUPPORT)
364 assert_param(IS_LL_ADC_MULTI_MODE(pADC_CommonInitStruct->Multimode));
365 if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
366 {
367 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(pADC_CommonInitStruct->MultiDMATransfer));
368 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(pADC_CommonInitStruct->MultiTwoSamplingDelay));
369 }
370 #endif /* ADC_MULTIMODE_SUPPORT */
371
372 /* Note: Hardware constraint (refer to description of functions */
373 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
374 /* On this STM32 series, setting of these features is conditioned to */
375 /* ADC state: */
376 /* All ADC instances of the ADC common group must be disabled. */
377 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
378 {
379 /* Configuration of ADC hierarchical scope: */
380 /* - common to several ADC */
381 /* (all ADC instances belonging to the same ADC common instance) */
382 /* - Set ADC clock (conversion clock) */
383 /* - multimode (if several ADC instances available on the */
384 /* selected device) */
385 /* - Set ADC multimode configuration */
386 /* - Set ADC multimode DMA transfer */
387 /* - Set ADC multimode: delay between 2 sampling phases */
388 #if defined(ADC_MULTIMODE_SUPPORT)
389 if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
390 {
391 MODIFY_REG(ADCxy_COMMON->CCR,
392 ADC_CCR_CKMODE
393 | ADC_CCR_PRESC
394 | ADC_CCR_DUAL
395 | ADC_CCR_DAMDF
396 | ADC_CCR_DELAY
397 ,
398 pADC_CommonInitStruct->CommonClock
399 | pADC_CommonInitStruct->Multimode
400 | pADC_CommonInitStruct->MultiDMATransfer
401 | pADC_CommonInitStruct->MultiTwoSamplingDelay
402 );
403 }
404 else
405 {
406 MODIFY_REG(ADCxy_COMMON->CCR,
407 ADC_CCR_CKMODE
408 | ADC_CCR_PRESC
409 | ADC_CCR_DUAL
410 | ADC_CCR_DAMDF
411 | ADC_CCR_DELAY
412 ,
413 pADC_CommonInitStruct->CommonClock
414 | LL_ADC_MULTI_INDEPENDENT
415 );
416 }
417 #else
418 LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock);
419 #endif
420 }
421 else
422 {
423 /* Initialization error: One or several ADC instances belonging to */
424 /* the same ADC common instance are not disabled. */
425 status = ERROR;
426 }
427
428 return status;
429 }
430
431 /**
432 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
433 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
434 * whose fields will be set to default values.
435 * @retval None
436 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)437 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
438 {
439 /* Set ADC_CommonInitStruct fields to default values */
440 /* Set fields of ADC common */
441 /* (all ADC instances belonging to the same ADC common instance) */
442 pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
443
444 #if defined(ADC_MULTIMODE_SUPPORT)
445 /* Set fields of ADC multimode */
446 pADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
447 pADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
448 pADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5;
449 #endif /* ADC_MULTIMODE_SUPPORT */
450 }
451
452 /**
453 * @brief De-initialize registers of the selected ADC instance
454 * to their default reset values.
455 * @note To reset all ADC instances quickly (perform a hard reset),
456 * use function @ref LL_ADC_CommonDeInit().
457 * @note If this functions returns error status, it means that ADC instance
458 * is in an unknown state.
459 * In this case, perform a hard reset using high level
460 * clock source RCC ADC reset.
461 * Caution: On this STM32 series, if several ADC instances are available
462 * on the selected device, RCC ADC reset will reset
463 * all ADC instances belonging to the common ADC instance.
464 * Refer to function @ref LL_ADC_CommonDeInit().
465 * @param ADCx ADC instance
466 * @retval An ErrorStatus enumeration value:
467 * - SUCCESS: ADC registers are de-initialized
468 * - ERROR: ADC registers are not de-initialized
469 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)470 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
471 {
472 ErrorStatus status = SUCCESS;
473
474 __IO uint32_t timeout_cpu_cycles = 0UL;
475
476 /* Check the parameters */
477 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
478
479 /* Disable ADC instance if not already disabled. */
480 if (LL_ADC_IsEnabled(ADCx) == 1UL)
481 {
482 /* Set ADC group regular trigger source to SW start to ensure to not */
483 /* have an external trigger event occurring during the conversion stop */
484 /* ADC disable process. */
485 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
486
487 /* Stop potential ADC conversion on going on ADC group regular. */
488 if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
489 {
490 if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
491 {
492 LL_ADC_REG_StopConversion(ADCx);
493 }
494 }
495
496 /* Set ADC group injected trigger source to SW start to ensure to not */
497 /* have an external trigger event occurring during the conversion stop */
498 /* ADC disable process. */
499 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
500
501 /* Stop potential ADC conversion on going on ADC group injected. */
502 if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
503 {
504 if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
505 {
506 LL_ADC_INJ_StopConversion(ADCx);
507 }
508 }
509
510 /* Wait for ADC conversions are effectively stopped */
511 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
512 while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
513 | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
514 {
515 timeout_cpu_cycles--;
516 if (timeout_cpu_cycles == 0UL)
517 {
518 /* Time-out error */
519 status = ERROR;
520 break;
521 }
522 }
523
524 /* Flush group injected contexts queue (register JSQR): */
525 /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
526 /* contexts queue is maintained with the last active context). */
527 LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
528
529 /* Disable the ADC instance */
530 LL_ADC_Disable(ADCx);
531
532 /* Wait for ADC instance is effectively disabled */
533 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
534 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
535 {
536 timeout_cpu_cycles--;
537 if (timeout_cpu_cycles == 0UL)
538 {
539 /* Time-out error */
540 status = ERROR;
541 break;
542 }
543 }
544 }
545
546 /* Check whether ADC state is compliant with expected state */
547 if (READ_BIT(ADCx->CR,
548 (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
549 | ADC_CR_ADDIS | ADC_CR_ADEN)
550 )
551 == 0UL)
552 {
553 /* ========== Reset ADC registers ========== */
554 /* Reset register IER */
555 CLEAR_BIT(ADCx->IER,
556 (LL_ADC_IT_ADRDY
557 | LL_ADC_IT_EOC
558 | LL_ADC_IT_EOS
559 | LL_ADC_IT_OVR
560 | LL_ADC_IT_EOSMP
561 | LL_ADC_IT_JEOC
562 | LL_ADC_IT_JEOS
563 | LL_ADC_IT_JQOVF
564 | LL_ADC_IT_AWD1
565 | LL_ADC_IT_AWD2
566 | LL_ADC_IT_AWD3
567 )
568 );
569
570 /* Reset register ISR */
571 SET_BIT(ADCx->ISR,
572 (LL_ADC_FLAG_ADRDY
573 | LL_ADC_FLAG_EOC
574 | LL_ADC_FLAG_EOS
575 | LL_ADC_FLAG_OVR
576 | LL_ADC_FLAG_EOSMP
577 | LL_ADC_FLAG_JEOC
578 | LL_ADC_FLAG_JEOS
579 | LL_ADC_FLAG_JQOVF
580 | LL_ADC_FLAG_AWD1
581 | LL_ADC_FLAG_AWD2
582 | LL_ADC_FLAG_AWD3
583 )
584 );
585
586 /* Reset register CR */
587 /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
588 /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
589 /* access mode "read-set": no direct reset applicable. */
590 /* - Reset Calibration mode to default setting (single ended). */
591 /* - Disable ADC internal voltage regulator. */
592 /* - Enable ADC deep power down. */
593 /* Note: ADC internal voltage regulator disable and ADC deep power */
594 /* down enable are conditioned to ADC state disabled: */
595 /* already done above. */
596 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
597 SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
598
599 /* Reset register CFGR */
600 CLEAR_BIT(ADCx->CFGR,
601 ( ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
602 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
603 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
604 | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
605 | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_RES
606 | ADC_CFGR_DMNGT )
607 );
608
609 SET_BIT(ADCx->CFGR, ADC_CFGR_JQDIS);
610
611 /* Reset register CFGR2 */
612 CLEAR_BIT(ADCx->CFGR2,
613 ( ADC_CFGR2_LSHIFT | ADC_CFGR2_OVSR | ADC_CFGR2_RSHIFT1
614 | ADC_CFGR2_RSHIFT4 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT2
615 | ADC_CFGR2_RSHIFT1 | ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS
616 | ADC_CFGR2_OVSS | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
617 );
618
619 /* Reset register SMPR1 */
620 CLEAR_BIT(ADCx->SMPR1,
621 (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
622 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
623 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
624 );
625
626 /* Reset register SMPR2 */
627 CLEAR_BIT(ADCx->SMPR2,
628 (ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17
629 | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14
630 | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11
631 | ADC_SMPR2_SMP10)
632 );
633
634 /* Reset register TR1 */
635 CLEAR_BIT(ADCx->LTR1, ADC_LTR1_LT1);
636 SET_BIT(ADCx->HTR1, ADC_HTR1_HT1);
637
638 CLEAR_BIT(ADCx->LTR2, ADC_LTR2_LT2);
639 SET_BIT(ADCx->HTR2, ADC_HTR2_HT2);
640 CLEAR_BIT(ADCx->LTR3, ADC_LTR3_LT3);
641 SET_BIT(ADCx->HTR3, ADC_HTR3_HT3);
642
643 /* Reset register SQR1 */
644 CLEAR_BIT(ADCx->SQR1,
645 (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
646 | ADC_SQR1_SQ1 | ADC_SQR1_L)
647 );
648
649 /* Reset register SQR2 */
650 CLEAR_BIT(ADCx->SQR2,
651 (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
652 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
653 );
654
655 /* Reset register SQR3 */
656 CLEAR_BIT(ADCx->SQR3,
657 (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
658 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
659 );
660
661 /* Reset register SQR4 */
662 CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
663
664 /* Reset register JSQR */
665 CLEAR_BIT(ADCx->JSQR,
666 (ADC_JSQR_JL
667 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
668 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
669 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1)
670 );
671
672 /* Reset register DR */
673 /* Note: bits in access mode read only, no direct reset applicable */
674
675 /* Reset register OFR1 */
676 CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_SSATE);
677 /* Reset register OFR2 */
678 CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2 | ADC_OFR2_OFFSET2_CH | ADC_OFR2_SSATE);
679 /* Reset register OFR3 */
680 CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3 | ADC_OFR3_OFFSET3_CH | ADC_OFR3_SSATE);
681 /* Reset register OFR4 */
682 CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4 | ADC_OFR4_OFFSET4_CH | ADC_OFR4_SSATE);
683
684 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
685 /* Note: bits in access mode read only, no direct reset applicable */
686
687 /* Reset register AWD2CR */
688 CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
689
690 /* Reset register AWD3CR */
691 CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
692
693 /* Reset register DIFSEL */
694 CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
695
696 /* Reset register CALFACT */
697 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
698
699 /* Reset register CALFACT2 */
700 CLEAR_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT);
701 }
702 else
703 {
704 /* ADC instance is in an unknown state */
705 /* Need to performing a hard reset of ADC instance, using high level */
706 /* clock source RCC ADC reset. */
707 /* Caution: On this STM32 series, if several ADC instances are available */
708 /* on the selected device, RCC ADC reset will reset */
709 /* all ADC instances belonging to the common ADC instance. */
710 /* Caution: On this STM32 series, if several ADC instances are available */
711 /* on the selected device, RCC ADC reset will reset */
712 /* all ADC instances belonging to the common ADC instance. */
713 status = ERROR;
714 }
715
716 return status;
717 }
718
719 /**
720 * @brief Initialize some features of ADC instance.
721 * @note These parameters have an impact on ADC scope: ADC instance.
722 * Affects both group regular and group injected (availability
723 * of ADC group injected depends on STM32 families).
724 * Refer to corresponding unitary functions into
725 * @ref ADC_LL_EF_Configuration_ADC_Instance .
726 * @note The setting of these parameters by function @ref LL_ADC_Init()
727 * is conditioned to ADC state:
728 * ADC instance must be disabled.
729 * This condition is applied to all ADC features, for efficiency
730 * and compatibility over all STM32 families. However, the different
731 * features can be set under different ADC state conditions
732 * (setting possible with ADC enabled without conversion on going,
733 * ADC enabled with conversion on going, ...)
734 * Each feature can be updated afterwards with a unitary function
735 * and potentially with ADC in a different state than disabled,
736 * refer to description of each function for setting
737 * conditioned to ADC state.
738 * @note After using this function, some other features must be configured
739 * using LL unitary functions.
740 * The minimum configuration remaining to be done is:
741 * - Set ADC group regular or group injected sequencer:
742 * map channel on the selected sequencer rank.
743 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
744 * - Set ADC channel sampling time
745 * Refer to function LL_ADC_SetChannelSamplingTime();
746 * @param ADCx ADC instance
747 * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
748 * @retval An ErrorStatus enumeration value:
749 * - SUCCESS: ADC registers are initialized
750 * - ERROR: ADC registers are not initialized
751 */
LL_ADC_Init(ADC_TypeDef * ADCx,LL_ADC_InitTypeDef * pADC_InitStruct)752 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *pADC_InitStruct)
753 {
754 ErrorStatus status = SUCCESS;
755
756 /* Check the parameters */
757 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
758
759 assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
760 assert_param(IS_LL_ADC_LEFT_BIT_SHIFT(pADC_InitStruct->LeftBitShift));
761 assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode));
762
763 /* Note: Hardware constraint (refer to description of this function): */
764 /* ADC instance must be disabled. */
765 if (LL_ADC_IsEnabled(ADCx) == 0UL)
766 {
767 /* Configuration of ADC hierarchical scope: */
768 /* - ADC instance */
769 /* - Set ADC data resolution */
770 /* - Set ADC conversion data alignment */
771 /* - Set ADC low power mode */
772 MODIFY_REG(ADCx->CFGR,
773 ADC_CFGR_RES
774 | ADC_CFGR_AUTDLY
775 ,
776 pADC_InitStruct->Resolution
777 | pADC_InitStruct->LowPowerMode
778 );
779
780 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LSHIFT, pADC_InitStruct->LeftBitShift);
781 }
782 else
783 {
784 /* Initialization error: ADC instance is not disabled. */
785 status = ERROR;
786 }
787
788 return status;
789 }
790
791 /**
792 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
793 * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
794 * whose fields will be set to default values.
795 * @retval None
796 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * pADC_InitStruct)797 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct)
798 {
799 /* Set ADC_InitStruct fields to default values */
800 /* Set fields of ADC instance */
801 pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_16B;
802 pADC_InitStruct->LeftBitShift = LL_ADC_LEFT_BIT_SHIFT_NONE;
803 pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
804
805 }
806
807 /**
808 * @brief Initialize some features of ADC group regular.
809 * @note These parameters have an impact on ADC scope: ADC group regular.
810 * Refer to corresponding unitary functions into
811 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
812 * (functions with prefix "REG").
813 * @note The setting of these parameters by function @ref LL_ADC_Init()
814 * is conditioned to ADC state:
815 * ADC instance must be disabled.
816 * This condition is applied to all ADC features, for efficiency
817 * and compatibility over all STM32 families. However, the different
818 * features can be set under different ADC state conditions
819 * (setting possible with ADC enabled without conversion on going,
820 * ADC enabled with conversion on going, ...)
821 * Each feature can be updated afterwards with a unitary function
822 * and potentially with ADC in a different state than disabled,
823 * refer to description of each function for setting
824 * conditioned to ADC state.
825 * @note After using this function, other features must be configured
826 * using LL unitary functions.
827 * The minimum configuration remaining to be done is:
828 * - Set ADC group regular or group injected sequencer:
829 * map channel on the selected sequencer rank.
830 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
831 * - Set ADC channel sampling time
832 * Refer to function LL_ADC_SetChannelSamplingTime();
833 * @param ADCx ADC instance
834 * @param pADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
835 * @retval An ErrorStatus enumeration value:
836 * - SUCCESS: ADC registers are initialized
837 * - ERROR: ADC registers are not initialized
838 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,LL_ADC_REG_InitTypeDef * pADC_REG_InitStruct)839 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *pADC_REG_InitStruct)
840 {
841 ErrorStatus status = SUCCESS;
842
843 /* Check the parameters */
844 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
845 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_REG_InitStruct->TriggerSource));
846 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_REG_InitStruct->SequencerLength));
847 if (pADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
848 {
849 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_REG_InitStruct->SequencerDiscont));
850
851 /* ADC group regular continuous mode and discontinuous mode */
852 /* can not be enabled simultenaeously */
853 assert_param((pADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
854 || (pADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
855 }
856 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_REG_InitStruct->ContinuousMode));
857 assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(pADC_REG_InitStruct->DataTransferMode));
858 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_REG_InitStruct->Overrun));
859
860 /* Note: Hardware constraint (refer to description of this function): */
861 /* ADC instance must be disabled. */
862 if (LL_ADC_IsEnabled(ADCx) == 0UL)
863 {
864 /* Configuration of ADC hierarchical scope: */
865 /* - ADC group regular */
866 /* - Set ADC group regular trigger source */
867 /* - Set ADC group regular sequencer length */
868 /* - Set ADC group regular sequencer discontinuous mode */
869 /* - Set ADC group regular continuous mode */
870 /* - Set ADC group regular conversion data transfer: no transfer or */
871 /* transfer by DMA, and DMA requests mode */
872 /* - Set ADC group regular overrun behavior */
873 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
874 /* setting of trigger source to SW start. */
875 if (pADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
876 {
877 MODIFY_REG(ADCx->CFGR,
878 ADC_CFGR_EXTSEL
879 | ADC_CFGR_EXTEN
880 | ADC_CFGR_DISCEN
881 | ADC_CFGR_DISCNUM
882 | ADC_CFGR_CONT
883 | ADC_CFGR_DMNGT
884 | ADC_CFGR_OVRMOD
885 ,
886 pADC_REG_InitStruct->TriggerSource
887 | pADC_REG_InitStruct->SequencerDiscont
888 | pADC_REG_InitStruct->ContinuousMode
889 | pADC_REG_InitStruct->DataTransferMode
890 | pADC_REG_InitStruct->Overrun
891 );
892 }
893 else
894 {
895 MODIFY_REG(ADCx->CFGR,
896 ADC_CFGR_EXTSEL
897 | ADC_CFGR_EXTEN
898 | ADC_CFGR_DISCEN
899 | ADC_CFGR_DISCNUM
900 | ADC_CFGR_CONT
901 | ADC_CFGR_DMNGT
902 | ADC_CFGR_OVRMOD
903 ,
904 pADC_REG_InitStruct->TriggerSource
905 | LL_ADC_REG_SEQ_DISCONT_DISABLE
906 | pADC_REG_InitStruct->ContinuousMode
907 | pADC_REG_InitStruct->DataTransferMode
908 | pADC_REG_InitStruct->Overrun
909 );
910 }
911
912 /* Set ADC group regular sequencer length and scan direction */
913 LL_ADC_REG_SetSequencerLength(ADCx, pADC_REG_InitStruct->SequencerLength);
914 }
915 else
916 {
917 /* Initialization error: ADC instance is not disabled. */
918 status = ERROR;
919 }
920 return status;
921 }
922
923 /**
924 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
925 * @param pADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
926 * whose fields will be set to default values.
927 * @retval None
928 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * pADC_REG_InitStruct)929 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_REG_InitStruct)
930 {
931 /* Set ADC_REG_InitStruct fields to default values */
932 /* Set fields of ADC group regular */
933 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
934 /* setting of trigger source to SW start. */
935 pADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
936 pADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
937 pADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
938 pADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
939 pADC_REG_InitStruct->DataTransferMode = LL_ADC_REG_DR_TRANSFER;
940 pADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
941 }
942
943 /**
944 * @brief Initialize some features of ADC group injected.
945 * @note These parameters have an impact on ADC scope: ADC group injected.
946 * Refer to corresponding unitary functions into
947 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
948 * (functions with prefix "INJ").
949 * @note The setting of these parameters by function @ref LL_ADC_Init()
950 * is conditioned to ADC state:
951 * ADC instance must be disabled.
952 * This condition is applied to all ADC features, for efficiency
953 * and compatibility over all STM32 families. However, the different
954 * features can be set under different ADC state conditions
955 * (setting possible with ADC enabled without conversion on going,
956 * ADC enabled with conversion on going, ...)
957 * Each feature can be updated afterwards with a unitary function
958 * and potentially with ADC in a different state than disabled,
959 * refer to description of each function for setting
960 * conditioned to ADC state.
961 * @note After using this function, other features must be configured
962 * using LL unitary functions.
963 * The minimum configuration remaining to be done is:
964 * - Set ADC group injected sequencer:
965 * map channel on the selected sequencer rank.
966 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
967 * - Set ADC channel sampling time
968 * Refer to function LL_ADC_SetChannelSamplingTime();
969 * @note Caution if feature ADC group injected contexts queue is enabled
970 * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
971 * using successively several times this function will appear as
972 * having no effect.
973 * To set several features of ADC group injected, use
974 * function @ref LL_ADC_INJ_ConfigQueueContext().
975 * @param ADCx ADC instance
976 * @param pADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
977 * @retval An ErrorStatus enumeration value:
978 * - SUCCESS: ADC registers are initialized
979 * - ERROR: ADC registers are not initialized
980 */
LL_ADC_INJ_Init(ADC_TypeDef * ADCx,LL_ADC_INJ_InitTypeDef * pADC_INJ_InitStruct)981 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *pADC_INJ_InitStruct)
982 {
983 ErrorStatus status = SUCCESS;
984
985 /* Check the parameters */
986 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
987 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(pADC_INJ_InitStruct->TriggerSource));
988 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(pADC_INJ_InitStruct->SequencerLength));
989 if (pADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
990 {
991 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(pADC_INJ_InitStruct->SequencerDiscont));
992 }
993 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(pADC_INJ_InitStruct->TrigAuto));
994
995 /* Note: Hardware constraint (refer to description of this function): */
996 /* ADC instance must be disabled. */
997 if (LL_ADC_IsEnabled(ADCx) == 0UL)
998 {
999 /* Configuration of ADC hierarchical scope: */
1000 /* - ADC group injected */
1001 /* - Set ADC group injected trigger source */
1002 /* - Set ADC group injected sequencer length */
1003 /* - Set ADC group injected sequencer discontinuous mode */
1004 /* - Set ADC group injected conversion trigger: independent or */
1005 /* from ADC group regular */
1006 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
1007 /* setting of trigger source to SW start. */
1008 if (pADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1009 {
1010 MODIFY_REG(ADCx->CFGR,
1011 ADC_CFGR_JDISCEN
1012 | ADC_CFGR_JAUTO
1013 ,
1014 pADC_INJ_InitStruct->SequencerDiscont
1015 | pADC_INJ_InitStruct->TrigAuto
1016 );
1017 }
1018 else
1019 {
1020 MODIFY_REG(ADCx->CFGR,
1021 ADC_CFGR_JDISCEN
1022 | ADC_CFGR_JAUTO
1023 ,
1024 LL_ADC_REG_SEQ_DISCONT_DISABLE
1025 | pADC_INJ_InitStruct->TrigAuto
1026 );
1027 }
1028
1029 MODIFY_REG(ADCx->JSQR,
1030 ADC_JSQR_JEXTSEL
1031 | ADC_JSQR_JEXTEN
1032 | ADC_JSQR_JL
1033 ,
1034 pADC_INJ_InitStruct->TriggerSource
1035 | pADC_INJ_InitStruct->SequencerLength
1036 );
1037 }
1038 else
1039 {
1040 /* Initialization error: ADC instance is not disabled. */
1041 status = ERROR;
1042 }
1043 return status;
1044 }
1045
1046 /**
1047 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
1048 * @param pADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1049 * whose fields will be set to default values.
1050 * @retval None
1051 */
LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef * pADC_INJ_InitStruct)1052 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_INJ_InitStruct)
1053 {
1054 /* Set ADC_INJ_InitStruct fields to default values */
1055 /* Set fields of ADC group injected */
1056 pADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
1057 pADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
1058 pADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
1059 pADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
1060 }
1061
1062 /**
1063 * @}
1064 */
1065
1066 /**
1067 * @}
1068 */
1069
1070 /**
1071 * @}
1072 */
1073
1074 #endif /* ADC1 || ADC2 */
1075
1076 /**
1077 * @}
1078 */
1079
1080 #endif /* USE_FULL_LL_DRIVER */
1081
