1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 ******************************************************************************
33 * @attention
34 *
35 * Copyright (c) 2019 STMicroelectronics.
36 * All rights reserved.
37 *
38 * This software is licensed under terms that can be found in the LICENSE file
39 * in the root directory of this software component.
40 * If no LICENSE file comes with this software, it is provided AS-IS.
41 *
42 ******************************************************************************
43 @verbatim
44 ==============================================================================
45 ##### TIMER Generic features #####
46 ==============================================================================
47 [..] The Timer features include:
48 (#) 16-bit up, down, up/down auto-reload counter.
49 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
50 counter clock frequency either by any factor between 1 and 65536.
51 (#) Up to 4 independent channels for:
52 (++) Input Capture
53 (++) Output Compare
54 (++) PWM generation (Edge and Center-aligned Mode)
55 (++) One-pulse mode output
56 (#) Synchronization circuit to control the timer with external signals and to interconnect
57 several timers together.
58 (#) Supports incremental encoder for positioning purposes
59
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 (#) Initialize the TIM low level resources by implementing the following functions
64 depending on the selected feature:
65 (++) Time Base : HAL_TIM_Base_MspInit()
66 (++) Input Capture : HAL_TIM_IC_MspInit()
67 (++) Output Compare : HAL_TIM_OC_MspInit()
68 (++) PWM generation : HAL_TIM_PWM_MspInit()
69 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
70 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
71
72 (#) Initialize the TIM low level resources :
73 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
74 (##) TIM pins configuration
75 (+++) Enable the clock for the TIM GPIOs using the following function:
76 __HAL_RCC_GPIOx_CLK_ENABLE();
77 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
78
79 (#) The external Clock can be configured, if needed (the default clock is the
80 internal clock from the APBx), using the following function:
81 HAL_TIM_ConfigClockSource, the clock configuration should be done before
82 any start function.
83
84 (#) Configure the TIM in the desired functioning mode using one of the
85 Initialization function of this driver:
86 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
87 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
88 Output Compare signal.
89 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
90 PWM signal.
91 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
92 external signal.
93 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
94 in One Pulse Mode.
95 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
96
97 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
98 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
99 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
100 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
101 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
102 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
103 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
104
105 (#) The DMA Burst is managed with the two following functions:
106 HAL_TIM_DMABurst_WriteStart()
107 HAL_TIM_DMABurst_ReadStart()
108
109 *** Callback registration ***
110 =============================================
111
112 [..]
113 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
114 allows the user to configure dynamically the driver callbacks.
115
116 [..]
117 Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
118 @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
119 the Callback ID and a pointer to the user callback function.
120
121 [..]
122 Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
123 weak function.
124 @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
125 and the Callback ID.
126
127 [..]
128 These functions allow to register/unregister following callbacks:
129 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
130 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
131 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
132 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
133 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
134 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
135 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
136 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
137 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
138 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
139 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
140 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
141 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
142 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
143 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
144 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
145 (+) TriggerCallback : TIM Trigger Callback.
146 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
147 (+) IC_CaptureCallback : TIM Input Capture Callback.
148 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
149 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
150 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
151 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
152 (+) ErrorCallback : TIM Error Callback.
153 (+) CommutationCallback : TIM Commutation Callback.
154 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
155 (+) BreakCallback : TIM Break Callback.
156 (+) Break2Callback : TIM Break2 Callback.
157
158 [..]
159 By default, after the Init and when the state is HAL_TIM_STATE_RESET
160 all interrupt callbacks are set to the corresponding weak functions:
161 examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
162
163 [..]
164 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
165 functionalities in the Init / DeInit only when these callbacks are null
166 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
167 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
168
169 [..]
170 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
171 Exception done MspInit / MspDeInit that can be registered / unregistered
172 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
173 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
174 In that case first register the MspInit/MspDeInit user callbacks
175 using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
176
177 [..]
178 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
179 not defined, the callback registration feature is not available and all callbacks
180 are set to the corresponding weak functions.
181
182 @endverbatim
183 ******************************************************************************
184 */
185
186 /* Includes ------------------------------------------------------------------*/
187 #include "stm32mp1xx_hal.h"
188
189 /** @addtogroup STM32MP1xx_HAL_Driver
190 * @{
191 */
192
193 /** @defgroup TIM TIM
194 * @brief TIM HAL module driver
195 * @{
196 */
197
198 #ifdef HAL_TIM_MODULE_ENABLED
199
200 /* Private typedef -----------------------------------------------------------*/
201 /* Private define ------------------------------------------------------------*/
202 /* Private macro -------------------------------------------------------------*/
203 /* Private variables ---------------------------------------------------------*/
204 /* Private function prototypes -----------------------------------------------*/
205 /** @addtogroup TIM_Private_Functions
206 * @{
207 */
208 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
209 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
210 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
211 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
212 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
213 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
214 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
215 uint32_t TIM_ICFilter);
216 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
217 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
218 uint32_t TIM_ICFilter);
219 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
220 uint32_t TIM_ICFilter);
221 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
222 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
223 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
224 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
225 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
226 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
227 TIM_SlaveConfigTypeDef *sSlaveConfig);
228 /**
229 * @}
230 */
231 /* Exported functions --------------------------------------------------------*/
232
233 /** @defgroup TIM_Exported_Functions TIM Exported Functions
234 * @{
235 */
236
237 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
238 * @brief Time Base functions
239 *
240 @verbatim
241 ==============================================================================
242 ##### Time Base functions #####
243 ==============================================================================
244 [..]
245 This section provides functions allowing to:
246 (+) Initialize and configure the TIM base.
247 (+) De-initialize the TIM base.
248 (+) Start the Time Base.
249 (+) Stop the Time Base.
250 (+) Start the Time Base and enable interrupt.
251 (+) Stop the Time Base and disable interrupt.
252 (+) Start the Time Base and enable DMA transfer.
253 (+) Stop the Time Base and disable DMA transfer.
254
255 @endverbatim
256 * @{
257 */
258 /**
259 * @brief Initializes the TIM Time base Unit according to the specified
260 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
261 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
262 * requires a timer reset to avoid unexpected direction
263 * due to DIR bit readonly in center aligned mode.
264 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
265 * @param htim TIM Base handle
266 * @retval HAL status
267 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)268 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
269 {
270 /* Check the TIM handle allocation */
271 if (htim == NULL)
272 {
273 return HAL_ERROR;
274 }
275
276 /* Check the parameters */
277 assert_param(IS_TIM_INSTANCE(htim->Instance));
278 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
279 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
280 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
281
282 if (htim->State == HAL_TIM_STATE_RESET)
283 {
284 /* Allocate lock resource and initialize it */
285 htim->Lock = HAL_UNLOCKED;
286
287 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
288 /* Reset interrupt callbacks to legacy weak callbacks */
289 TIM_ResetCallback(htim);
290
291 if (htim->Base_MspInitCallback == NULL)
292 {
293 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
294 }
295 /* Init the low level hardware : GPIO, CLOCK, NVIC */
296 htim->Base_MspInitCallback(htim);
297 #else
298 /* Init the low level hardware : GPIO, CLOCK, NVIC */
299 HAL_TIM_Base_MspInit(htim);
300 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
301 }
302
303 /* Set the TIM state */
304 htim->State = HAL_TIM_STATE_BUSY;
305
306 /* Set the Time Base configuration */
307 TIM_Base_SetConfig(htim->Instance, &htim->Init);
308
309 /* Initialize the TIM state*/
310 htim->State = HAL_TIM_STATE_READY;
311
312 return HAL_OK;
313 }
314
315 /**
316 * @brief DeInitializes the TIM Base peripheral
317 * @param htim TIM Base handle
318 * @retval HAL status
319 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)320 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
321 {
322 /* Check the parameters */
323 assert_param(IS_TIM_INSTANCE(htim->Instance));
324
325 htim->State = HAL_TIM_STATE_BUSY;
326
327 /* Disable the TIM Peripheral Clock */
328 __HAL_TIM_DISABLE(htim);
329
330 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
331 if (htim->Base_MspDeInitCallback == NULL)
332 {
333 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
334 }
335 /* DeInit the low level hardware */
336 htim->Base_MspDeInitCallback(htim);
337 #else
338 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
339 HAL_TIM_Base_MspDeInit(htim);
340 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
341
342 /* Change TIM state */
343 htim->State = HAL_TIM_STATE_RESET;
344
345 /* Release Lock */
346 __HAL_UNLOCK(htim);
347
348 return HAL_OK;
349 }
350
351 /**
352 * @brief Initializes the TIM Base MSP.
353 * @param htim TIM Base handle
354 * @retval None
355 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)356 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
357 {
358 /* Prevent unused argument(s) compilation warning */
359 UNUSED(htim);
360
361 /* NOTE : This function should not be modified, when the callback is needed,
362 the HAL_TIM_Base_MspInit could be implemented in the user file
363 */
364 }
365
366 /**
367 * @brief DeInitializes TIM Base MSP.
368 * @param htim TIM Base handle
369 * @retval None
370 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)371 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
372 {
373 /* Prevent unused argument(s) compilation warning */
374 UNUSED(htim);
375
376 /* NOTE : This function should not be modified, when the callback is needed,
377 the HAL_TIM_Base_MspDeInit could be implemented in the user file
378 */
379 }
380
381
382 /**
383 * @brief Starts the TIM Base generation.
384 * @param htim TIM Base handle
385 * @retval HAL status
386 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)387 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
388 {
389 uint32_t tmpsmcr;
390
391 /* Check the parameters */
392 assert_param(IS_TIM_INSTANCE(htim->Instance));
393
394 /* Set the TIM state */
395 htim->State = HAL_TIM_STATE_BUSY;
396
397 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
398 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
399 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
400 {
401 __HAL_TIM_ENABLE(htim);
402 }
403
404 /* Change the TIM state*/
405 htim->State = HAL_TIM_STATE_READY;
406
407 /* Return function status */
408 return HAL_OK;
409 }
410
411 /**
412 * @brief Stops the TIM Base generation.
413 * @param htim TIM Base handle
414 * @retval HAL status
415 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)416 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
417 {
418 /* Check the parameters */
419 assert_param(IS_TIM_INSTANCE(htim->Instance));
420
421 /* Set the TIM state */
422 htim->State = HAL_TIM_STATE_BUSY;
423
424 /* Disable the Peripheral */
425 __HAL_TIM_DISABLE(htim);
426
427 /* Change the TIM state*/
428 htim->State = HAL_TIM_STATE_READY;
429
430 /* Return function status */
431 return HAL_OK;
432 }
433
434 /**
435 * @brief Starts the TIM Base generation in interrupt mode.
436 * @param htim TIM Base handle
437 * @retval HAL status
438 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)439 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
440 {
441 uint32_t tmpsmcr;
442
443 /* Check the parameters */
444 assert_param(IS_TIM_INSTANCE(htim->Instance));
445
446 /* Enable the TIM Update interrupt */
447 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
448
449 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
450 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
451 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
452 {
453 __HAL_TIM_ENABLE(htim);
454 }
455
456 /* Return function status */
457 return HAL_OK;
458 }
459
460 /**
461 * @brief Stops the TIM Base generation in interrupt mode.
462 * @param htim TIM Base handle
463 * @retval HAL status
464 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)465 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
466 {
467 /* Check the parameters */
468 assert_param(IS_TIM_INSTANCE(htim->Instance));
469 /* Disable the TIM Update interrupt */
470 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
471
472 /* Disable the Peripheral */
473 __HAL_TIM_DISABLE(htim);
474
475 /* Return function status */
476 return HAL_OK;
477 }
478
479 /**
480 * @brief Starts the TIM Base generation in DMA mode.
481 * @param htim TIM Base handle
482 * @param pData The source Buffer address.
483 * @param Length The length of data to be transferred from memory to peripheral.
484 * @retval HAL status
485 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)486 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
487 {
488 uint32_t tmpsmcr;
489
490 /* Check the parameters */
491 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
492
493 if (htim->State == HAL_TIM_STATE_BUSY)
494 {
495 return HAL_BUSY;
496 }
497 else if (htim->State == HAL_TIM_STATE_READY)
498 {
499 if ((pData == NULL) && (Length > 0U))
500 {
501 return HAL_ERROR;
502 }
503 else
504 {
505 htim->State = HAL_TIM_STATE_BUSY;
506 }
507 }
508 else
509 {
510 /* nothing to do */
511 }
512
513 /* Set the DMA Period elapsed callbacks */
514 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
515 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
516
517 /* Set the DMA error callback */
518 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
519
520 /* Enable the DMA channel */
521 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
522 {
523 return HAL_ERROR;
524 }
525
526 /* Enable the TIM Update DMA request */
527 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
528
529 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
530 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
531 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
532 {
533 __HAL_TIM_ENABLE(htim);
534 }
535
536 /* Return function status */
537 return HAL_OK;
538 }
539
540 /**
541 * @brief Stops the TIM Base generation in DMA mode.
542 * @param htim TIM Base handle
543 * @retval HAL status
544 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)545 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
546 {
547 /* Check the parameters */
548 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
549
550 /* Disable the TIM Update DMA request */
551 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
552
553 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
554
555 /* Disable the Peripheral */
556 __HAL_TIM_DISABLE(htim);
557
558 /* Change the htim state */
559 htim->State = HAL_TIM_STATE_READY;
560
561 /* Return function status */
562 return HAL_OK;
563 }
564
565 /**
566 * @}
567 */
568
569 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
570 * @brief TIM Output Compare functions
571 *
572 @verbatim
573 ==============================================================================
574 ##### TIM Output Compare functions #####
575 ==============================================================================
576 [..]
577 This section provides functions allowing to:
578 (+) Initialize and configure the TIM Output Compare.
579 (+) De-initialize the TIM Output Compare.
580 (+) Start the TIM Output Compare.
581 (+) Stop the TIM Output Compare.
582 (+) Start the TIM Output Compare and enable interrupt.
583 (+) Stop the TIM Output Compare and disable interrupt.
584 (+) Start the TIM Output Compare and enable DMA transfer.
585 (+) Stop the TIM Output Compare and disable DMA transfer.
586
587 @endverbatim
588 * @{
589 */
590 /**
591 * @brief Initializes the TIM Output Compare according to the specified
592 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
593 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
594 * requires a timer reset to avoid unexpected direction
595 * due to DIR bit readonly in center aligned mode.
596 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
597 * @param htim TIM Output Compare handle
598 * @retval HAL status
599 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)600 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
601 {
602 /* Check the TIM handle allocation */
603 if (htim == NULL)
604 {
605 return HAL_ERROR;
606 }
607
608 /* Check the parameters */
609 assert_param(IS_TIM_INSTANCE(htim->Instance));
610 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
611 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
612 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
613
614 if (htim->State == HAL_TIM_STATE_RESET)
615 {
616 /* Allocate lock resource and initialize it */
617 htim->Lock = HAL_UNLOCKED;
618
619 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
620 /* Reset interrupt callbacks to legacy weak callbacks */
621 TIM_ResetCallback(htim);
622
623 if (htim->OC_MspInitCallback == NULL)
624 {
625 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
626 }
627 /* Init the low level hardware : GPIO, CLOCK, NVIC */
628 htim->OC_MspInitCallback(htim);
629 #else
630 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
631 HAL_TIM_OC_MspInit(htim);
632 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
633 }
634
635 /* Set the TIM state */
636 htim->State = HAL_TIM_STATE_BUSY;
637
638 /* Init the base time for the Output Compare */
639 TIM_Base_SetConfig(htim->Instance, &htim->Init);
640
641 /* Initialize the TIM state*/
642 htim->State = HAL_TIM_STATE_READY;
643
644 return HAL_OK;
645 }
646
647 /**
648 * @brief DeInitializes the TIM peripheral
649 * @param htim TIM Output Compare handle
650 * @retval HAL status
651 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)652 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
653 {
654 /* Check the parameters */
655 assert_param(IS_TIM_INSTANCE(htim->Instance));
656
657 htim->State = HAL_TIM_STATE_BUSY;
658
659 /* Disable the TIM Peripheral Clock */
660 __HAL_TIM_DISABLE(htim);
661
662 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
663 if (htim->OC_MspDeInitCallback == NULL)
664 {
665 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
666 }
667 /* DeInit the low level hardware */
668 htim->OC_MspDeInitCallback(htim);
669 #else
670 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
671 HAL_TIM_OC_MspDeInit(htim);
672 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
673
674 /* Change TIM state */
675 htim->State = HAL_TIM_STATE_RESET;
676
677 /* Release Lock */
678 __HAL_UNLOCK(htim);
679
680 return HAL_OK;
681 }
682
683 /**
684 * @brief Initializes the TIM Output Compare MSP.
685 * @param htim TIM Output Compare handle
686 * @retval None
687 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)688 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
689 {
690 /* Prevent unused argument(s) compilation warning */
691 UNUSED(htim);
692
693 /* NOTE : This function should not be modified, when the callback is needed,
694 the HAL_TIM_OC_MspInit could be implemented in the user file
695 */
696 }
697
698 /**
699 * @brief DeInitializes TIM Output Compare MSP.
700 * @param htim TIM Output Compare handle
701 * @retval None
702 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)703 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
704 {
705 /* Prevent unused argument(s) compilation warning */
706 UNUSED(htim);
707
708 /* NOTE : This function should not be modified, when the callback is needed,
709 the HAL_TIM_OC_MspDeInit could be implemented in the user file
710 */
711 }
712
713 /**
714 * @brief Starts the TIM Output Compare signal generation.
715 * @param htim TIM Output Compare handle
716 * @param Channel TIM Channel to be enabled
717 * This parameter can be one of the following values:
718 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
719 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
720 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
721 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
722 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
723 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
724 * @retval HAL status
725 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)726 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
727 {
728 uint32_t tmpsmcr;
729
730 /* Check the parameters */
731 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
732
733 /* Enable the Output compare channel */
734 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
735
736 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
737 {
738 /* Enable the main output */
739 __HAL_TIM_MOE_ENABLE(htim);
740 }
741
742 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
743 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
744 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
745 {
746 __HAL_TIM_ENABLE(htim);
747 }
748
749 /* Return function status */
750 return HAL_OK;
751 }
752
753 /**
754 * @brief Stops the TIM Output Compare signal generation.
755 * @param htim TIM Output Compare handle
756 * @param Channel TIM Channel to be disabled
757 * This parameter can be one of the following values:
758 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
759 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
760 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
761 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
762 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
763 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
764 * @retval HAL status
765 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)766 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
767 {
768 /* Check the parameters */
769 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
770
771 /* Disable the Output compare channel */
772 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
773
774 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
775 {
776 /* Disable the Main Output */
777 __HAL_TIM_MOE_DISABLE(htim);
778 }
779
780 /* Disable the Peripheral */
781 __HAL_TIM_DISABLE(htim);
782
783 /* Return function status */
784 return HAL_OK;
785 }
786
787 /**
788 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
789 * @param htim TIM Output Compare handle
790 * @param Channel TIM Channel to be enabled
791 * This parameter can be one of the following values:
792 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
793 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
794 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
795 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
796 * @retval HAL status
797 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)798 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
799 {
800 uint32_t tmpsmcr;
801
802 /* Check the parameters */
803 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
804
805 switch (Channel)
806 {
807 case TIM_CHANNEL_1:
808 {
809 /* Enable the TIM Capture/Compare 1 interrupt */
810 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
811 break;
812 }
813
814 case TIM_CHANNEL_2:
815 {
816 /* Enable the TIM Capture/Compare 2 interrupt */
817 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
818 break;
819 }
820
821 case TIM_CHANNEL_3:
822 {
823 /* Enable the TIM Capture/Compare 3 interrupt */
824 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
825 break;
826 }
827
828 case TIM_CHANNEL_4:
829 {
830 /* Enable the TIM Capture/Compare 4 interrupt */
831 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
832 break;
833 }
834
835 default:
836 break;
837 }
838
839 /* Enable the Output compare channel */
840 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
841
842 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
843 {
844 /* Enable the main output */
845 __HAL_TIM_MOE_ENABLE(htim);
846 }
847
848 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
849 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
850 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
851 {
852 __HAL_TIM_ENABLE(htim);
853 }
854
855 /* Return function status */
856 return HAL_OK;
857 }
858
859 /**
860 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
861 * @param htim TIM Output Compare handle
862 * @param Channel TIM Channel to be disabled
863 * This parameter can be one of the following values:
864 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
865 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
866 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
867 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
868 * @retval HAL status
869 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)870 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
871 {
872 /* Check the parameters */
873 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
874
875 switch (Channel)
876 {
877 case TIM_CHANNEL_1:
878 {
879 /* Disable the TIM Capture/Compare 1 interrupt */
880 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
881 break;
882 }
883
884 case TIM_CHANNEL_2:
885 {
886 /* Disable the TIM Capture/Compare 2 interrupt */
887 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
888 break;
889 }
890
891 case TIM_CHANNEL_3:
892 {
893 /* Disable the TIM Capture/Compare 3 interrupt */
894 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
895 break;
896 }
897
898 case TIM_CHANNEL_4:
899 {
900 /* Disable the TIM Capture/Compare 4 interrupt */
901 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
902 break;
903 }
904
905 default:
906 break;
907 }
908
909 /* Disable the Output compare channel */
910 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
911
912 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
913 {
914 /* Disable the Main Output */
915 __HAL_TIM_MOE_DISABLE(htim);
916 }
917
918 /* Disable the Peripheral */
919 __HAL_TIM_DISABLE(htim);
920
921 /* Return function status */
922 return HAL_OK;
923 }
924
925 /**
926 * @brief Starts the TIM Output Compare signal generation in DMA mode.
927 * @param htim TIM Output Compare handle
928 * @param Channel TIM Channel to be enabled
929 * This parameter can be one of the following values:
930 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
931 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
932 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
933 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
934 * @param pData The source Buffer address.
935 * @param Length The length of data to be transferred from memory to TIM peripheral
936 * @retval HAL status
937 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)938 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
939 {
940 uint32_t tmpsmcr;
941
942 /* Check the parameters */
943 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
944
945 if (htim->State == HAL_TIM_STATE_BUSY)
946 {
947 return HAL_BUSY;
948 }
949 else if (htim->State == HAL_TIM_STATE_READY)
950 {
951 if ((pData == NULL) && (Length > 0U))
952 {
953 return HAL_ERROR;
954 }
955 else
956 {
957 htim->State = HAL_TIM_STATE_BUSY;
958 }
959 }
960 else
961 {
962 /* nothing to do */
963 }
964
965 switch (Channel)
966 {
967 case TIM_CHANNEL_1:
968 {
969 /* Set the DMA compare callbacks */
970 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
971 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
972
973 /* Set the DMA error callback */
974 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
975
976 /* Enable the DMA channel */
977 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
978 {
979 return HAL_ERROR;
980 }
981
982 /* Enable the TIM Capture/Compare 1 DMA request */
983 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
984 break;
985 }
986
987 case TIM_CHANNEL_2:
988 {
989 /* Set the DMA compare callbacks */
990 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
991 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
992
993 /* Set the DMA error callback */
994 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
995
996 /* Enable the DMA channel */
997 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
998 {
999 return HAL_ERROR;
1000 }
1001
1002 /* Enable the TIM Capture/Compare 2 DMA request */
1003 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1004 break;
1005 }
1006
1007 case TIM_CHANNEL_3:
1008 {
1009 /* Set the DMA compare callbacks */
1010 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1011 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1012
1013 /* Set the DMA error callback */
1014 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1015
1016 /* Enable the DMA channel */
1017 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
1018 {
1019 return HAL_ERROR;
1020 }
1021 /* Enable the TIM Capture/Compare 3 DMA request */
1022 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1023 break;
1024 }
1025
1026 case TIM_CHANNEL_4:
1027 {
1028 /* Set the DMA compare callbacks */
1029 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1030 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1031
1032 /* Set the DMA error callback */
1033 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1034
1035 /* Enable the DMA channel */
1036 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
1037 {
1038 return HAL_ERROR;
1039 }
1040 /* Enable the TIM Capture/Compare 4 DMA request */
1041 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1042 break;
1043 }
1044
1045 default:
1046 break;
1047 }
1048
1049 /* Enable the Output compare channel */
1050 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1051
1052 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1053 {
1054 /* Enable the main output */
1055 __HAL_TIM_MOE_ENABLE(htim);
1056 }
1057
1058 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1059 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1060 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1061 {
1062 __HAL_TIM_ENABLE(htim);
1063 }
1064
1065 /* Return function status */
1066 return HAL_OK;
1067 }
1068
1069 /**
1070 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1071 * @param htim TIM Output Compare handle
1072 * @param Channel TIM Channel to be disabled
1073 * This parameter can be one of the following values:
1074 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1075 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1076 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1077 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1078 * @retval HAL status
1079 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1080 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1081 {
1082 /* Check the parameters */
1083 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1084
1085 switch (Channel)
1086 {
1087 case TIM_CHANNEL_1:
1088 {
1089 /* Disable the TIM Capture/Compare 1 DMA request */
1090 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1091 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1092 break;
1093 }
1094
1095 case TIM_CHANNEL_2:
1096 {
1097 /* Disable the TIM Capture/Compare 2 DMA request */
1098 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1099 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1100 break;
1101 }
1102
1103 case TIM_CHANNEL_3:
1104 {
1105 /* Disable the TIM Capture/Compare 3 DMA request */
1106 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1107 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1108 break;
1109 }
1110
1111 case TIM_CHANNEL_4:
1112 {
1113 /* Disable the TIM Capture/Compare 4 interrupt */
1114 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1115 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1116 break;
1117 }
1118
1119 default:
1120 break;
1121 }
1122
1123 /* Disable the Output compare channel */
1124 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1125
1126 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1127 {
1128 /* Disable the Main Output */
1129 __HAL_TIM_MOE_DISABLE(htim);
1130 }
1131
1132 /* Disable the Peripheral */
1133 __HAL_TIM_DISABLE(htim);
1134
1135 /* Change the htim state */
1136 htim->State = HAL_TIM_STATE_READY;
1137
1138 /* Return function status */
1139 return HAL_OK;
1140 }
1141
1142 /**
1143 * @}
1144 */
1145
1146 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1147 * @brief TIM PWM functions
1148 *
1149 @verbatim
1150 ==============================================================================
1151 ##### TIM PWM functions #####
1152 ==============================================================================
1153 [..]
1154 This section provides functions allowing to:
1155 (+) Initialize and configure the TIM PWM.
1156 (+) De-initialize the TIM PWM.
1157 (+) Start the TIM PWM.
1158 (+) Stop the TIM PWM.
1159 (+) Start the TIM PWM and enable interrupt.
1160 (+) Stop the TIM PWM and disable interrupt.
1161 (+) Start the TIM PWM and enable DMA transfer.
1162 (+) Stop the TIM PWM and disable DMA transfer.
1163
1164 @endverbatim
1165 * @{
1166 */
1167 /**
1168 * @brief Initializes the TIM PWM Time Base according to the specified
1169 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1170 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1171 * requires a timer reset to avoid unexpected direction
1172 * due to DIR bit readonly in center aligned mode.
1173 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1174 * @param htim TIM PWM handle
1175 * @retval HAL status
1176 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1177 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1178 {
1179 /* Check the TIM handle allocation */
1180 if (htim == NULL)
1181 {
1182 return HAL_ERROR;
1183 }
1184
1185 /* Check the parameters */
1186 assert_param(IS_TIM_INSTANCE(htim->Instance));
1187 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1188 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1189 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1190
1191 if (htim->State == HAL_TIM_STATE_RESET)
1192 {
1193 /* Allocate lock resource and initialize it */
1194 htim->Lock = HAL_UNLOCKED;
1195
1196 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1197 /* Reset interrupt callbacks to legacy weak callbacks */
1198 TIM_ResetCallback(htim);
1199
1200 if (htim->PWM_MspInitCallback == NULL)
1201 {
1202 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1203 }
1204 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1205 htim->PWM_MspInitCallback(htim);
1206 #else
1207 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1208 HAL_TIM_PWM_MspInit(htim);
1209 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1210 }
1211
1212 /* Set the TIM state */
1213 htim->State = HAL_TIM_STATE_BUSY;
1214
1215 /* Init the base time for the PWM */
1216 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1217
1218 /* Initialize the TIM state*/
1219 htim->State = HAL_TIM_STATE_READY;
1220
1221 return HAL_OK;
1222 }
1223
1224 /**
1225 * @brief DeInitializes the TIM peripheral
1226 * @param htim TIM PWM handle
1227 * @retval HAL status
1228 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1229 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1230 {
1231 /* Check the parameters */
1232 assert_param(IS_TIM_INSTANCE(htim->Instance));
1233
1234 htim->State = HAL_TIM_STATE_BUSY;
1235
1236 /* Disable the TIM Peripheral Clock */
1237 __HAL_TIM_DISABLE(htim);
1238
1239 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1240 if (htim->PWM_MspDeInitCallback == NULL)
1241 {
1242 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1243 }
1244 /* DeInit the low level hardware */
1245 htim->PWM_MspDeInitCallback(htim);
1246 #else
1247 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1248 HAL_TIM_PWM_MspDeInit(htim);
1249 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1250
1251 /* Change TIM state */
1252 htim->State = HAL_TIM_STATE_RESET;
1253
1254 /* Release Lock */
1255 __HAL_UNLOCK(htim);
1256
1257 return HAL_OK;
1258 }
1259
1260 /**
1261 * @brief Initializes the TIM PWM MSP.
1262 * @param htim TIM PWM handle
1263 * @retval None
1264 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1265 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1266 {
1267 /* Prevent unused argument(s) compilation warning */
1268 UNUSED(htim);
1269
1270 /* NOTE : This function should not be modified, when the callback is needed,
1271 the HAL_TIM_PWM_MspInit could be implemented in the user file
1272 */
1273 }
1274
1275 /**
1276 * @brief DeInitializes TIM PWM MSP.
1277 * @param htim TIM PWM handle
1278 * @retval None
1279 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1280 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1281 {
1282 /* Prevent unused argument(s) compilation warning */
1283 UNUSED(htim);
1284
1285 /* NOTE : This function should not be modified, when the callback is needed,
1286 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1287 */
1288 }
1289
1290 /**
1291 * @brief Starts the PWM signal generation.
1292 * @param htim TIM handle
1293 * @param Channel TIM Channels to be enabled
1294 * This parameter can be one of the following values:
1295 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1296 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1297 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1298 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1299 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1300 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1301 * @retval HAL status
1302 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1303 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1304 {
1305 uint32_t tmpsmcr;
1306
1307 /* Check the parameters */
1308 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1309
1310 /* Enable the Capture compare channel */
1311 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1312
1313 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1314 {
1315 /* Enable the main output */
1316 __HAL_TIM_MOE_ENABLE(htim);
1317 }
1318
1319 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1320 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1321 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1322 {
1323 __HAL_TIM_ENABLE(htim);
1324 }
1325
1326 /* Return function status */
1327 return HAL_OK;
1328 }
1329
1330 /**
1331 * @brief Stops the PWM signal generation.
1332 * @param htim TIM PWM handle
1333 * @param Channel TIM Channels to be disabled
1334 * This parameter can be one of the following values:
1335 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1336 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1337 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1338 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1339 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1340 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1341 * @retval HAL status
1342 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1343 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1344 {
1345 /* Check the parameters */
1346 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1347
1348 /* Disable the Capture compare channel */
1349 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1350
1351 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1352 {
1353 /* Disable the Main Output */
1354 __HAL_TIM_MOE_DISABLE(htim);
1355 }
1356
1357 /* Disable the Peripheral */
1358 __HAL_TIM_DISABLE(htim);
1359
1360 /* Change the htim state */
1361 htim->State = HAL_TIM_STATE_READY;
1362
1363 /* Return function status */
1364 return HAL_OK;
1365 }
1366
1367 /**
1368 * @brief Starts the PWM signal generation in interrupt mode.
1369 * @param htim TIM PWM handle
1370 * @param Channel TIM Channel to be enabled
1371 * This parameter can be one of the following values:
1372 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1373 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1374 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1375 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1376 * @retval HAL status
1377 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1378 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1379 {
1380 uint32_t tmpsmcr;
1381 /* Check the parameters */
1382 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1383
1384 switch (Channel)
1385 {
1386 case TIM_CHANNEL_1:
1387 {
1388 /* Enable the TIM Capture/Compare 1 interrupt */
1389 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1390 break;
1391 }
1392
1393 case TIM_CHANNEL_2:
1394 {
1395 /* Enable the TIM Capture/Compare 2 interrupt */
1396 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1397 break;
1398 }
1399
1400 case TIM_CHANNEL_3:
1401 {
1402 /* Enable the TIM Capture/Compare 3 interrupt */
1403 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1404 break;
1405 }
1406
1407 case TIM_CHANNEL_4:
1408 {
1409 /* Enable the TIM Capture/Compare 4 interrupt */
1410 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1411 break;
1412 }
1413
1414 default:
1415 break;
1416 }
1417
1418 /* Enable the Capture compare channel */
1419 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1420
1421 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1422 {
1423 /* Enable the main output */
1424 __HAL_TIM_MOE_ENABLE(htim);
1425 }
1426
1427 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1428 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1429 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1430 {
1431 __HAL_TIM_ENABLE(htim);
1432 }
1433
1434 /* Return function status */
1435 return HAL_OK;
1436 }
1437
1438 /**
1439 * @brief Stops the PWM signal generation in interrupt mode.
1440 * @param htim TIM PWM handle
1441 * @param Channel TIM Channels to be disabled
1442 * This parameter can be one of the following values:
1443 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1444 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1445 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1446 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1447 * @retval HAL status
1448 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1449 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1450 {
1451 /* Check the parameters */
1452 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1453
1454 switch (Channel)
1455 {
1456 case TIM_CHANNEL_1:
1457 {
1458 /* Disable the TIM Capture/Compare 1 interrupt */
1459 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1460 break;
1461 }
1462
1463 case TIM_CHANNEL_2:
1464 {
1465 /* Disable the TIM Capture/Compare 2 interrupt */
1466 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1467 break;
1468 }
1469
1470 case TIM_CHANNEL_3:
1471 {
1472 /* Disable the TIM Capture/Compare 3 interrupt */
1473 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1474 break;
1475 }
1476
1477 case TIM_CHANNEL_4:
1478 {
1479 /* Disable the TIM Capture/Compare 4 interrupt */
1480 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1481 break;
1482 }
1483
1484 default:
1485 break;
1486 }
1487
1488 /* Disable the Capture compare channel */
1489 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1490
1491 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1492 {
1493 /* Disable the Main Output */
1494 __HAL_TIM_MOE_DISABLE(htim);
1495 }
1496
1497 /* Disable the Peripheral */
1498 __HAL_TIM_DISABLE(htim);
1499
1500 /* Return function status */
1501 return HAL_OK;
1502 }
1503
1504 /**
1505 * @brief Starts the TIM PWM signal generation in DMA mode.
1506 * @param htim TIM PWM handle
1507 * @param Channel TIM Channels to be enabled
1508 * This parameter can be one of the following values:
1509 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1510 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1511 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1512 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1513 * @param pData The source Buffer address.
1514 * @param Length The length of data to be transferred from memory to TIM peripheral
1515 * @retval HAL status
1516 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)1517 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1518 {
1519 uint32_t tmpsmcr;
1520
1521 /* Check the parameters */
1522 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1523
1524 if (htim->State == HAL_TIM_STATE_BUSY)
1525 {
1526 return HAL_BUSY;
1527 }
1528 else if (htim->State == HAL_TIM_STATE_READY)
1529 {
1530 if ((pData == NULL) && (Length > 0U))
1531 {
1532 return HAL_ERROR;
1533 }
1534 else
1535 {
1536 htim->State = HAL_TIM_STATE_BUSY;
1537 }
1538 }
1539 else
1540 {
1541 /* nothing to do */
1542 }
1543
1544 switch (Channel)
1545 {
1546 case TIM_CHANNEL_1:
1547 {
1548 /* Set the DMA compare callbacks */
1549 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1550 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1551
1552 /* Set the DMA error callback */
1553 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1554
1555 /* Enable the DMA channel */
1556 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
1557 {
1558 return HAL_ERROR;
1559 }
1560
1561 /* Enable the TIM Capture/Compare 1 DMA request */
1562 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1563 break;
1564 }
1565
1566 case TIM_CHANNEL_2:
1567 {
1568 /* Set the DMA compare callbacks */
1569 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1570 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1571
1572 /* Set the DMA error callback */
1573 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1574
1575 /* Enable the DMA channel */
1576 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
1577 {
1578 return HAL_ERROR;
1579 }
1580 /* Enable the TIM Capture/Compare 2 DMA request */
1581 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1582 break;
1583 }
1584
1585 case TIM_CHANNEL_3:
1586 {
1587 /* Set the DMA compare callbacks */
1588 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1589 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1590
1591 /* Set the DMA error callback */
1592 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1593
1594 /* Enable the DMA channel */
1595 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
1596 {
1597 return HAL_ERROR;
1598 }
1599 /* Enable the TIM Output Capture/Compare 3 request */
1600 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1601 break;
1602 }
1603
1604 case TIM_CHANNEL_4:
1605 {
1606 /* Set the DMA compare callbacks */
1607 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1608 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1609
1610 /* Set the DMA error callback */
1611 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1612
1613 /* Enable the DMA channel */
1614 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
1615 {
1616 return HAL_ERROR;
1617 }
1618 /* Enable the TIM Capture/Compare 4 DMA request */
1619 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1620 break;
1621 }
1622
1623 default:
1624 break;
1625 }
1626
1627 /* Enable the Capture compare channel */
1628 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1629
1630 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1631 {
1632 /* Enable the main output */
1633 __HAL_TIM_MOE_ENABLE(htim);
1634 }
1635
1636 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1637 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1638 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1639 {
1640 __HAL_TIM_ENABLE(htim);
1641 }
1642
1643 /* Return function status */
1644 return HAL_OK;
1645 }
1646
1647 /**
1648 * @brief Stops the TIM PWM signal generation in DMA mode.
1649 * @param htim TIM PWM handle
1650 * @param Channel TIM Channels to be disabled
1651 * This parameter can be one of the following values:
1652 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1653 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1654 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1655 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1656 * @retval HAL status
1657 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1658 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1659 {
1660 /* Check the parameters */
1661 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1662
1663 switch (Channel)
1664 {
1665 case TIM_CHANNEL_1:
1666 {
1667 /* Disable the TIM Capture/Compare 1 DMA request */
1668 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1669 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1670 break;
1671 }
1672
1673 case TIM_CHANNEL_2:
1674 {
1675 /* Disable the TIM Capture/Compare 2 DMA request */
1676 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1677 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1678 break;
1679 }
1680
1681 case TIM_CHANNEL_3:
1682 {
1683 /* Disable the TIM Capture/Compare 3 DMA request */
1684 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1685 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1686 break;
1687 }
1688
1689 case TIM_CHANNEL_4:
1690 {
1691 /* Disable the TIM Capture/Compare 4 interrupt */
1692 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1693 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1694 break;
1695 }
1696
1697 default:
1698 break;
1699 }
1700
1701 /* Disable the Capture compare channel */
1702 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1703
1704 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1705 {
1706 /* Disable the Main Output */
1707 __HAL_TIM_MOE_DISABLE(htim);
1708 }
1709
1710 /* Disable the Peripheral */
1711 __HAL_TIM_DISABLE(htim);
1712
1713 /* Change the htim state */
1714 htim->State = HAL_TIM_STATE_READY;
1715
1716 /* Return function status */
1717 return HAL_OK;
1718 }
1719
1720 /**
1721 * @}
1722 */
1723
1724 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1725 * @brief TIM Input Capture functions
1726 *
1727 @verbatim
1728 ==============================================================================
1729 ##### TIM Input Capture functions #####
1730 ==============================================================================
1731 [..]
1732 This section provides functions allowing to:
1733 (+) Initialize and configure the TIM Input Capture.
1734 (+) De-initialize the TIM Input Capture.
1735 (+) Start the TIM Input Capture.
1736 (+) Stop the TIM Input Capture.
1737 (+) Start the TIM Input Capture and enable interrupt.
1738 (+) Stop the TIM Input Capture and disable interrupt.
1739 (+) Start the TIM Input Capture and enable DMA transfer.
1740 (+) Stop the TIM Input Capture and disable DMA transfer.
1741
1742 @endverbatim
1743 * @{
1744 */
1745 /**
1746 * @brief Initializes the TIM Input Capture Time base according to the specified
1747 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1748 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1749 * requires a timer reset to avoid unexpected direction
1750 * due to DIR bit readonly in center aligned mode.
1751 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1752 * @param htim TIM Input Capture handle
1753 * @retval HAL status
1754 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)1755 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1756 {
1757 /* Check the TIM handle allocation */
1758 if (htim == NULL)
1759 {
1760 return HAL_ERROR;
1761 }
1762
1763 /* Check the parameters */
1764 assert_param(IS_TIM_INSTANCE(htim->Instance));
1765 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1766 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1767 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1768
1769 if (htim->State == HAL_TIM_STATE_RESET)
1770 {
1771 /* Allocate lock resource and initialize it */
1772 htim->Lock = HAL_UNLOCKED;
1773
1774 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1775 /* Reset interrupt callbacks to legacy weak callbacks */
1776 TIM_ResetCallback(htim);
1777
1778 if (htim->IC_MspInitCallback == NULL)
1779 {
1780 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
1781 }
1782 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1783 htim->IC_MspInitCallback(htim);
1784 #else
1785 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1786 HAL_TIM_IC_MspInit(htim);
1787 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1788 }
1789
1790 /* Set the TIM state */
1791 htim->State = HAL_TIM_STATE_BUSY;
1792
1793 /* Init the base time for the input capture */
1794 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1795
1796 /* Initialize the TIM state*/
1797 htim->State = HAL_TIM_STATE_READY;
1798
1799 return HAL_OK;
1800 }
1801
1802 /**
1803 * @brief DeInitializes the TIM peripheral
1804 * @param htim TIM Input Capture handle
1805 * @retval HAL status
1806 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)1807 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1808 {
1809 /* Check the parameters */
1810 assert_param(IS_TIM_INSTANCE(htim->Instance));
1811
1812 htim->State = HAL_TIM_STATE_BUSY;
1813
1814 /* Disable the TIM Peripheral Clock */
1815 __HAL_TIM_DISABLE(htim);
1816
1817 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1818 if (htim->IC_MspDeInitCallback == NULL)
1819 {
1820 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
1821 }
1822 /* DeInit the low level hardware */
1823 htim->IC_MspDeInitCallback(htim);
1824 #else
1825 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1826 HAL_TIM_IC_MspDeInit(htim);
1827 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1828
1829 /* Change TIM state */
1830 htim->State = HAL_TIM_STATE_RESET;
1831
1832 /* Release Lock */
1833 __HAL_UNLOCK(htim);
1834
1835 return HAL_OK;
1836 }
1837
1838 /**
1839 * @brief Initializes the TIM Input Capture MSP.
1840 * @param htim TIM Input Capture handle
1841 * @retval None
1842 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)1843 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
1844 {
1845 /* Prevent unused argument(s) compilation warning */
1846 UNUSED(htim);
1847
1848 /* NOTE : This function should not be modified, when the callback is needed,
1849 the HAL_TIM_IC_MspInit could be implemented in the user file
1850 */
1851 }
1852
1853 /**
1854 * @brief DeInitializes TIM Input Capture MSP.
1855 * @param htim TIM handle
1856 * @retval None
1857 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)1858 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
1859 {
1860 /* Prevent unused argument(s) compilation warning */
1861 UNUSED(htim);
1862
1863 /* NOTE : This function should not be modified, when the callback is needed,
1864 the HAL_TIM_IC_MspDeInit could be implemented in the user file
1865 */
1866 }
1867
1868 /**
1869 * @brief Starts the TIM Input Capture measurement.
1870 * @param htim TIM Input Capture handle
1871 * @param Channel TIM Channels to be enabled
1872 * This parameter can be one of the following values:
1873 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1874 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1875 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1876 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1877 * @retval HAL status
1878 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1879 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1880 {
1881 uint32_t tmpsmcr;
1882
1883 /* Check the parameters */
1884 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1885
1886 /* Enable the Input Capture channel */
1887 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1888
1889 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1890 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1891 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1892 {
1893 __HAL_TIM_ENABLE(htim);
1894 }
1895
1896 /* Return function status */
1897 return HAL_OK;
1898 }
1899
1900 /**
1901 * @brief Stops the TIM Input Capture measurement.
1902 * @param htim TIM Input Capture handle
1903 * @param Channel TIM Channels to be disabled
1904 * This parameter can be one of the following values:
1905 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1906 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1907 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1908 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1909 * @retval HAL status
1910 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1911 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1912 {
1913 /* Check the parameters */
1914 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1915
1916 /* Disable the Input Capture channel */
1917 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1918
1919 /* Disable the Peripheral */
1920 __HAL_TIM_DISABLE(htim);
1921
1922 /* Return function status */
1923 return HAL_OK;
1924 }
1925
1926 /**
1927 * @brief Starts the TIM Input Capture measurement in interrupt mode.
1928 * @param htim TIM Input Capture handle
1929 * @param Channel TIM Channels to be enabled
1930 * This parameter can be one of the following values:
1931 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1932 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1933 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1934 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1935 * @retval HAL status
1936 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1937 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1938 {
1939 uint32_t tmpsmcr;
1940
1941 /* Check the parameters */
1942 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1943
1944 switch (Channel)
1945 {
1946 case TIM_CHANNEL_1:
1947 {
1948 /* Enable the TIM Capture/Compare 1 interrupt */
1949 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1950 break;
1951 }
1952
1953 case TIM_CHANNEL_2:
1954 {
1955 /* Enable the TIM Capture/Compare 2 interrupt */
1956 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1957 break;
1958 }
1959
1960 case TIM_CHANNEL_3:
1961 {
1962 /* Enable the TIM Capture/Compare 3 interrupt */
1963 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1964 break;
1965 }
1966
1967 case TIM_CHANNEL_4:
1968 {
1969 /* Enable the TIM Capture/Compare 4 interrupt */
1970 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1971 break;
1972 }
1973
1974 default:
1975 break;
1976 }
1977 /* Enable the Input Capture channel */
1978 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1979
1980 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1981 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1982 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1983 {
1984 __HAL_TIM_ENABLE(htim);
1985 }
1986
1987 /* Return function status */
1988 return HAL_OK;
1989 }
1990
1991 /**
1992 * @brief Stops the TIM Input Capture measurement in interrupt mode.
1993 * @param htim TIM Input Capture handle
1994 * @param Channel TIM Channels to be disabled
1995 * This parameter can be one of the following values:
1996 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1997 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1998 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1999 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2000 * @retval HAL status
2001 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2002 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2003 {
2004 /* Check the parameters */
2005 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2006
2007 switch (Channel)
2008 {
2009 case TIM_CHANNEL_1:
2010 {
2011 /* Disable the TIM Capture/Compare 1 interrupt */
2012 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2013 break;
2014 }
2015
2016 case TIM_CHANNEL_2:
2017 {
2018 /* Disable the TIM Capture/Compare 2 interrupt */
2019 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2020 break;
2021 }
2022
2023 case TIM_CHANNEL_3:
2024 {
2025 /* Disable the TIM Capture/Compare 3 interrupt */
2026 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2027 break;
2028 }
2029
2030 case TIM_CHANNEL_4:
2031 {
2032 /* Disable the TIM Capture/Compare 4 interrupt */
2033 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2034 break;
2035 }
2036
2037 default:
2038 break;
2039 }
2040
2041 /* Disable the Input Capture channel */
2042 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2043
2044 /* Disable the Peripheral */
2045 __HAL_TIM_DISABLE(htim);
2046
2047 /* Return function status */
2048 return HAL_OK;
2049 }
2050
2051 /**
2052 * @brief Starts the TIM Input Capture measurement in DMA mode.
2053 * @param htim TIM Input Capture handle
2054 * @param Channel TIM Channels to be enabled
2055 * This parameter can be one of the following values:
2056 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2057 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2058 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2059 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2060 * @param pData The destination Buffer address.
2061 * @param Length The length of data to be transferred from TIM peripheral to memory.
2062 * @retval HAL status
2063 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2064 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2065 {
2066 uint32_t tmpsmcr;
2067
2068 /* Check the parameters */
2069 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2070 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2071
2072 if (htim->State == HAL_TIM_STATE_BUSY)
2073 {
2074 return HAL_BUSY;
2075 }
2076 else if (htim->State == HAL_TIM_STATE_READY)
2077 {
2078 if ((pData == NULL) && (Length > 0U))
2079 {
2080 return HAL_ERROR;
2081 }
2082 else
2083 {
2084 htim->State = HAL_TIM_STATE_BUSY;
2085 }
2086 }
2087 else
2088 {
2089 /* nothing to do */
2090 }
2091
2092 switch (Channel)
2093 {
2094 case TIM_CHANNEL_1:
2095 {
2096 /* Set the DMA capture callbacks */
2097 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2098 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2099
2100 /* Set the DMA error callback */
2101 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2102
2103 /* Enable the DMA channel */
2104 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
2105 {
2106 return HAL_ERROR;
2107 }
2108 /* Enable the TIM Capture/Compare 1 DMA request */
2109 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2110 break;
2111 }
2112
2113 case TIM_CHANNEL_2:
2114 {
2115 /* Set the DMA capture callbacks */
2116 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2117 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2118
2119 /* Set the DMA error callback */
2120 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2121
2122 /* Enable the DMA channel */
2123 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
2124 {
2125 return HAL_ERROR;
2126 }
2127 /* Enable the TIM Capture/Compare 2 DMA request */
2128 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2129 break;
2130 }
2131
2132 case TIM_CHANNEL_3:
2133 {
2134 /* Set the DMA capture callbacks */
2135 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2136 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2137
2138 /* Set the DMA error callback */
2139 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2140
2141 /* Enable the DMA channel */
2142 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
2143 {
2144 return HAL_ERROR;
2145 }
2146 /* Enable the TIM Capture/Compare 3 DMA request */
2147 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2148 break;
2149 }
2150
2151 case TIM_CHANNEL_4:
2152 {
2153 /* Set the DMA capture callbacks */
2154 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2155 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2156
2157 /* Set the DMA error callback */
2158 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2159
2160 /* Enable the DMA channel */
2161 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
2162 {
2163 return HAL_ERROR;
2164 }
2165 /* Enable the TIM Capture/Compare 4 DMA request */
2166 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2167 break;
2168 }
2169
2170 default:
2171 break;
2172 }
2173
2174 /* Enable the Input Capture channel */
2175 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2176
2177 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2178 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2179 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2180 {
2181 __HAL_TIM_ENABLE(htim);
2182 }
2183
2184 /* Return function status */
2185 return HAL_OK;
2186 }
2187
2188 /**
2189 * @brief Stops the TIM Input Capture measurement in DMA mode.
2190 * @param htim TIM Input Capture handle
2191 * @param Channel TIM Channels to be disabled
2192 * This parameter can be one of the following values:
2193 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2194 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2195 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2196 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2197 * @retval HAL status
2198 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2199 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2200 {
2201 /* Check the parameters */
2202 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2203 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2204
2205 switch (Channel)
2206 {
2207 case TIM_CHANNEL_1:
2208 {
2209 /* Disable the TIM Capture/Compare 1 DMA request */
2210 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2211 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2212 break;
2213 }
2214
2215 case TIM_CHANNEL_2:
2216 {
2217 /* Disable the TIM Capture/Compare 2 DMA request */
2218 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2219 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2220 break;
2221 }
2222
2223 case TIM_CHANNEL_3:
2224 {
2225 /* Disable the TIM Capture/Compare 3 DMA request */
2226 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2227 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2228 break;
2229 }
2230
2231 case TIM_CHANNEL_4:
2232 {
2233 /* Disable the TIM Capture/Compare 4 DMA request */
2234 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2235 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2236 break;
2237 }
2238
2239 default:
2240 break;
2241 }
2242
2243 /* Disable the Input Capture channel */
2244 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2245
2246 /* Disable the Peripheral */
2247 __HAL_TIM_DISABLE(htim);
2248
2249 /* Change the htim state */
2250 htim->State = HAL_TIM_STATE_READY;
2251
2252 /* Return function status */
2253 return HAL_OK;
2254 }
2255 /**
2256 * @}
2257 */
2258
2259 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2260 * @brief TIM One Pulse functions
2261 *
2262 @verbatim
2263 ==============================================================================
2264 ##### TIM One Pulse functions #####
2265 ==============================================================================
2266 [..]
2267 This section provides functions allowing to:
2268 (+) Initialize and configure the TIM One Pulse.
2269 (+) De-initialize the TIM One Pulse.
2270 (+) Start the TIM One Pulse.
2271 (+) Stop the TIM One Pulse.
2272 (+) Start the TIM One Pulse and enable interrupt.
2273 (+) Stop the TIM One Pulse and disable interrupt.
2274 (+) Start the TIM One Pulse and enable DMA transfer.
2275 (+) Stop the TIM One Pulse and disable DMA transfer.
2276
2277 @endverbatim
2278 * @{
2279 */
2280 /**
2281 * @brief Initializes the TIM One Pulse Time Base according to the specified
2282 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2283 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2284 * requires a timer reset to avoid unexpected direction
2285 * due to DIR bit readonly in center aligned mode.
2286 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2287 * @param htim TIM One Pulse handle
2288 * @param OnePulseMode Select the One pulse mode.
2289 * This parameter can be one of the following values:
2290 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2291 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2292 * @retval HAL status
2293 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2294 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2295 {
2296 /* Check the TIM handle allocation */
2297 if (htim == NULL)
2298 {
2299 return HAL_ERROR;
2300 }
2301
2302 /* Check the parameters */
2303 assert_param(IS_TIM_INSTANCE(htim->Instance));
2304 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2305 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2306 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2307 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2308
2309 if (htim->State == HAL_TIM_STATE_RESET)
2310 {
2311 /* Allocate lock resource and initialize it */
2312 htim->Lock = HAL_UNLOCKED;
2313
2314 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2315 /* Reset interrupt callbacks to legacy weak callbacks */
2316 TIM_ResetCallback(htim);
2317
2318 if (htim->OnePulse_MspInitCallback == NULL)
2319 {
2320 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2321 }
2322 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2323 htim->OnePulse_MspInitCallback(htim);
2324 #else
2325 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2326 HAL_TIM_OnePulse_MspInit(htim);
2327 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2328 }
2329
2330 /* Set the TIM state */
2331 htim->State = HAL_TIM_STATE_BUSY;
2332
2333 /* Configure the Time base in the One Pulse Mode */
2334 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2335
2336 /* Reset the OPM Bit */
2337 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2338
2339 /* Configure the OPM Mode */
2340 htim->Instance->CR1 |= OnePulseMode;
2341
2342 /* Initialize the TIM state*/
2343 htim->State = HAL_TIM_STATE_READY;
2344
2345 return HAL_OK;
2346 }
2347
2348 /**
2349 * @brief DeInitializes the TIM One Pulse
2350 * @param htim TIM One Pulse handle
2351 * @retval HAL status
2352 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2353 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2354 {
2355 /* Check the parameters */
2356 assert_param(IS_TIM_INSTANCE(htim->Instance));
2357
2358 htim->State = HAL_TIM_STATE_BUSY;
2359
2360 /* Disable the TIM Peripheral Clock */
2361 __HAL_TIM_DISABLE(htim);
2362
2363 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2364 if (htim->OnePulse_MspDeInitCallback == NULL)
2365 {
2366 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2367 }
2368 /* DeInit the low level hardware */
2369 htim->OnePulse_MspDeInitCallback(htim);
2370 #else
2371 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2372 HAL_TIM_OnePulse_MspDeInit(htim);
2373 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2374
2375 /* Change TIM state */
2376 htim->State = HAL_TIM_STATE_RESET;
2377
2378 /* Release Lock */
2379 __HAL_UNLOCK(htim);
2380
2381 return HAL_OK;
2382 }
2383
2384 /**
2385 * @brief Initializes the TIM One Pulse MSP.
2386 * @param htim TIM One Pulse handle
2387 * @retval None
2388 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2389 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2390 {
2391 /* Prevent unused argument(s) compilation warning */
2392 UNUSED(htim);
2393
2394 /* NOTE : This function should not be modified, when the callback is needed,
2395 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2396 */
2397 }
2398
2399 /**
2400 * @brief DeInitializes TIM One Pulse MSP.
2401 * @param htim TIM One Pulse handle
2402 * @retval None
2403 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2404 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2405 {
2406 /* Prevent unused argument(s) compilation warning */
2407 UNUSED(htim);
2408
2409 /* NOTE : This function should not be modified, when the callback is needed,
2410 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2411 */
2412 }
2413
2414 /**
2415 * @brief Starts the TIM One Pulse signal generation.
2416 * @param htim TIM One Pulse handle
2417 * @param OutputChannel TIM Channels to be enabled
2418 * This parameter can be one of the following values:
2419 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2420 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2421 * @retval HAL status
2422 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2423 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2424 {
2425 /* Prevent unused argument(s) compilation warning */
2426 UNUSED(OutputChannel);
2427
2428 /* Enable the Capture compare and the Input Capture channels
2429 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2430 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2431 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2432 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2433
2434 No need to enable the counter, it's enabled automatically by hardware
2435 (the counter starts in response to a stimulus and generate a pulse */
2436
2437 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2438 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2439
2440 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2441 {
2442 /* Enable the main output */
2443 __HAL_TIM_MOE_ENABLE(htim);
2444 }
2445
2446 /* Return function status */
2447 return HAL_OK;
2448 }
2449
2450 /**
2451 * @brief Stops the TIM One Pulse signal generation.
2452 * @param htim TIM One Pulse handle
2453 * @param OutputChannel TIM Channels to be disable
2454 * This parameter can be one of the following values:
2455 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2456 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2457 * @retval HAL status
2458 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2459 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2460 {
2461 /* Prevent unused argument(s) compilation warning */
2462 UNUSED(OutputChannel);
2463
2464 /* Disable the Capture compare and the Input Capture channels
2465 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2466 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2467 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2468 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2469
2470 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2471 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2472
2473 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2474 {
2475 /* Disable the Main Output */
2476 __HAL_TIM_MOE_DISABLE(htim);
2477 }
2478
2479 /* Disable the Peripheral */
2480 __HAL_TIM_DISABLE(htim);
2481
2482 /* Return function status */
2483 return HAL_OK;
2484 }
2485
2486 /**
2487 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2488 * @param htim TIM One Pulse handle
2489 * @param OutputChannel TIM Channels to be enabled
2490 * This parameter can be one of the following values:
2491 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2492 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2493 * @retval HAL status
2494 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2495 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2496 {
2497 /* Prevent unused argument(s) compilation warning */
2498 UNUSED(OutputChannel);
2499
2500 /* Enable the Capture compare and the Input Capture channels
2501 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2502 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2503 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2504 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2505
2506 No need to enable the counter, it's enabled automatically by hardware
2507 (the counter starts in response to a stimulus and generate a pulse */
2508
2509 /* Enable the TIM Capture/Compare 1 interrupt */
2510 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2511
2512 /* Enable the TIM Capture/Compare 2 interrupt */
2513 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2514
2515 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2516 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2517
2518 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2519 {
2520 /* Enable the main output */
2521 __HAL_TIM_MOE_ENABLE(htim);
2522 }
2523
2524 /* Return function status */
2525 return HAL_OK;
2526 }
2527
2528 /**
2529 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2530 * @param htim TIM One Pulse handle
2531 * @param OutputChannel TIM Channels to be enabled
2532 * This parameter can be one of the following values:
2533 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2534 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2535 * @retval HAL status
2536 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2537 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2538 {
2539 /* Prevent unused argument(s) compilation warning */
2540 UNUSED(OutputChannel);
2541
2542 /* Disable the TIM Capture/Compare 1 interrupt */
2543 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2544
2545 /* Disable the TIM Capture/Compare 2 interrupt */
2546 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2547
2548 /* Disable the Capture compare and the Input Capture channels
2549 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2550 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2551 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2552 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2553 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2554 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2555
2556 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2557 {
2558 /* Disable the Main Output */
2559 __HAL_TIM_MOE_DISABLE(htim);
2560 }
2561
2562 /* Disable the Peripheral */
2563 __HAL_TIM_DISABLE(htim);
2564
2565 /* Return function status */
2566 return HAL_OK;
2567 }
2568
2569 /**
2570 * @}
2571 */
2572
2573 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
2574 * @brief TIM Encoder functions
2575 *
2576 @verbatim
2577 ==============================================================================
2578 ##### TIM Encoder functions #####
2579 ==============================================================================
2580 [..]
2581 This section provides functions allowing to:
2582 (+) Initialize and configure the TIM Encoder.
2583 (+) De-initialize the TIM Encoder.
2584 (+) Start the TIM Encoder.
2585 (+) Stop the TIM Encoder.
2586 (+) Start the TIM Encoder and enable interrupt.
2587 (+) Stop the TIM Encoder and disable interrupt.
2588 (+) Start the TIM Encoder and enable DMA transfer.
2589 (+) Stop the TIM Encoder and disable DMA transfer.
2590
2591 @endverbatim
2592 * @{
2593 */
2594 /**
2595 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
2596 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2597 * requires a timer reset to avoid unexpected direction
2598 * due to DIR bit readonly in center aligned mode.
2599 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
2600 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
2601 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
2602 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
2603 * @param htim TIM Encoder Interface handle
2604 * @param sConfig TIM Encoder Interface configuration structure
2605 * @retval HAL status
2606 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,TIM_Encoder_InitTypeDef * sConfig)2607 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
2608 {
2609 uint32_t tmpsmcr;
2610 uint32_t tmpccmr1;
2611 uint32_t tmpccer;
2612
2613 /* Check the TIM handle allocation */
2614 if (htim == NULL)
2615 {
2616 return HAL_ERROR;
2617 }
2618
2619 /* Check the parameters */
2620 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2621 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2622 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2623 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2624 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2625 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2626 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2627 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
2628 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
2629 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2630 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2631 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2632 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2633
2634 if (htim->State == HAL_TIM_STATE_RESET)
2635 {
2636 /* Allocate lock resource and initialize it */
2637 htim->Lock = HAL_UNLOCKED;
2638
2639 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2640 /* Reset interrupt callbacks to legacy weak callbacks */
2641 TIM_ResetCallback(htim);
2642
2643 if (htim->Encoder_MspInitCallback == NULL)
2644 {
2645 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
2646 }
2647 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2648 htim->Encoder_MspInitCallback(htim);
2649 #else
2650 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2651 HAL_TIM_Encoder_MspInit(htim);
2652 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2653 }
2654
2655 /* Set the TIM state */
2656 htim->State = HAL_TIM_STATE_BUSY;
2657
2658 /* Reset the SMS and ECE bits */
2659 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
2660
2661 /* Configure the Time base in the Encoder Mode */
2662 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2663
2664 /* Get the TIMx SMCR register value */
2665 tmpsmcr = htim->Instance->SMCR;
2666
2667 /* Get the TIMx CCMR1 register value */
2668 tmpccmr1 = htim->Instance->CCMR1;
2669
2670 /* Get the TIMx CCER register value */
2671 tmpccer = htim->Instance->CCER;
2672
2673 /* Set the encoder Mode */
2674 tmpsmcr |= sConfig->EncoderMode;
2675
2676 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2677 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
2678 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
2679
2680 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2681 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
2682 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
2683 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
2684 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
2685
2686 /* Set the TI1 and the TI2 Polarities */
2687 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
2688 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
2689 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
2690
2691 /* Write to TIMx SMCR */
2692 htim->Instance->SMCR = tmpsmcr;
2693
2694 /* Write to TIMx CCMR1 */
2695 htim->Instance->CCMR1 = tmpccmr1;
2696
2697 /* Write to TIMx CCER */
2698 htim->Instance->CCER = tmpccer;
2699
2700 /* Initialize the TIM state*/
2701 htim->State = HAL_TIM_STATE_READY;
2702
2703 return HAL_OK;
2704 }
2705
2706
2707 /**
2708 * @brief DeInitializes the TIM Encoder interface
2709 * @param htim TIM Encoder Interface handle
2710 * @retval HAL status
2711 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)2712 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
2713 {
2714 /* Check the parameters */
2715 assert_param(IS_TIM_INSTANCE(htim->Instance));
2716
2717 htim->State = HAL_TIM_STATE_BUSY;
2718
2719 /* Disable the TIM Peripheral Clock */
2720 __HAL_TIM_DISABLE(htim);
2721
2722 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2723 if (htim->Encoder_MspDeInitCallback == NULL)
2724 {
2725 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
2726 }
2727 /* DeInit the low level hardware */
2728 htim->Encoder_MspDeInitCallback(htim);
2729 #else
2730 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2731 HAL_TIM_Encoder_MspDeInit(htim);
2732 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2733
2734 /* Change TIM state */
2735 htim->State = HAL_TIM_STATE_RESET;
2736
2737 /* Release Lock */
2738 __HAL_UNLOCK(htim);
2739
2740 return HAL_OK;
2741 }
2742
2743 /**
2744 * @brief Initializes the TIM Encoder Interface MSP.
2745 * @param htim TIM Encoder Interface handle
2746 * @retval None
2747 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)2748 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
2749 {
2750 /* Prevent unused argument(s) compilation warning */
2751 UNUSED(htim);
2752
2753 /* NOTE : This function should not be modified, when the callback is needed,
2754 the HAL_TIM_Encoder_MspInit could be implemented in the user file
2755 */
2756 }
2757
2758 /**
2759 * @brief DeInitializes TIM Encoder Interface MSP.
2760 * @param htim TIM Encoder Interface handle
2761 * @retval None
2762 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)2763 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
2764 {
2765 /* Prevent unused argument(s) compilation warning */
2766 UNUSED(htim);
2767
2768 /* NOTE : This function should not be modified, when the callback is needed,
2769 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
2770 */
2771 }
2772
2773 /**
2774 * @brief Starts the TIM Encoder Interface.
2775 * @param htim TIM Encoder Interface handle
2776 * @param Channel TIM Channels to be enabled
2777 * This parameter can be one of the following values:
2778 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2779 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2780 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2781 * @retval HAL status
2782 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2783 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2784 {
2785 /* Check the parameters */
2786 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2787
2788 /* Enable the encoder interface channels */
2789 switch (Channel)
2790 {
2791 case TIM_CHANNEL_1:
2792 {
2793 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2794 break;
2795 }
2796
2797 case TIM_CHANNEL_2:
2798 {
2799 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2800 break;
2801 }
2802
2803 default :
2804 {
2805 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2806 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2807 break;
2808 }
2809 }
2810 /* Enable the Peripheral */
2811 __HAL_TIM_ENABLE(htim);
2812
2813 /* Return function status */
2814 return HAL_OK;
2815 }
2816
2817 /**
2818 * @brief Stops the TIM Encoder Interface.
2819 * @param htim TIM Encoder Interface handle
2820 * @param Channel TIM Channels to be disabled
2821 * This parameter can be one of the following values:
2822 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2823 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2824 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2825 * @retval HAL status
2826 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2827 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2828 {
2829 /* Check the parameters */
2830 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2831
2832 /* Disable the Input Capture channels 1 and 2
2833 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2834 switch (Channel)
2835 {
2836 case TIM_CHANNEL_1:
2837 {
2838 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2839 break;
2840 }
2841
2842 case TIM_CHANNEL_2:
2843 {
2844 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2845 break;
2846 }
2847
2848 default :
2849 {
2850 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2851 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2852 break;
2853 }
2854 }
2855
2856 /* Disable the Peripheral */
2857 __HAL_TIM_DISABLE(htim);
2858
2859 /* Return function status */
2860 return HAL_OK;
2861 }
2862
2863 /**
2864 * @brief Starts the TIM Encoder Interface in interrupt mode.
2865 * @param htim TIM Encoder Interface handle
2866 * @param Channel TIM Channels to be enabled
2867 * This parameter can be one of the following values:
2868 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2869 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2870 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2871 * @retval HAL status
2872 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2873 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2874 {
2875 /* Check the parameters */
2876 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2877
2878 /* Enable the encoder interface channels */
2879 /* Enable the capture compare Interrupts 1 and/or 2 */
2880 switch (Channel)
2881 {
2882 case TIM_CHANNEL_1:
2883 {
2884 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2885 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2886 break;
2887 }
2888
2889 case TIM_CHANNEL_2:
2890 {
2891 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2892 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2893 break;
2894 }
2895
2896 default :
2897 {
2898 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2899 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2900 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2901 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2902 break;
2903 }
2904 }
2905
2906 /* Enable the Peripheral */
2907 __HAL_TIM_ENABLE(htim);
2908
2909 /* Return function status */
2910 return HAL_OK;
2911 }
2912
2913 /**
2914 * @brief Stops the TIM Encoder Interface in interrupt mode.
2915 * @param htim TIM Encoder Interface handle
2916 * @param Channel TIM Channels to be disabled
2917 * This parameter can be one of the following values:
2918 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2919 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2920 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2921 * @retval HAL status
2922 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2923 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2924 {
2925 /* Check the parameters */
2926 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2927
2928 /* Disable the Input Capture channels 1 and 2
2929 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2930 if (Channel == TIM_CHANNEL_1)
2931 {
2932 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2933
2934 /* Disable the capture compare Interrupts 1 */
2935 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2936 }
2937 else if (Channel == TIM_CHANNEL_2)
2938 {
2939 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2940
2941 /* Disable the capture compare Interrupts 2 */
2942 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2943 }
2944 else
2945 {
2946 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2947 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2948
2949 /* Disable the capture compare Interrupts 1 and 2 */
2950 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2951 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2952 }
2953
2954 /* Disable the Peripheral */
2955 __HAL_TIM_DISABLE(htim);
2956
2957 /* Change the htim state */
2958 htim->State = HAL_TIM_STATE_READY;
2959
2960 /* Return function status */
2961 return HAL_OK;
2962 }
2963
2964 /**
2965 * @brief Starts the TIM Encoder Interface in DMA mode.
2966 * @param htim TIM Encoder Interface handle
2967 * @param Channel TIM Channels to be enabled
2968 * This parameter can be one of the following values:
2969 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2970 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2971 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2972 * @param pData1 The destination Buffer address for IC1.
2973 * @param pData2 The destination Buffer address for IC2.
2974 * @param Length The length of data to be transferred from TIM peripheral to memory.
2975 * @retval HAL status
2976 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)2977 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
2978 uint32_t *pData2, uint16_t Length)
2979 {
2980 /* Check the parameters */
2981 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2982
2983 if (htim->State == HAL_TIM_STATE_BUSY)
2984 {
2985 return HAL_BUSY;
2986 }
2987 else if (htim->State == HAL_TIM_STATE_READY)
2988 {
2989 if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
2990 {
2991 return HAL_ERROR;
2992 }
2993 else
2994 {
2995 htim->State = HAL_TIM_STATE_BUSY;
2996 }
2997 }
2998 else
2999 {
3000 /* nothing to do */
3001 }
3002
3003 switch (Channel)
3004 {
3005 case TIM_CHANNEL_1:
3006 {
3007 /* Set the DMA capture callbacks */
3008 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3009 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3010
3011 /* Set the DMA error callback */
3012 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3013
3014 /* Enable the DMA channel */
3015 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
3016 {
3017 return HAL_ERROR;
3018 }
3019 /* Enable the TIM Input Capture DMA request */
3020 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3021
3022 /* Enable the Peripheral */
3023 __HAL_TIM_ENABLE(htim);
3024
3025 /* Enable the Capture compare channel */
3026 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3027 break;
3028 }
3029
3030 case TIM_CHANNEL_2:
3031 {
3032 /* Set the DMA capture callbacks */
3033 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3034 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3035
3036 /* Set the DMA error callback */
3037 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3038 /* Enable the DMA channel */
3039 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
3040 {
3041 return HAL_ERROR;
3042 }
3043 /* Enable the TIM Input Capture DMA request */
3044 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3045
3046 /* Enable the Peripheral */
3047 __HAL_TIM_ENABLE(htim);
3048
3049 /* Enable the Capture compare channel */
3050 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3051 break;
3052 }
3053
3054 case TIM_CHANNEL_ALL:
3055 {
3056 /* Set the DMA capture callbacks */
3057 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3058 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3059
3060 /* Set the DMA error callback */
3061 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3062
3063 /* Enable the DMA channel */
3064 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
3065 {
3066 return HAL_ERROR;
3067 }
3068
3069 /* Set the DMA capture callbacks */
3070 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3071 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3072
3073 /* Set the DMA error callback */
3074 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3075
3076 /* Enable the DMA channel */
3077 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
3078 {
3079 return HAL_ERROR;
3080 }
3081 /* Enable the Peripheral */
3082 __HAL_TIM_ENABLE(htim);
3083
3084 /* Enable the Capture compare channel */
3085 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3086 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3087
3088 /* Enable the TIM Input Capture DMA request */
3089 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3090 /* Enable the TIM Input Capture DMA request */
3091 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3092 break;
3093 }
3094
3095 default:
3096 break;
3097 }
3098 /* Return function status */
3099 return HAL_OK;
3100 }
3101
3102 /**
3103 * @brief Stops the TIM Encoder Interface in DMA mode.
3104 * @param htim TIM Encoder Interface handle
3105 * @param Channel TIM Channels to be enabled
3106 * This parameter can be one of the following values:
3107 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3108 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3109 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3110 * @retval HAL status
3111 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3112 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3113 {
3114 /* Check the parameters */
3115 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
3116
3117 /* Disable the Input Capture channels 1 and 2
3118 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3119 if (Channel == TIM_CHANNEL_1)
3120 {
3121 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3122
3123 /* Disable the capture compare DMA Request 1 */
3124 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3125 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3126 }
3127 else if (Channel == TIM_CHANNEL_2)
3128 {
3129 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3130
3131 /* Disable the capture compare DMA Request 2 */
3132 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3133 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3134 }
3135 else
3136 {
3137 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3138 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3139
3140 /* Disable the capture compare DMA Request 1 and 2 */
3141 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3142 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3143 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3144 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3145 }
3146
3147 /* Disable the Peripheral */
3148 __HAL_TIM_DISABLE(htim);
3149
3150 /* Change the htim state */
3151 htim->State = HAL_TIM_STATE_READY;
3152
3153 /* Return function status */
3154 return HAL_OK;
3155 }
3156
3157 /**
3158 * @}
3159 */
3160 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3161 * @brief TIM IRQ handler management
3162 *
3163 @verbatim
3164 ==============================================================================
3165 ##### IRQ handler management #####
3166 ==============================================================================
3167 [..]
3168 This section provides Timer IRQ handler function.
3169
3170 @endverbatim
3171 * @{
3172 */
3173 /**
3174 * @brief This function handles TIM interrupts requests.
3175 * @param htim TIM handle
3176 * @retval None
3177 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3178 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3179 {
3180 /* Capture compare 1 event */
3181 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
3182 {
3183 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
3184 {
3185 {
3186 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
3187 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3188
3189 /* Input capture event */
3190 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3191 {
3192 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3193 htim->IC_CaptureCallback(htim);
3194 #else
3195 HAL_TIM_IC_CaptureCallback(htim);
3196 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3197 }
3198 /* Output compare event */
3199 else
3200 {
3201 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3202 htim->OC_DelayElapsedCallback(htim);
3203 htim->PWM_PulseFinishedCallback(htim);
3204 #else
3205 HAL_TIM_OC_DelayElapsedCallback(htim);
3206 HAL_TIM_PWM_PulseFinishedCallback(htim);
3207 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3208 }
3209 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3210 }
3211 }
3212 }
3213 /* Capture compare 2 event */
3214 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
3215 {
3216 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
3217 {
3218 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
3219 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3220 /* Input capture event */
3221 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3222 {
3223 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3224 htim->IC_CaptureCallback(htim);
3225 #else
3226 HAL_TIM_IC_CaptureCallback(htim);
3227 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3228 }
3229 /* Output compare event */
3230 else
3231 {
3232 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3233 htim->OC_DelayElapsedCallback(htim);
3234 htim->PWM_PulseFinishedCallback(htim);
3235 #else
3236 HAL_TIM_OC_DelayElapsedCallback(htim);
3237 HAL_TIM_PWM_PulseFinishedCallback(htim);
3238 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3239 }
3240 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3241 }
3242 }
3243 /* Capture compare 3 event */
3244 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
3245 {
3246 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
3247 {
3248 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
3249 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3250 /* Input capture event */
3251 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3252 {
3253 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3254 htim->IC_CaptureCallback(htim);
3255 #else
3256 HAL_TIM_IC_CaptureCallback(htim);
3257 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3258 }
3259 /* Output compare event */
3260 else
3261 {
3262 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3263 htim->OC_DelayElapsedCallback(htim);
3264 htim->PWM_PulseFinishedCallback(htim);
3265 #else
3266 HAL_TIM_OC_DelayElapsedCallback(htim);
3267 HAL_TIM_PWM_PulseFinishedCallback(htim);
3268 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3269 }
3270 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3271 }
3272 }
3273 /* Capture compare 4 event */
3274 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
3275 {
3276 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
3277 {
3278 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
3279 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3280 /* Input capture event */
3281 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3282 {
3283 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3284 htim->IC_CaptureCallback(htim);
3285 #else
3286 HAL_TIM_IC_CaptureCallback(htim);
3287 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3288 }
3289 /* Output compare event */
3290 else
3291 {
3292 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3293 htim->OC_DelayElapsedCallback(htim);
3294 htim->PWM_PulseFinishedCallback(htim);
3295 #else
3296 HAL_TIM_OC_DelayElapsedCallback(htim);
3297 HAL_TIM_PWM_PulseFinishedCallback(htim);
3298 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3299 }
3300 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3301 }
3302 }
3303 /* TIM Update event */
3304 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
3305 {
3306 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
3307 {
3308 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
3309 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3310 htim->PeriodElapsedCallback(htim);
3311 #else
3312 HAL_TIM_PeriodElapsedCallback(htim);
3313 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3314 }
3315 }
3316 /* TIM Break input event */
3317 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
3318 {
3319 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3320 {
3321 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
3322 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3323 htim->BreakCallback(htim);
3324 #else
3325 HAL_TIMEx_BreakCallback(htim);
3326 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3327 }
3328 }
3329 /* TIM Break2 input event */
3330 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
3331 {
3332 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3333 {
3334 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
3335 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3336 htim->Break2Callback(htim);
3337 #else
3338 HAL_TIMEx_Break2Callback(htim);
3339 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3340 }
3341 }
3342 /* TIM Trigger detection event */
3343 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
3344 {
3345 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
3346 {
3347 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
3348 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3349 htim->TriggerCallback(htim);
3350 #else
3351 HAL_TIM_TriggerCallback(htim);
3352 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3353 }
3354 }
3355 /* TIM commutation event */
3356 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
3357 {
3358 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
3359 {
3360 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
3361 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3362 htim->CommutationCallback(htim);
3363 #else
3364 HAL_TIMEx_CommutCallback(htim);
3365 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3366 }
3367 }
3368 }
3369
3370 /**
3371 * @}
3372 */
3373
3374 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
3375 * @brief TIM Peripheral Control functions
3376 *
3377 @verbatim
3378 ==============================================================================
3379 ##### Peripheral Control functions #####
3380 ==============================================================================
3381 [..]
3382 This section provides functions allowing to:
3383 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
3384 (+) Configure External Clock source.
3385 (+) Configure Complementary channels, break features and dead time.
3386 (+) Configure Master and the Slave synchronization.
3387 (+) Configure the DMA Burst Mode.
3388
3389 @endverbatim
3390 * @{
3391 */
3392
3393 /**
3394 * @brief Initializes the TIM Output Compare Channels according to the specified
3395 * parameters in the TIM_OC_InitTypeDef.
3396 * @param htim TIM Output Compare handle
3397 * @param sConfig TIM Output Compare configuration structure
3398 * @param Channel TIM Channels to configure
3399 * This parameter can be one of the following values:
3400 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3401 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3402 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3403 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3404 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
3405 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
3406 * @retval HAL status
3407 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OC_InitTypeDef * sConfig,uint32_t Channel)3408 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
3409 TIM_OC_InitTypeDef *sConfig,
3410 uint32_t Channel)
3411 {
3412 /* Check the parameters */
3413 assert_param(IS_TIM_CHANNELS(Channel));
3414 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
3415 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3416
3417 /* Process Locked */
3418 __HAL_LOCK(htim);
3419
3420 htim->State = HAL_TIM_STATE_BUSY;
3421
3422 switch (Channel)
3423 {
3424 case TIM_CHANNEL_1:
3425 {
3426 /* Check the parameters */
3427 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3428
3429 /* Configure the TIM Channel 1 in Output Compare */
3430 TIM_OC1_SetConfig(htim->Instance, sConfig);
3431 break;
3432 }
3433
3434 case TIM_CHANNEL_2:
3435 {
3436 /* Check the parameters */
3437 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3438
3439 /* Configure the TIM Channel 2 in Output Compare */
3440 TIM_OC2_SetConfig(htim->Instance, sConfig);
3441 break;
3442 }
3443
3444 case TIM_CHANNEL_3:
3445 {
3446 /* Check the parameters */
3447 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3448
3449 /* Configure the TIM Channel 3 in Output Compare */
3450 TIM_OC3_SetConfig(htim->Instance, sConfig);
3451 break;
3452 }
3453
3454 case TIM_CHANNEL_4:
3455 {
3456 /* Check the parameters */
3457 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3458
3459 /* Configure the TIM Channel 4 in Output Compare */
3460 TIM_OC4_SetConfig(htim->Instance, sConfig);
3461 break;
3462 }
3463
3464 case TIM_CHANNEL_5:
3465 {
3466 /* Check the parameters */
3467 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
3468
3469 /* Configure the TIM Channel 5 in Output Compare */
3470 TIM_OC5_SetConfig(htim->Instance, sConfig);
3471 break;
3472 }
3473
3474 case TIM_CHANNEL_6:
3475 {
3476 /* Check the parameters */
3477 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
3478
3479 /* Configure the TIM Channel 6 in Output Compare */
3480 TIM_OC6_SetConfig(htim->Instance, sConfig);
3481 break;
3482 }
3483
3484 default:
3485 break;
3486 }
3487
3488 htim->State = HAL_TIM_STATE_READY;
3489
3490 __HAL_UNLOCK(htim);
3491
3492 return HAL_OK;
3493 }
3494
3495 /**
3496 * @brief Initializes the TIM Input Capture Channels according to the specified
3497 * parameters in the TIM_IC_InitTypeDef.
3498 * @param htim TIM IC handle
3499 * @param sConfig TIM Input Capture configuration structure
3500 * @param Channel TIM Channel to configure
3501 * This parameter can be one of the following values:
3502 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3503 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3504 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3505 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3506 * @retval HAL status
3507 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,TIM_IC_InitTypeDef * sConfig,uint32_t Channel)3508 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
3509 {
3510 /* Check the parameters */
3511 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3512 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
3513 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
3514 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
3515 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
3516
3517 /* Process Locked */
3518 __HAL_LOCK(htim);
3519
3520 htim->State = HAL_TIM_STATE_BUSY;
3521
3522 if (Channel == TIM_CHANNEL_1)
3523 {
3524 /* TI1 Configuration */
3525 TIM_TI1_SetConfig(htim->Instance,
3526 sConfig->ICPolarity,
3527 sConfig->ICSelection,
3528 sConfig->ICFilter);
3529
3530 /* Reset the IC1PSC Bits */
3531 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3532
3533 /* Set the IC1PSC value */
3534 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
3535 }
3536 else if (Channel == TIM_CHANNEL_2)
3537 {
3538 /* TI2 Configuration */
3539 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3540
3541 TIM_TI2_SetConfig(htim->Instance,
3542 sConfig->ICPolarity,
3543 sConfig->ICSelection,
3544 sConfig->ICFilter);
3545
3546 /* Reset the IC2PSC Bits */
3547 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3548
3549 /* Set the IC2PSC value */
3550 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
3551 }
3552 else if (Channel == TIM_CHANNEL_3)
3553 {
3554 /* TI3 Configuration */
3555 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3556
3557 TIM_TI3_SetConfig(htim->Instance,
3558 sConfig->ICPolarity,
3559 sConfig->ICSelection,
3560 sConfig->ICFilter);
3561
3562 /* Reset the IC3PSC Bits */
3563 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
3564
3565 /* Set the IC3PSC value */
3566 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
3567 }
3568 else
3569 {
3570 /* TI4 Configuration */
3571 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3572
3573 TIM_TI4_SetConfig(htim->Instance,
3574 sConfig->ICPolarity,
3575 sConfig->ICSelection,
3576 sConfig->ICFilter);
3577
3578 /* Reset the IC4PSC Bits */
3579 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
3580
3581 /* Set the IC4PSC value */
3582 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
3583 }
3584
3585 htim->State = HAL_TIM_STATE_READY;
3586
3587 __HAL_UNLOCK(htim);
3588
3589 return HAL_OK;
3590 }
3591
3592 /**
3593 * @brief Initializes the TIM PWM channels according to the specified
3594 * parameters in the TIM_OC_InitTypeDef.
3595 * @param htim TIM PWM handle
3596 * @param sConfig TIM PWM configuration structure
3597 * @param Channel TIM Channels to be configured
3598 * This parameter can be one of the following values:
3599 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3600 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3601 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3602 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3603 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
3604 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
3605 * @retval HAL status
3606 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OC_InitTypeDef * sConfig,uint32_t Channel)3607 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
3608 TIM_OC_InitTypeDef *sConfig,
3609 uint32_t Channel)
3610 {
3611 /* Check the parameters */
3612 assert_param(IS_TIM_CHANNELS(Channel));
3613 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
3614 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3615 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
3616
3617 /* Process Locked */
3618 __HAL_LOCK(htim);
3619
3620 htim->State = HAL_TIM_STATE_BUSY;
3621
3622 switch (Channel)
3623 {
3624 case TIM_CHANNEL_1:
3625 {
3626 /* Check the parameters */
3627 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3628
3629 /* Configure the Channel 1 in PWM mode */
3630 TIM_OC1_SetConfig(htim->Instance, sConfig);
3631
3632 /* Set the Preload enable bit for channel1 */
3633 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
3634
3635 /* Configure the Output Fast mode */
3636 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
3637 htim->Instance->CCMR1 |= sConfig->OCFastMode;
3638 break;
3639 }
3640
3641 case TIM_CHANNEL_2:
3642 {
3643 /* Check the parameters */
3644 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3645
3646 /* Configure the Channel 2 in PWM mode */
3647 TIM_OC2_SetConfig(htim->Instance, sConfig);
3648
3649 /* Set the Preload enable bit for channel2 */
3650 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
3651
3652 /* Configure the Output Fast mode */
3653 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
3654 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
3655 break;
3656 }
3657
3658 case TIM_CHANNEL_3:
3659 {
3660 /* Check the parameters */
3661 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3662
3663 /* Configure the Channel 3 in PWM mode */
3664 TIM_OC3_SetConfig(htim->Instance, sConfig);
3665
3666 /* Set the Preload enable bit for channel3 */
3667 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
3668
3669 /* Configure the Output Fast mode */
3670 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
3671 htim->Instance->CCMR2 |= sConfig->OCFastMode;
3672 break;
3673 }
3674
3675 case TIM_CHANNEL_4:
3676 {
3677 /* Check the parameters */
3678 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3679
3680 /* Configure the Channel 4 in PWM mode */
3681 TIM_OC4_SetConfig(htim->Instance, sConfig);
3682
3683 /* Set the Preload enable bit for channel4 */
3684 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
3685
3686 /* Configure the Output Fast mode */
3687 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
3688 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
3689 break;
3690 }
3691
3692 case TIM_CHANNEL_5:
3693 {
3694 /* Check the parameters */
3695 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
3696
3697 /* Configure the Channel 5 in PWM mode */
3698 TIM_OC5_SetConfig(htim->Instance, sConfig);
3699
3700 /* Set the Preload enable bit for channel5*/
3701 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
3702
3703 /* Configure the Output Fast mode */
3704 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
3705 htim->Instance->CCMR3 |= sConfig->OCFastMode;
3706 break;
3707 }
3708
3709 case TIM_CHANNEL_6:
3710 {
3711 /* Check the parameters */
3712 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
3713
3714 /* Configure the Channel 6 in PWM mode */
3715 TIM_OC6_SetConfig(htim->Instance, sConfig);
3716
3717 /* Set the Preload enable bit for channel6 */
3718 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
3719
3720 /* Configure the Output Fast mode */
3721 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
3722 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
3723 break;
3724 }
3725
3726 default:
3727 break;
3728 }
3729
3730 htim->State = HAL_TIM_STATE_READY;
3731
3732 __HAL_UNLOCK(htim);
3733
3734 return HAL_OK;
3735 }
3736
3737 /**
3738 * @brief Initializes the TIM One Pulse Channels according to the specified
3739 * parameters in the TIM_OnePulse_InitTypeDef.
3740 * @param htim TIM One Pulse handle
3741 * @param sConfig TIM One Pulse configuration structure
3742 * @param OutputChannel TIM output channel to configure
3743 * This parameter can be one of the following values:
3744 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3745 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3746 * @param InputChannel TIM input Channel to configure
3747 * This parameter can be one of the following values:
3748 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3749 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3750 * @note To output a waveform with a minimum delay user can enable the fast
3751 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
3752 * output is forced in response to the edge detection on TIx input,
3753 * without taking in account the comparison.
3754 * @retval HAL status
3755 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)3756 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
3757 uint32_t OutputChannel, uint32_t InputChannel)
3758 {
3759 TIM_OC_InitTypeDef temp1;
3760
3761 /* Check the parameters */
3762 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
3763 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
3764
3765 if (OutputChannel != InputChannel)
3766 {
3767 /* Process Locked */
3768 __HAL_LOCK(htim);
3769
3770 htim->State = HAL_TIM_STATE_BUSY;
3771
3772 /* Extract the Output compare configuration from sConfig structure */
3773 temp1.OCMode = sConfig->OCMode;
3774 temp1.Pulse = sConfig->Pulse;
3775 temp1.OCPolarity = sConfig->OCPolarity;
3776 temp1.OCNPolarity = sConfig->OCNPolarity;
3777 temp1.OCIdleState = sConfig->OCIdleState;
3778 temp1.OCNIdleState = sConfig->OCNIdleState;
3779
3780 switch (OutputChannel)
3781 {
3782 case TIM_CHANNEL_1:
3783 {
3784 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3785
3786 TIM_OC1_SetConfig(htim->Instance, &temp1);
3787 break;
3788 }
3789 case TIM_CHANNEL_2:
3790 {
3791 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3792
3793 TIM_OC2_SetConfig(htim->Instance, &temp1);
3794 break;
3795 }
3796 default:
3797 break;
3798 }
3799
3800 switch (InputChannel)
3801 {
3802 case TIM_CHANNEL_1:
3803 {
3804 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3805
3806 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
3807 sConfig->ICSelection, sConfig->ICFilter);
3808
3809 /* Reset the IC1PSC Bits */
3810 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3811
3812 /* Select the Trigger source */
3813 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3814 htim->Instance->SMCR |= TIM_TS_TI1FP1;
3815
3816 /* Select the Slave Mode */
3817 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3818 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3819 break;
3820 }
3821 case TIM_CHANNEL_2:
3822 {
3823 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3824
3825 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
3826 sConfig->ICSelection, sConfig->ICFilter);
3827
3828 /* Reset the IC2PSC Bits */
3829 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3830
3831 /* Select the Trigger source */
3832 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3833 htim->Instance->SMCR |= TIM_TS_TI2FP2;
3834
3835 /* Select the Slave Mode */
3836 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3837 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3838 break;
3839 }
3840
3841 default:
3842 break;
3843 }
3844
3845 htim->State = HAL_TIM_STATE_READY;
3846
3847 __HAL_UNLOCK(htim);
3848
3849 return HAL_OK;
3850 }
3851 else
3852 {
3853 return HAL_ERROR;
3854 }
3855 }
3856
3857 /**
3858 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
3859 * @param htim TIM handle
3860 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
3861 * This parameter can be one of the following values:
3862 * @arg TIM_DMABASE_CR1
3863 * @arg TIM_DMABASE_CR2
3864 * @arg TIM_DMABASE_SMCR
3865 * @arg TIM_DMABASE_DIER
3866 * @arg TIM_DMABASE_SR
3867 * @arg TIM_DMABASE_EGR
3868 * @arg TIM_DMABASE_CCMR1
3869 * @arg TIM_DMABASE_CCMR2
3870 * @arg TIM_DMABASE_CCER
3871 * @arg TIM_DMABASE_CNT
3872 * @arg TIM_DMABASE_PSC
3873 * @arg TIM_DMABASE_ARR
3874 * @arg TIM_DMABASE_RCR
3875 * @arg TIM_DMABASE_CCR1
3876 * @arg TIM_DMABASE_CCR2
3877 * @arg TIM_DMABASE_CCR3
3878 * @arg TIM_DMABASE_CCR4
3879 * @arg TIM_DMABASE_BDTR
3880 * @arg TIM_DMABASE_CCMR3
3881 * @arg TIM_DMABASE_CCR5
3882 * @arg TIM_DMABASE_CCR6
3883 * @arg TIM_DMABASE_AF1
3884 * @arg TIM_DMABASE_AF2
3885 * @arg TIM_DMABASE_TISEL
3886 * @param BurstRequestSrc TIM DMA Request sources
3887 * This parameter can be one of the following values:
3888 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3889 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3890 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3891 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3892 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3893 * @arg TIM_DMA_COM: TIM Commutation DMA source
3894 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3895 * @param BurstBuffer The Buffer address.
3896 * @param BurstLength DMA Burst length. This parameter can be one value
3897 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
3898 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
3899 * @retval HAL status
3900 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)3901 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3902 uint32_t *BurstBuffer, uint32_t BurstLength)
3903 {
3904 /* Check the parameters */
3905 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3906 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3907 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3908 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3909
3910 if (htim->State == HAL_TIM_STATE_BUSY)
3911 {
3912 return HAL_BUSY;
3913 }
3914 else if (htim->State == HAL_TIM_STATE_READY)
3915 {
3916 if ((BurstBuffer == NULL) && (BurstLength > 0U))
3917 {
3918 return HAL_ERROR;
3919 }
3920 else
3921 {
3922 htim->State = HAL_TIM_STATE_BUSY;
3923 }
3924 }
3925 else
3926 {
3927 /* nothing to do */
3928 }
3929 switch (BurstRequestSrc)
3930 {
3931 case TIM_DMA_UPDATE:
3932 {
3933 /* Set the DMA Period elapsed callbacks */
3934 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3935 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
3936
3937 /* Set the DMA error callback */
3938 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
3939
3940 /* Enable the DMA channel */
3941 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3942 {
3943 return HAL_ERROR;
3944 }
3945 break;
3946 }
3947 case TIM_DMA_CC1:
3948 {
3949 /* Set the DMA compare callbacks */
3950 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
3951 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
3952
3953 /* Set the DMA error callback */
3954 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3955
3956 /* Enable the DMA channel */
3957 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
3958 (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3959 {
3960 return HAL_ERROR;
3961 }
3962 break;
3963 }
3964 case TIM_DMA_CC2:
3965 {
3966 /* Set the DMA compare callbacks */
3967 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
3968 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
3969
3970 /* Set the DMA error callback */
3971 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3972
3973 /* Enable the DMA channel */
3974 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
3975 (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3976 {
3977 return HAL_ERROR;
3978 }
3979 break;
3980 }
3981 case TIM_DMA_CC3:
3982 {
3983 /* Set the DMA compare callbacks */
3984 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
3985 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
3986
3987 /* Set the DMA error callback */
3988 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
3989
3990 /* Enable the DMA channel */
3991 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
3992 (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
3993 {
3994 return HAL_ERROR;
3995 }
3996 break;
3997 }
3998 case TIM_DMA_CC4:
3999 {
4000 /* Set the DMA compare callbacks */
4001 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4002 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4003
4004 /* Set the DMA error callback */
4005 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4006
4007 /* Enable the DMA channel */
4008 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4009 (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4010 {
4011 return HAL_ERROR;
4012 }
4013 break;
4014 }
4015 case TIM_DMA_COM:
4016 {
4017 /* Set the DMA commutation callbacks */
4018 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4019 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4020
4021 /* Set the DMA error callback */
4022 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4023
4024 /* Enable the DMA channel */
4025 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4026 (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4027 {
4028 return HAL_ERROR;
4029 }
4030 break;
4031 }
4032 case TIM_DMA_TRIGGER:
4033 {
4034 /* Set the DMA trigger callbacks */
4035 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4036 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4037
4038 /* Set the DMA error callback */
4039 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4040
4041 /* Enable the DMA channel */
4042 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4043 (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4044 {
4045 return HAL_ERROR;
4046 }
4047 break;
4048 }
4049 default:
4050 break;
4051 }
4052 /* configure the DMA Burst Mode */
4053 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4054
4055 /* Enable the TIM DMA Request */
4056 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4057
4058 htim->State = HAL_TIM_STATE_READY;
4059
4060 /* Return function status */
4061 return HAL_OK;
4062 }
4063
4064 /**
4065 * @brief Stops the TIM DMA Burst mode
4066 * @param htim TIM handle
4067 * @param BurstRequestSrc TIM DMA Request sources to disable
4068 * @retval HAL status
4069 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4070 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4071 {
4072 HAL_StatusTypeDef status = HAL_OK;
4073 /* Check the parameters */
4074 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4075
4076 /* Abort the DMA transfer (at least disable the DMA channel) */
4077 switch (BurstRequestSrc)
4078 {
4079 case TIM_DMA_UPDATE:
4080 {
4081 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4082 break;
4083 }
4084 case TIM_DMA_CC1:
4085 {
4086 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4087 break;
4088 }
4089 case TIM_DMA_CC2:
4090 {
4091 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4092 break;
4093 }
4094 case TIM_DMA_CC3:
4095 {
4096 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4097 break;
4098 }
4099 case TIM_DMA_CC4:
4100 {
4101 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4102 break;
4103 }
4104 case TIM_DMA_COM:
4105 {
4106 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4107 break;
4108 }
4109 case TIM_DMA_TRIGGER:
4110 {
4111 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4112 break;
4113 }
4114 default:
4115 break;
4116 }
4117
4118 if (HAL_OK == status)
4119 {
4120 /* Disable the TIM Update DMA request */
4121 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4122 }
4123
4124 /* Return function status */
4125 return status;
4126 }
4127
4128 /**
4129 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4130 * @param htim TIM handle
4131 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4132 * This parameter can be one of the following values:
4133 * @arg TIM_DMABASE_CR1
4134 * @arg TIM_DMABASE_CR2
4135 * @arg TIM_DMABASE_SMCR
4136 * @arg TIM_DMABASE_DIER
4137 * @arg TIM_DMABASE_SR
4138 * @arg TIM_DMABASE_EGR
4139 * @arg TIM_DMABASE_CCMR1
4140 * @arg TIM_DMABASE_CCMR2
4141 * @arg TIM_DMABASE_CCER
4142 * @arg TIM_DMABASE_CNT
4143 * @arg TIM_DMABASE_PSC
4144 * @arg TIM_DMABASE_ARR
4145 * @arg TIM_DMABASE_RCR
4146 * @arg TIM_DMABASE_CCR1
4147 * @arg TIM_DMABASE_CCR2
4148 * @arg TIM_DMABASE_CCR3
4149 * @arg TIM_DMABASE_CCR4
4150 * @arg TIM_DMABASE_BDTR
4151 * @arg TIM_DMABASE_CCMR3
4152 * @arg TIM_DMABASE_CCR5
4153 * @arg TIM_DMABASE_CCR6
4154 * @arg TIM_DMABASE_AF1
4155 * @arg TIM_DMABASE_AF2
4156 * @arg TIM_DMABASE_TISEL
4157 * @param BurstRequestSrc TIM DMA Request sources
4158 * This parameter can be one of the following values:
4159 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4160 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4161 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4162 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4163 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4164 * @arg TIM_DMA_COM: TIM Commutation DMA source
4165 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4166 * @param BurstBuffer The Buffer address.
4167 * @param BurstLength DMA Burst length. This parameter can be one value
4168 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
4169 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4170 * @retval HAL status
4171 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4172 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4173 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4174 {
4175 /* Check the parameters */
4176 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4177 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4178 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4179 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4180
4181 if (htim->State == HAL_TIM_STATE_BUSY)
4182 {
4183 return HAL_BUSY;
4184 }
4185 else if (htim->State == HAL_TIM_STATE_READY)
4186 {
4187 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4188 {
4189 return HAL_ERROR;
4190 }
4191 else
4192 {
4193 htim->State = HAL_TIM_STATE_BUSY;
4194 }
4195 }
4196 else
4197 {
4198 /* nothing to do */
4199 }
4200 switch (BurstRequestSrc)
4201 {
4202 case TIM_DMA_UPDATE:
4203 {
4204 /* Set the DMA Period elapsed callbacks */
4205 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4206 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4207
4208 /* Set the DMA error callback */
4209 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4210
4211 /* Enable the DMA channel */
4212 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4213 {
4214 return HAL_ERROR;
4215 }
4216 break;
4217 }
4218 case TIM_DMA_CC1:
4219 {
4220 /* Set the DMA capture callbacks */
4221 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
4222 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4223
4224 /* Set the DMA error callback */
4225 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4226
4227 /* Enable the DMA channel */
4228 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4229 {
4230 return HAL_ERROR;
4231 }
4232 break;
4233 }
4234 case TIM_DMA_CC2:
4235 {
4236 /* Set the DMA capture/compare callbacks */
4237 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
4238 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4239
4240 /* Set the DMA error callback */
4241 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4242
4243 /* Enable the DMA channel */
4244 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4245 {
4246 return HAL_ERROR;
4247 }
4248 break;
4249 }
4250 case TIM_DMA_CC3:
4251 {
4252 /* Set the DMA capture callbacks */
4253 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
4254 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4255
4256 /* Set the DMA error callback */
4257 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4258
4259 /* Enable the DMA channel */
4260 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4261 {
4262 return HAL_ERROR;
4263 }
4264 break;
4265 }
4266 case TIM_DMA_CC4:
4267 {
4268 /* Set the DMA capture callbacks */
4269 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
4270 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4271
4272 /* Set the DMA error callback */
4273 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4274
4275 /* Enable the DMA channel */
4276 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4277 {
4278 return HAL_ERROR;
4279 }
4280 break;
4281 }
4282 case TIM_DMA_COM:
4283 {
4284 /* Set the DMA commutation callbacks */
4285 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4286 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4287
4288 /* Set the DMA error callback */
4289 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4290
4291 /* Enable the DMA channel */
4292 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4293 {
4294 return HAL_ERROR;
4295 }
4296 break;
4297 }
4298 case TIM_DMA_TRIGGER:
4299 {
4300 /* Set the DMA trigger callbacks */
4301 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4302 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4303
4304 /* Set the DMA error callback */
4305 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4306
4307 /* Enable the DMA channel */
4308 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
4309 {
4310 return HAL_ERROR;
4311 }
4312 break;
4313 }
4314 default:
4315 break;
4316 }
4317
4318 /* configure the DMA Burst Mode */
4319 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4320
4321 /* Enable the TIM DMA Request */
4322 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4323
4324 htim->State = HAL_TIM_STATE_READY;
4325
4326 /* Return function status */
4327 return HAL_OK;
4328 }
4329
4330 /**
4331 * @brief Stop the DMA burst reading
4332 * @param htim TIM handle
4333 * @param BurstRequestSrc TIM DMA Request sources to disable.
4334 * @retval HAL status
4335 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4336 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4337 {
4338 HAL_StatusTypeDef status = HAL_OK;
4339 /* Check the parameters */
4340 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4341
4342 /* Abort the DMA transfer (at least disable the DMA channel) */
4343 switch (BurstRequestSrc)
4344 {
4345 case TIM_DMA_UPDATE:
4346 {
4347 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4348 break;
4349 }
4350 case TIM_DMA_CC1:
4351 {
4352 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4353 break;
4354 }
4355 case TIM_DMA_CC2:
4356 {
4357 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4358 break;
4359 }
4360 case TIM_DMA_CC3:
4361 {
4362 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4363 break;
4364 }
4365 case TIM_DMA_CC4:
4366 {
4367 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4368 break;
4369 }
4370 case TIM_DMA_COM:
4371 {
4372 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4373 break;
4374 }
4375 case TIM_DMA_TRIGGER:
4376 {
4377 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4378 break;
4379 }
4380 default:
4381 break;
4382 }
4383
4384 if (HAL_OK == status)
4385 {
4386 /* Disable the TIM Update DMA request */
4387 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4388 }
4389
4390 /* Return function status */
4391 return status;
4392 }
4393
4394 /**
4395 * @brief Generate a software event
4396 * @param htim TIM handle
4397 * @param EventSource specifies the event source.
4398 * This parameter can be one of the following values:
4399 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
4400 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
4401 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
4402 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
4403 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
4404 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
4405 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
4406 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
4407 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
4408 * @note Basic timers can only generate an update event.
4409 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
4410 * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
4411 * only for timer instances supporting break input(s).
4412 * @retval HAL status
4413 */
4414
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)4415 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
4416 {
4417 /* Check the parameters */
4418 assert_param(IS_TIM_INSTANCE(htim->Instance));
4419 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
4420
4421 /* Process Locked */
4422 __HAL_LOCK(htim);
4423
4424 /* Change the TIM state */
4425 htim->State = HAL_TIM_STATE_BUSY;
4426
4427 /* Set the event sources */
4428 htim->Instance->EGR = EventSource;
4429
4430 /* Change the TIM state */
4431 htim->State = HAL_TIM_STATE_READY;
4432
4433 __HAL_UNLOCK(htim);
4434
4435 /* Return function status */
4436 return HAL_OK;
4437 }
4438
4439 /**
4440 * @brief Configures the OCRef clear feature
4441 * @param htim TIM handle
4442 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
4443 * contains the OCREF clear feature and parameters for the TIM peripheral.
4444 * @param Channel specifies the TIM Channel
4445 * This parameter can be one of the following values:
4446 * @arg TIM_CHANNEL_1: TIM Channel 1
4447 * @arg TIM_CHANNEL_2: TIM Channel 2
4448 * @arg TIM_CHANNEL_3: TIM Channel 3
4449 * @arg TIM_CHANNEL_4: TIM Channel 4
4450 * @arg TIM_CHANNEL_5: TIM Channel 5
4451 * @arg TIM_CHANNEL_6: TIM Channel 6
4452 * @retval HAL status
4453 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)4454 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
4455 TIM_ClearInputConfigTypeDef *sClearInputConfig,
4456 uint32_t Channel)
4457 {
4458 /* Check the parameters */
4459 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
4460 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
4461
4462 /* Process Locked */
4463 __HAL_LOCK(htim);
4464
4465 htim->State = HAL_TIM_STATE_BUSY;
4466
4467 switch (sClearInputConfig->ClearInputSource)
4468 {
4469 case TIM_CLEARINPUTSOURCE_NONE:
4470 {
4471 /* Clear the OCREF clear selection bit and the the ETR Bits */
4472 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
4473 break;
4474 }
4475
4476 case TIM_CLEARINPUTSOURCE_ETR:
4477 {
4478 /* Check the parameters */
4479 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
4480 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
4481 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
4482
4483 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
4484 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
4485 {
4486 htim->State = HAL_TIM_STATE_READY;
4487 __HAL_UNLOCK(htim);
4488 return HAL_ERROR;
4489 }
4490
4491 TIM_ETR_SetConfig(htim->Instance,
4492 sClearInputConfig->ClearInputPrescaler,
4493 sClearInputConfig->ClearInputPolarity,
4494 sClearInputConfig->ClearInputFilter);
4495 break;
4496 }
4497
4498 default:
4499 break;
4500 }
4501
4502 switch (Channel)
4503 {
4504 case TIM_CHANNEL_1:
4505 {
4506 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4507 {
4508 /* Enable the OCREF clear feature for Channel 1 */
4509 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
4510 }
4511 else
4512 {
4513 /* Disable the OCREF clear feature for Channel 1 */
4514 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
4515 }
4516 break;
4517 }
4518 case TIM_CHANNEL_2:
4519 {
4520 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4521 {
4522 /* Enable the OCREF clear feature for Channel 2 */
4523 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
4524 }
4525 else
4526 {
4527 /* Disable the OCREF clear feature for Channel 2 */
4528 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
4529 }
4530 break;
4531 }
4532 case TIM_CHANNEL_3:
4533 {
4534 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4535 {
4536 /* Enable the OCREF clear feature for Channel 3 */
4537 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
4538 }
4539 else
4540 {
4541 /* Disable the OCREF clear feature for Channel 3 */
4542 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
4543 }
4544 break;
4545 }
4546 case TIM_CHANNEL_4:
4547 {
4548 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4549 {
4550 /* Enable the OCREF clear feature for Channel 4 */
4551 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
4552 }
4553 else
4554 {
4555 /* Disable the OCREF clear feature for Channel 4 */
4556 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
4557 }
4558 break;
4559 }
4560 case TIM_CHANNEL_5:
4561 {
4562 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4563 {
4564 /* Enable the OCREF clear feature for Channel 5 */
4565 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
4566 }
4567 else
4568 {
4569 /* Disable the OCREF clear feature for Channel 5 */
4570 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
4571 }
4572 break;
4573 }
4574 case TIM_CHANNEL_6:
4575 {
4576 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
4577 {
4578 /* Enable the OCREF clear feature for Channel 6 */
4579 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
4580 }
4581 else
4582 {
4583 /* Disable the OCREF clear feature for Channel 6 */
4584 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
4585 }
4586 break;
4587 }
4588 default:
4589 break;
4590 }
4591
4592 htim->State = HAL_TIM_STATE_READY;
4593
4594 __HAL_UNLOCK(htim);
4595
4596 return HAL_OK;
4597 }
4598
4599 /**
4600 * @brief Configures the clock source to be used
4601 * @param htim TIM handle
4602 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
4603 * contains the clock source information for the TIM peripheral.
4604 * @retval HAL status
4605 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,TIM_ClockConfigTypeDef * sClockSourceConfig)4606 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
4607 {
4608 uint32_t tmpsmcr;
4609
4610 /* Process Locked */
4611 __HAL_LOCK(htim);
4612
4613 htim->State = HAL_TIM_STATE_BUSY;
4614
4615 /* Check the parameters */
4616 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
4617
4618 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
4619 tmpsmcr = htim->Instance->SMCR;
4620 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
4621 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
4622 htim->Instance->SMCR = tmpsmcr;
4623
4624 switch (sClockSourceConfig->ClockSource)
4625 {
4626 case TIM_CLOCKSOURCE_INTERNAL:
4627 {
4628 assert_param(IS_TIM_INSTANCE(htim->Instance));
4629 break;
4630 }
4631
4632 case TIM_CLOCKSOURCE_ETRMODE1:
4633 {
4634 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
4635 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
4636
4637 /* Check ETR input conditioning related parameters */
4638 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
4639 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4640 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4641
4642 /* Configure the ETR Clock source */
4643 TIM_ETR_SetConfig(htim->Instance,
4644 sClockSourceConfig->ClockPrescaler,
4645 sClockSourceConfig->ClockPolarity,
4646 sClockSourceConfig->ClockFilter);
4647
4648 /* Select the External clock mode1 and the ETRF trigger */
4649 tmpsmcr = htim->Instance->SMCR;
4650 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
4651 /* Write to TIMx SMCR */
4652 htim->Instance->SMCR = tmpsmcr;
4653 break;
4654 }
4655
4656 case TIM_CLOCKSOURCE_ETRMODE2:
4657 {
4658 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
4659 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
4660
4661 /* Check ETR input conditioning related parameters */
4662 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
4663 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4664 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4665
4666 /* Configure the ETR Clock source */
4667 TIM_ETR_SetConfig(htim->Instance,
4668 sClockSourceConfig->ClockPrescaler,
4669 sClockSourceConfig->ClockPolarity,
4670 sClockSourceConfig->ClockFilter);
4671 /* Enable the External clock mode2 */
4672 htim->Instance->SMCR |= TIM_SMCR_ECE;
4673 break;
4674 }
4675
4676 case TIM_CLOCKSOURCE_TI1:
4677 {
4678 /* Check whether or not the timer instance supports external clock mode 1 */
4679 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
4680
4681 /* Check TI1 input conditioning related parameters */
4682 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4683 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4684
4685 TIM_TI1_ConfigInputStage(htim->Instance,
4686 sClockSourceConfig->ClockPolarity,
4687 sClockSourceConfig->ClockFilter);
4688 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
4689 break;
4690 }
4691
4692 case TIM_CLOCKSOURCE_TI2:
4693 {
4694 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
4695 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
4696
4697 /* Check TI2 input conditioning related parameters */
4698 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4699 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4700
4701 TIM_TI2_ConfigInputStage(htim->Instance,
4702 sClockSourceConfig->ClockPolarity,
4703 sClockSourceConfig->ClockFilter);
4704 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
4705 break;
4706 }
4707
4708 case TIM_CLOCKSOURCE_TI1ED:
4709 {
4710 /* Check whether or not the timer instance supports external clock mode 1 */
4711 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
4712
4713 /* Check TI1 input conditioning related parameters */
4714 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4715 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4716
4717 TIM_TI1_ConfigInputStage(htim->Instance,
4718 sClockSourceConfig->ClockPolarity,
4719 sClockSourceConfig->ClockFilter);
4720 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
4721 break;
4722 }
4723
4724 case TIM_CLOCKSOURCE_ITR0:
4725 case TIM_CLOCKSOURCE_ITR1:
4726 case TIM_CLOCKSOURCE_ITR2:
4727 case TIM_CLOCKSOURCE_ITR3:
4728 {
4729 /* Check whether or not the timer instance supports internal trigger input */
4730 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
4731
4732 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
4733 break;
4734 }
4735
4736 default:
4737 break;
4738 }
4739 htim->State = HAL_TIM_STATE_READY;
4740
4741 __HAL_UNLOCK(htim);
4742
4743 return HAL_OK;
4744 }
4745
4746 /**
4747 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
4748 * or a XOR combination between CH1_input, CH2_input & CH3_input
4749 * @param htim TIM handle.
4750 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
4751 * output of a XOR gate.
4752 * This parameter can be one of the following values:
4753 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
4754 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
4755 * pins are connected to the TI1 input (XOR combination)
4756 * @retval HAL status
4757 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)4758 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
4759 {
4760 uint32_t tmpcr2;
4761
4762 /* Check the parameters */
4763 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
4764 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
4765
4766 /* Get the TIMx CR2 register value */
4767 tmpcr2 = htim->Instance->CR2;
4768
4769 /* Reset the TI1 selection */
4770 tmpcr2 &= ~TIM_CR2_TI1S;
4771
4772 /* Set the TI1 selection */
4773 tmpcr2 |= TI1_Selection;
4774
4775 /* Write to TIMxCR2 */
4776 htim->Instance->CR2 = tmpcr2;
4777
4778 return HAL_OK;
4779 }
4780
4781 /**
4782 * @brief Configures the TIM in Slave mode
4783 * @param htim TIM handle.
4784 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
4785 * contains the selected trigger (internal trigger input, filtered
4786 * timer input or external trigger input) and the Slave mode
4787 * (Disable, Reset, Gated, Trigger, External clock mode 1).
4788 * @retval HAL status
4789 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)4790 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
4791 {
4792 /* Check the parameters */
4793 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
4794 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
4795 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4796
4797 __HAL_LOCK(htim);
4798
4799 htim->State = HAL_TIM_STATE_BUSY;
4800
4801 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
4802 {
4803 htim->State = HAL_TIM_STATE_READY;
4804 __HAL_UNLOCK(htim);
4805 return HAL_ERROR;
4806 }
4807
4808 /* Disable Trigger Interrupt */
4809 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
4810
4811 /* Disable Trigger DMA request */
4812 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
4813
4814 htim->State = HAL_TIM_STATE_READY;
4815
4816 __HAL_UNLOCK(htim);
4817
4818 return HAL_OK;
4819 }
4820
4821 /**
4822 * @brief Configures the TIM in Slave mode in interrupt mode
4823 * @param htim TIM handle.
4824 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
4825 * contains the selected trigger (internal trigger input, filtered
4826 * timer input or external trigger input) and the Slave mode
4827 * (Disable, Reset, Gated, Trigger, External clock mode 1).
4828 * @retval HAL status
4829 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)4830 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
4831 TIM_SlaveConfigTypeDef *sSlaveConfig)
4832 {
4833 /* Check the parameters */
4834 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
4835 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
4836 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4837
4838 __HAL_LOCK(htim);
4839
4840 htim->State = HAL_TIM_STATE_BUSY;
4841
4842 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
4843 {
4844 htim->State = HAL_TIM_STATE_READY;
4845 __HAL_UNLOCK(htim);
4846 return HAL_ERROR;
4847 }
4848
4849 /* Enable Trigger Interrupt */
4850 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
4851
4852 /* Disable Trigger DMA request */
4853 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
4854
4855 htim->State = HAL_TIM_STATE_READY;
4856
4857 __HAL_UNLOCK(htim);
4858
4859 return HAL_OK;
4860 }
4861
4862 /**
4863 * @brief Read the captured value from Capture Compare unit
4864 * @param htim TIM handle.
4865 * @param Channel TIM Channels to be enabled
4866 * This parameter can be one of the following values:
4867 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4868 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4869 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4870 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4871 * @retval Captured value
4872 */
HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef * htim,uint32_t Channel)4873 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
4874 {
4875 uint32_t tmpreg = 0U;
4876
4877 switch (Channel)
4878 {
4879 case TIM_CHANNEL_1:
4880 {
4881 /* Check the parameters */
4882 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4883
4884 /* Return the capture 1 value */
4885 tmpreg = htim->Instance->CCR1;
4886
4887 break;
4888 }
4889 case TIM_CHANNEL_2:
4890 {
4891 /* Check the parameters */
4892 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4893
4894 /* Return the capture 2 value */
4895 tmpreg = htim->Instance->CCR2;
4896
4897 break;
4898 }
4899
4900 case TIM_CHANNEL_3:
4901 {
4902 /* Check the parameters */
4903 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4904
4905 /* Return the capture 3 value */
4906 tmpreg = htim->Instance->CCR3;
4907
4908 break;
4909 }
4910
4911 case TIM_CHANNEL_4:
4912 {
4913 /* Check the parameters */
4914 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4915
4916 /* Return the capture 4 value */
4917 tmpreg = htim->Instance->CCR4;
4918
4919 break;
4920 }
4921
4922 default:
4923 break;
4924 }
4925
4926 return tmpreg;
4927 }
4928
4929 /**
4930 * @}
4931 */
4932
4933 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
4934 * @brief TIM Callbacks functions
4935 *
4936 @verbatim
4937 ==============================================================================
4938 ##### TIM Callbacks functions #####
4939 ==============================================================================
4940 [..]
4941 This section provides TIM callback functions:
4942 (+) TIM Period elapsed callback
4943 (+) TIM Output Compare callback
4944 (+) TIM Input capture callback
4945 (+) TIM Trigger callback
4946 (+) TIM Error callback
4947
4948 @endverbatim
4949 * @{
4950 */
4951
4952 /**
4953 * @brief Period elapsed callback in non-blocking mode
4954 * @param htim TIM handle
4955 * @retval None
4956 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)4957 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
4958 {
4959 /* Prevent unused argument(s) compilation warning */
4960 UNUSED(htim);
4961
4962 /* NOTE : This function should not be modified, when the callback is needed,
4963 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
4964 */
4965 }
4966
4967 /**
4968 * @brief Period elapsed half complete callback in non-blocking mode
4969 * @param htim TIM handle
4970 * @retval None
4971 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)4972 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
4973 {
4974 /* Prevent unused argument(s) compilation warning */
4975 UNUSED(htim);
4976
4977 /* NOTE : This function should not be modified, when the callback is needed,
4978 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
4979 */
4980 }
4981
4982 /**
4983 * @brief Output Compare callback in non-blocking mode
4984 * @param htim TIM OC handle
4985 * @retval None
4986 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)4987 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
4988 {
4989 /* Prevent unused argument(s) compilation warning */
4990 UNUSED(htim);
4991
4992 /* NOTE : This function should not be modified, when the callback is needed,
4993 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
4994 */
4995 }
4996
4997 /**
4998 * @brief Input Capture callback in non-blocking mode
4999 * @param htim TIM IC handle
5000 * @retval None
5001 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)5002 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
5003 {
5004 /* Prevent unused argument(s) compilation warning */
5005 UNUSED(htim);
5006
5007 /* NOTE : This function should not be modified, when the callback is needed,
5008 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
5009 */
5010 }
5011
5012 /**
5013 * @brief Input Capture half complete callback in non-blocking mode
5014 * @param htim TIM IC handle
5015 * @retval None
5016 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)5017 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
5018 {
5019 /* Prevent unused argument(s) compilation warning */
5020 UNUSED(htim);
5021
5022 /* NOTE : This function should not be modified, when the callback is needed,
5023 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
5024 */
5025 }
5026
5027 /**
5028 * @brief PWM Pulse finished callback in non-blocking mode
5029 * @param htim TIM handle
5030 * @retval None
5031 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)5032 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
5033 {
5034 /* Prevent unused argument(s) compilation warning */
5035 UNUSED(htim);
5036
5037 /* NOTE : This function should not be modified, when the callback is needed,
5038 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
5039 */
5040 }
5041
5042 /**
5043 * @brief PWM Pulse finished half complete callback in non-blocking mode
5044 * @param htim TIM handle
5045 * @retval None
5046 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)5047 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
5048 {
5049 /* Prevent unused argument(s) compilation warning */
5050 UNUSED(htim);
5051
5052 /* NOTE : This function should not be modified, when the callback is needed,
5053 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
5054 */
5055 }
5056
5057 /**
5058 * @brief Hall Trigger detection callback in non-blocking mode
5059 * @param htim TIM handle
5060 * @retval None
5061 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)5062 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
5063 {
5064 /* Prevent unused argument(s) compilation warning */
5065 UNUSED(htim);
5066
5067 /* NOTE : This function should not be modified, when the callback is needed,
5068 the HAL_TIM_TriggerCallback could be implemented in the user file
5069 */
5070 }
5071
5072 /**
5073 * @brief Hall Trigger detection half complete callback in non-blocking mode
5074 * @param htim TIM handle
5075 * @retval None
5076 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)5077 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
5078 {
5079 /* Prevent unused argument(s) compilation warning */
5080 UNUSED(htim);
5081
5082 /* NOTE : This function should not be modified, when the callback is needed,
5083 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
5084 */
5085 }
5086
5087 /**
5088 * @brief Timer error callback in non-blocking mode
5089 * @param htim TIM handle
5090 * @retval None
5091 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)5092 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
5093 {
5094 /* Prevent unused argument(s) compilation warning */
5095 UNUSED(htim);
5096
5097 /* NOTE : This function should not be modified, when the callback is needed,
5098 the HAL_TIM_ErrorCallback could be implemented in the user file
5099 */
5100 }
5101
5102 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5103 /**
5104 * @brief Register a User TIM callback to be used instead of the weak predefined callback
5105 * @param htim tim handle
5106 * @param CallbackID ID of the callback to be registered
5107 * This parameter can be one of the following values:
5108 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5109 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5110 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5111 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5112 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5113 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5114 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5115 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5116 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5117 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5118 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5119 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5120 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5121 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5122 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5123 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5124 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5125 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5126 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5127 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5128 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5129 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5130 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5131 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5132 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5133 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
5134 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5135 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
5136 * @param pCallback pointer to the callback function
5137 * @retval status
5138 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)5139 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
5140 pTIM_CallbackTypeDef pCallback)
5141 {
5142 HAL_StatusTypeDef status = HAL_OK;
5143
5144 if (pCallback == NULL)
5145 {
5146 return HAL_ERROR;
5147 }
5148 /* Process locked */
5149 __HAL_LOCK(htim);
5150
5151 if (htim->State == HAL_TIM_STATE_READY)
5152 {
5153 switch (CallbackID)
5154 {
5155 case HAL_TIM_BASE_MSPINIT_CB_ID :
5156 htim->Base_MspInitCallback = pCallback;
5157 break;
5158
5159 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5160 htim->Base_MspDeInitCallback = pCallback;
5161 break;
5162
5163 case HAL_TIM_IC_MSPINIT_CB_ID :
5164 htim->IC_MspInitCallback = pCallback;
5165 break;
5166
5167 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5168 htim->IC_MspDeInitCallback = pCallback;
5169 break;
5170
5171 case HAL_TIM_OC_MSPINIT_CB_ID :
5172 htim->OC_MspInitCallback = pCallback;
5173 break;
5174
5175 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5176 htim->OC_MspDeInitCallback = pCallback;
5177 break;
5178
5179 case HAL_TIM_PWM_MSPINIT_CB_ID :
5180 htim->PWM_MspInitCallback = pCallback;
5181 break;
5182
5183 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5184 htim->PWM_MspDeInitCallback = pCallback;
5185 break;
5186
5187 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5188 htim->OnePulse_MspInitCallback = pCallback;
5189 break;
5190
5191 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5192 htim->OnePulse_MspDeInitCallback = pCallback;
5193 break;
5194
5195 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5196 htim->Encoder_MspInitCallback = pCallback;
5197 break;
5198
5199 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5200 htim->Encoder_MspDeInitCallback = pCallback;
5201 break;
5202
5203 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5204 htim->HallSensor_MspInitCallback = pCallback;
5205 break;
5206
5207 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5208 htim->HallSensor_MspDeInitCallback = pCallback;
5209 break;
5210
5211 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5212 htim->PeriodElapsedCallback = pCallback;
5213 break;
5214
5215 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5216 htim->PeriodElapsedHalfCpltCallback = pCallback;
5217 break;
5218
5219 case HAL_TIM_TRIGGER_CB_ID :
5220 htim->TriggerCallback = pCallback;
5221 break;
5222
5223 case HAL_TIM_TRIGGER_HALF_CB_ID :
5224 htim->TriggerHalfCpltCallback = pCallback;
5225 break;
5226
5227 case HAL_TIM_IC_CAPTURE_CB_ID :
5228 htim->IC_CaptureCallback = pCallback;
5229 break;
5230
5231 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5232 htim->IC_CaptureHalfCpltCallback = pCallback;
5233 break;
5234
5235 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5236 htim->OC_DelayElapsedCallback = pCallback;
5237 break;
5238
5239 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5240 htim->PWM_PulseFinishedCallback = pCallback;
5241 break;
5242
5243 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
5244 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
5245 break;
5246
5247 case HAL_TIM_ERROR_CB_ID :
5248 htim->ErrorCallback = pCallback;
5249 break;
5250
5251 case HAL_TIM_COMMUTATION_CB_ID :
5252 htim->CommutationCallback = pCallback;
5253 break;
5254
5255 case HAL_TIM_COMMUTATION_HALF_CB_ID :
5256 htim->CommutationHalfCpltCallback = pCallback;
5257 break;
5258
5259 case HAL_TIM_BREAK_CB_ID :
5260 htim->BreakCallback = pCallback;
5261 break;
5262
5263 case HAL_TIM_BREAK2_CB_ID :
5264 htim->Break2Callback = pCallback;
5265 break;
5266
5267 default :
5268 /* Return error status */
5269 status = HAL_ERROR;
5270 break;
5271 }
5272 }
5273 else if (htim->State == HAL_TIM_STATE_RESET)
5274 {
5275 switch (CallbackID)
5276 {
5277 case HAL_TIM_BASE_MSPINIT_CB_ID :
5278 htim->Base_MspInitCallback = pCallback;
5279 break;
5280
5281 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5282 htim->Base_MspDeInitCallback = pCallback;
5283 break;
5284
5285 case HAL_TIM_IC_MSPINIT_CB_ID :
5286 htim->IC_MspInitCallback = pCallback;
5287 break;
5288
5289 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5290 htim->IC_MspDeInitCallback = pCallback;
5291 break;
5292
5293 case HAL_TIM_OC_MSPINIT_CB_ID :
5294 htim->OC_MspInitCallback = pCallback;
5295 break;
5296
5297 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5298 htim->OC_MspDeInitCallback = pCallback;
5299 break;
5300
5301 case HAL_TIM_PWM_MSPINIT_CB_ID :
5302 htim->PWM_MspInitCallback = pCallback;
5303 break;
5304
5305 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5306 htim->PWM_MspDeInitCallback = pCallback;
5307 break;
5308
5309 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5310 htim->OnePulse_MspInitCallback = pCallback;
5311 break;
5312
5313 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5314 htim->OnePulse_MspDeInitCallback = pCallback;
5315 break;
5316
5317 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5318 htim->Encoder_MspInitCallback = pCallback;
5319 break;
5320
5321 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5322 htim->Encoder_MspDeInitCallback = pCallback;
5323 break;
5324
5325 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5326 htim->HallSensor_MspInitCallback = pCallback;
5327 break;
5328
5329 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5330 htim->HallSensor_MspDeInitCallback = pCallback;
5331 break;
5332
5333 default :
5334 /* Return error status */
5335 status = HAL_ERROR;
5336 break;
5337 }
5338 }
5339 else
5340 {
5341 /* Return error status */
5342 status = HAL_ERROR;
5343 }
5344
5345 /* Release Lock */
5346 __HAL_UNLOCK(htim);
5347
5348 return status;
5349 }
5350
5351 /**
5352 * @brief Unregister a TIM callback
5353 * TIM callback is redirected to the weak predefined callback
5354 * @param htim tim handle
5355 * @param CallbackID ID of the callback to be unregistered
5356 * This parameter can be one of the following values:
5357 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5358 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5359 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5360 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5361 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5362 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5363 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5364 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5365 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5366 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5367 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5368 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5369 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5370 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5371 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5372 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5373 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5374 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5375 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5376 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5377 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5378 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5379 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5380 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5381 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5382 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
5383 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5384 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
5385 * @retval status
5386 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)5387 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
5388 {
5389 HAL_StatusTypeDef status = HAL_OK;
5390
5391 /* Process locked */
5392 __HAL_LOCK(htim);
5393
5394 if (htim->State == HAL_TIM_STATE_READY)
5395 {
5396 switch (CallbackID)
5397 {
5398 case HAL_TIM_BASE_MSPINIT_CB_ID :
5399 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
5400 break;
5401
5402 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5403 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
5404 break;
5405
5406 case HAL_TIM_IC_MSPINIT_CB_ID :
5407 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
5408 break;
5409
5410 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5411 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
5412 break;
5413
5414 case HAL_TIM_OC_MSPINIT_CB_ID :
5415 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
5416 break;
5417
5418 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5419 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
5420 break;
5421
5422 case HAL_TIM_PWM_MSPINIT_CB_ID :
5423 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
5424 break;
5425
5426 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5427 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
5428 break;
5429
5430 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5431 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
5432 break;
5433
5434 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5435 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
5436 break;
5437
5438 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5439 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
5440 break;
5441
5442 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5443 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
5444 break;
5445
5446 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5447 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
5448 break;
5449
5450 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5451 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
5452 break;
5453
5454 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5455 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
5456 break;
5457
5458 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5459 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */
5460 break;
5461
5462 case HAL_TIM_TRIGGER_CB_ID :
5463 htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
5464 break;
5465
5466 case HAL_TIM_TRIGGER_HALF_CB_ID :
5467 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */
5468 break;
5469
5470 case HAL_TIM_IC_CAPTURE_CB_ID :
5471 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
5472 break;
5473
5474 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5475 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */
5476 break;
5477
5478 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5479 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
5480 break;
5481
5482 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5483 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
5484 break;
5485
5486 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
5487 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
5488 break;
5489
5490 case HAL_TIM_ERROR_CB_ID :
5491 htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
5492 break;
5493
5494 case HAL_TIM_COMMUTATION_CB_ID :
5495 htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */
5496 break;
5497
5498 case HAL_TIM_COMMUTATION_HALF_CB_ID :
5499 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */
5500 break;
5501
5502 case HAL_TIM_BREAK_CB_ID :
5503 htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
5504 break;
5505
5506 case HAL_TIM_BREAK2_CB_ID :
5507 htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */
5508 break;
5509
5510 default :
5511 /* Return error status */
5512 status = HAL_ERROR;
5513 break;
5514 }
5515 }
5516 else if (htim->State == HAL_TIM_STATE_RESET)
5517 {
5518 switch (CallbackID)
5519 {
5520 case HAL_TIM_BASE_MSPINIT_CB_ID :
5521 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
5522 break;
5523
5524 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5525 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
5526 break;
5527
5528 case HAL_TIM_IC_MSPINIT_CB_ID :
5529 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
5530 break;
5531
5532 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5533 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
5534 break;
5535
5536 case HAL_TIM_OC_MSPINIT_CB_ID :
5537 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
5538 break;
5539
5540 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5541 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
5542 break;
5543
5544 case HAL_TIM_PWM_MSPINIT_CB_ID :
5545 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
5546 break;
5547
5548 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5549 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
5550 break;
5551
5552 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5553 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
5554 break;
5555
5556 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5557 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
5558 break;
5559
5560 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5561 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
5562 break;
5563
5564 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5565 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
5566 break;
5567
5568 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5569 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
5570 break;
5571
5572 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5573 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
5574 break;
5575
5576 default :
5577 /* Return error status */
5578 status = HAL_ERROR;
5579 break;
5580 }
5581 }
5582 else
5583 {
5584 /* Return error status */
5585 status = HAL_ERROR;
5586 }
5587
5588 /* Release Lock */
5589 __HAL_UNLOCK(htim);
5590
5591 return status;
5592 }
5593 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5594
5595 /**
5596 * @}
5597 */
5598
5599 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
5600 * @brief TIM Peripheral State functions
5601 *
5602 @verbatim
5603 ==============================================================================
5604 ##### Peripheral State functions #####
5605 ==============================================================================
5606 [..]
5607 This subsection permits to get in run-time the status of the peripheral
5608 and the data flow.
5609
5610 @endverbatim
5611 * @{
5612 */
5613
5614 /**
5615 * @brief Return the TIM Base handle state.
5616 * @param htim TIM Base handle
5617 * @retval HAL state
5618 */
HAL_TIM_Base_GetState(TIM_HandleTypeDef * htim)5619 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
5620 {
5621 return htim->State;
5622 }
5623
5624 /**
5625 * @brief Return the TIM OC handle state.
5626 * @param htim TIM Output Compare handle
5627 * @retval HAL state
5628 */
HAL_TIM_OC_GetState(TIM_HandleTypeDef * htim)5629 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
5630 {
5631 return htim->State;
5632 }
5633
5634 /**
5635 * @brief Return the TIM PWM handle state.
5636 * @param htim TIM handle
5637 * @retval HAL state
5638 */
HAL_TIM_PWM_GetState(TIM_HandleTypeDef * htim)5639 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
5640 {
5641 return htim->State;
5642 }
5643
5644 /**
5645 * @brief Return the TIM Input Capture handle state.
5646 * @param htim TIM IC handle
5647 * @retval HAL state
5648 */
HAL_TIM_IC_GetState(TIM_HandleTypeDef * htim)5649 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
5650 {
5651 return htim->State;
5652 }
5653
5654 /**
5655 * @brief Return the TIM One Pulse Mode handle state.
5656 * @param htim TIM OPM handle
5657 * @retval HAL state
5658 */
HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef * htim)5659 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
5660 {
5661 return htim->State;
5662 }
5663
5664 /**
5665 * @brief Return the TIM Encoder Mode handle state.
5666 * @param htim TIM Encoder Interface handle
5667 * @retval HAL state
5668 */
HAL_TIM_Encoder_GetState(TIM_HandleTypeDef * htim)5669 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
5670 {
5671 return htim->State;
5672 }
5673
5674 /**
5675 * @}
5676 */
5677
5678 /**
5679 * @}
5680 */
5681
5682 /** @defgroup TIM_Private_Functions TIM Private Functions
5683 * @{
5684 */
5685
5686 /**
5687 * @brief TIM DMA error callback
5688 * @param hdma pointer to DMA handle.
5689 * @retval None
5690 */
TIM_DMAError(DMA_HandleTypeDef * hdma)5691 void TIM_DMAError(DMA_HandleTypeDef *hdma)
5692 {
5693 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5694
5695 htim->State = HAL_TIM_STATE_READY;
5696
5697 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5698 htim->ErrorCallback(htim);
5699 #else
5700 HAL_TIM_ErrorCallback(htim);
5701 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5702 }
5703
5704 /**
5705 * @brief TIM DMA Delay Pulse complete callback.
5706 * @param hdma pointer to DMA handle.
5707 * @retval None
5708 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)5709 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
5710 {
5711 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5712
5713 htim->State = HAL_TIM_STATE_READY;
5714
5715 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
5716 {
5717 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
5718 }
5719 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
5720 {
5721 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
5722 }
5723 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
5724 {
5725 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
5726 }
5727 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
5728 {
5729 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
5730 }
5731 else
5732 {
5733 /* nothing to do */
5734 }
5735
5736 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5737 htim->PWM_PulseFinishedCallback(htim);
5738 #else
5739 HAL_TIM_PWM_PulseFinishedCallback(htim);
5740 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5741
5742 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
5743 }
5744
5745 /**
5746 * @brief TIM DMA Delay Pulse half complete callback.
5747 * @param hdma pointer to DMA handle.
5748 * @retval None
5749 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)5750 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
5751 {
5752 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5753
5754 htim->State = HAL_TIM_STATE_READY;
5755
5756 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
5757 {
5758 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
5759 }
5760 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
5761 {
5762 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
5763 }
5764 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
5765 {
5766 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
5767 }
5768 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
5769 {
5770 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
5771 }
5772 else
5773 {
5774 /* nothing to do */
5775 }
5776
5777 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5778 htim->PWM_PulseFinishedHalfCpltCallback(htim);
5779 #else
5780 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
5781 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5782
5783 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
5784 }
5785
5786 /**
5787 * @brief TIM DMA Capture complete callback.
5788 * @param hdma pointer to DMA handle.
5789 * @retval None
5790 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)5791 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
5792 {
5793 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5794
5795 htim->State = HAL_TIM_STATE_READY;
5796
5797 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
5798 {
5799 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
5800 }
5801 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
5802 {
5803 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
5804 }
5805 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
5806 {
5807 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
5808 }
5809 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
5810 {
5811 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
5812 }
5813 else
5814 {
5815 /* nothing to do */
5816 }
5817
5818 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5819 htim->IC_CaptureCallback(htim);
5820 #else
5821 HAL_TIM_IC_CaptureCallback(htim);
5822 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5823
5824 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
5825 }
5826
5827 /**
5828 * @brief TIM DMA Capture half complete callback.
5829 * @param hdma pointer to DMA handle.
5830 * @retval None
5831 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)5832 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
5833 {
5834 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5835
5836 htim->State = HAL_TIM_STATE_READY;
5837
5838 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
5839 {
5840 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
5841 }
5842 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
5843 {
5844 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
5845 }
5846 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
5847 {
5848 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
5849 }
5850 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
5851 {
5852 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
5853 }
5854 else
5855 {
5856 /* nothing to do */
5857 }
5858
5859 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5860 htim->IC_CaptureHalfCpltCallback(htim);
5861 #else
5862 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
5863 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5864
5865 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
5866 }
5867
5868 /**
5869 * @brief TIM DMA Period Elapse complete callback.
5870 * @param hdma pointer to DMA handle.
5871 * @retval None
5872 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)5873 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
5874 {
5875 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5876
5877 htim->State = HAL_TIM_STATE_READY;
5878
5879 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5880 htim->PeriodElapsedCallback(htim);
5881 #else
5882 HAL_TIM_PeriodElapsedCallback(htim);
5883 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5884 }
5885
5886 /**
5887 * @brief TIM DMA Period Elapse half complete callback.
5888 * @param hdma pointer to DMA handle.
5889 * @retval None
5890 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)5891 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
5892 {
5893 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5894
5895 htim->State = HAL_TIM_STATE_READY;
5896
5897 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5898 htim->PeriodElapsedHalfCpltCallback(htim);
5899 #else
5900 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
5901 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5902 }
5903
5904 /**
5905 * @brief TIM DMA Trigger callback.
5906 * @param hdma pointer to DMA handle.
5907 * @retval None
5908 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)5909 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
5910 {
5911 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5912
5913 htim->State = HAL_TIM_STATE_READY;
5914
5915 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5916 htim->TriggerCallback(htim);
5917 #else
5918 HAL_TIM_TriggerCallback(htim);
5919 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5920 }
5921
5922 /**
5923 * @brief TIM DMA Trigger half complete callback.
5924 * @param hdma pointer to DMA handle.
5925 * @retval None
5926 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)5927 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
5928 {
5929 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
5930
5931 htim->State = HAL_TIM_STATE_READY;
5932
5933 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5934 htim->TriggerHalfCpltCallback(htim);
5935 #else
5936 HAL_TIM_TriggerHalfCpltCallback(htim);
5937 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
5938 }
5939
5940 /**
5941 * @brief Time Base configuration
5942 * @param TIMx TIM peripheral
5943 * @param Structure TIM Base configuration structure
5944 * @retval None
5945 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,TIM_Base_InitTypeDef * Structure)5946 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
5947 {
5948 uint32_t tmpcr1;
5949 tmpcr1 = TIMx->CR1;
5950
5951 /* Set TIM Time Base Unit parameters ---------------------------------------*/
5952 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
5953 {
5954 /* Select the Counter Mode */
5955 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
5956 tmpcr1 |= Structure->CounterMode;
5957 }
5958
5959 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
5960 {
5961 /* Set the clock division */
5962 tmpcr1 &= ~TIM_CR1_CKD;
5963 tmpcr1 |= (uint32_t)Structure->ClockDivision;
5964 }
5965
5966 /* Set the auto-reload preload */
5967 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
5968
5969 TIMx->CR1 = tmpcr1;
5970
5971 /* Set the Autoreload value */
5972 TIMx->ARR = (uint32_t)Structure->Period ;
5973
5974 /* Set the Prescaler value */
5975 TIMx->PSC = Structure->Prescaler;
5976
5977 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
5978 {
5979 /* Set the Repetition Counter value */
5980 TIMx->RCR = Structure->RepetitionCounter;
5981 }
5982
5983 /* Generate an update event to reload the Prescaler
5984 and the repetition counter (only for advanced timer) value immediately */
5985 TIMx->EGR = TIM_EGR_UG;
5986 }
5987
5988 /**
5989 * @brief Timer Output Compare 1 configuration
5990 * @param TIMx to select the TIM peripheral
5991 * @param OC_Config The ouput configuration structure
5992 * @retval None
5993 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)5994 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
5995 {
5996 uint32_t tmpccmrx;
5997 uint32_t tmpccer;
5998 uint32_t tmpcr2;
5999
6000 /* Disable the Channel 1: Reset the CC1E Bit */
6001 TIMx->CCER &= ~TIM_CCER_CC1E;
6002
6003 /* Get the TIMx CCER register value */
6004 tmpccer = TIMx->CCER;
6005 /* Get the TIMx CR2 register value */
6006 tmpcr2 = TIMx->CR2;
6007
6008 /* Get the TIMx CCMR1 register value */
6009 tmpccmrx = TIMx->CCMR1;
6010
6011 /* Reset the Output Compare Mode Bits */
6012 tmpccmrx &= ~TIM_CCMR1_OC1M;
6013 tmpccmrx &= ~TIM_CCMR1_CC1S;
6014 /* Select the Output Compare Mode */
6015 tmpccmrx |= OC_Config->OCMode;
6016
6017 /* Reset the Output Polarity level */
6018 tmpccer &= ~TIM_CCER_CC1P;
6019 /* Set the Output Compare Polarity */
6020 tmpccer |= OC_Config->OCPolarity;
6021
6022 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
6023 {
6024 /* Check parameters */
6025 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6026
6027 /* Reset the Output N Polarity level */
6028 tmpccer &= ~TIM_CCER_CC1NP;
6029 /* Set the Output N Polarity */
6030 tmpccer |= OC_Config->OCNPolarity;
6031 /* Reset the Output N State */
6032 tmpccer &= ~TIM_CCER_CC1NE;
6033 }
6034
6035 if (IS_TIM_BREAK_INSTANCE(TIMx))
6036 {
6037 /* Check parameters */
6038 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6039 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6040
6041 /* Reset the Output Compare and Output Compare N IDLE State */
6042 tmpcr2 &= ~TIM_CR2_OIS1;
6043 tmpcr2 &= ~TIM_CR2_OIS1N;
6044 /* Set the Output Idle state */
6045 tmpcr2 |= OC_Config->OCIdleState;
6046 /* Set the Output N Idle state */
6047 tmpcr2 |= OC_Config->OCNIdleState;
6048 }
6049
6050 /* Write to TIMx CR2 */
6051 TIMx->CR2 = tmpcr2;
6052
6053 /* Write to TIMx CCMR1 */
6054 TIMx->CCMR1 = tmpccmrx;
6055
6056 /* Set the Capture Compare Register value */
6057 TIMx->CCR1 = OC_Config->Pulse;
6058
6059 /* Write to TIMx CCER */
6060 TIMx->CCER = tmpccer;
6061 }
6062
6063 /**
6064 * @brief Timer Output Compare 2 configuration
6065 * @param TIMx to select the TIM peripheral
6066 * @param OC_Config The ouput configuration structure
6067 * @retval None
6068 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6069 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6070 {
6071 uint32_t tmpccmrx;
6072 uint32_t tmpccer;
6073 uint32_t tmpcr2;
6074
6075 /* Disable the Channel 2: Reset the CC2E Bit */
6076 TIMx->CCER &= ~TIM_CCER_CC2E;
6077
6078 /* Get the TIMx CCER register value */
6079 tmpccer = TIMx->CCER;
6080 /* Get the TIMx CR2 register value */
6081 tmpcr2 = TIMx->CR2;
6082
6083 /* Get the TIMx CCMR1 register value */
6084 tmpccmrx = TIMx->CCMR1;
6085
6086 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6087 tmpccmrx &= ~TIM_CCMR1_OC2M;
6088 tmpccmrx &= ~TIM_CCMR1_CC2S;
6089
6090 /* Select the Output Compare Mode */
6091 tmpccmrx |= (OC_Config->OCMode << 8U);
6092
6093 /* Reset the Output Polarity level */
6094 tmpccer &= ~TIM_CCER_CC2P;
6095 /* Set the Output Compare Polarity */
6096 tmpccer |= (OC_Config->OCPolarity << 4U);
6097
6098 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
6099 {
6100 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6101
6102 /* Reset the Output N Polarity level */
6103 tmpccer &= ~TIM_CCER_CC2NP;
6104 /* Set the Output N Polarity */
6105 tmpccer |= (OC_Config->OCNPolarity << 4U);
6106 /* Reset the Output N State */
6107 tmpccer &= ~TIM_CCER_CC2NE;
6108
6109 }
6110
6111 if (IS_TIM_BREAK_INSTANCE(TIMx))
6112 {
6113 /* Check parameters */
6114 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6115 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6116
6117 /* Reset the Output Compare and Output Compare N IDLE State */
6118 tmpcr2 &= ~TIM_CR2_OIS2;
6119 tmpcr2 &= ~TIM_CR2_OIS2N;
6120 /* Set the Output Idle state */
6121 tmpcr2 |= (OC_Config->OCIdleState << 2U);
6122 /* Set the Output N Idle state */
6123 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
6124 }
6125
6126 /* Write to TIMx CR2 */
6127 TIMx->CR2 = tmpcr2;
6128
6129 /* Write to TIMx CCMR1 */
6130 TIMx->CCMR1 = tmpccmrx;
6131
6132 /* Set the Capture Compare Register value */
6133 TIMx->CCR2 = OC_Config->Pulse;
6134
6135 /* Write to TIMx CCER */
6136 TIMx->CCER = tmpccer;
6137 }
6138
6139 /**
6140 * @brief Timer Output Compare 3 configuration
6141 * @param TIMx to select the TIM peripheral
6142 * @param OC_Config The ouput configuration structure
6143 * @retval None
6144 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6145 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6146 {
6147 uint32_t tmpccmrx;
6148 uint32_t tmpccer;
6149 uint32_t tmpcr2;
6150
6151 /* Disable the Channel 3: Reset the CC2E Bit */
6152 TIMx->CCER &= ~TIM_CCER_CC3E;
6153
6154 /* Get the TIMx CCER register value */
6155 tmpccer = TIMx->CCER;
6156 /* Get the TIMx CR2 register value */
6157 tmpcr2 = TIMx->CR2;
6158
6159 /* Get the TIMx CCMR2 register value */
6160 tmpccmrx = TIMx->CCMR2;
6161
6162 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6163 tmpccmrx &= ~TIM_CCMR2_OC3M;
6164 tmpccmrx &= ~TIM_CCMR2_CC3S;
6165 /* Select the Output Compare Mode */
6166 tmpccmrx |= OC_Config->OCMode;
6167
6168 /* Reset the Output Polarity level */
6169 tmpccer &= ~TIM_CCER_CC3P;
6170 /* Set the Output Compare Polarity */
6171 tmpccer |= (OC_Config->OCPolarity << 8U);
6172
6173 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
6174 {
6175 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6176
6177 /* Reset the Output N Polarity level */
6178 tmpccer &= ~TIM_CCER_CC3NP;
6179 /* Set the Output N Polarity */
6180 tmpccer |= (OC_Config->OCNPolarity << 8U);
6181 /* Reset the Output N State */
6182 tmpccer &= ~TIM_CCER_CC3NE;
6183 }
6184
6185 if (IS_TIM_BREAK_INSTANCE(TIMx))
6186 {
6187 /* Check parameters */
6188 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6189 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6190
6191 /* Reset the Output Compare and Output Compare N IDLE State */
6192 tmpcr2 &= ~TIM_CR2_OIS3;
6193 tmpcr2 &= ~TIM_CR2_OIS3N;
6194 /* Set the Output Idle state */
6195 tmpcr2 |= (OC_Config->OCIdleState << 4U);
6196 /* Set the Output N Idle state */
6197 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
6198 }
6199
6200 /* Write to TIMx CR2 */
6201 TIMx->CR2 = tmpcr2;
6202
6203 /* Write to TIMx CCMR2 */
6204 TIMx->CCMR2 = tmpccmrx;
6205
6206 /* Set the Capture Compare Register value */
6207 TIMx->CCR3 = OC_Config->Pulse;
6208
6209 /* Write to TIMx CCER */
6210 TIMx->CCER = tmpccer;
6211 }
6212
6213 /**
6214 * @brief Timer Output Compare 4 configuration
6215 * @param TIMx to select the TIM peripheral
6216 * @param OC_Config The ouput configuration structure
6217 * @retval None
6218 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6219 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6220 {
6221 uint32_t tmpccmrx;
6222 uint32_t tmpccer;
6223 uint32_t tmpcr2;
6224
6225 /* Disable the Channel 4: Reset the CC4E Bit */
6226 TIMx->CCER &= ~TIM_CCER_CC4E;
6227
6228 /* Get the TIMx CCER register value */
6229 tmpccer = TIMx->CCER;
6230 /* Get the TIMx CR2 register value */
6231 tmpcr2 = TIMx->CR2;
6232
6233 /* Get the TIMx CCMR2 register value */
6234 tmpccmrx = TIMx->CCMR2;
6235
6236 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6237 tmpccmrx &= ~TIM_CCMR2_OC4M;
6238 tmpccmrx &= ~TIM_CCMR2_CC4S;
6239
6240 /* Select the Output Compare Mode */
6241 tmpccmrx |= (OC_Config->OCMode << 8U);
6242
6243 /* Reset the Output Polarity level */
6244 tmpccer &= ~TIM_CCER_CC4P;
6245 /* Set the Output Compare Polarity */
6246 tmpccer |= (OC_Config->OCPolarity << 12U);
6247
6248 if (IS_TIM_BREAK_INSTANCE(TIMx))
6249 {
6250 /* Check parameters */
6251 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6252
6253 /* Reset the Output Compare IDLE State */
6254 tmpcr2 &= ~TIM_CR2_OIS4;
6255
6256 /* Set the Output Idle state */
6257 tmpcr2 |= (OC_Config->OCIdleState << 6U);
6258 }
6259
6260 /* Write to TIMx CR2 */
6261 TIMx->CR2 = tmpcr2;
6262
6263 /* Write to TIMx CCMR2 */
6264 TIMx->CCMR2 = tmpccmrx;
6265
6266 /* Set the Capture Compare Register value */
6267 TIMx->CCR4 = OC_Config->Pulse;
6268
6269 /* Write to TIMx CCER */
6270 TIMx->CCER = tmpccer;
6271 }
6272
6273 /**
6274 * @brief Timer Output Compare 5 configuration
6275 * @param TIMx to select the TIM peripheral
6276 * @param OC_Config The ouput configuration structure
6277 * @retval None
6278 */
TIM_OC5_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6279 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
6280 TIM_OC_InitTypeDef *OC_Config)
6281 {
6282 uint32_t tmpccmrx;
6283 uint32_t tmpccer;
6284 uint32_t tmpcr2;
6285
6286 /* Disable the output: Reset the CCxE Bit */
6287 TIMx->CCER &= ~TIM_CCER_CC5E;
6288
6289 /* Get the TIMx CCER register value */
6290 tmpccer = TIMx->CCER;
6291 /* Get the TIMx CR2 register value */
6292 tmpcr2 = TIMx->CR2;
6293 /* Get the TIMx CCMR1 register value */
6294 tmpccmrx = TIMx->CCMR3;
6295
6296 /* Reset the Output Compare Mode Bits */
6297 tmpccmrx &= ~(TIM_CCMR3_OC5M);
6298 /* Select the Output Compare Mode */
6299 tmpccmrx |= OC_Config->OCMode;
6300
6301 /* Reset the Output Polarity level */
6302 tmpccer &= ~TIM_CCER_CC5P;
6303 /* Set the Output Compare Polarity */
6304 tmpccer |= (OC_Config->OCPolarity << 16U);
6305
6306 if (IS_TIM_BREAK_INSTANCE(TIMx))
6307 {
6308 /* Reset the Output Compare IDLE State */
6309 tmpcr2 &= ~TIM_CR2_OIS5;
6310 /* Set the Output Idle state */
6311 tmpcr2 |= (OC_Config->OCIdleState << 8U);
6312 }
6313 /* Write to TIMx CR2 */
6314 TIMx->CR2 = tmpcr2;
6315
6316 /* Write to TIMx CCMR3 */
6317 TIMx->CCMR3 = tmpccmrx;
6318
6319 /* Set the Capture Compare Register value */
6320 TIMx->CCR5 = OC_Config->Pulse;
6321
6322 /* Write to TIMx CCER */
6323 TIMx->CCER = tmpccer;
6324 }
6325
6326 /**
6327 * @brief Timer Output Compare 6 configuration
6328 * @param TIMx to select the TIM peripheral
6329 * @param OC_Config The ouput configuration structure
6330 * @retval None
6331 */
TIM_OC6_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6332 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
6333 TIM_OC_InitTypeDef *OC_Config)
6334 {
6335 uint32_t tmpccmrx;
6336 uint32_t tmpccer;
6337 uint32_t tmpcr2;
6338
6339 /* Disable the output: Reset the CCxE Bit */
6340 TIMx->CCER &= ~TIM_CCER_CC6E;
6341
6342 /* Get the TIMx CCER register value */
6343 tmpccer = TIMx->CCER;
6344 /* Get the TIMx CR2 register value */
6345 tmpcr2 = TIMx->CR2;
6346 /* Get the TIMx CCMR1 register value */
6347 tmpccmrx = TIMx->CCMR3;
6348
6349 /* Reset the Output Compare Mode Bits */
6350 tmpccmrx &= ~(TIM_CCMR3_OC6M);
6351 /* Select the Output Compare Mode */
6352 tmpccmrx |= (OC_Config->OCMode << 8U);
6353
6354 /* Reset the Output Polarity level */
6355 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
6356 /* Set the Output Compare Polarity */
6357 tmpccer |= (OC_Config->OCPolarity << 20U);
6358
6359 if (IS_TIM_BREAK_INSTANCE(TIMx))
6360 {
6361 /* Reset the Output Compare IDLE State */
6362 tmpcr2 &= ~TIM_CR2_OIS6;
6363 /* Set the Output Idle state */
6364 tmpcr2 |= (OC_Config->OCIdleState << 10U);
6365 }
6366
6367 /* Write to TIMx CR2 */
6368 TIMx->CR2 = tmpcr2;
6369
6370 /* Write to TIMx CCMR3 */
6371 TIMx->CCMR3 = tmpccmrx;
6372
6373 /* Set the Capture Compare Register value */
6374 TIMx->CCR6 = OC_Config->Pulse;
6375
6376 /* Write to TIMx CCER */
6377 TIMx->CCER = tmpccer;
6378 }
6379
6380 /**
6381 * @brief Slave Timer configuration function
6382 * @param htim TIM handle
6383 * @param sSlaveConfig Slave timer configuration
6384 * @retval None
6385 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)6386 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
6387 TIM_SlaveConfigTypeDef *sSlaveConfig)
6388 {
6389 uint32_t tmpsmcr;
6390 uint32_t tmpccmr1;
6391 uint32_t tmpccer;
6392
6393 /* Get the TIMx SMCR register value */
6394 tmpsmcr = htim->Instance->SMCR;
6395
6396 /* Reset the Trigger Selection Bits */
6397 tmpsmcr &= ~TIM_SMCR_TS;
6398 /* Set the Input Trigger source */
6399 tmpsmcr |= sSlaveConfig->InputTrigger;
6400
6401 /* Reset the slave mode Bits */
6402 tmpsmcr &= ~TIM_SMCR_SMS;
6403 /* Set the slave mode */
6404 tmpsmcr |= sSlaveConfig->SlaveMode;
6405
6406 /* Write to TIMx SMCR */
6407 htim->Instance->SMCR = tmpsmcr;
6408
6409 /* Configure the trigger prescaler, filter, and polarity */
6410 switch (sSlaveConfig->InputTrigger)
6411 {
6412 case TIM_TS_ETRF:
6413 {
6414 /* Check the parameters */
6415 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
6416 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
6417 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6418 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6419 /* Configure the ETR Trigger source */
6420 TIM_ETR_SetConfig(htim->Instance,
6421 sSlaveConfig->TriggerPrescaler,
6422 sSlaveConfig->TriggerPolarity,
6423 sSlaveConfig->TriggerFilter);
6424 break;
6425 }
6426
6427 case TIM_TS_TI1F_ED:
6428 {
6429 /* Check the parameters */
6430 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
6431 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6432
6433 if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
6434 {
6435 return HAL_ERROR;
6436 }
6437
6438 /* Disable the Channel 1: Reset the CC1E Bit */
6439 tmpccer = htim->Instance->CCER;
6440 htim->Instance->CCER &= ~TIM_CCER_CC1E;
6441 tmpccmr1 = htim->Instance->CCMR1;
6442
6443 /* Set the filter */
6444 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6445 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
6446
6447 /* Write to TIMx CCMR1 and CCER registers */
6448 htim->Instance->CCMR1 = tmpccmr1;
6449 htim->Instance->CCER = tmpccer;
6450 break;
6451 }
6452
6453 case TIM_TS_TI1FP1:
6454 {
6455 /* Check the parameters */
6456 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
6457 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6458 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6459
6460 /* Configure TI1 Filter and Polarity */
6461 TIM_TI1_ConfigInputStage(htim->Instance,
6462 sSlaveConfig->TriggerPolarity,
6463 sSlaveConfig->TriggerFilter);
6464 break;
6465 }
6466
6467 case TIM_TS_TI2FP2:
6468 {
6469 /* Check the parameters */
6470 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
6471 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
6472 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
6473
6474 /* Configure TI2 Filter and Polarity */
6475 TIM_TI2_ConfigInputStage(htim->Instance,
6476 sSlaveConfig->TriggerPolarity,
6477 sSlaveConfig->TriggerFilter);
6478 break;
6479 }
6480
6481 case TIM_TS_ITR0:
6482 case TIM_TS_ITR1:
6483 case TIM_TS_ITR2:
6484 case TIM_TS_ITR3:
6485 {
6486 /* Check the parameter */
6487 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
6488 break;
6489 }
6490
6491 default:
6492 break;
6493 }
6494 return HAL_OK;
6495 }
6496
6497 /**
6498 * @brief Configure the TI1 as Input.
6499 * @param TIMx to select the TIM peripheral.
6500 * @param TIM_ICPolarity The Input Polarity.
6501 * This parameter can be one of the following values:
6502 * @arg TIM_ICPOLARITY_RISING
6503 * @arg TIM_ICPOLARITY_FALLING
6504 * @arg TIM_ICPOLARITY_BOTHEDGE
6505 * @param TIM_ICSelection specifies the input to be used.
6506 * This parameter can be one of the following values:
6507 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
6508 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
6509 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
6510 * @param TIM_ICFilter Specifies the Input Capture Filter.
6511 * This parameter must be a value between 0x00 and 0x0F.
6512 * @retval None
6513 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
6514 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
6515 * protected against un-initialized filter and polarity values.
6516 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6517 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6518 uint32_t TIM_ICFilter)
6519 {
6520 uint32_t tmpccmr1;
6521 uint32_t tmpccer;
6522
6523 /* Disable the Channel 1: Reset the CC1E Bit */
6524 TIMx->CCER &= ~TIM_CCER_CC1E;
6525 tmpccmr1 = TIMx->CCMR1;
6526 tmpccer = TIMx->CCER;
6527
6528 /* Select the Input */
6529 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
6530 {
6531 tmpccmr1 &= ~TIM_CCMR1_CC1S;
6532 tmpccmr1 |= TIM_ICSelection;
6533 }
6534 else
6535 {
6536 tmpccmr1 |= TIM_CCMR1_CC1S_0;
6537 }
6538
6539 /* Set the filter */
6540 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6541 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
6542
6543 /* Select the Polarity and set the CC1E Bit */
6544 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
6545 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
6546
6547 /* Write to TIMx CCMR1 and CCER registers */
6548 TIMx->CCMR1 = tmpccmr1;
6549 TIMx->CCER = tmpccer;
6550 }
6551
6552 /**
6553 * @brief Configure the Polarity and Filter for TI1.
6554 * @param TIMx to select the TIM peripheral.
6555 * @param TIM_ICPolarity The Input Polarity.
6556 * This parameter can be one of the following values:
6557 * @arg TIM_ICPOLARITY_RISING
6558 * @arg TIM_ICPOLARITY_FALLING
6559 * @arg TIM_ICPOLARITY_BOTHEDGE
6560 * @param TIM_ICFilter Specifies the Input Capture Filter.
6561 * This parameter must be a value between 0x00 and 0x0F.
6562 * @retval None
6563 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)6564 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
6565 {
6566 uint32_t tmpccmr1;
6567 uint32_t tmpccer;
6568
6569 /* Disable the Channel 1: Reset the CC1E Bit */
6570 tmpccer = TIMx->CCER;
6571 TIMx->CCER &= ~TIM_CCER_CC1E;
6572 tmpccmr1 = TIMx->CCMR1;
6573
6574 /* Set the filter */
6575 tmpccmr1 &= ~TIM_CCMR1_IC1F;
6576 tmpccmr1 |= (TIM_ICFilter << 4U);
6577
6578 /* Select the Polarity and set the CC1E Bit */
6579 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
6580 tmpccer |= TIM_ICPolarity;
6581
6582 /* Write to TIMx CCMR1 and CCER registers */
6583 TIMx->CCMR1 = tmpccmr1;
6584 TIMx->CCER = tmpccer;
6585 }
6586
6587 /**
6588 * @brief Configure the TI2 as Input.
6589 * @param TIMx to select the TIM peripheral
6590 * @param TIM_ICPolarity The Input Polarity.
6591 * This parameter can be one of the following values:
6592 * @arg TIM_ICPOLARITY_RISING
6593 * @arg TIM_ICPOLARITY_FALLING
6594 * @arg TIM_ICPOLARITY_BOTHEDGE
6595 * @param TIM_ICSelection specifies the input to be used.
6596 * This parameter can be one of the following values:
6597 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
6598 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
6599 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
6600 * @param TIM_ICFilter Specifies the Input Capture Filter.
6601 * This parameter must be a value between 0x00 and 0x0F.
6602 * @retval None
6603 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
6604 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
6605 * protected against un-initialized filter and polarity values.
6606 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6607 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6608 uint32_t TIM_ICFilter)
6609 {
6610 uint32_t tmpccmr1;
6611 uint32_t tmpccer;
6612
6613 /* Disable the Channel 2: Reset the CC2E Bit */
6614 TIMx->CCER &= ~TIM_CCER_CC2E;
6615 tmpccmr1 = TIMx->CCMR1;
6616 tmpccer = TIMx->CCER;
6617
6618 /* Select the Input */
6619 tmpccmr1 &= ~TIM_CCMR1_CC2S;
6620 tmpccmr1 |= (TIM_ICSelection << 8U);
6621
6622 /* Set the filter */
6623 tmpccmr1 &= ~TIM_CCMR1_IC2F;
6624 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
6625
6626 /* Select the Polarity and set the CC2E Bit */
6627 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
6628 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
6629
6630 /* Write to TIMx CCMR1 and CCER registers */
6631 TIMx->CCMR1 = tmpccmr1 ;
6632 TIMx->CCER = tmpccer;
6633 }
6634
6635 /**
6636 * @brief Configure the Polarity and Filter for TI2.
6637 * @param TIMx to select the TIM peripheral.
6638 * @param TIM_ICPolarity The Input Polarity.
6639 * This parameter can be one of the following values:
6640 * @arg TIM_ICPOLARITY_RISING
6641 * @arg TIM_ICPOLARITY_FALLING
6642 * @arg TIM_ICPOLARITY_BOTHEDGE
6643 * @param TIM_ICFilter Specifies the Input Capture Filter.
6644 * This parameter must be a value between 0x00 and 0x0F.
6645 * @retval None
6646 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)6647 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
6648 {
6649 uint32_t tmpccmr1;
6650 uint32_t tmpccer;
6651
6652 /* Disable the Channel 2: Reset the CC2E Bit */
6653 TIMx->CCER &= ~TIM_CCER_CC2E;
6654 tmpccmr1 = TIMx->CCMR1;
6655 tmpccer = TIMx->CCER;
6656
6657 /* Set the filter */
6658 tmpccmr1 &= ~TIM_CCMR1_IC2F;
6659 tmpccmr1 |= (TIM_ICFilter << 12U);
6660
6661 /* Select the Polarity and set the CC2E Bit */
6662 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
6663 tmpccer |= (TIM_ICPolarity << 4U);
6664
6665 /* Write to TIMx CCMR1 and CCER registers */
6666 TIMx->CCMR1 = tmpccmr1 ;
6667 TIMx->CCER = tmpccer;
6668 }
6669
6670 /**
6671 * @brief Configure the TI3 as Input.
6672 * @param TIMx to select the TIM peripheral
6673 * @param TIM_ICPolarity The Input Polarity.
6674 * This parameter can be one of the following values:
6675 * @arg TIM_ICPOLARITY_RISING
6676 * @arg TIM_ICPOLARITY_FALLING
6677 * @arg TIM_ICPOLARITY_BOTHEDGE
6678 * @param TIM_ICSelection specifies the input to be used.
6679 * This parameter can be one of the following values:
6680 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
6681 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
6682 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
6683 * @param TIM_ICFilter Specifies the Input Capture Filter.
6684 * This parameter must be a value between 0x00 and 0x0F.
6685 * @retval None
6686 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
6687 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
6688 * protected against un-initialized filter and polarity values.
6689 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6690 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6691 uint32_t TIM_ICFilter)
6692 {
6693 uint32_t tmpccmr2;
6694 uint32_t tmpccer;
6695
6696 /* Disable the Channel 3: Reset the CC3E Bit */
6697 TIMx->CCER &= ~TIM_CCER_CC3E;
6698 tmpccmr2 = TIMx->CCMR2;
6699 tmpccer = TIMx->CCER;
6700
6701 /* Select the Input */
6702 tmpccmr2 &= ~TIM_CCMR2_CC3S;
6703 tmpccmr2 |= TIM_ICSelection;
6704
6705 /* Set the filter */
6706 tmpccmr2 &= ~TIM_CCMR2_IC3F;
6707 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
6708
6709 /* Select the Polarity and set the CC3E Bit */
6710 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
6711 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
6712
6713 /* Write to TIMx CCMR2 and CCER registers */
6714 TIMx->CCMR2 = tmpccmr2;
6715 TIMx->CCER = tmpccer;
6716 }
6717
6718 /**
6719 * @brief Configure the TI4 as Input.
6720 * @param TIMx to select the TIM peripheral
6721 * @param TIM_ICPolarity The Input Polarity.
6722 * This parameter can be one of the following values:
6723 * @arg TIM_ICPOLARITY_RISING
6724 * @arg TIM_ICPOLARITY_FALLING
6725 * @arg TIM_ICPOLARITY_BOTHEDGE
6726 * @param TIM_ICSelection specifies the input to be used.
6727 * This parameter can be one of the following values:
6728 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
6729 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
6730 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
6731 * @param TIM_ICFilter Specifies the Input Capture Filter.
6732 * This parameter must be a value between 0x00 and 0x0F.
6733 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
6734 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
6735 * protected against un-initialized filter and polarity values.
6736 * @retval None
6737 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)6738 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
6739 uint32_t TIM_ICFilter)
6740 {
6741 uint32_t tmpccmr2;
6742 uint32_t tmpccer;
6743
6744 /* Disable the Channel 4: Reset the CC4E Bit */
6745 TIMx->CCER &= ~TIM_CCER_CC4E;
6746 tmpccmr2 = TIMx->CCMR2;
6747 tmpccer = TIMx->CCER;
6748
6749 /* Select the Input */
6750 tmpccmr2 &= ~TIM_CCMR2_CC4S;
6751 tmpccmr2 |= (TIM_ICSelection << 8U);
6752
6753 /* Set the filter */
6754 tmpccmr2 &= ~TIM_CCMR2_IC4F;
6755 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
6756
6757 /* Select the Polarity and set the CC4E Bit */
6758 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
6759 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
6760
6761 /* Write to TIMx CCMR2 and CCER registers */
6762 TIMx->CCMR2 = tmpccmr2;
6763 TIMx->CCER = tmpccer ;
6764 }
6765
6766 /**
6767 * @brief Selects the Input Trigger source
6768 * @param TIMx to select the TIM peripheral
6769 * @param InputTriggerSource The Input Trigger source.
6770 * This parameter can be one of the following values:
6771 * @arg TIM_TS_ITR0: Internal Trigger 0
6772 * @arg TIM_TS_ITR1: Internal Trigger 1
6773 * @arg TIM_TS_ITR2: Internal Trigger 2
6774 * @arg TIM_TS_ITR3: Internal Trigger 3
6775 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
6776 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
6777 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
6778 * @arg TIM_TS_ETRF: External Trigger input
6779 * @retval None
6780 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)6781 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
6782 {
6783 uint32_t tmpsmcr;
6784
6785 /* Get the TIMx SMCR register value */
6786 tmpsmcr = TIMx->SMCR;
6787 /* Reset the TS Bits */
6788 tmpsmcr &= ~TIM_SMCR_TS;
6789 /* Set the Input Trigger source and the slave mode*/
6790 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
6791 /* Write to TIMx SMCR */
6792 TIMx->SMCR = tmpsmcr;
6793 }
6794 /**
6795 * @brief Configures the TIMx External Trigger (ETR).
6796 * @param TIMx to select the TIM peripheral
6797 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
6798 * This parameter can be one of the following values:
6799 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
6800 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
6801 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
6802 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
6803 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
6804 * This parameter can be one of the following values:
6805 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
6806 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
6807 * @param ExtTRGFilter External Trigger Filter.
6808 * This parameter must be a value between 0x00 and 0x0F
6809 * @retval None
6810 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)6811 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
6812 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
6813 {
6814 uint32_t tmpsmcr;
6815
6816 tmpsmcr = TIMx->SMCR;
6817
6818 /* Reset the ETR Bits */
6819 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
6820
6821 /* Set the Prescaler, the Filter value and the Polarity */
6822 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
6823
6824 /* Write to TIMx SMCR */
6825 TIMx->SMCR = tmpsmcr;
6826 }
6827
6828 /**
6829 * @brief Enables or disables the TIM Capture Compare Channel x.
6830 * @param TIMx to select the TIM peripheral
6831 * @param Channel specifies the TIM Channel
6832 * This parameter can be one of the following values:
6833 * @arg TIM_CHANNEL_1: TIM Channel 1
6834 * @arg TIM_CHANNEL_2: TIM Channel 2
6835 * @arg TIM_CHANNEL_3: TIM Channel 3
6836 * @arg TIM_CHANNEL_4: TIM Channel 4
6837 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
6838 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
6839 * @param ChannelState specifies the TIM Channel CCxE bit new state.
6840 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
6841 * @retval None
6842 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)6843 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
6844 {
6845 uint32_t tmp;
6846
6847 /* Check the parameters */
6848 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
6849 assert_param(IS_TIM_CHANNELS(Channel));
6850
6851 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
6852
6853 /* Reset the CCxE Bit */
6854 TIMx->CCER &= ~tmp;
6855
6856 /* Set or reset the CCxE Bit */
6857 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
6858 }
6859
6860 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6861 /**
6862 * @brief Reset interrupt callbacks to the legacy weak callbacks.
6863 * @param htim pointer to a TIM_HandleTypeDef structure that contains
6864 * the configuration information for TIM module.
6865 * @retval None
6866 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)6867 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
6868 {
6869 /* Reset the TIM callback to the legacy weak callbacks */
6870 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
6871 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */
6872 htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
6873 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */
6874 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
6875 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */
6876 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
6877 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
6878 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
6879 htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
6880 htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */
6881 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */
6882 htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
6883 htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */
6884 }
6885 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6886
6887 /**
6888 * @}
6889 */
6890
6891 #endif /* HAL_TIM_MODULE_ENABLED */
6892 /**
6893 * @}
6894 */
6895
6896 /**
6897 * @}
6898 */
6899
