1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_hal_spi_ex.c
4 * @author MCD Application Team
5 * @brief Extended SPI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * SPI peripheral extended functionalities :
8 * + IO operation functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2019 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 */
23
24 /* Includes ------------------------------------------------------------------*/
25 #include "stm32mp1xx_hal.h"
26
27 /** @addtogroup STM32MP1xx_HAL_Driver
28 * @{
29 */
30
31 /** @defgroup SPIEx SPIEx
32 * @brief SPI Extended HAL module driver
33 * @{
34 */
35 #ifdef HAL_SPI_MODULE_ENABLED
36
37 /* Private typedef -----------------------------------------------------------*/
38 /* Private defines -----------------------------------------------------------*/
39 /* Private macros ------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private function prototypes -----------------------------------------------*/
42 /* Exported functions --------------------------------------------------------*/
43
44 /** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
45 * @{
46 */
47
48 /** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
49 * @brief Data transfers functions
50 *
51 @verbatim
52 ==============================================================================
53 ##### IO operation functions #####
54 ===============================================================================
55 [..]
56 This subsection provides a set of extended functions to manage the SPI
57 data transfers.
58
59 (#) SPIEx function:
60 (++) HAL_SPIEx_FlushRxFifo()
61 (++) HAL_SPIEx_FlushRxFifo()
62 (++) HAL_SPIEx_EnableLockConfiguration()
63 (++) HAL_SPIEx_ConfigureUnderrun()
64
65 @endverbatim
66 * @{
67 */
68
69 /**
70 * @brief Flush the RX fifo.
71 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
72 * the configuration information for the specified SPI module.
73 * @retval HAL status
74 */
HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef * hspi)75 HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi)
76 {
77 uint8_t count = 0;
78 uint32_t itflag = hspi->Instance->SR;
79 __IO uint32_t tmpreg;
80
81 while (((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_RX_FIFO_0PACKET) || ((itflag & SPI_FLAG_RXWNE) != 0UL))
82 {
83 count += (uint8_t)4UL;
84 tmpreg = hspi->Instance->RXDR;
85 UNUSED(tmpreg); /* To avoid GCC warning */
86
87 if (IS_SPI_HIGHEND_INSTANCE(hspi->Instance))
88 {
89 if (count > SPI_HIGHEND_FIFO_SIZE)
90 {
91 return HAL_TIMEOUT;
92 }
93 }
94 else
95 {
96 if (count > SPI_LOWEND_FIFO_SIZE)
97 {
98 return HAL_TIMEOUT;
99 }
100 }
101 }
102 return HAL_OK;
103 }
104
105
106 /**
107 * @brief Enable the Lock for the AF configuration of associated IOs
108 * and write protect the Content of Configuration register 2
109 * when SPI is enabled
110 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
111 * the configuration information for SPI module.
112 * @retval None
113 */
HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef * hspi)114 HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi)
115 {
116 HAL_StatusTypeDef errorcode = HAL_OK;
117
118 /* Process Locked */
119 __HAL_LOCK(hspi);
120
121 if (hspi->State != HAL_SPI_STATE_READY)
122 {
123 errorcode = HAL_BUSY;
124 hspi->State = HAL_SPI_STATE_READY;
125 /* Process Unlocked */
126 __HAL_UNLOCK(hspi);
127 return errorcode;
128 }
129
130 /* Check if the SPI is disabled to edit IOLOCK bit */
131 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
132 {
133 SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK);
134 }
135 else
136 {
137 /* Disable SPI peripheral */
138 __HAL_SPI_DISABLE(hspi);
139
140 SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK);
141
142 /* Enable SPI peripheral */
143 __HAL_SPI_ENABLE(hspi);
144 }
145
146 hspi->State = HAL_SPI_STATE_READY;
147 /* Process Unlocked */
148 __HAL_UNLOCK(hspi);
149 return errorcode;
150 }
151
152 /**
153 * @brief Configure the UNDERRUN condition and behavior of slave transmitter.
154 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
155 * the configuration information for SPI module.
156 * @param UnderrunDetection : Detection of underrun condition at slave transmitter
157 * This parameter can be a value of @ref SPI_Underrun_Detection.
158 * @param UnderrunBehaviour : Behavior of slave transmitter at underrun condition
159 * This parameter can be a value of @ref SPI_Underrun_Behaviour.
160 * @retval None
161 */
HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef * hspi,uint32_t UnderrunDetection,uint32_t UnderrunBehaviour)162 HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection,
163 uint32_t UnderrunBehaviour)
164 {
165 HAL_StatusTypeDef errorcode = HAL_OK;
166
167 /* Process Locked */
168 __HAL_LOCK(hspi);
169
170 /* Check State and Insure that Underrun configuration is managed only by Salve */
171 if ((hspi->State != HAL_SPI_STATE_READY) || (hspi->Init.Mode != SPI_MODE_SLAVE))
172 {
173 errorcode = HAL_BUSY;
174 hspi->State = HAL_SPI_STATE_READY;
175 /* Process Unlocked */
176 __HAL_UNLOCK(hspi);
177 return errorcode;
178 }
179
180 /* Check the parameters */
181 assert_param(IS_SPI_UNDERRUN_DETECTION(UnderrunDetection));
182 assert_param(IS_SPI_UNDERRUN_BEHAVIOUR(UnderrunBehaviour));
183
184 /* Check if the SPI is disabled to edit CFG1 register */
185 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
186 {
187 /* Configure Underrun fields */
188 MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, UnderrunDetection);
189 MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
190 }
191 else
192 {
193 /* Disable SPI peripheral */
194 __HAL_SPI_DISABLE(hspi);
195
196 /* Configure Underrun fields */
197 MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, UnderrunDetection);
198 MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour);
199
200 /* Enable SPI peripheral */
201 __HAL_SPI_ENABLE(hspi);
202 }
203
204
205 hspi->State = HAL_SPI_STATE_READY;
206 /* Process Unlocked */
207 __HAL_UNLOCK(hspi);
208 return errorcode;
209 }
210
211 /**
212 * @}
213 */
214
215 /**
216 * @}
217 */
218
219 #endif /* HAL_SPI_MODULE_ENABLED */
220
221 /**
222 * @}
223 */
224
225 /**
226 * @}
227 */
228
