1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_hal_lptim.c
4 * @author MCD Application Team
5 * @brief LPTIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Low Power Timer (LPTIM) peripheral:
8 * + Initialization and de-initialization functions.
9 * + Start/Stop operation functions in polling mode.
10 * + Start/Stop operation functions in interrupt mode.
11 * + Reading operation functions.
12 * + Peripheral State functions.
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2019 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### How to use this driver #####
28 ==============================================================================
29 [..]
30 The LPTIM HAL driver can be used as follows:
31
32 (#)Initialize the LPTIM low level resources by implementing the
33 HAL_LPTIM_MspInit():
34 (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
35 (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
36 (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
37 (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
38 (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
39
40 (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
41 configures mainly:
42 (++) The instance: LPTIM1, LPTIM2, LPTIM3, LPTIM4 or LPTIM5.
43 (++) Clock: the counter clock.
44 (+++) Source : it can be either the ULPTIM input (IN1) or one of
45 the internal clock; (APB, LSE, LSI or MSI).
46 (+++) Prescaler: select the clock divider.
47 (++) UltraLowPowerClock : To be used only if the ULPTIM is selected
48 as counter clock source.
49 (+++) Polarity: polarity of the active edge for the counter unit
50 if the ULPTIM input is selected.
51 (+++) SampleTime: clock sampling time to configure the clock glitch
52 filter.
53 (++) Trigger: How the counter start.
54 (+++) Source: trigger can be software or one of the hardware triggers.
55 (+++) ActiveEdge : only for hardware trigger.
56 (+++) SampleTime : trigger sampling time to configure the trigger
57 glitch filter.
58 (++) OutputPolarity : 2 opposite polarities are possible.
59 (++) UpdateMode: specifies whether the update of the autoreload and
60 the compare values is done immediately or after the end of current
61 period.
62 (++) Input1Source: Source selected for input1 (GPIO or comparator output).
63 (++) Input2Source: Source selected for input2 (GPIO or comparator output).
64 Input2 is used only for encoder feature so is used only for LPTIM1 instance.
65
66 (#)Six modes are available:
67
68 (++) PWM Mode: To generate a PWM signal with specified period and pulse,
69 call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
70 mode.
71
72 (++) One Pulse Mode: To generate pulse with specified width in response
73 to a stimulus, call HAL_LPTIM_OnePulse_Start() or
74 HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
75
76 (++) Set once Mode: In this mode, the output changes the level (from
77 low level to high level if the output polarity is configured high, else
78 the opposite) when a compare match occurs. To start this mode, call
79 HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
80 interruption mode.
81
82 (++) Encoder Mode: To use the encoder interface call
83 HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
84 interruption mode. Only available for LPTIM1 instance.
85
86 (++) Time out Mode: an active edge on one selected trigger input rests
87 the counter. The first trigger event will start the timer, any
88 successive trigger event will reset the counter and the timer will
89 restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
90 HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
91
92 (++) Counter Mode: counter can be used to count external events on
93 the LPTIM Input1 or it can be used to count internal clock cycles.
94 To start this mode, call HAL_LPTIM_Counter_Start() or
95 HAL_LPTIM_Counter_Start_IT() for interruption mode.
96
97
98 (#) User can stop any process by calling the corresponding API:
99 HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
100 already started in interruption mode.
101
102 (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
103
104 *** Callback registration ***
105 =============================================
106 [..]
107 The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
108 allows the user to configure dynamically the driver callbacks.
109 [..]
110 Use Function HAL_LPTIM_RegisterCallback() to register a callback.
111 HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
112 the Callback ID and a pointer to the user callback function.
113 [..]
114 Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the
115 default weak function.
116 HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
117 and the Callback ID.
118 [..]
119 These functions allow to register/unregister following callbacks:
120
121 (+) MspInitCallback : LPTIM Base Msp Init Callback.
122 (+) MspDeInitCallback : LPTIM Base Msp DeInit Callback.
123 (+) CompareMatchCallback : Compare match Callback.
124 (+) AutoReloadMatchCallback : Auto-reload match Callback.
125 (+) TriggerCallback : External trigger event detection Callback.
126 (+) CompareWriteCallback : Compare register write complete Callback.
127 (+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
128 (+) DirectionUpCallback : Up-counting direction change Callback.
129 (+) DirectionDownCallback : Down-counting direction change Callback.
130
131 [..]
132 By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
133 all interrupt callbacks are set to the corresponding weak functions:
134 examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback().
135
136 [..]
137 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
138 functionalities in the Init/DeInit only when these callbacks are null
139 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
140 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
141
142 [..]
143 Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
144 Exception done MspInit/MspDeInit that can be registered/unregistered
145 in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
146 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
147 In that case first register the MspInit/MspDeInit user callbacks
148 using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
149
150 [..]
151 When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
152 not defined, the callback registration feature is not available and all callbacks
153 are set to the corresponding weak functions.
154
155 @endverbatim
156 ******************************************************************************
157 */
158
159 /* Includes ------------------------------------------------------------------*/
160 #include "stm32mp1xx_hal.h"
161
162 /** @addtogroup STM32MP1xx_HAL_Driver
163 * @{
164 */
165
166 /** @defgroup LPTIM LPTIM
167 * @brief LPTIM HAL module driver.
168 * @{
169 */
170
171 #ifdef HAL_LPTIM_MODULE_ENABLED
172
173 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5)
174
175 /* Private typedef -----------------------------------------------------------*/
176 /* Private define ------------------------------------------------------------*/
177 /** @addtogroup LPTIM_Private_Constants
178 * @{
179 */
180 #define TIMEOUT 1000UL /* Timeout is 1s */
181 /**
182 * @}
183 */
184
185 /* Private macro -------------------------------------------------------------*/
186 /* Private variables ---------------------------------------------------------*/
187 /* Private function prototypes -----------------------------------------------*/
188 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
189 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
190 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
191 static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag);
192
193 /* Exported functions --------------------------------------------------------*/
194
195 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
196 * @{
197 */
198
199 /** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
200 * @brief Initialization and Configuration functions.
201 *
202 @verbatim
203 ==============================================================================
204 ##### Initialization and de-initialization functions #####
205 ==============================================================================
206 [..] This section provides functions allowing to:
207 (+) Initialize the LPTIM according to the specified parameters in the
208 LPTIM_InitTypeDef and initialize the associated handle.
209 (+) DeInitialize the LPTIM peripheral.
210 (+) Initialize the LPTIM MSP.
211 (+) DeInitialize the LPTIM MSP.
212
213 @endverbatim
214 * @{
215 */
216
217 /**
218 * @brief Initialize the LPTIM according to the specified parameters in the
219 * LPTIM_InitTypeDef and initialize the associated handle.
220 * @param hlptim LPTIM handle
221 * @retval HAL status
222 */
HAL_LPTIM_Init(LPTIM_HandleTypeDef * hlptim)223 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
224 {
225 uint32_t tmpcfgr;
226
227 /* Check the LPTIM handle allocation */
228 if (hlptim == NULL)
229 {
230 return HAL_ERROR;
231 }
232
233 /* Check the parameters */
234 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
235
236 assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
237 assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
238 if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
239 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
240 {
241 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
242 assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
243 }
244 assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
245 if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
246 {
247 assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
248 assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
249 }
250 assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
251 assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
252 assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
253
254 if (hlptim->State == HAL_LPTIM_STATE_RESET)
255 {
256 /* Allocate lock resource and initialize it */
257 hlptim->Lock = HAL_UNLOCKED;
258
259 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
260 /* Reset interrupt callbacks to legacy weak callbacks */
261 LPTIM_ResetCallback(hlptim);
262
263 if (hlptim->MspInitCallback == NULL)
264 {
265 hlptim->MspInitCallback = HAL_LPTIM_MspInit;
266 }
267
268 /* Init the low level hardware : GPIO, CLOCK, NVIC */
269 hlptim->MspInitCallback(hlptim);
270 #else
271 /* Init the low level hardware : GPIO, CLOCK, NVIC */
272 HAL_LPTIM_MspInit(hlptim);
273 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
274 }
275
276 /* Change the LPTIM state */
277 hlptim->State = HAL_LPTIM_STATE_BUSY;
278
279 /* Get the LPTIMx CFGR value */
280 tmpcfgr = hlptim->Instance->CFGR;
281
282 if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
283 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
284 {
285 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
286 }
287 if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
288 {
289 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
290 }
291
292 /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
293 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
294 LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
295
296 /* Set initialization parameters */
297 tmpcfgr |= (hlptim->Init.Clock.Source |
298 hlptim->Init.Clock.Prescaler |
299 hlptim->Init.OutputPolarity |
300 hlptim->Init.UpdateMode |
301 hlptim->Init.CounterSource);
302
303 /* Glitch filters for internal triggers and external inputs are configured
304 * only if an internal clock source is provided to the LPTIM
305 */
306 if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
307 {
308 tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
309 hlptim->Init.UltraLowPowerClock.SampleTime);
310 }
311
312 /* Configure LPTIM external clock polarity and digital filter */
313 if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
314 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
315 {
316 tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
317 hlptim->Init.UltraLowPowerClock.SampleTime);
318 }
319
320 /* Configure LPTIM external trigger */
321 if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
322 {
323 /* Enable External trigger and set the trigger source */
324 tmpcfgr |= (hlptim->Init.Trigger.Source |
325 hlptim->Init.Trigger.ActiveEdge |
326 hlptim->Init.Trigger.SampleTime);
327 }
328
329 /* Write to LPTIMx CFGR */
330 hlptim->Instance->CFGR = tmpcfgr;
331
332 /* Configure LPTIM input sources */
333 if ((hlptim->Instance == LPTIM1) || (hlptim->Instance == LPTIM2))
334 {
335 /* Check LPTIM Input1 and Input2 sources */
336 assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
337 assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance, hlptim->Init.Input2Source));
338
339 /* Configure LPTIM Input1 and Input2 sources */
340 hlptim->Instance->CFGR2 = (hlptim->Init.Input1Source | hlptim->Init.Input2Source);
341 }
342 else
343 {
344 if (hlptim->Instance == LPTIM3)
345 {
346 /* Check LPTIM3 Input1 source */
347 assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
348
349 /* Configure LPTIM3 Input1 source */
350 hlptim->Instance->CFGR2 = hlptim->Init.Input1Source;
351 }
352 }
353
354 /* Change the LPTIM state */
355 hlptim->State = HAL_LPTIM_STATE_READY;
356
357 /* Return function status */
358 return HAL_OK;
359 }
360
361 /**
362 * @brief DeInitialize the LPTIM peripheral.
363 * @param hlptim LPTIM handle
364 * @retval HAL status
365 */
HAL_LPTIM_DeInit(LPTIM_HandleTypeDef * hlptim)366 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
367 {
368 /* Check the LPTIM handle allocation */
369 if (hlptim == NULL)
370 {
371 return HAL_ERROR;
372 }
373
374 /* Change the LPTIM state */
375 hlptim->State = HAL_LPTIM_STATE_BUSY;
376
377 /* Disable the LPTIM Peripheral Clock */
378 __HAL_LPTIM_DISABLE(hlptim);
379
380 if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
381 {
382 return HAL_TIMEOUT;
383 }
384
385 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
386 if (hlptim->MspDeInitCallback == NULL)
387 {
388 hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
389 }
390
391 /* DeInit the low level hardware: CLOCK, NVIC.*/
392 hlptim->MspDeInitCallback(hlptim);
393 #else
394 /* DeInit the low level hardware: CLOCK, NVIC.*/
395 HAL_LPTIM_MspDeInit(hlptim);
396 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
397
398 /* Change the LPTIM state */
399 hlptim->State = HAL_LPTIM_STATE_RESET;
400
401 /* Release Lock */
402 __HAL_UNLOCK(hlptim);
403
404 /* Return function status */
405 return HAL_OK;
406 }
407
408 /**
409 * @brief Initialize the LPTIM MSP.
410 * @param hlptim LPTIM handle
411 * @retval None
412 */
HAL_LPTIM_MspInit(LPTIM_HandleTypeDef * hlptim)413 __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
414 {
415 /* Prevent unused argument(s) compilation warning */
416 UNUSED(hlptim);
417
418 /* NOTE : This function should not be modified, when the callback is needed,
419 the HAL_LPTIM_MspInit could be implemented in the user file
420 */
421 }
422
423 /**
424 * @brief DeInitialize LPTIM MSP.
425 * @param hlptim LPTIM handle
426 * @retval None
427 */
HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef * hlptim)428 __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
429 {
430 /* Prevent unused argument(s) compilation warning */
431 UNUSED(hlptim);
432
433 /* NOTE : This function should not be modified, when the callback is needed,
434 the HAL_LPTIM_MspDeInit could be implemented in the user file
435 */
436 }
437
438 /**
439 * @}
440 */
441
442 /** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
443 * @brief Start-Stop operation functions.
444 *
445 @verbatim
446 ==============================================================================
447 ##### LPTIM Start Stop operation functions #####
448 ==============================================================================
449 [..] This section provides functions allowing to:
450 (+) Start the PWM mode.
451 (+) Stop the PWM mode.
452 (+) Start the One pulse mode.
453 (+) Stop the One pulse mode.
454 (+) Start the Set once mode.
455 (+) Stop the Set once mode.
456 (+) Start the Encoder mode.
457 (+) Stop the Encoder mode.
458 (+) Start the Timeout mode.
459 (+) Stop the Timeout mode.
460 (+) Start the Counter mode.
461 (+) Stop the Counter mode.
462
463
464 @endverbatim
465 * @{
466 */
467
468 /**
469 * @brief Start the LPTIM PWM generation.
470 * @param hlptim LPTIM handle
471 * @param Period Specifies the Autoreload value.
472 * This parameter must be a value between 0x0000 and 0xFFFF.
473 * @param Pulse Specifies the compare value.
474 * This parameter must be a value between 0x0000 and 0xFFFF.
475 * @retval HAL status
476 */
HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Period,uint32_t Pulse)477 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
478 {
479 /* Check the parameters */
480 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
481 assert_param(IS_LPTIM_PERIOD(Period));
482 assert_param(IS_LPTIM_PULSE(Pulse));
483
484 /* Set the LPTIM state */
485 hlptim->State = HAL_LPTIM_STATE_BUSY;
486
487 /* Reset WAVE bit to set PWM mode */
488 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
489
490 /* Enable the Peripheral */
491 __HAL_LPTIM_ENABLE(hlptim);
492
493 /* Clear flag */
494 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
495
496 /* Load the period value in the autoreload register */
497 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
498
499 /* Wait for the completion of the write operation to the LPTIM_ARR register */
500 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
501 {
502 return HAL_TIMEOUT;
503 }
504
505 /* Clear flag */
506 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
507
508 /* Load the pulse value in the compare register */
509 __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
510
511 /* Wait for the completion of the write operation to the LPTIM_CMP register */
512 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
513 {
514 return HAL_TIMEOUT;
515 }
516
517 /* Start timer in continuous mode */
518 __HAL_LPTIM_START_CONTINUOUS(hlptim);
519
520 /* Change the TIM state*/
521 hlptim->State = HAL_LPTIM_STATE_READY;
522
523 /* Return function status */
524 return HAL_OK;
525 }
526
527 /**
528 * @brief Stop the LPTIM PWM generation.
529 * @param hlptim LPTIM handle
530 * @retval HAL status
531 */
HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef * hlptim)532 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
533 {
534 /* Check the parameters */
535 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
536
537 /* Set the LPTIM state */
538 hlptim->State = HAL_LPTIM_STATE_BUSY;
539
540 /* Disable the Peripheral */
541 __HAL_LPTIM_DISABLE(hlptim);
542
543 if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
544 {
545 return HAL_TIMEOUT;
546 }
547
548 /* Change the LPTIM state*/
549 hlptim->State = HAL_LPTIM_STATE_READY;
550
551 /* Return function status */
552 return HAL_OK;
553 }
554
555 /**
556 * @brief Start the LPTIM PWM generation in interrupt mode.
557 * @param hlptim LPTIM handle
558 * @param Period Specifies the Autoreload value.
559 * This parameter must be a value between 0x0000 and 0xFFFF
560 * @param Pulse Specifies the compare value.
561 * This parameter must be a value between 0x0000 and 0xFFFF
562 * @retval HAL status
563 */
HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Period,uint32_t Pulse)564 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
565 {
566 /* Check the parameters */
567 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
568 assert_param(IS_LPTIM_PERIOD(Period));
569 assert_param(IS_LPTIM_PULSE(Pulse));
570
571 /* Set the LPTIM state */
572 hlptim->State = HAL_LPTIM_STATE_BUSY;
573
574 /* Reset WAVE bit to set PWM mode */
575 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
576
577 /* Enable the Peripheral */
578 __HAL_LPTIM_ENABLE(hlptim);
579
580 /* Clear flag */
581 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
582
583 /* Load the period value in the autoreload register */
584 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
585
586 /* Wait for the completion of the write operation to the LPTIM_ARR register */
587 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
588 {
589 return HAL_TIMEOUT;
590 }
591
592 /* Clear flag */
593 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
594
595 /* Load the pulse value in the compare register */
596 __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
597
598 /* Wait for the completion of the write operation to the LPTIM_CMP register */
599 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
600 {
601 return HAL_TIMEOUT;
602 }
603
604 /* Disable the Peripheral */
605 __HAL_LPTIM_DISABLE(hlptim);
606
607 if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
608 {
609 return HAL_TIMEOUT;
610 }
611
612 /* Enable Autoreload write complete interrupt */
613 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
614
615 /* Enable Compare write complete interrupt */
616 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
617
618 /* Enable Autoreload match interrupt */
619 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
620
621 /* Enable Compare match interrupt */
622 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
623
624 /* If external trigger source is used, then enable external trigger interrupt */
625 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
626 {
627 /* Enable external trigger interrupt */
628 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
629 }
630
631 /* Enable the Peripheral */
632 __HAL_LPTIM_ENABLE(hlptim);
633
634 /* Start timer in continuous mode */
635 __HAL_LPTIM_START_CONTINUOUS(hlptim);
636
637 /* Change the TIM state*/
638 hlptim->State = HAL_LPTIM_STATE_READY;
639
640 /* Return function status */
641 return HAL_OK;
642 }
643
644 /**
645 * @brief Stop the LPTIM PWM generation in interrupt mode.
646 * @param hlptim LPTIM handle
647 * @retval HAL status
648 */
HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef * hlptim)649 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
650 {
651 /* Check the parameters */
652 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
653
654 /* Set the LPTIM state */
655 hlptim->State = HAL_LPTIM_STATE_BUSY;
656
657 /* Disable the Peripheral */
658 __HAL_LPTIM_DISABLE(hlptim);
659
660 if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
661 {
662 return HAL_TIMEOUT;
663 }
664
665 /* Disable Autoreload write complete interrupt */
666 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
667
668 /* Disable Compare write complete interrupt */
669 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
670
671 /* Disable Autoreload match interrupt */
672 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
673
674 /* Disable Compare match interrupt */
675 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
676
677 /* If external trigger source is used, then disable external trigger interrupt */
678 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
679 {
680 /* Disable external trigger interrupt */
681 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
682 }
683
684 /* Change the LPTIM state*/
685 hlptim->State = HAL_LPTIM_STATE_READY;
686
687 /* Return function status */
688 return HAL_OK;
689 }
690
691 /**
692 * @brief Start the LPTIM One pulse generation.
693 * @param hlptim LPTIM handle
694 * @param Period Specifies the Autoreload value.
695 * This parameter must be a value between 0x0000 and 0xFFFF.
696 * @param Pulse Specifies the compare value.
697 * This parameter must be a value between 0x0000 and 0xFFFF.
698 * @retval HAL status
699 */
HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Period,uint32_t Pulse)700 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
701 {
702 /* Check the parameters */
703 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
704 assert_param(IS_LPTIM_PERIOD(Period));
705 assert_param(IS_LPTIM_PULSE(Pulse));
706
707 /* Set the LPTIM state */
708 hlptim->State = HAL_LPTIM_STATE_BUSY;
709
710 /* Reset WAVE bit to set one pulse mode */
711 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
712
713 /* Enable the Peripheral */
714 __HAL_LPTIM_ENABLE(hlptim);
715
716 /* Clear flag */
717 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
718
719 /* Load the period value in the autoreload register */
720 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
721
722 /* Wait for the completion of the write operation to the LPTIM_ARR register */
723 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
724 {
725 return HAL_TIMEOUT;
726 }
727
728 /* Clear flag */
729 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
730
731 /* Load the pulse value in the compare register */
732 __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
733
734 /* Wait for the completion of the write operation to the LPTIM_CMP register */
735 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
736 {
737 return HAL_TIMEOUT;
738 }
739
740 /* Start timer in single (one shot) mode */
741 __HAL_LPTIM_START_SINGLE(hlptim);
742
743 /* Change the TIM state*/
744 hlptim->State = HAL_LPTIM_STATE_READY;
745
746 /* Return function status */
747 return HAL_OK;
748 }
749
750 /**
751 * @brief Stop the LPTIM One pulse generation.
752 * @param hlptim LPTIM handle
753 * @retval HAL status
754 */
HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef * hlptim)755 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
756 {
757 /* Check the parameters */
758 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
759
760 /* Set the LPTIM state */
761 hlptim->State = HAL_LPTIM_STATE_BUSY;
762
763 /* Disable the Peripheral */
764 __HAL_LPTIM_DISABLE(hlptim);
765
766 if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
767 {
768 return HAL_TIMEOUT;
769 }
770
771 /* Change the LPTIM state*/
772 hlptim->State = HAL_LPTIM_STATE_READY;
773
774 /* Return function status */
775 return HAL_OK;
776 }
777
778 /**
779 * @brief Start the LPTIM One pulse generation in interrupt mode.
780 * @param hlptim LPTIM handle
781 * @param Period Specifies the Autoreload value.
782 * This parameter must be a value between 0x0000 and 0xFFFF.
783 * @param Pulse Specifies the compare value.
784 * This parameter must be a value between 0x0000 and 0xFFFF.
785 * @retval HAL status
786 */
HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Period,uint32_t Pulse)787 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
788 {
789 /* Check the parameters */
790 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
791 assert_param(IS_LPTIM_PERIOD(Period));
792 assert_param(IS_LPTIM_PULSE(Pulse));
793
794 /* Set the LPTIM state */
795 hlptim->State = HAL_LPTIM_STATE_BUSY;
796
797 /* Reset WAVE bit to set one pulse mode */
798 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
799
800 /* Enable the Peripheral */
801 __HAL_LPTIM_ENABLE(hlptim);
802
803 /* Clear flag */
804 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
805
806 /* Load the period value in the autoreload register */
807 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
808
809 /* Wait for the completion of the write operation to the LPTIM_ARR register */
810 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
811 {
812 return HAL_TIMEOUT;
813 }
814
815 /* Clear flag */
816 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
817
818 /* Load the pulse value in the compare register */
819 __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
820
821 /* Wait for the completion of the write operation to the LPTIM_CMP register */
822 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
823 {
824 return HAL_TIMEOUT;
825 }
826
827 /* Disable the Peripheral */
828 __HAL_LPTIM_DISABLE(hlptim);
829
830 if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
831 {
832 return HAL_TIMEOUT;
833 }
834
835 /* Enable Autoreload write complete interrupt */
836 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
837
838 /* Enable Compare write complete interrupt */
839 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
840
841 /* Enable Autoreload match interrupt */
842 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
843
844 /* Enable Compare match interrupt */
845 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
846
847 /* If external trigger source is used, then enable external trigger interrupt */
848 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
849 {
850 /* Enable external trigger interrupt */
851 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
852 }
853
854 /* Enable the Peripheral */
855 __HAL_LPTIM_ENABLE(hlptim);
856
857 /* Start timer in single (one shot) mode */
858 __HAL_LPTIM_START_SINGLE(hlptim);
859
860 /* Change the TIM state*/
861 hlptim->State = HAL_LPTIM_STATE_READY;
862
863 /* Return function status */
864 return HAL_OK;
865 }
866
867 /**
868 * @brief Stop the LPTIM One pulse generation in interrupt mode.
869 * @param hlptim LPTIM handle
870 * @retval HAL status
871 */
HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef * hlptim)872 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
873 {
874 /* Check the parameters */
875 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
876
877 /* Set the LPTIM state */
878 hlptim->State = HAL_LPTIM_STATE_BUSY;
879
880 /* Disable the Peripheral */
881 __HAL_LPTIM_DISABLE(hlptim);
882
883 if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
884 {
885 return HAL_TIMEOUT;
886 }
887
888 /* Disable Autoreload write complete interrupt */
889 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
890
891 /* Disable Compare write complete interrupt */
892 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
893
894 /* Disable Autoreload match interrupt */
895 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
896
897 /* Disable Compare match interrupt */
898 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
899
900 /* If external trigger source is used, then disable external trigger interrupt */
901 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
902 {
903 /* Disable external trigger interrupt */
904 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
905 }
906
907 /* Change the LPTIM state*/
908 hlptim->State = HAL_LPTIM_STATE_READY;
909
910 /* Return function status */
911 return HAL_OK;
912 }
913
914 /**
915 * @brief Start the LPTIM in Set once mode.
916 * @param hlptim LPTIM handle
917 * @param Period Specifies the Autoreload value.
918 * This parameter must be a value between 0x0000 and 0xFFFF.
919 * @param Pulse Specifies the compare value.
920 * This parameter must be a value between 0x0000 and 0xFFFF.
921 * @retval HAL status
922 */
HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Period,uint32_t Pulse)923 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
924 {
925 /* Check the parameters */
926 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
927 assert_param(IS_LPTIM_PERIOD(Period));
928 assert_param(IS_LPTIM_PULSE(Pulse));
929
930 /* Set the LPTIM state */
931 hlptim->State = HAL_LPTIM_STATE_BUSY;
932
933 /* Set WAVE bit to enable the set once mode */
934 hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
935
936 /* Enable the Peripheral */
937 __HAL_LPTIM_ENABLE(hlptim);
938
939 /* Clear flag */
940 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
941
942 /* Load the period value in the autoreload register */
943 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
944
945 /* Wait for the completion of the write operation to the LPTIM_ARR register */
946 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
947 {
948 return HAL_TIMEOUT;
949 }
950
951 /* Clear flag */
952 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
953
954 /* Load the pulse value in the compare register */
955 __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
956
957 /* Wait for the completion of the write operation to the LPTIM_CMP register */
958 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
959 {
960 return HAL_TIMEOUT;
961 }
962
963 /* Start timer in single (one shot) mode */
964 __HAL_LPTIM_START_SINGLE(hlptim);
965
966 /* Change the TIM state*/
967 hlptim->State = HAL_LPTIM_STATE_READY;
968
969 /* Return function status */
970 return HAL_OK;
971 }
972
973 /**
974 * @brief Stop the LPTIM Set once mode.
975 * @param hlptim LPTIM handle
976 * @retval HAL status
977 */
HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef * hlptim)978 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
979 {
980 /* Check the parameters */
981 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
982
983 /* Set the LPTIM state */
984 hlptim->State = HAL_LPTIM_STATE_BUSY;
985
986 /* Disable the Peripheral */
987 __HAL_LPTIM_DISABLE(hlptim);
988
989 if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
990 {
991 return HAL_TIMEOUT;
992 }
993
994 /* Change the LPTIM state*/
995 hlptim->State = HAL_LPTIM_STATE_READY;
996
997 /* Return function status */
998 return HAL_OK;
999 }
1000
1001 /**
1002 * @brief Start the LPTIM Set once mode in interrupt mode.
1003 * @param hlptim LPTIM handle
1004 * @param Period Specifies the Autoreload value.
1005 * This parameter must be a value between 0x0000 and 0xFFFF.
1006 * @param Pulse Specifies the compare value.
1007 * This parameter must be a value between 0x0000 and 0xFFFF.
1008 * @retval HAL status
1009 */
HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Period,uint32_t Pulse)1010 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
1011 {
1012 /* Check the parameters */
1013 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1014 assert_param(IS_LPTIM_PERIOD(Period));
1015 assert_param(IS_LPTIM_PULSE(Pulse));
1016
1017 /* Set the LPTIM state */
1018 hlptim->State = HAL_LPTIM_STATE_BUSY;
1019
1020 /* Set WAVE bit to enable the set once mode */
1021 hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
1022
1023 /* Enable the Peripheral */
1024 __HAL_LPTIM_ENABLE(hlptim);
1025
1026 /* Clear flag */
1027 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
1028
1029 /* Load the period value in the autoreload register */
1030 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
1031
1032 /* Wait for the completion of the write operation to the LPTIM_ARR register */
1033 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
1034 {
1035 return HAL_TIMEOUT;
1036 }
1037
1038 /* Clear flag */
1039 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
1040
1041 /* Load the pulse value in the compare register */
1042 __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
1043
1044 /* Wait for the completion of the write operation to the LPTIM_CMP register */
1045 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
1046 {
1047 return HAL_TIMEOUT;
1048 }
1049
1050 /* Disable the Peripheral */
1051 __HAL_LPTIM_DISABLE(hlptim);
1052
1053 if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
1054 {
1055 return HAL_TIMEOUT;
1056 }
1057
1058 /* Enable Autoreload write complete interrupt */
1059 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
1060
1061 /* Enable Compare write complete interrupt */
1062 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
1063
1064 /* Enable Autoreload match interrupt */
1065 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
1066
1067 /* Enable Compare match interrupt */
1068 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
1069
1070 /* If external trigger source is used, then enable external trigger interrupt */
1071 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1072 {
1073 /* Enable external trigger interrupt */
1074 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1075 }
1076
1077 /* Enable the Peripheral */
1078 __HAL_LPTIM_ENABLE(hlptim);
1079
1080 /* Start timer in single (one shot) mode */
1081 __HAL_LPTIM_START_SINGLE(hlptim);
1082
1083 /* Change the TIM state*/
1084 hlptim->State = HAL_LPTIM_STATE_READY;
1085
1086 /* Return function status */
1087 return HAL_OK;
1088 }
1089
1090 /**
1091 * @brief Stop the LPTIM Set once mode in interrupt mode.
1092 * @param hlptim LPTIM handle
1093 * @retval HAL status
1094 */
HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef * hlptim)1095 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
1096 {
1097 /* Check the parameters */
1098 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1099
1100 /* Set the LPTIM state */
1101 hlptim->State = HAL_LPTIM_STATE_BUSY;
1102
1103 /* Disable the Peripheral */
1104 __HAL_LPTIM_DISABLE(hlptim);
1105
1106 if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
1107 {
1108 return HAL_TIMEOUT;
1109 }
1110
1111 /* Disable Autoreload write complete interrupt */
1112 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
1113
1114 /* Disable Compare write complete interrupt */
1115 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
1116
1117 /* Disable Autoreload match interrupt */
1118 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
1119
1120 /* Disable Compare match interrupt */
1121 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
1122
1123 /* If external trigger source is used, then disable external trigger interrupt */
1124 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1125 {
1126 /* Disable external trigger interrupt */
1127 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1128 }
1129
1130 /* Change the LPTIM state*/
1131 hlptim->State = HAL_LPTIM_STATE_READY;
1132
1133 /* Return function status */
1134 return HAL_OK;
1135 }
1136
1137 /**
1138 * @brief Start the Encoder interface.
1139 * @param hlptim LPTIM handle
1140 * @param Period Specifies the Autoreload value.
1141 * This parameter must be a value between 0x0000 and 0xFFFF.
1142 * @retval HAL status
1143 */
HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Period)1144 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
1145 {
1146 uint32_t tmpcfgr;
1147
1148 /* Check the parameters */
1149 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1150 assert_param(IS_LPTIM_PERIOD(Period));
1151 assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
1152 assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
1153 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
1154
1155 /* Set the LPTIM state */
1156 hlptim->State = HAL_LPTIM_STATE_BUSY;
1157
1158 /* Get the LPTIMx CFGR value */
1159 tmpcfgr = hlptim->Instance->CFGR;
1160
1161 /* Clear CKPOL bits */
1162 tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
1163
1164 /* Set Input polarity */
1165 tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
1166
1167 /* Write to LPTIMx CFGR */
1168 hlptim->Instance->CFGR = tmpcfgr;
1169
1170 /* Set ENC bit to enable the encoder interface */
1171 hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
1172
1173 /* Enable the Peripheral */
1174 __HAL_LPTIM_ENABLE(hlptim);
1175
1176 /* Clear flag */
1177 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
1178
1179 /* Load the period value in the autoreload register */
1180 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
1181
1182 /* Wait for the completion of the write operation to the LPTIM_ARR register */
1183 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
1184 {
1185 return HAL_TIMEOUT;
1186 }
1187
1188 /* Start timer in continuous mode */
1189 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1190
1191 /* Change the TIM state*/
1192 hlptim->State = HAL_LPTIM_STATE_READY;
1193
1194 /* Return function status */
1195 return HAL_OK;
1196 }
1197
1198 /**
1199 * @brief Stop the Encoder interface.
1200 * @param hlptim LPTIM handle
1201 * @retval HAL status
1202 */
HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef * hlptim)1203 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
1204 {
1205 /* Check the parameters */
1206 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1207
1208 /* Set the LPTIM state */
1209 hlptim->State = HAL_LPTIM_STATE_BUSY;
1210
1211 /* Disable the Peripheral */
1212 __HAL_LPTIM_DISABLE(hlptim);
1213
1214 if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
1215 {
1216 return HAL_TIMEOUT;
1217 }
1218
1219 /* Reset ENC bit to disable the encoder interface */
1220 hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
1221
1222 /* Change the TIM state*/
1223 hlptim->State = HAL_LPTIM_STATE_READY;
1224
1225 /* Return function status */
1226 return HAL_OK;
1227 }
1228
1229 /**
1230 * @brief Start the Encoder interface in interrupt mode.
1231 * @param hlptim LPTIM handle
1232 * @param Period Specifies the Autoreload value.
1233 * This parameter must be a value between 0x0000 and 0xFFFF.
1234 * @retval HAL status
1235 */
HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Period)1236 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
1237 {
1238 uint32_t tmpcfgr;
1239
1240 /* Check the parameters */
1241 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1242 assert_param(IS_LPTIM_PERIOD(Period));
1243 assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
1244 assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
1245 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
1246
1247 /* Set the LPTIM state */
1248 hlptim->State = HAL_LPTIM_STATE_BUSY;
1249
1250 /* Configure edge sensitivity for encoder mode */
1251 /* Get the LPTIMx CFGR value */
1252 tmpcfgr = hlptim->Instance->CFGR;
1253
1254 /* Clear CKPOL bits */
1255 tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
1256
1257 /* Set Input polarity */
1258 tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
1259
1260 /* Write to LPTIMx CFGR */
1261 hlptim->Instance->CFGR = tmpcfgr;
1262
1263 /* Set ENC bit to enable the encoder interface */
1264 hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
1265
1266 /* Enable the Peripheral */
1267 __HAL_LPTIM_ENABLE(hlptim);
1268
1269 /* Clear flag */
1270 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
1271
1272 /* Load the period value in the autoreload register */
1273 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
1274
1275 /* Wait for the completion of the write operation to the LPTIM_ARR register */
1276 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
1277 {
1278 return HAL_TIMEOUT;
1279 }
1280
1281 /* Disable the Peripheral */
1282 __HAL_LPTIM_DISABLE(hlptim);
1283
1284 if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
1285 {
1286 return HAL_TIMEOUT;
1287 }
1288
1289 /* Enable "switch to down direction" interrupt */
1290 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
1291
1292 /* Enable "switch to up direction" interrupt */
1293 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);
1294
1295 /* Enable the Peripheral */
1296 __HAL_LPTIM_ENABLE(hlptim);
1297
1298 /* Start timer in continuous mode */
1299 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1300
1301 /* Change the TIM state*/
1302 hlptim->State = HAL_LPTIM_STATE_READY;
1303
1304 /* Return function status */
1305 return HAL_OK;
1306 }
1307
1308 /**
1309 * @brief Stop the Encoder interface in interrupt mode.
1310 * @param hlptim LPTIM handle
1311 * @retval HAL status
1312 */
HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef * hlptim)1313 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
1314 {
1315 /* Check the parameters */
1316 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1317
1318 /* Set the LPTIM state */
1319 hlptim->State = HAL_LPTIM_STATE_BUSY;
1320
1321 /* Disable the Peripheral */
1322 __HAL_LPTIM_DISABLE(hlptim);
1323
1324 if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
1325 {
1326 return HAL_TIMEOUT;
1327 }
1328
1329 /* Reset ENC bit to disable the encoder interface */
1330 hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
1331
1332 /* Disable "switch to down direction" interrupt */
1333 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);
1334
1335 /* Disable "switch to up direction" interrupt */
1336 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
1337
1338 /* Change the TIM state*/
1339 hlptim->State = HAL_LPTIM_STATE_READY;
1340
1341 /* Return function status */
1342 return HAL_OK;
1343 }
1344
1345 /**
1346 * @brief Start the Timeout function.
1347 * @note The first trigger event will start the timer, any successive
1348 * trigger event will reset the counter and the timer restarts.
1349 * @param hlptim LPTIM handle
1350 * @param Period Specifies the Autoreload value.
1351 * This parameter must be a value between 0x0000 and 0xFFFF.
1352 * @param Timeout Specifies the TimeOut value to reset the counter.
1353 * This parameter must be a value between 0x0000 and 0xFFFF.
1354 * @retval HAL status
1355 */
HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Period,uint32_t Timeout)1356 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
1357 {
1358 /* Check the parameters */
1359 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1360 assert_param(IS_LPTIM_PERIOD(Period));
1361 assert_param(IS_LPTIM_PULSE(Timeout));
1362
1363 /* Set the LPTIM state */
1364 hlptim->State = HAL_LPTIM_STATE_BUSY;
1365
1366 /* Set TIMOUT bit to enable the timeout function */
1367 hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
1368
1369 /* Enable the Peripheral */
1370 __HAL_LPTIM_ENABLE(hlptim);
1371
1372 /* Clear flag */
1373 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
1374
1375 /* Load the period value in the autoreload register */
1376 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
1377
1378 /* Wait for the completion of the write operation to the LPTIM_ARR register */
1379 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
1380 {
1381 return HAL_TIMEOUT;
1382 }
1383
1384 /* Clear flag */
1385 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
1386
1387 /* Load the Timeout value in the compare register */
1388 __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
1389
1390 /* Wait for the completion of the write operation to the LPTIM_CMP register */
1391 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
1392 {
1393 return HAL_TIMEOUT;
1394 }
1395
1396 /* Start timer in continuous mode */
1397 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1398
1399 /* Change the TIM state*/
1400 hlptim->State = HAL_LPTIM_STATE_READY;
1401
1402 /* Return function status */
1403 return HAL_OK;
1404 }
1405
1406 /**
1407 * @brief Stop the Timeout function.
1408 * @param hlptim LPTIM handle
1409 * @retval HAL status
1410 */
HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef * hlptim)1411 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
1412 {
1413 /* Check the parameters */
1414 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1415
1416 /* Set the LPTIM state */
1417 hlptim->State = HAL_LPTIM_STATE_BUSY;
1418
1419 /* Disable the Peripheral */
1420 __HAL_LPTIM_DISABLE(hlptim);
1421
1422 if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
1423 {
1424 return HAL_TIMEOUT;
1425 }
1426
1427 /* Reset TIMOUT bit to enable the timeout function */
1428 hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
1429
1430 /* Change the TIM state*/
1431 hlptim->State = HAL_LPTIM_STATE_READY;
1432
1433 /* Return function status */
1434 return HAL_OK;
1435 }
1436
1437 /**
1438 * @brief Start the Timeout function in interrupt mode.
1439 * @note The first trigger event will start the timer, any successive
1440 * trigger event will reset the counter and the timer restarts.
1441 * @param hlptim LPTIM handle
1442 * @param Period Specifies the Autoreload value.
1443 * This parameter must be a value between 0x0000 and 0xFFFF.
1444 * @param Timeout Specifies the TimeOut value to reset the counter.
1445 * This parameter must be a value between 0x0000 and 0xFFFF.
1446 * @retval HAL status
1447 */
HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Period,uint32_t Timeout)1448 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
1449 {
1450 /* Check the parameters */
1451 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1452 assert_param(IS_LPTIM_PERIOD(Period));
1453 assert_param(IS_LPTIM_PULSE(Timeout));
1454
1455 /* Set the LPTIM state */
1456 hlptim->State = HAL_LPTIM_STATE_BUSY;
1457
1458 /* Set TIMOUT bit to enable the timeout function */
1459 hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
1460
1461 /* Enable the Peripheral */
1462 __HAL_LPTIM_ENABLE(hlptim);
1463
1464 /* Clear flag */
1465 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
1466
1467 /* Load the period value in the autoreload register */
1468 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
1469
1470 /* Wait for the completion of the write operation to the LPTIM_ARR register */
1471 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
1472 {
1473 return HAL_TIMEOUT;
1474 }
1475
1476 /* Clear flag */
1477 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
1478
1479 /* Load the Timeout value in the compare register */
1480 __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
1481
1482 /* Wait for the completion of the write operation to the LPTIM_CMP register */
1483 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
1484 {
1485 return HAL_TIMEOUT;
1486 }
1487
1488 /* Disable the Peripheral */
1489 __HAL_LPTIM_DISABLE(hlptim);
1490
1491 if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
1492 {
1493 return HAL_TIMEOUT;
1494 }
1495
1496 /* Enable Compare match interrupt */
1497 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
1498
1499 /* Enable the Peripheral */
1500 __HAL_LPTIM_ENABLE(hlptim);
1501
1502 /* Start timer in continuous mode */
1503 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1504
1505 /* Change the TIM state*/
1506 hlptim->State = HAL_LPTIM_STATE_READY;
1507
1508 /* Return function status */
1509 return HAL_OK;
1510 }
1511
1512 /**
1513 * @brief Stop the Timeout function in interrupt mode.
1514 * @param hlptim LPTIM handle
1515 * @retval HAL status
1516 */
HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef * hlptim)1517 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
1518 {
1519 /* Check the parameters */
1520 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1521
1522 /* Set the LPTIM state */
1523 hlptim->State = HAL_LPTIM_STATE_BUSY;
1524
1525 /* Disable the Peripheral */
1526 __HAL_LPTIM_DISABLE(hlptim);
1527
1528 if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
1529 {
1530 return HAL_TIMEOUT;
1531 }
1532
1533 /* Reset TIMOUT bit to enable the timeout function */
1534 hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
1535
1536 /* Disable Compare match interrupt */
1537 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
1538
1539 /* Change the TIM state*/
1540 hlptim->State = HAL_LPTIM_STATE_READY;
1541
1542 /* Return function status */
1543 return HAL_OK;
1544 }
1545
1546 /**
1547 * @brief Start the Counter mode.
1548 * @param hlptim LPTIM handle
1549 * @param Period Specifies the Autoreload value.
1550 * This parameter must be a value between 0x0000 and 0xFFFF.
1551 * @retval HAL status
1552 */
HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Period)1553 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
1554 {
1555 /* Check the parameters */
1556 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1557 assert_param(IS_LPTIM_PERIOD(Period));
1558
1559 /* Set the LPTIM state */
1560 hlptim->State = HAL_LPTIM_STATE_BUSY;
1561
1562 /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
1563 if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
1564 && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
1565 {
1566 /* Check if clock is prescaled */
1567 assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
1568 /* Set clock prescaler to 0 */
1569 hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
1570 }
1571
1572 /* Enable the Peripheral */
1573 __HAL_LPTIM_ENABLE(hlptim);
1574
1575 /* Clear flag */
1576 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
1577
1578 /* Load the period value in the autoreload register */
1579 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
1580
1581 /* Wait for the completion of the write operation to the LPTIM_ARR register */
1582 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
1583 {
1584 return HAL_TIMEOUT;
1585 }
1586
1587 /* Start timer in continuous mode */
1588 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1589
1590 /* Change the TIM state*/
1591 hlptim->State = HAL_LPTIM_STATE_READY;
1592
1593 /* Return function status */
1594 return HAL_OK;
1595 }
1596
1597 /**
1598 * @brief Stop the Counter mode.
1599 * @param hlptim LPTIM handle
1600 * @retval HAL status
1601 */
HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef * hlptim)1602 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
1603 {
1604 /* Check the parameters */
1605 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1606
1607 /* Set the LPTIM state */
1608 hlptim->State = HAL_LPTIM_STATE_BUSY;
1609
1610 /* Disable the Peripheral */
1611 __HAL_LPTIM_DISABLE(hlptim);
1612
1613 if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
1614 {
1615 return HAL_TIMEOUT;
1616 }
1617
1618 /* Change the TIM state*/
1619 hlptim->State = HAL_LPTIM_STATE_READY;
1620
1621 /* Return function status */
1622 return HAL_OK;
1623 }
1624
1625 /**
1626 * @brief Start the Counter mode in interrupt mode.
1627 * @param hlptim LPTIM handle
1628 * @param Period Specifies the Autoreload value.
1629 * This parameter must be a value between 0x0000 and 0xFFFF.
1630 * @retval HAL status
1631 */
HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Period)1632 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
1633 {
1634 /* Check the parameters */
1635 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1636 assert_param(IS_LPTIM_PERIOD(Period));
1637
1638 /* Set the LPTIM state */
1639 hlptim->State = HAL_LPTIM_STATE_BUSY;
1640
1641 /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
1642 if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
1643 && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
1644 {
1645 /* Check if clock is prescaled */
1646 assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
1647 /* Set clock prescaler to 0 */
1648 hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
1649 }
1650
1651 /* Enable the Peripheral */
1652 __HAL_LPTIM_ENABLE(hlptim);
1653
1654 /* Clear flag */
1655 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
1656
1657 /* Load the period value in the autoreload register */
1658 __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
1659
1660 /* Wait for the completion of the write operation to the LPTIM_ARR register */
1661 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
1662 {
1663 return HAL_TIMEOUT;
1664 }
1665
1666 /* Disable the Peripheral */
1667 __HAL_LPTIM_DISABLE(hlptim);
1668
1669 if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
1670 {
1671 return HAL_TIMEOUT;
1672 }
1673
1674 /* Enable Autoreload write complete interrupt */
1675 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
1676
1677 /* Enable Autoreload match interrupt */
1678 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
1679
1680 /* Enable the Peripheral */
1681 __HAL_LPTIM_ENABLE(hlptim);
1682
1683 /* Start timer in continuous mode */
1684 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1685
1686 /* Change the TIM state*/
1687 hlptim->State = HAL_LPTIM_STATE_READY;
1688
1689 /* Return function status */
1690 return HAL_OK;
1691 }
1692
1693 /**
1694 * @brief Stop the Counter mode in interrupt mode.
1695 * @param hlptim LPTIM handle
1696 * @retval HAL status
1697 */
HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef * hlptim)1698 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
1699 {
1700 /* Check the parameters */
1701 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1702
1703 /* Set the LPTIM state */
1704 hlptim->State = HAL_LPTIM_STATE_BUSY;
1705
1706 /* Disable the Peripheral */
1707 __HAL_LPTIM_DISABLE(hlptim);
1708
1709 if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
1710 {
1711 return HAL_TIMEOUT;
1712 }
1713
1714 /* Disable Autoreload write complete interrupt */
1715 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
1716
1717 /* Disable Autoreload match interrupt */
1718 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
1719 /* Change the TIM state*/
1720 hlptim->State = HAL_LPTIM_STATE_READY;
1721
1722 /* Return function status */
1723 return HAL_OK;
1724 }
1725
1726 /**
1727 * @}
1728 */
1729
1730 /** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
1731 * @brief Read operation functions.
1732 *
1733 @verbatim
1734 ==============================================================================
1735 ##### LPTIM Read operation functions #####
1736 ==============================================================================
1737 [..] This section provides LPTIM Reading functions.
1738 (+) Read the counter value.
1739 (+) Read the period (Auto-reload) value.
1740 (+) Read the pulse (Compare)value.
1741 @endverbatim
1742 * @{
1743 */
1744
1745 /**
1746 * @brief Return the current counter value.
1747 * @param hlptim LPTIM handle
1748 * @retval Counter value.
1749 */
HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef * hlptim)1750 uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
1751 {
1752 /* Check the parameters */
1753 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1754
1755 return (hlptim->Instance->CNT);
1756 }
1757
1758 /**
1759 * @brief Return the current Autoreload (Period) value.
1760 * @param hlptim LPTIM handle
1761 * @retval Autoreload value.
1762 */
HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef * hlptim)1763 uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
1764 {
1765 /* Check the parameters */
1766 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1767
1768 return (hlptim->Instance->ARR);
1769 }
1770
1771 /**
1772 * @brief Return the current Compare (Pulse) value.
1773 * @param hlptim LPTIM handle
1774 * @retval Compare value.
1775 */
HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef * hlptim)1776 uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
1777 {
1778 /* Check the parameters */
1779 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1780
1781 return (hlptim->Instance->CMP);
1782 }
1783
1784 /**
1785 * @}
1786 */
1787
1788 /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
1789 * @brief LPTIM IRQ handler.
1790 *
1791 @verbatim
1792 ==============================================================================
1793 ##### LPTIM IRQ handler and callbacks #####
1794 ==============================================================================
1795 [..] This section provides LPTIM IRQ handler and callback functions called within
1796 the IRQ handler:
1797 (+) LPTIM interrupt request handler
1798 (+) Compare match Callback
1799 (+) Auto-reload match Callback
1800 (+) External trigger event detection Callback
1801 (+) Compare register write complete Callback
1802 (+) Auto-reload register write complete Callback
1803 (+) Up-counting direction change Callback
1804 (+) Down-counting direction change Callback
1805
1806 @endverbatim
1807 * @{
1808 */
1809
1810 /**
1811 * @brief Handle LPTIM interrupt request.
1812 * @param hlptim LPTIM handle
1813 * @retval None
1814 */
HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef * hlptim)1815 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
1816 {
1817 /* Compare match interrupt */
1818 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
1819 {
1820 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) != RESET)
1821 {
1822 /* Clear Compare match flag */
1823 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
1824
1825 /* Compare match Callback */
1826 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
1827 hlptim->CompareMatchCallback(hlptim);
1828 #else
1829 HAL_LPTIM_CompareMatchCallback(hlptim);
1830 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
1831 }
1832 }
1833
1834 /* Autoreload match interrupt */
1835 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
1836 {
1837 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
1838 {
1839 /* Clear Autoreload match flag */
1840 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
1841
1842 /* Autoreload match Callback */
1843 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
1844 hlptim->AutoReloadMatchCallback(hlptim);
1845 #else
1846 HAL_LPTIM_AutoReloadMatchCallback(hlptim);
1847 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
1848 }
1849 }
1850
1851 /* Trigger detected interrupt */
1852 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
1853 {
1854 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
1855 {
1856 /* Clear Trigger detected flag */
1857 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
1858
1859 /* Trigger detected callback */
1860 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
1861 hlptim->TriggerCallback(hlptim);
1862 #else
1863 HAL_LPTIM_TriggerCallback(hlptim);
1864 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
1865 }
1866 }
1867
1868 /* Compare write interrupt */
1869 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
1870 {
1871 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) != RESET)
1872 {
1873 /* Clear Compare write flag */
1874 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
1875
1876 /* Compare write Callback */
1877 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
1878 hlptim->CompareWriteCallback(hlptim);
1879 #else
1880 HAL_LPTIM_CompareWriteCallback(hlptim);
1881 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
1882 }
1883 }
1884
1885 /* Autoreload write interrupt */
1886 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
1887 {
1888 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
1889 {
1890 /* Clear Autoreload write flag */
1891 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
1892
1893 /* Autoreload write Callback */
1894 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
1895 hlptim->AutoReloadWriteCallback(hlptim);
1896 #else
1897 HAL_LPTIM_AutoReloadWriteCallback(hlptim);
1898 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
1899 }
1900 }
1901
1902 /* Direction counter changed from Down to Up interrupt */
1903 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
1904 {
1905 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
1906 {
1907 /* Clear Direction counter changed from Down to Up flag */
1908 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
1909
1910 /* Direction counter changed from Down to Up Callback */
1911 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
1912 hlptim->DirectionUpCallback(hlptim);
1913 #else
1914 HAL_LPTIM_DirectionUpCallback(hlptim);
1915 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
1916 }
1917 }
1918
1919 /* Direction counter changed from Up to Down interrupt */
1920 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
1921 {
1922 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
1923 {
1924 /* Clear Direction counter changed from Up to Down flag */
1925 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
1926
1927 /* Direction counter changed from Up to Down Callback */
1928 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
1929 hlptim->DirectionDownCallback(hlptim);
1930 #else
1931 HAL_LPTIM_DirectionDownCallback(hlptim);
1932 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
1933 }
1934 }
1935 }
1936
1937 /**
1938 * @brief Compare match callback in non-blocking mode.
1939 * @param hlptim LPTIM handle
1940 * @retval None
1941 */
HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef * hlptim)1942 __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
1943 {
1944 /* Prevent unused argument(s) compilation warning */
1945 UNUSED(hlptim);
1946
1947 /* NOTE : This function should not be modified, when the callback is needed,
1948 the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
1949 */
1950 }
1951
1952 /**
1953 * @brief Autoreload match callback in non-blocking mode.
1954 * @param hlptim LPTIM handle
1955 * @retval None
1956 */
HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef * hlptim)1957 __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
1958 {
1959 /* Prevent unused argument(s) compilation warning */
1960 UNUSED(hlptim);
1961
1962 /* NOTE : This function should not be modified, when the callback is needed,
1963 the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
1964 */
1965 }
1966
1967 /**
1968 * @brief Trigger detected callback in non-blocking mode.
1969 * @param hlptim LPTIM handle
1970 * @retval None
1971 */
HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef * hlptim)1972 __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
1973 {
1974 /* Prevent unused argument(s) compilation warning */
1975 UNUSED(hlptim);
1976
1977 /* NOTE : This function should not be modified, when the callback is needed,
1978 the HAL_LPTIM_TriggerCallback could be implemented in the user file
1979 */
1980 }
1981
1982 /**
1983 * @brief Compare write callback in non-blocking mode.
1984 * @param hlptim LPTIM handle
1985 * @retval None
1986 */
HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef * hlptim)1987 __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
1988 {
1989 /* Prevent unused argument(s) compilation warning */
1990 UNUSED(hlptim);
1991
1992 /* NOTE : This function should not be modified, when the callback is needed,
1993 the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
1994 */
1995 }
1996
1997 /**
1998 * @brief Autoreload write callback in non-blocking mode.
1999 * @param hlptim LPTIM handle
2000 * @retval None
2001 */
HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef * hlptim)2002 __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
2003 {
2004 /* Prevent unused argument(s) compilation warning */
2005 UNUSED(hlptim);
2006
2007 /* NOTE : This function should not be modified, when the callback is needed,
2008 the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
2009 */
2010 }
2011
2012 /**
2013 * @brief Direction counter changed from Down to Up callback in non-blocking mode.
2014 * @param hlptim LPTIM handle
2015 * @retval None
2016 */
HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef * hlptim)2017 __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
2018 {
2019 /* Prevent unused argument(s) compilation warning */
2020 UNUSED(hlptim);
2021
2022 /* NOTE : This function should not be modified, when the callback is needed,
2023 the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
2024 */
2025 }
2026
2027 /**
2028 * @brief Direction counter changed from Up to Down callback in non-blocking mode.
2029 * @param hlptim LPTIM handle
2030 * @retval None
2031 */
HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef * hlptim)2032 __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
2033 {
2034 /* Prevent unused argument(s) compilation warning */
2035 UNUSED(hlptim);
2036
2037 /* NOTE : This function should not be modified, when the callback is needed,
2038 the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
2039 */
2040 }
2041
2042 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2043 /**
2044 * @brief Register a User LPTIM callback to be used instead of the weak predefined callback
2045 * @param hlptim LPTIM handle
2046 * @param CallbackID ID of the callback to be registered
2047 * This parameter can be one of the following values:
2048 * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
2049 * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
2050 * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
2051 * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
2052 * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
2053 * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
2054 * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
2055 * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
2056 * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
2057 * @param pCallback pointer to the callback function
2058 * @retval status
2059 */
HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef * hlptim,HAL_LPTIM_CallbackIDTypeDef CallbackID,pLPTIM_CallbackTypeDef pCallback)2060 HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim,
2061 HAL_LPTIM_CallbackIDTypeDef CallbackID,
2062 pLPTIM_CallbackTypeDef pCallback)
2063 {
2064 HAL_StatusTypeDef status = HAL_OK;
2065
2066 if (pCallback == NULL)
2067 {
2068 return HAL_ERROR;
2069 }
2070
2071 /* Process locked */
2072 __HAL_LOCK(hlptim);
2073
2074 if (hlptim->State == HAL_LPTIM_STATE_READY)
2075 {
2076 switch (CallbackID)
2077 {
2078 case HAL_LPTIM_MSPINIT_CB_ID :
2079 hlptim->MspInitCallback = pCallback;
2080 break;
2081
2082 case HAL_LPTIM_MSPDEINIT_CB_ID :
2083 hlptim->MspDeInitCallback = pCallback;
2084 break;
2085
2086 case HAL_LPTIM_COMPARE_MATCH_CB_ID :
2087 hlptim->CompareMatchCallback = pCallback;
2088 break;
2089
2090 case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
2091 hlptim->AutoReloadMatchCallback = pCallback;
2092 break;
2093
2094 case HAL_LPTIM_TRIGGER_CB_ID :
2095 hlptim->TriggerCallback = pCallback;
2096 break;
2097
2098 case HAL_LPTIM_COMPARE_WRITE_CB_ID :
2099 hlptim->CompareWriteCallback = pCallback;
2100 break;
2101
2102 case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
2103 hlptim->AutoReloadWriteCallback = pCallback;
2104 break;
2105
2106 case HAL_LPTIM_DIRECTION_UP_CB_ID :
2107 hlptim->DirectionUpCallback = pCallback;
2108 break;
2109
2110 case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
2111 hlptim->DirectionDownCallback = pCallback;
2112 break;
2113
2114 default :
2115 /* Return error status */
2116 status = HAL_ERROR;
2117 break;
2118 }
2119 }
2120 else if (hlptim->State == HAL_LPTIM_STATE_RESET)
2121 {
2122 switch (CallbackID)
2123 {
2124 case HAL_LPTIM_MSPINIT_CB_ID :
2125 hlptim->MspInitCallback = pCallback;
2126 break;
2127
2128 case HAL_LPTIM_MSPDEINIT_CB_ID :
2129 hlptim->MspDeInitCallback = pCallback;
2130 break;
2131
2132 default :
2133 /* Return error status */
2134 status = HAL_ERROR;
2135 break;
2136 }
2137 }
2138 else
2139 {
2140 /* Return error status */
2141 status = HAL_ERROR;
2142 }
2143
2144 /* Release Lock */
2145 __HAL_UNLOCK(hlptim);
2146
2147 return status;
2148 }
2149
2150 /**
2151 * @brief Unregister a LPTIM callback
2152 * LLPTIM callback is redirected to the weak predefined callback
2153 * @param hlptim LPTIM handle
2154 * @param CallbackID ID of the callback to be unregistered
2155 * This parameter can be one of the following values:
2156 * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
2157 * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
2158 * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
2159 * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
2160 * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
2161 * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
2162 * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
2163 * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
2164 * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
2165 * @retval status
2166 */
HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef * hlptim,HAL_LPTIM_CallbackIDTypeDef CallbackID)2167 HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim,
2168 HAL_LPTIM_CallbackIDTypeDef CallbackID)
2169 {
2170 HAL_StatusTypeDef status = HAL_OK;
2171
2172 /* Process locked */
2173 __HAL_LOCK(hlptim);
2174
2175 if (hlptim->State == HAL_LPTIM_STATE_READY)
2176 {
2177 switch (CallbackID)
2178 {
2179 case HAL_LPTIM_MSPINIT_CB_ID :
2180 /* Legacy weak MspInit Callback */
2181 hlptim->MspInitCallback = HAL_LPTIM_MspInit;
2182 break;
2183
2184 case HAL_LPTIM_MSPDEINIT_CB_ID :
2185 /* Legacy weak Msp DeInit Callback */
2186 hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
2187 break;
2188
2189 case HAL_LPTIM_COMPARE_MATCH_CB_ID :
2190 /* Legacy weak Compare match Callback */
2191 hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
2192 break;
2193
2194 case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
2195 /* Legacy weak Auto-reload match Callback */
2196 hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
2197 break;
2198
2199 case HAL_LPTIM_TRIGGER_CB_ID :
2200 /* Legacy weak External trigger event detection Callback */
2201 hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
2202 break;
2203
2204 case HAL_LPTIM_COMPARE_WRITE_CB_ID :
2205 /* Legacy weak Compare register write complete Callback */
2206 hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
2207 break;
2208
2209 case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
2210 /* Legacy weak Auto-reload register write complete Callback */
2211 hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
2212 break;
2213
2214 case HAL_LPTIM_DIRECTION_UP_CB_ID :
2215 /* Legacy weak Up-counting direction change Callback */
2216 hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
2217 break;
2218
2219 case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
2220 /* Legacy weak Down-counting direction change Callback */
2221 hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
2222 break;
2223
2224 default :
2225 /* Return error status */
2226 status = HAL_ERROR;
2227 break;
2228 }
2229 }
2230 else if (hlptim->State == HAL_LPTIM_STATE_RESET)
2231 {
2232 switch (CallbackID)
2233 {
2234 case HAL_LPTIM_MSPINIT_CB_ID :
2235 /* Legacy weak MspInit Callback */
2236 hlptim->MspInitCallback = HAL_LPTIM_MspInit;
2237 break;
2238
2239 case HAL_LPTIM_MSPDEINIT_CB_ID :
2240 /* Legacy weak Msp DeInit Callback */
2241 hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
2242 break;
2243
2244 default :
2245 /* Return error status */
2246 status = HAL_ERROR;
2247 break;
2248 }
2249 }
2250 else
2251 {
2252 /* Return error status */
2253 status = HAL_ERROR;
2254 }
2255
2256 /* Release Lock */
2257 __HAL_UNLOCK(hlptim);
2258
2259 return status;
2260 }
2261 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2262
2263 /**
2264 * @}
2265 */
2266
2267 /** @defgroup LPTIM_Group5 Peripheral State functions
2268 * @brief Peripheral State functions.
2269 *
2270 @verbatim
2271 ==============================================================================
2272 ##### Peripheral State functions #####
2273 ==============================================================================
2274 [..]
2275 This subsection permits to get in run-time the status of the peripheral.
2276
2277 @endverbatim
2278 * @{
2279 */
2280
2281 /**
2282 * @brief Return the LPTIM handle state.
2283 * @param hlptim LPTIM handle
2284 * @retval HAL state
2285 */
HAL_LPTIM_GetState(LPTIM_HandleTypeDef * hlptim)2286 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
2287 {
2288 /* Return LPTIM handle state */
2289 return hlptim->State;
2290 }
2291
2292 /**
2293 * @}
2294 */
2295
2296
2297 /**
2298 * @}
2299 */
2300
2301 /* Private functions ---------------------------------------------------------*/
2302
2303 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
2304 * @{
2305 */
2306 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2307 /**
2308 * @brief Reset interrupt callbacks to the legacy weak callbacks.
2309 * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains
2310 * the configuration information for LPTIM module.
2311 * @retval None
2312 */
LPTIM_ResetCallback(LPTIM_HandleTypeDef * lptim)2313 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
2314 {
2315 /* Reset the LPTIM callback to the legacy weak callbacks */
2316 lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
2317 lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
2318 lptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
2319 lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
2320 lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
2321 lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
2322 lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
2323 }
2324 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2325
2326 /**
2327 * @brief LPTimer Wait for flag set
2328 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
2329 * the configuration information for LPTIM module.
2330 * @param flag The lptim flag
2331 * @retval HAL status
2332 */
LPTIM_WaitForFlag(LPTIM_HandleTypeDef * hlptim,uint32_t flag)2333 static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag)
2334 {
2335 HAL_StatusTypeDef result = HAL_OK;
2336 uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
2337 do
2338 {
2339 count--;
2340 if (count == 0UL)
2341 {
2342 result = HAL_TIMEOUT;
2343 }
2344 } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
2345
2346 return result;
2347 }
2348
2349 /**
2350 * @brief Disable LPTIM HW instance.
2351 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
2352 * the configuration information for LPTIM module.
2353 * @note The following sequence is required to solve LPTIM disable HW limitation.
2354 * Please check Errata Sheet ES0335 for more details under "MCU may remain
2355 * stuck in LPTIM interrupt when entering Stop mode" section.
2356 * @retval None
2357 */
LPTIM_Disable(LPTIM_HandleTypeDef * hlptim)2358 void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
2359 {
2360 uint32_t tmpclksource = 0;
2361 uint32_t tmpIER;
2362 uint32_t tmpCFGR;
2363 uint32_t tmpCMP;
2364 uint32_t tmpARR;
2365 uint32_t primask_bit;
2366 uint32_t tmpCFGR2;
2367
2368 /* Enter critical section */
2369 primask_bit = __get_PRIMASK();
2370 __set_PRIMASK(1) ;
2371
2372 /*********** Save LPTIM Config ***********/
2373 /* Save LPTIM source clock */
2374 switch ((uint32_t)hlptim->Instance)
2375 {
2376 case LPTIM1_BASE:
2377 tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
2378 break;
2379 case LPTIM2_BASE:
2380 tmpclksource = __HAL_RCC_GET_LPTIM23_SOURCE();
2381 break;
2382 case LPTIM3_BASE:
2383 tmpclksource = __HAL_RCC_GET_LPTIM23_SOURCE();
2384 break;
2385 case LPTIM4_BASE:
2386 tmpclksource = __HAL_RCC_GET_LPTIM45_SOURCE();
2387 break;
2388 case LPTIM5_BASE:
2389 tmpclksource = __HAL_RCC_GET_LPTIM45_SOURCE();
2390 break;
2391 default:
2392 break;
2393 }
2394
2395 /* Save LPTIM configuration registers */
2396 tmpIER = hlptim->Instance->IER;
2397 tmpCFGR = hlptim->Instance->CFGR;
2398 tmpCMP = hlptim->Instance->CMP;
2399 tmpARR = hlptim->Instance->ARR;
2400 tmpCFGR2 = hlptim->Instance->CFGR2;
2401
2402 /*********** Reset LPTIM ***********/
2403 switch ((uint32_t)hlptim->Instance)
2404 {
2405 case LPTIM1_BASE:
2406 __HAL_RCC_LPTIM1_FORCE_RESET();
2407 __HAL_RCC_LPTIM1_RELEASE_RESET();
2408 break;
2409 case LPTIM2_BASE:
2410 __HAL_RCC_LPTIM2_FORCE_RESET();
2411 __HAL_RCC_LPTIM2_RELEASE_RESET();
2412 break;
2413 case LPTIM3_BASE:
2414 __HAL_RCC_LPTIM3_FORCE_RESET();
2415 __HAL_RCC_LPTIM3_RELEASE_RESET();
2416 break;
2417 case LPTIM4_BASE:
2418 __HAL_RCC_LPTIM4_FORCE_RESET();
2419 __HAL_RCC_LPTIM4_RELEASE_RESET();
2420 break;
2421 case LPTIM5_BASE:
2422 __HAL_RCC_LPTIM5_FORCE_RESET();
2423 __HAL_RCC_LPTIM5_RELEASE_RESET();
2424 break;
2425 default:
2426 break;
2427 }
2428
2429 /*********** Restore LPTIM Config ***********/
2430 if ((tmpCMP != 0UL) || (tmpARR != 0UL))
2431 {
2432 /* Force LPTIM source kernel clock from APB */
2433 switch ((uint32_t)hlptim->Instance)
2434 {
2435 case LPTIM1_BASE:
2436 __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1);
2437 break;
2438 case LPTIM2_BASE:
2439 __HAL_RCC_LPTIM23_CONFIG(RCC_LPTIM23CLKSOURCE_PCLK3);
2440 break;
2441 case LPTIM3_BASE:
2442 __HAL_RCC_LPTIM23_CONFIG(RCC_LPTIM23CLKSOURCE_PCLK3);
2443 break;
2444 case LPTIM4_BASE:
2445 __HAL_RCC_LPTIM45_CONFIG(RCC_LPTIM45CLKSOURCE_PCLK3);
2446 break;
2447 case LPTIM5_BASE:
2448 __HAL_RCC_LPTIM45_CONFIG(RCC_LPTIM45CLKSOURCE_PCLK3);
2449 break;
2450 default:
2451 break;
2452 }
2453
2454 if (tmpCMP != 0UL)
2455 {
2456 /* Restore CMP register (LPTIM should be enabled first) */
2457 hlptim->Instance->CR |= LPTIM_CR_ENABLE;
2458 hlptim->Instance->CMP = tmpCMP;
2459
2460 /* Wait for the completion of the write operation to the LPTIM_CMP register */
2461 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
2462 {
2463 hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
2464 }
2465 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
2466 }
2467
2468 if (tmpARR != 0UL)
2469 {
2470 /* Restore ARR register (LPTIM should be enabled first) */
2471 hlptim->Instance->CR |= LPTIM_CR_ENABLE;
2472 hlptim->Instance->ARR = tmpARR;
2473
2474 /* Wait for the completion of the write operation to the LPTIM_ARR register */
2475 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
2476 {
2477 hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
2478 }
2479
2480 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
2481 }
2482
2483 /* Restore LPTIM source kernel clock */
2484 switch ((uint32_t)hlptim->Instance)
2485 {
2486 case LPTIM1_BASE:
2487 __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
2488 break;
2489 case LPTIM2_BASE:
2490 __HAL_RCC_LPTIM23_CONFIG(tmpclksource);
2491 break;
2492 case LPTIM3_BASE:
2493 __HAL_RCC_LPTIM23_CONFIG(tmpclksource);
2494 break;
2495 case LPTIM4_BASE:
2496 __HAL_RCC_LPTIM45_CONFIG(tmpclksource);
2497 case LPTIM5_BASE:
2498 __HAL_RCC_LPTIM45_CONFIG(tmpclksource);
2499 break;
2500 default:
2501 break;
2502 }
2503 }
2504
2505 /* Restore configuration registers (LPTIM should be disabled first) */
2506 hlptim->Instance->CR &= ~(LPTIM_CR_ENABLE);
2507 hlptim->Instance->IER = tmpIER;
2508 hlptim->Instance->CFGR = tmpCFGR;
2509 hlptim->Instance->CFGR2 = tmpCFGR2;
2510
2511 /* Exit critical section: restore previous priority mask */
2512 __set_PRIMASK(primask_bit);
2513 }
2514 /**
2515 * @}
2516 */
2517 #endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 */
2518
2519 #endif /* HAL_LPTIM_MODULE_ENABLED */
2520 /**
2521 * @}
2522 */
2523
2524 /**
2525 * @}
2526 */
2527
