1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and Errors functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2019 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The I2C HAL driver can be used as follows:
29
30 (#) Declare a I2C_HandleTypeDef handle structure, for example:
31 I2C_HandleTypeDef hi2c;
32
33 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
34 (##) Enable the I2Cx interface clock
35 (##) I2C pins configuration
36 (+++) Enable the clock for the I2C GPIOs
37 (+++) Configure I2C pins as alternate function open-drain
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the I2Cx interrupt priority
40 (+++) Enable the NVIC I2C IRQ Channel
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for
43 the transmit or receive stream
44 (+++) Enable the DMAx interface clock using
45 (+++) Configure the DMA handle parameters
46 (+++) Configure the DMA Tx or Rx stream
47 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
48 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
49 the DMA Tx or Rx stream
50
51 (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
52 Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
53
54 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
55 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
56
57 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
58
59 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
60
61 *** Polling mode IO operation ***
62 =================================
63 [..]
64 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
65 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
66 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
67 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
68
69 *** Polling mode IO MEM operation ***
70 =====================================
71 [..]
72 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
73 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
74
75
76 *** Interrupt mode IO operation ***
77 ===================================
78 [..]
79 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
80 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
81 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
82 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
83 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
84 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
85 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
86 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
87 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
88 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
89 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
90 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
91 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
92 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
93 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
94 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
95 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
96 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
97 This action will inform Master to generate a Stop condition to discard the communication.
98
99
100 *** Interrupt mode or DMA mode IO sequential operation ***
101 ==========================================================
102 [..]
103 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
104 when a direction change during transfer
105 [..]
106 (+) A specific option field manage the different steps of a sequential transfer
107 (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
108 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
109 no sequential mode
110 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
111 and data to transfer without a final stop condition
112 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
113 start condition, address and data to transfer without a final stop condition,
114 an then permit a call the same master sequential interface several times
115 (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
116 or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
117 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
118 and with new data to transfer if the direction change or manage only the new data to
119 transfer
120 if no direction change and without a final stop condition in both cases
121 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
122 and with new data to transfer if the direction change or manage only the new data to
123 transfer
124 if no direction change and with a final stop condition in both cases
125 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
126 after several call of the same master sequential interface several times
127 (link with option I2C_FIRST_AND_NEXT_FRAME).
128 Usage can, transfer several bytes one by one using
129 HAL_I2C_Master_Seq_Transmit_IT
130 or HAL_I2C_Master_Seq_Receive_IT
131 or HAL_I2C_Master_Seq_Transmit_DMA
132 or HAL_I2C_Master_Seq_Receive_DMA
133 with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
134 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
135 Receive sequence permit to call the opposite interface Receive or Transmit
136 without stopping the communication and so generate a restart condition.
137 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
138 each call of the same master sequential
139 interface.
140 Usage can, transfer several bytes one by one with a restart with slave address between
141 each bytes using
142 HAL_I2C_Master_Seq_Transmit_IT
143 or HAL_I2C_Master_Seq_Receive_IT
144 or HAL_I2C_Master_Seq_Transmit_DMA
145 or HAL_I2C_Master_Seq_Receive_DMA
146 with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
147 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
148 generation of STOP condition.
149
150 (+) Different sequential I2C interfaces are listed below:
151 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
152 HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
153 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
154 users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
155 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
156 HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
157 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
158 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
159 (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
160 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
161 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
162 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
163 HAL_I2C_DisableListen_IT()
164 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
165 add their own code to check the Address Match Code and the transmission direction request by master
166 (Write/Read).
167 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
168 add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
169 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
170 HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
171 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
172 users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
173 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
174 HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
175 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
176 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
177 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
178 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
179 (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
180 This action will inform Master to generate a Stop condition to discard the communication.
181
182 *** Interrupt mode IO MEM operation ***
183 =======================================
184 [..]
185 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
186 HAL_I2C_Mem_Write_IT()
187 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
188 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
189 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
190 HAL_I2C_Mem_Read_IT()
191 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
192 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
193 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
194 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
195
196 *** DMA mode IO operation ***
197 ==============================
198 [..]
199 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
200 HAL_I2C_Master_Transmit_DMA()
201 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
202 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
203 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
204 HAL_I2C_Master_Receive_DMA()
205 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
206 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
207 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
208 HAL_I2C_Slave_Transmit_DMA()
209 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
210 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
211 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
212 HAL_I2C_Slave_Receive_DMA()
213 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
214 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
215 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
216 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
217 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
218 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
219 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
220 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
221 This action will inform Master to generate a Stop condition to discard the communication.
222
223 *** DMA mode IO MEM operation ***
224 =================================
225 [..]
226 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
227 HAL_I2C_Mem_Write_DMA()
228 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
229 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
230 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
231 HAL_I2C_Mem_Read_DMA()
232 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
233 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
234 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
235 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
236
237
238 *** I2C HAL driver macros list ***
239 ==================================
240 [..]
241 Below the list of most used macros in I2C HAL driver.
242
243 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
244 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
245 (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
246 (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
247 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
248 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
249 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
250
251 *** Callback registration ***
252 =============================================
253 [..]
254 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
255 allows the user to configure dynamically the driver callbacks.
256 Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
257 to register an interrupt callback.
258 [..]
259 Function HAL_I2C_RegisterCallback() allows to register following callbacks:
260 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
261 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
262 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
263 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
264 (+) ListenCpltCallback : callback for end of listen mode.
265 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
266 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
267 (+) ErrorCallback : callback for error detection.
268 (+) AbortCpltCallback : callback for abort completion process.
269 (+) MspInitCallback : callback for Msp Init.
270 (+) MspDeInitCallback : callback for Msp DeInit.
271 This function takes as parameters the HAL peripheral handle, the Callback ID
272 and a pointer to the user callback function.
273 [..]
274 For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
275 [..]
276 Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
277 weak function.
278 HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
279 and the Callback ID.
280 This function allows to reset following callbacks:
281 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
282 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
283 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
284 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
285 (+) ListenCpltCallback : callback for end of listen mode.
286 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
287 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
288 (+) ErrorCallback : callback for error detection.
289 (+) AbortCpltCallback : callback for abort completion process.
290 (+) MspInitCallback : callback for Msp Init.
291 (+) MspDeInitCallback : callback for Msp DeInit.
292 [..]
293 For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
294 [..]
295 By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
296 all callbacks are set to the corresponding weak functions:
297 examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
298 Exception done for MspInit and MspDeInit functions that are
299 reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
300 these callbacks are null (not registered beforehand).
301 If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
302 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
303 [..]
304 Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
305 Exception done MspInit/MspDeInit functions that can be registered/unregistered
306 in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
307 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
308 Then, the user first registers the MspInit/MspDeInit user callbacks
309 using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
310 or HAL_I2C_Init() function.
311 [..]
312 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
313 not defined, the callback registration feature is not available and all callbacks
314 are set to the corresponding weak functions.
315
316 [..]
317 (@) You can refer to the I2C HAL driver header file for more useful macros
318
319 @endverbatim
320 */
321
322 /* Includes ------------------------------------------------------------------*/
323 #include "stm32mp1xx_hal.h"
324
325 /** @addtogroup STM32MP1xx_HAL_Driver
326 * @{
327 */
328
329 /** @defgroup I2C I2C
330 * @brief I2C HAL module driver
331 * @{
332 */
333
334 #ifdef HAL_I2C_MODULE_ENABLED
335
336 /* Private typedef -----------------------------------------------------------*/
337 /* Private define ------------------------------------------------------------*/
338
339 /** @defgroup I2C_Private_Define I2C Private Define
340 * @{
341 */
342 #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
343 #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
344 #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
345 #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
346 #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
347 #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
348 #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
349 #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
350 #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
351 #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
352
353 #define MAX_NBYTE_SIZE 255U
354 #define SLAVE_ADDR_SHIFT 7U
355 #define SLAVE_ADDR_MSK 0x06U
356
357 /* Private define for @ref PreviousState usage */
358 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
359 (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
360 (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
361 /*!< Mask State define, keep only RX and TX bits */
362 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
363 /*!< Default Value */
364 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
365 (uint32_t)HAL_I2C_MODE_MASTER))
366 /*!< Master Busy TX, combinaison of State LSB and Mode enum */
367 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
368 (uint32_t)HAL_I2C_MODE_MASTER))
369 /*!< Master Busy RX, combinaison of State LSB and Mode enum */
370 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
371 (uint32_t)HAL_I2C_MODE_SLAVE))
372 /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
373 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
374 (uint32_t)HAL_I2C_MODE_SLAVE))
375 /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
376 #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
377 (uint32_t)HAL_I2C_MODE_MEM))
378 /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
379 #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
380 (uint32_t)HAL_I2C_MODE_MEM))
381 /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
382
383
384 /* Private define to centralize the enable/disable of Interrupts */
385 #define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with
386 @ref I2C_XFER_LISTEN_IT */
387 #define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with
388 @ref I2C_XFER_LISTEN_IT */
389 #define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
390 and @ref I2C_XFER_RX_IT */
391
392 #define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error
393 and NACK treatment */
394 #define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */
395 #define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */
396
397 /* Private define Sequential Transfer Options default/reset value */
398 #define I2C_NO_OPTION_FRAME (0xFFFF0000U)
399 /**
400 * @}
401 */
402
403 /* Private macro -------------------------------------------------------------*/
404 /* Macro to get remaining data to transfer on DMA side */
405 #ifdef HAL_MDMA_MODULE_ENABLED
406 #define I2C_GET_MDMA_REMAIN_DATA_RX(__HANDLE__) ((uint32_t)(((MDMA_Channel_TypeDef *) \
407 (__HANDLE__)->hmdmarx->Instance)->CBNDTR))
408
409 #define I2C_GET_MDMA_REMAIN_DATA_TX(__HANDLE__) ((uint32_t)(((MDMA_Channel_TypeDef *) \
410 (__HANDLE__)->hmdmatx->Instance)->CBNDTR))
411 #endif /* HAL_MDMA_MODULE_ENABLED */
412 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
413
414 /* Private variables ---------------------------------------------------------*/
415 /* Private function prototypes -----------------------------------------------*/
416
417 /** @defgroup I2C_Private_Functions I2C Private Functions
418 * @{
419 */
420 /* Private functions to handle DMA transfer */
421 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
422 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
423 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
424 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
425 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
426 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
427
428 #ifdef HAL_MDMA_MODULE_ENABLED
429 /* Private functions to handle MDMA transfer */
430 static void I2C_MDMAMasterTransmitCplt(MDMA_HandleTypeDef *hmdma);
431 static void I2C_MDMAMasterReceiveCplt(MDMA_HandleTypeDef *hmdma);
432 static void I2C_MDMASlaveTransmitCplt(MDMA_HandleTypeDef *hmdma);
433 static void I2C_MDMASlaveReceiveCplt(MDMA_HandleTypeDef *hmdma);
434 static void I2C_MDMAError(MDMA_HandleTypeDef *hmdma);
435 static void I2C_MDMAAbort(MDMA_HandleTypeDef *hmdma);
436 #endif /* HAL_MDMA_MODULE_ENABLED */
437
438 /* Private functions to handle IT transfer */
439 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
440 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
441 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
442 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
443 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
444 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
445 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
446
447 /* Private functions to handle IT transfer */
448 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
449 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
450 uint32_t Tickstart);
451 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
452 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
453 uint32_t Tickstart);
454
455 /* Private functions for I2C transfer IRQ handler */
456 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
457 uint32_t ITSources);
458 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
459 uint32_t ITSources);
460 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
461 uint32_t ITSources);
462 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
463 uint32_t ITSources);
464
465 /* Private functions to handle flags during polling transfer */
466 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
467 uint32_t Timeout, uint32_t Tickstart);
468 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
469 uint32_t Tickstart);
470 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
471 uint32_t Tickstart);
472 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
473 uint32_t Tickstart);
474 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
475 uint32_t Tickstart);
476
477 /* Private functions to centralize the enable/disable of Interrupts */
478 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
479 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
480
481 /* Private function to treat different error callback */
482 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
483
484 /* Private function to flush TXDR register */
485 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
486
487 /* Private function to handle start, restart or stop a transfer */
488 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
489 uint32_t Request);
490
491 /* Private function to Convert Specific options */
492 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
493 /**
494 * @}
495 */
496
497 /* Exported functions --------------------------------------------------------*/
498
499 /** @defgroup I2C_Exported_Functions I2C Exported Functions
500 * @{
501 */
502
503 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
504 * @brief Initialization and Configuration functions
505 *
506 @verbatim
507 ===============================================================================
508 ##### Initialization and de-initialization functions #####
509 ===============================================================================
510 [..] This subsection provides a set of functions allowing to initialize and
511 deinitialize the I2Cx peripheral:
512
513 (+) User must Implement HAL_I2C_MspInit() function in which he configures
514 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
515
516 (+) Call the function HAL_I2C_Init() to configure the selected device with
517 the selected configuration:
518 (++) Clock Timing
519 (++) Own Address 1
520 (++) Addressing mode (Master, Slave)
521 (++) Dual Addressing mode
522 (++) Own Address 2
523 (++) Own Address 2 Mask
524 (++) General call mode
525 (++) Nostretch mode
526
527 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
528 of the selected I2Cx peripheral.
529
530 @endverbatim
531 * @{
532 */
533
534 /**
535 * @brief Initializes the I2C according to the specified parameters
536 * in the I2C_InitTypeDef and initialize the associated handle.
537 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
538 * the configuration information for the specified I2C.
539 * @retval HAL status
540 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)541 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
542 {
543 /* Check the I2C handle allocation */
544 if (hi2c == NULL)
545 {
546 return HAL_ERROR;
547 }
548
549 /* Check the parameters */
550 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
551 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
552 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
553 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
554 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
555 assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
556 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
557 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
558
559 if (hi2c->State == HAL_I2C_STATE_RESET)
560 {
561 /* Allocate lock resource and initialize it */
562 hi2c->Lock = HAL_UNLOCKED;
563
564 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
565 /* Init the I2C Callback settings */
566 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
567 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
568 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
569 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
570 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
571 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
572 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
573 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
574 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
575 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
576
577 if (hi2c->MspInitCallback == NULL)
578 {
579 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
580 }
581
582 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
583 hi2c->MspInitCallback(hi2c);
584 #else
585 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
586 HAL_I2C_MspInit(hi2c);
587 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
588 }
589
590 hi2c->State = HAL_I2C_STATE_BUSY;
591
592 /* Disable the selected I2C peripheral */
593 __HAL_I2C_DISABLE(hi2c);
594
595 /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
596 /* Configure I2Cx: Frequency range */
597 hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
598
599 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
600 /* Disable Own Address1 before set the Own Address1 configuration */
601 hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
602
603 /* Configure I2Cx: Own Address1 and ack own address1 mode */
604 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
605 {
606 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
607 }
608 else /* I2C_ADDRESSINGMODE_10BIT */
609 {
610 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
611 }
612
613 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
614 /* Configure I2Cx: Addressing Master mode */
615 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
616 {
617 hi2c->Instance->CR2 = (I2C_CR2_ADD10);
618 }
619 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
620 hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
621
622 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
623 /* Disable Own Address2 before set the Own Address2 configuration */
624 hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
625
626 /* Configure I2Cx: Dual mode and Own Address2 */
627 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
628 (hi2c->Init.OwnAddress2Masks << 8));
629
630 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
631 /* Configure I2Cx: Generalcall and NoStretch mode */
632 hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
633
634 /* Enable the selected I2C peripheral */
635 __HAL_I2C_ENABLE(hi2c);
636
637 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
638 hi2c->State = HAL_I2C_STATE_READY;
639 hi2c->PreviousState = I2C_STATE_NONE;
640 hi2c->Mode = HAL_I2C_MODE_NONE;
641
642 return HAL_OK;
643 }
644
645 /**
646 * @brief DeInitialize the I2C peripheral.
647 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
648 * the configuration information for the specified I2C.
649 * @retval HAL status
650 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)651 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
652 {
653 /* Check the I2C handle allocation */
654 if (hi2c == NULL)
655 {
656 return HAL_ERROR;
657 }
658
659 /* Check the parameters */
660 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
661
662 hi2c->State = HAL_I2C_STATE_BUSY;
663
664 /* Disable the I2C Peripheral Clock */
665 __HAL_I2C_DISABLE(hi2c);
666
667 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
668 if (hi2c->MspDeInitCallback == NULL)
669 {
670 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
671 }
672
673 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
674 hi2c->MspDeInitCallback(hi2c);
675 #else
676 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
677 HAL_I2C_MspDeInit(hi2c);
678 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
679
680 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
681 hi2c->State = HAL_I2C_STATE_RESET;
682 hi2c->PreviousState = I2C_STATE_NONE;
683 hi2c->Mode = HAL_I2C_MODE_NONE;
684
685 /* Release Lock */
686 __HAL_UNLOCK(hi2c);
687
688 return HAL_OK;
689 }
690
691 /**
692 * @brief Initialize the I2C MSP.
693 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
694 * the configuration information for the specified I2C.
695 * @retval None
696 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)697 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
698 {
699 /* Prevent unused argument(s) compilation warning */
700 UNUSED(hi2c);
701
702 /* NOTE : This function should not be modified, when the callback is needed,
703 the HAL_I2C_MspInit could be implemented in the user file
704 */
705 }
706
707 /**
708 * @brief DeInitialize the I2C MSP.
709 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
710 * the configuration information for the specified I2C.
711 * @retval None
712 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)713 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
714 {
715 /* Prevent unused argument(s) compilation warning */
716 UNUSED(hi2c);
717
718 /* NOTE : This function should not be modified, when the callback is needed,
719 the HAL_I2C_MspDeInit could be implemented in the user file
720 */
721 }
722
723 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
724 /**
725 * @brief Register a User I2C Callback
726 * To be used instead of the weak predefined callback
727 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
728 * the configuration information for the specified I2C.
729 * @param CallbackID ID of the callback to be registered
730 * This parameter can be one of the following values:
731 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
732 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
733 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
734 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
735 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
736 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
737 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
738 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
739 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
740 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
741 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
742 * @param pCallback pointer to the Callback function
743 * @retval HAL status
744 */
HAL_I2C_RegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID,pI2C_CallbackTypeDef pCallback)745 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
746 pI2C_CallbackTypeDef pCallback)
747 {
748 HAL_StatusTypeDef status = HAL_OK;
749
750 if (pCallback == NULL)
751 {
752 /* Update the error code */
753 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
754
755 return HAL_ERROR;
756 }
757 /* Process locked */
758 __HAL_LOCK(hi2c);
759
760 if (HAL_I2C_STATE_READY == hi2c->State)
761 {
762 switch (CallbackID)
763 {
764 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
765 hi2c->MasterTxCpltCallback = pCallback;
766 break;
767
768 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
769 hi2c->MasterRxCpltCallback = pCallback;
770 break;
771
772 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
773 hi2c->SlaveTxCpltCallback = pCallback;
774 break;
775
776 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
777 hi2c->SlaveRxCpltCallback = pCallback;
778 break;
779
780 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
781 hi2c->ListenCpltCallback = pCallback;
782 break;
783
784 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
785 hi2c->MemTxCpltCallback = pCallback;
786 break;
787
788 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
789 hi2c->MemRxCpltCallback = pCallback;
790 break;
791
792 case HAL_I2C_ERROR_CB_ID :
793 hi2c->ErrorCallback = pCallback;
794 break;
795
796 case HAL_I2C_ABORT_CB_ID :
797 hi2c->AbortCpltCallback = pCallback;
798 break;
799
800 case HAL_I2C_MSPINIT_CB_ID :
801 hi2c->MspInitCallback = pCallback;
802 break;
803
804 case HAL_I2C_MSPDEINIT_CB_ID :
805 hi2c->MspDeInitCallback = pCallback;
806 break;
807
808 default :
809 /* Update the error code */
810 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
811
812 /* Return error status */
813 status = HAL_ERROR;
814 break;
815 }
816 }
817 else if (HAL_I2C_STATE_RESET == hi2c->State)
818 {
819 switch (CallbackID)
820 {
821 case HAL_I2C_MSPINIT_CB_ID :
822 hi2c->MspInitCallback = pCallback;
823 break;
824
825 case HAL_I2C_MSPDEINIT_CB_ID :
826 hi2c->MspDeInitCallback = pCallback;
827 break;
828
829 default :
830 /* Update the error code */
831 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
832
833 /* Return error status */
834 status = HAL_ERROR;
835 break;
836 }
837 }
838 else
839 {
840 /* Update the error code */
841 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
842
843 /* Return error status */
844 status = HAL_ERROR;
845 }
846
847 /* Release Lock */
848 __HAL_UNLOCK(hi2c);
849 return status;
850 }
851
852 /**
853 * @brief Unregister an I2C Callback
854 * I2C callback is redirected to the weak predefined callback
855 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
856 * the configuration information for the specified I2C.
857 * @param CallbackID ID of the callback to be unregistered
858 * This parameter can be one of the following values:
859 * This parameter can be one of the following values:
860 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
861 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
862 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
863 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
864 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
865 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
866 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
867 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
868 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
869 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
870 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
871 * @retval HAL status
872 */
HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID)873 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
874 {
875 HAL_StatusTypeDef status = HAL_OK;
876
877 /* Process locked */
878 __HAL_LOCK(hi2c);
879
880 if (HAL_I2C_STATE_READY == hi2c->State)
881 {
882 switch (CallbackID)
883 {
884 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
885 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
886 break;
887
888 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
889 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
890 break;
891
892 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
893 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
894 break;
895
896 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
897 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
898 break;
899
900 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
901 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
902 break;
903
904 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
905 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
906 break;
907
908 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
909 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
910 break;
911
912 case HAL_I2C_ERROR_CB_ID :
913 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
914 break;
915
916 case HAL_I2C_ABORT_CB_ID :
917 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
918 break;
919
920 case HAL_I2C_MSPINIT_CB_ID :
921 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
922 break;
923
924 case HAL_I2C_MSPDEINIT_CB_ID :
925 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
926 break;
927
928 default :
929 /* Update the error code */
930 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
931
932 /* Return error status */
933 status = HAL_ERROR;
934 break;
935 }
936 }
937 else if (HAL_I2C_STATE_RESET == hi2c->State)
938 {
939 switch (CallbackID)
940 {
941 case HAL_I2C_MSPINIT_CB_ID :
942 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
943 break;
944
945 case HAL_I2C_MSPDEINIT_CB_ID :
946 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
947 break;
948
949 default :
950 /* Update the error code */
951 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
952
953 /* Return error status */
954 status = HAL_ERROR;
955 break;
956 }
957 }
958 else
959 {
960 /* Update the error code */
961 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
962
963 /* Return error status */
964 status = HAL_ERROR;
965 }
966
967 /* Release Lock */
968 __HAL_UNLOCK(hi2c);
969 return status;
970 }
971
972 /**
973 * @brief Register the Slave Address Match I2C Callback
974 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
975 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
976 * the configuration information for the specified I2C.
977 * @param pCallback pointer to the Address Match Callback function
978 * @retval HAL status
979 */
HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef * hi2c,pI2C_AddrCallbackTypeDef pCallback)980 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
981 {
982 HAL_StatusTypeDef status = HAL_OK;
983
984 if (pCallback == NULL)
985 {
986 /* Update the error code */
987 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
988
989 return HAL_ERROR;
990 }
991 /* Process locked */
992 __HAL_LOCK(hi2c);
993
994 if (HAL_I2C_STATE_READY == hi2c->State)
995 {
996 hi2c->AddrCallback = pCallback;
997 }
998 else
999 {
1000 /* Update the error code */
1001 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
1002
1003 /* Return error status */
1004 status = HAL_ERROR;
1005 }
1006
1007 /* Release Lock */
1008 __HAL_UNLOCK(hi2c);
1009 return status;
1010 }
1011
1012 /**
1013 * @brief UnRegister the Slave Address Match I2C Callback
1014 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
1015 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1016 * the configuration information for the specified I2C.
1017 * @retval HAL status
1018 */
HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef * hi2c)1019 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
1020 {
1021 HAL_StatusTypeDef status = HAL_OK;
1022
1023 /* Process locked */
1024 __HAL_LOCK(hi2c);
1025
1026 if (HAL_I2C_STATE_READY == hi2c->State)
1027 {
1028 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
1029 }
1030 else
1031 {
1032 /* Update the error code */
1033 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
1034
1035 /* Return error status */
1036 status = HAL_ERROR;
1037 }
1038
1039 /* Release Lock */
1040 __HAL_UNLOCK(hi2c);
1041 return status;
1042 }
1043
1044 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
1045
1046 /**
1047 * @}
1048 */
1049
1050 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
1051 * @brief Data transfers functions
1052 *
1053 @verbatim
1054 ===============================================================================
1055 ##### IO operation functions #####
1056 ===============================================================================
1057 [..]
1058 This subsection provides a set of functions allowing to manage the I2C data
1059 transfers.
1060
1061 (#) There are two modes of transfer:
1062 (++) Blocking mode : The communication is performed in the polling mode.
1063 The status of all data processing is returned by the same function
1064 after finishing transfer.
1065 (++) No-Blocking mode : The communication is performed using Interrupts
1066 or DMA. These functions return the status of the transfer startup.
1067 The end of the data processing will be indicated through the
1068 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
1069 using DMA mode.
1070
1071 (#) Blocking mode functions are :
1072 (++) HAL_I2C_Master_Transmit()
1073 (++) HAL_I2C_Master_Receive()
1074 (++) HAL_I2C_Slave_Transmit()
1075 (++) HAL_I2C_Slave_Receive()
1076 (++) HAL_I2C_Mem_Write()
1077 (++) HAL_I2C_Mem_Read()
1078 (++) HAL_I2C_IsDeviceReady()
1079
1080 (#) No-Blocking mode functions with Interrupt are :
1081 (++) HAL_I2C_Master_Transmit_IT()
1082 (++) HAL_I2C_Master_Receive_IT()
1083 (++) HAL_I2C_Slave_Transmit_IT()
1084 (++) HAL_I2C_Slave_Receive_IT()
1085 (++) HAL_I2C_Mem_Write_IT()
1086 (++) HAL_I2C_Mem_Read_IT()
1087 (++) HAL_I2C_Master_Seq_Transmit_IT()
1088 (++) HAL_I2C_Master_Seq_Receive_IT()
1089 (++) HAL_I2C_Slave_Seq_Transmit_IT()
1090 (++) HAL_I2C_Slave_Seq_Receive_IT()
1091 (++) HAL_I2C_EnableListen_IT()
1092 (++) HAL_I2C_DisableListen_IT()
1093 (++) HAL_I2C_Master_Abort_IT()
1094
1095 (#) No-Blocking mode functions with DMA are :
1096 (++) HAL_I2C_Master_Transmit_DMA()
1097 (++) HAL_I2C_Master_Receive_DMA()
1098 (++) HAL_I2C_Slave_Transmit_DMA()
1099 (++) HAL_I2C_Slave_Receive_DMA()
1100 (++) HAL_I2C_Mem_Write_DMA()
1101 (++) HAL_I2C_Mem_Read_DMA()
1102 (++) HAL_I2C_Master_Seq_Transmit_DMA()
1103 (++) HAL_I2C_Master_Seq_Receive_DMA()
1104 (++) HAL_I2C_Slave_Seq_Transmit_DMA()
1105 (++) HAL_I2C_Slave_Seq_Receive_DMA()
1106
1107 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
1108 (++) HAL_I2C_MasterTxCpltCallback()
1109 (++) HAL_I2C_MasterRxCpltCallback()
1110 (++) HAL_I2C_SlaveTxCpltCallback()
1111 (++) HAL_I2C_SlaveRxCpltCallback()
1112 (++) HAL_I2C_MemTxCpltCallback()
1113 (++) HAL_I2C_MemRxCpltCallback()
1114 (++) HAL_I2C_AddrCallback()
1115 (++) HAL_I2C_ListenCpltCallback()
1116 (++) HAL_I2C_ErrorCallback()
1117 (++) HAL_I2C_AbortCpltCallback()
1118
1119 @endverbatim
1120 * @{
1121 */
1122
1123 /**
1124 * @brief Transmits in master mode an amount of data in blocking mode.
1125 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1126 * the configuration information for the specified I2C.
1127 * @param DevAddress Target device address: The device 7 bits address value
1128 * in datasheet must be shifted to the left before calling the interface
1129 * @param pData Pointer to data buffer
1130 * @param Size Amount of data to be sent
1131 * @param Timeout Timeout duration
1132 * @retval HAL status
1133 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1134 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1135 uint16_t Size, uint32_t Timeout)
1136 {
1137 uint32_t tickstart;
1138
1139 if (hi2c->State == HAL_I2C_STATE_READY)
1140 {
1141 /* Process Locked */
1142 __HAL_LOCK(hi2c);
1143
1144 /* Init tickstart for timeout management*/
1145 tickstart = HAL_GetTick();
1146
1147 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1148 {
1149 return HAL_ERROR;
1150 }
1151
1152 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1153 hi2c->Mode = HAL_I2C_MODE_MASTER;
1154 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1155
1156 /* Prepare transfer parameters */
1157 hi2c->pBuffPtr = pData;
1158 hi2c->XferCount = Size;
1159 hi2c->XferISR = NULL;
1160
1161 /* Send Slave Address */
1162 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1163 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1164 {
1165 hi2c->XferSize = MAX_NBYTE_SIZE;
1166 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1167 I2C_GENERATE_START_WRITE);
1168 }
1169 else
1170 {
1171 hi2c->XferSize = hi2c->XferCount;
1172 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1173 I2C_GENERATE_START_WRITE);
1174 }
1175
1176 while (hi2c->XferCount > 0U)
1177 {
1178 /* Wait until TXIS flag is set */
1179 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1180 {
1181 return HAL_ERROR;
1182 }
1183 /* Write data to TXDR */
1184 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1185
1186 /* Increment Buffer pointer */
1187 hi2c->pBuffPtr++;
1188
1189 hi2c->XferCount--;
1190 hi2c->XferSize--;
1191
1192 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1193 {
1194 /* Wait until TCR flag is set */
1195 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1196 {
1197 return HAL_ERROR;
1198 }
1199
1200 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1201 {
1202 hi2c->XferSize = MAX_NBYTE_SIZE;
1203 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1204 I2C_NO_STARTSTOP);
1205 }
1206 else
1207 {
1208 hi2c->XferSize = hi2c->XferCount;
1209 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1210 I2C_NO_STARTSTOP);
1211 }
1212 }
1213 }
1214
1215 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1216 /* Wait until STOPF flag is set */
1217 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1218 {
1219 return HAL_ERROR;
1220 }
1221
1222 /* Clear STOP Flag */
1223 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1224
1225 /* Clear Configuration Register 2 */
1226 I2C_RESET_CR2(hi2c);
1227
1228 hi2c->State = HAL_I2C_STATE_READY;
1229 hi2c->Mode = HAL_I2C_MODE_NONE;
1230
1231 /* Process Unlocked */
1232 __HAL_UNLOCK(hi2c);
1233
1234 return HAL_OK;
1235 }
1236 else
1237 {
1238 return HAL_BUSY;
1239 }
1240 }
1241
1242 /**
1243 * @brief Receives in master mode an amount of data in blocking mode.
1244 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1245 * the configuration information for the specified I2C.
1246 * @param DevAddress Target device address: The device 7 bits address value
1247 * in datasheet must be shifted to the left before calling the interface
1248 * @param pData Pointer to data buffer
1249 * @param Size Amount of data to be sent
1250 * @param Timeout Timeout duration
1251 * @retval HAL status
1252 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1253 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1254 uint16_t Size, uint32_t Timeout)
1255 {
1256 uint32_t tickstart;
1257
1258 if (hi2c->State == HAL_I2C_STATE_READY)
1259 {
1260 /* Process Locked */
1261 __HAL_LOCK(hi2c);
1262
1263 /* Init tickstart for timeout management*/
1264 tickstart = HAL_GetTick();
1265
1266 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1267 {
1268 return HAL_ERROR;
1269 }
1270
1271 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1272 hi2c->Mode = HAL_I2C_MODE_MASTER;
1273 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1274
1275 /* Prepare transfer parameters */
1276 hi2c->pBuffPtr = pData;
1277 hi2c->XferCount = Size;
1278 hi2c->XferISR = NULL;
1279
1280 /* Send Slave Address */
1281 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1282 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1283 {
1284 hi2c->XferSize = MAX_NBYTE_SIZE;
1285 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1286 I2C_GENERATE_START_READ);
1287 }
1288 else
1289 {
1290 hi2c->XferSize = hi2c->XferCount;
1291 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1292 I2C_GENERATE_START_READ);
1293 }
1294
1295 while (hi2c->XferCount > 0U)
1296 {
1297 /* Wait until RXNE flag is set */
1298 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1299 {
1300 return HAL_ERROR;
1301 }
1302
1303 /* Read data from RXDR */
1304 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1305
1306 /* Increment Buffer pointer */
1307 hi2c->pBuffPtr++;
1308
1309 hi2c->XferSize--;
1310 hi2c->XferCount--;
1311
1312 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1313 {
1314 /* Wait until TCR flag is set */
1315 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1316 {
1317 return HAL_ERROR;
1318 }
1319
1320 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1321 {
1322 hi2c->XferSize = MAX_NBYTE_SIZE;
1323 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1324 I2C_NO_STARTSTOP);
1325 }
1326 else
1327 {
1328 hi2c->XferSize = hi2c->XferCount;
1329 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1330 I2C_NO_STARTSTOP);
1331 }
1332 }
1333 }
1334
1335 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1336 /* Wait until STOPF flag is set */
1337 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1338 {
1339 return HAL_ERROR;
1340 }
1341
1342 /* Clear STOP Flag */
1343 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1344
1345 /* Clear Configuration Register 2 */
1346 I2C_RESET_CR2(hi2c);
1347
1348 hi2c->State = HAL_I2C_STATE_READY;
1349 hi2c->Mode = HAL_I2C_MODE_NONE;
1350
1351 /* Process Unlocked */
1352 __HAL_UNLOCK(hi2c);
1353
1354 return HAL_OK;
1355 }
1356 else
1357 {
1358 return HAL_BUSY;
1359 }
1360 }
1361
1362 /**
1363 * @brief Transmits in slave mode an amount of data in blocking mode.
1364 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1365 * the configuration information for the specified I2C.
1366 * @param pData Pointer to data buffer
1367 * @param Size Amount of data to be sent
1368 * @param Timeout Timeout duration
1369 * @retval HAL status
1370 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1371 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1372 uint32_t Timeout)
1373 {
1374 uint32_t tickstart;
1375
1376 if (hi2c->State == HAL_I2C_STATE_READY)
1377 {
1378 if ((pData == NULL) || (Size == 0U))
1379 {
1380 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1381 return HAL_ERROR;
1382 }
1383 /* Process Locked */
1384 __HAL_LOCK(hi2c);
1385
1386 /* Init tickstart for timeout management*/
1387 tickstart = HAL_GetTick();
1388
1389 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1390 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1391 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1392
1393 /* Prepare transfer parameters */
1394 hi2c->pBuffPtr = pData;
1395 hi2c->XferCount = Size;
1396 hi2c->XferISR = NULL;
1397
1398 /* Enable Address Acknowledge */
1399 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1400
1401 /* Wait until ADDR flag is set */
1402 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1403 {
1404 /* Disable Address Acknowledge */
1405 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1406 return HAL_ERROR;
1407 }
1408
1409 /* Clear ADDR flag */
1410 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1411
1412 /* If 10bit addressing mode is selected */
1413 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1414 {
1415 /* Wait until ADDR flag is set */
1416 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1417 {
1418 /* Disable Address Acknowledge */
1419 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1420 return HAL_ERROR;
1421 }
1422
1423 /* Clear ADDR flag */
1424 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1425 }
1426
1427 /* Wait until DIR flag is set Transmitter mode */
1428 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
1429 {
1430 /* Disable Address Acknowledge */
1431 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1432 return HAL_ERROR;
1433 }
1434
1435 while (hi2c->XferCount > 0U)
1436 {
1437 /* Wait until TXIS flag is set */
1438 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1439 {
1440 /* Disable Address Acknowledge */
1441 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1442 return HAL_ERROR;
1443 }
1444
1445 /* Write data to TXDR */
1446 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1447
1448 /* Increment Buffer pointer */
1449 hi2c->pBuffPtr++;
1450
1451 hi2c->XferCount--;
1452 }
1453
1454 /* Wait until AF flag is set */
1455 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
1456 {
1457 /* Disable Address Acknowledge */
1458 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1459 return HAL_ERROR;
1460 }
1461
1462 /* Flush TX register */
1463 I2C_Flush_TXDR(hi2c);
1464
1465 /* Clear AF flag */
1466 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1467
1468 /* Wait until STOP flag is set */
1469 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1470 {
1471 /* Disable Address Acknowledge */
1472 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1473
1474 return HAL_ERROR;
1475 }
1476
1477 /* Clear STOP flag */
1478 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1479
1480 /* Wait until BUSY flag is reset */
1481 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1482 {
1483 /* Disable Address Acknowledge */
1484 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1485 return HAL_ERROR;
1486 }
1487
1488 /* Disable Address Acknowledge */
1489 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1490
1491 hi2c->State = HAL_I2C_STATE_READY;
1492 hi2c->Mode = HAL_I2C_MODE_NONE;
1493
1494 /* Process Unlocked */
1495 __HAL_UNLOCK(hi2c);
1496
1497 return HAL_OK;
1498 }
1499 else
1500 {
1501 return HAL_BUSY;
1502 }
1503 }
1504
1505 /**
1506 * @brief Receive in slave mode an amount of data in blocking mode
1507 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1508 * the configuration information for the specified I2C.
1509 * @param pData Pointer to data buffer
1510 * @param Size Amount of data to be sent
1511 * @param Timeout Timeout duration
1512 * @retval HAL status
1513 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1514 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1515 uint32_t Timeout)
1516 {
1517 uint32_t tickstart;
1518
1519 if (hi2c->State == HAL_I2C_STATE_READY)
1520 {
1521 if ((pData == NULL) || (Size == 0U))
1522 {
1523 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1524 return HAL_ERROR;
1525 }
1526 /* Process Locked */
1527 __HAL_LOCK(hi2c);
1528
1529 /* Init tickstart for timeout management*/
1530 tickstart = HAL_GetTick();
1531
1532 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1533 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1534 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1535
1536 /* Prepare transfer parameters */
1537 hi2c->pBuffPtr = pData;
1538 hi2c->XferCount = Size;
1539 hi2c->XferSize = hi2c->XferCount;
1540 hi2c->XferISR = NULL;
1541
1542 /* Enable Address Acknowledge */
1543 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1544
1545 /* Wait until ADDR flag is set */
1546 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1547 {
1548 /* Disable Address Acknowledge */
1549 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1550 return HAL_ERROR;
1551 }
1552
1553 /* Clear ADDR flag */
1554 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1555
1556 /* Wait until DIR flag is reset Receiver mode */
1557 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
1558 {
1559 /* Disable Address Acknowledge */
1560 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1561 return HAL_ERROR;
1562 }
1563
1564 while (hi2c->XferCount > 0U)
1565 {
1566 /* Wait until RXNE flag is set */
1567 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1568 {
1569 /* Disable Address Acknowledge */
1570 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1571
1572 /* Store Last receive data if any */
1573 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
1574 {
1575 /* Read data from RXDR */
1576 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1577
1578 /* Increment Buffer pointer */
1579 hi2c->pBuffPtr++;
1580
1581 hi2c->XferCount--;
1582 hi2c->XferSize--;
1583 }
1584
1585 return HAL_ERROR;
1586 }
1587
1588 /* Read data from RXDR */
1589 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1590
1591 /* Increment Buffer pointer */
1592 hi2c->pBuffPtr++;
1593
1594 hi2c->XferCount--;
1595 hi2c->XferSize--;
1596 }
1597
1598 /* Wait until STOP flag is set */
1599 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1600 {
1601 /* Disable Address Acknowledge */
1602 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1603 return HAL_ERROR;
1604 }
1605
1606 /* Clear STOP flag */
1607 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1608
1609 /* Wait until BUSY flag is reset */
1610 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1611 {
1612 /* Disable Address Acknowledge */
1613 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1614 return HAL_ERROR;
1615 }
1616
1617 /* Disable Address Acknowledge */
1618 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1619
1620 hi2c->State = HAL_I2C_STATE_READY;
1621 hi2c->Mode = HAL_I2C_MODE_NONE;
1622
1623 /* Process Unlocked */
1624 __HAL_UNLOCK(hi2c);
1625
1626 return HAL_OK;
1627 }
1628 else
1629 {
1630 return HAL_BUSY;
1631 }
1632 }
1633
1634 /**
1635 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1636 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1637 * the configuration information for the specified I2C.
1638 * @param DevAddress Target device address: The device 7 bits address value
1639 * in datasheet must be shifted to the left before calling the interface
1640 * @param pData Pointer to data buffer
1641 * @param Size Amount of data to be sent
1642 * @retval HAL status
1643 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1644 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1645 uint16_t Size)
1646 {
1647 uint32_t xfermode;
1648
1649 if (hi2c->State == HAL_I2C_STATE_READY)
1650 {
1651 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1652 {
1653 return HAL_BUSY;
1654 }
1655
1656 /* Process Locked */
1657 __HAL_LOCK(hi2c);
1658
1659 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1660 hi2c->Mode = HAL_I2C_MODE_MASTER;
1661 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1662
1663 /* Prepare transfer parameters */
1664 hi2c->pBuffPtr = pData;
1665 hi2c->XferCount = Size;
1666 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1667 hi2c->XferISR = I2C_Master_ISR_IT;
1668
1669 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1670 {
1671 hi2c->XferSize = MAX_NBYTE_SIZE;
1672 xfermode = I2C_RELOAD_MODE;
1673 }
1674 else
1675 {
1676 hi2c->XferSize = hi2c->XferCount;
1677 xfermode = I2C_AUTOEND_MODE;
1678 }
1679
1680 /* Send Slave Address */
1681 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1682 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1683
1684 /* Process Unlocked */
1685 __HAL_UNLOCK(hi2c);
1686
1687 /* Note : The I2C interrupts must be enabled after unlocking current process
1688 to avoid the risk of I2C interrupt handle execution before current
1689 process unlock */
1690
1691 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1692 /* possible to enable all of these */
1693 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1694 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1695 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1696
1697 return HAL_OK;
1698 }
1699 else
1700 {
1701 return HAL_BUSY;
1702 }
1703 }
1704
1705 /**
1706 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1707 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1708 * the configuration information for the specified I2C.
1709 * @param DevAddress Target device address: The device 7 bits address value
1710 * in datasheet must be shifted to the left before calling the interface
1711 * @param pData Pointer to data buffer
1712 * @param Size Amount of data to be sent
1713 * @retval HAL status
1714 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1715 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1716 uint16_t Size)
1717 {
1718 uint32_t xfermode;
1719
1720 if (hi2c->State == HAL_I2C_STATE_READY)
1721 {
1722 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1723 {
1724 return HAL_BUSY;
1725 }
1726
1727 /* Process Locked */
1728 __HAL_LOCK(hi2c);
1729
1730 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1731 hi2c->Mode = HAL_I2C_MODE_MASTER;
1732 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1733
1734 /* Prepare transfer parameters */
1735 hi2c->pBuffPtr = pData;
1736 hi2c->XferCount = Size;
1737 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1738 hi2c->XferISR = I2C_Master_ISR_IT;
1739
1740 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1741 {
1742 hi2c->XferSize = MAX_NBYTE_SIZE;
1743 xfermode = I2C_RELOAD_MODE;
1744 }
1745 else
1746 {
1747 hi2c->XferSize = hi2c->XferCount;
1748 xfermode = I2C_AUTOEND_MODE;
1749 }
1750
1751 /* Send Slave Address */
1752 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1753 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
1754
1755 /* Process Unlocked */
1756 __HAL_UNLOCK(hi2c);
1757
1758 /* Note : The I2C interrupts must be enabled after unlocking current process
1759 to avoid the risk of I2C interrupt handle execution before current
1760 process unlock */
1761
1762 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1763 /* possible to enable all of these */
1764 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1765 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1766 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
1767
1768 return HAL_OK;
1769 }
1770 else
1771 {
1772 return HAL_BUSY;
1773 }
1774 }
1775
1776 /**
1777 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1778 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1779 * the configuration information for the specified I2C.
1780 * @param pData Pointer to data buffer
1781 * @param Size Amount of data to be sent
1782 * @retval HAL status
1783 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1784 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1785 {
1786 if (hi2c->State == HAL_I2C_STATE_READY)
1787 {
1788 /* Process Locked */
1789 __HAL_LOCK(hi2c);
1790
1791 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1792 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1793 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1794
1795 /* Enable Address Acknowledge */
1796 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1797
1798 /* Prepare transfer parameters */
1799 hi2c->pBuffPtr = pData;
1800 hi2c->XferCount = Size;
1801 hi2c->XferSize = hi2c->XferCount;
1802 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1803 hi2c->XferISR = I2C_Slave_ISR_IT;
1804
1805 /* Process Unlocked */
1806 __HAL_UNLOCK(hi2c);
1807
1808 /* Note : The I2C interrupts must be enabled after unlocking current process
1809 to avoid the risk of I2C interrupt handle execution before current
1810 process unlock */
1811
1812 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1813 /* possible to enable all of these */
1814 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1815 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1816 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
1817
1818 return HAL_OK;
1819 }
1820 else
1821 {
1822 return HAL_BUSY;
1823 }
1824 }
1825
1826 /**
1827 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1828 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1829 * the configuration information for the specified I2C.
1830 * @param pData Pointer to data buffer
1831 * @param Size Amount of data to be sent
1832 * @retval HAL status
1833 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1834 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1835 {
1836 if (hi2c->State == HAL_I2C_STATE_READY)
1837 {
1838 /* Process Locked */
1839 __HAL_LOCK(hi2c);
1840
1841 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1842 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1843 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1844
1845 /* Enable Address Acknowledge */
1846 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1847
1848 /* Prepare transfer parameters */
1849 hi2c->pBuffPtr = pData;
1850 hi2c->XferCount = Size;
1851 hi2c->XferSize = hi2c->XferCount;
1852 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1853 hi2c->XferISR = I2C_Slave_ISR_IT;
1854
1855 /* Process Unlocked */
1856 __HAL_UNLOCK(hi2c);
1857
1858 /* Note : The I2C interrupts must be enabled after unlocking current process
1859 to avoid the risk of I2C interrupt handle execution before current
1860 process unlock */
1861
1862 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1863 /* possible to enable all of these */
1864 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1865 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1866 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
1867
1868 return HAL_OK;
1869 }
1870 else
1871 {
1872 return HAL_BUSY;
1873 }
1874 }
1875
1876 /**
1877 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1878 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1879 * the configuration information for the specified I2C.
1880 * @param DevAddress Target device address: The device 7 bits address value
1881 * in datasheet must be shifted to the left before calling the interface
1882 * @param pData Pointer to data buffer
1883 * @param Size Amount of data to be sent
1884 * @retval HAL status
1885 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1886 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1887 uint16_t Size)
1888 {
1889 uint32_t xfermode;
1890 HAL_StatusTypeDef dmaxferstatus;
1891
1892 if (hi2c->State == HAL_I2C_STATE_READY)
1893 {
1894 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1895 {
1896 return HAL_BUSY;
1897 }
1898
1899 /* Process Locked */
1900 __HAL_LOCK(hi2c);
1901
1902 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1903 hi2c->Mode = HAL_I2C_MODE_MASTER;
1904 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1905
1906 /* Prepare transfer parameters */
1907 hi2c->pBuffPtr = pData;
1908 hi2c->XferCount = Size;
1909 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1910 hi2c->XferISR = I2C_Master_ISR_DMA;
1911
1912 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1913 {
1914 hi2c->XferSize = MAX_NBYTE_SIZE;
1915 xfermode = I2C_RELOAD_MODE;
1916 }
1917 else
1918 {
1919 hi2c->XferSize = hi2c->XferCount;
1920 xfermode = I2C_AUTOEND_MODE;
1921 }
1922
1923 if (hi2c->XferSize > 0U)
1924 {
1925 if (hi2c->hdmatx != NULL)
1926 {
1927 /* Set the I2C DMA transfer complete callback */
1928 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
1929
1930 /* Set the DMA error callback */
1931 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1932
1933 /* Set the unused DMA callbacks to NULL */
1934 hi2c->hdmatx->XferHalfCpltCallback = NULL;
1935 hi2c->hdmatx->XferAbortCallback = NULL;
1936
1937 /* Enable the DMA stream */
1938 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
1939 hi2c->XferSize);
1940 }
1941 #ifdef HAL_MDMA_MODULE_ENABLED
1942 else if (hi2c->hmdmatx != NULL)
1943 {
1944 /* Set the I2C MDMA transfer complete callback */
1945 hi2c->hmdmatx->XferCpltCallback = I2C_MDMAMasterTransmitCplt;
1946
1947 /* Set the MDMA error callback */
1948 hi2c->hmdmatx->XferErrorCallback = I2C_MDMAError;
1949
1950 /* Set the unused MDMA callbacks to NULL */
1951 hi2c->hmdmatx->XferAbortCallback = NULL;
1952
1953 /* Enable the MDMA stream */
1954 dmaxferstatus = HAL_MDMA_Start_IT(hi2c->hmdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
1955 hi2c->XferSize, 1);
1956 }
1957 #endif /* HAL_MDMA_MODULE_ENABLED */
1958 else
1959 {
1960 /* Update I2C state */
1961 hi2c->State = HAL_I2C_STATE_READY;
1962 hi2c->Mode = HAL_I2C_MODE_NONE;
1963
1964 /* Update I2C error code */
1965 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
1966
1967 /* Process Unlocked */
1968 __HAL_UNLOCK(hi2c);
1969
1970 return HAL_ERROR;
1971 }
1972
1973 if (dmaxferstatus == HAL_OK)
1974 {
1975 /* Send Slave Address */
1976 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1977 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1978
1979 /* Update XferCount value */
1980 hi2c->XferCount -= hi2c->XferSize;
1981
1982 /* Process Unlocked */
1983 __HAL_UNLOCK(hi2c);
1984
1985 /* Note : The I2C interrupts must be enabled after unlocking current process
1986 to avoid the risk of I2C interrupt handle execution before current
1987 process unlock */
1988 /* Enable ERR and NACK interrupts */
1989 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
1990
1991 /* Enable DMA Request */
1992 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
1993 }
1994 else
1995 {
1996 /* Update I2C state */
1997 hi2c->State = HAL_I2C_STATE_READY;
1998 hi2c->Mode = HAL_I2C_MODE_NONE;
1999
2000 /* Update I2C error code */
2001 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2002
2003 /* Process Unlocked */
2004 __HAL_UNLOCK(hi2c);
2005
2006 return HAL_ERROR;
2007 }
2008 }
2009 else
2010 {
2011 /* Update Transfer ISR function pointer */
2012 hi2c->XferISR = I2C_Master_ISR_IT;
2013
2014 /* Send Slave Address */
2015 /* Set NBYTES to write and generate START condition */
2016 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2017 I2C_GENERATE_START_WRITE);
2018
2019 /* Process Unlocked */
2020 __HAL_UNLOCK(hi2c);
2021
2022 /* Note : The I2C interrupts must be enabled after unlocking current process
2023 to avoid the risk of I2C interrupt handle execution before current
2024 process unlock */
2025 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2026 /* possible to enable all of these */
2027 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2028 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2029 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2030 }
2031
2032 return HAL_OK;
2033 }
2034 else
2035 {
2036 return HAL_BUSY;
2037 }
2038 }
2039
2040 /**
2041 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2042 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2043 * the configuration information for the specified I2C.
2044 * @param DevAddress Target device address: The device 7 bits address value
2045 * in datasheet must be shifted to the left before calling the interface
2046 * @param pData Pointer to data buffer
2047 * @param Size Amount of data to be sent
2048 * @retval HAL status
2049 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2050 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
2051 uint16_t Size)
2052 {
2053 uint32_t xfermode;
2054 HAL_StatusTypeDef dmaxferstatus;
2055
2056 if (hi2c->State == HAL_I2C_STATE_READY)
2057 {
2058 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2059 {
2060 return HAL_BUSY;
2061 }
2062
2063 /* Process Locked */
2064 __HAL_LOCK(hi2c);
2065
2066 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2067 hi2c->Mode = HAL_I2C_MODE_MASTER;
2068 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2069
2070 /* Prepare transfer parameters */
2071 hi2c->pBuffPtr = pData;
2072 hi2c->XferCount = Size;
2073 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2074 hi2c->XferISR = I2C_Master_ISR_DMA;
2075
2076 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2077 {
2078 hi2c->XferSize = MAX_NBYTE_SIZE;
2079 xfermode = I2C_RELOAD_MODE;
2080 }
2081 else
2082 {
2083 hi2c->XferSize = hi2c->XferCount;
2084 xfermode = I2C_AUTOEND_MODE;
2085 }
2086
2087 if (hi2c->XferSize > 0U)
2088 {
2089 if (hi2c->hdmarx != NULL)
2090 {
2091 /* Set the I2C DMA transfer complete callback */
2092 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
2093
2094 /* Set the DMA error callback */
2095 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2096
2097 /* Set the unused DMA callbacks to NULL */
2098 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2099 hi2c->hdmarx->XferAbortCallback = NULL;
2100
2101 /* Enable the DMA stream */
2102 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2103 hi2c->XferSize);
2104 }
2105 #ifdef HAL_MDMA_MODULE_ENABLED
2106 else if (hi2c->hmdmarx != NULL)
2107 {
2108 /* Set the I2C MDMA transfer complete callback */
2109 hi2c->hmdmarx->XferCpltCallback = I2C_MDMAMasterReceiveCplt;
2110
2111 /* Set the MDMA error callback */
2112 hi2c->hmdmarx->XferErrorCallback = I2C_MDMAError;
2113
2114 /* Set the unused MDMA callbacks to NULL */
2115 hi2c->hmdmarx->XferAbortCallback = NULL;
2116
2117 /* Enable the MDMA stream */
2118 dmaxferstatus = HAL_MDMA_Start_IT(hi2c->hmdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2119 hi2c->XferSize, 1);
2120 }
2121 #endif /* HAL_MDMA_MODULE_ENABLED */
2122 else
2123 {
2124 /* Update I2C state */
2125 hi2c->State = HAL_I2C_STATE_READY;
2126 hi2c->Mode = HAL_I2C_MODE_NONE;
2127
2128 /* Update I2C error code */
2129 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2130
2131 /* Process Unlocked */
2132 __HAL_UNLOCK(hi2c);
2133
2134 return HAL_ERROR;
2135 }
2136
2137 if (dmaxferstatus == HAL_OK)
2138 {
2139 /* Send Slave Address */
2140 /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2141 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2142
2143 /* Update XferCount value */
2144 hi2c->XferCount -= hi2c->XferSize;
2145
2146 /* Process Unlocked */
2147 __HAL_UNLOCK(hi2c);
2148
2149 /* Note : The I2C interrupts must be enabled after unlocking current process
2150 to avoid the risk of I2C interrupt handle execution before current
2151 process unlock */
2152 /* Enable ERR and NACK interrupts */
2153 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2154
2155 /* Enable DMA Request */
2156 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2157 }
2158 else
2159 {
2160 /* Update I2C state */
2161 hi2c->State = HAL_I2C_STATE_READY;
2162 hi2c->Mode = HAL_I2C_MODE_NONE;
2163
2164 /* Update I2C error code */
2165 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2166
2167 /* Process Unlocked */
2168 __HAL_UNLOCK(hi2c);
2169
2170 return HAL_ERROR;
2171 }
2172 }
2173 else
2174 {
2175 /* Update Transfer ISR function pointer */
2176 hi2c->XferISR = I2C_Master_ISR_IT;
2177
2178 /* Send Slave Address */
2179 /* Set NBYTES to read and generate START condition */
2180 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2181 I2C_GENERATE_START_READ);
2182
2183 /* Process Unlocked */
2184 __HAL_UNLOCK(hi2c);
2185
2186 /* Note : The I2C interrupts must be enabled after unlocking current process
2187 to avoid the risk of I2C interrupt handle execution before current
2188 process unlock */
2189 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2190 /* possible to enable all of these */
2191 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2192 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2193 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2194 }
2195
2196 return HAL_OK;
2197 }
2198 else
2199 {
2200 return HAL_BUSY;
2201 }
2202 }
2203
2204 /**
2205 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2206 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2207 * the configuration information for the specified I2C.
2208 * @param pData Pointer to data buffer
2209 * @param Size Amount of data to be sent
2210 * @retval HAL status
2211 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2212 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2213 {
2214 HAL_StatusTypeDef dmaxferstatus;
2215
2216 if (hi2c->State == HAL_I2C_STATE_READY)
2217 {
2218 if ((pData == NULL) || (Size == 0U))
2219 {
2220 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2221 return HAL_ERROR;
2222 }
2223 /* Process Locked */
2224 __HAL_LOCK(hi2c);
2225
2226 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2227 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2228 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2229
2230 /* Prepare transfer parameters */
2231 hi2c->pBuffPtr = pData;
2232 hi2c->XferCount = Size;
2233 hi2c->XferSize = hi2c->XferCount;
2234 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2235 hi2c->XferISR = I2C_Slave_ISR_DMA;
2236
2237 if (hi2c->hdmatx != NULL)
2238 {
2239 /* Set the I2C DMA transfer complete callback */
2240 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
2241
2242 /* Set the DMA error callback */
2243 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2244
2245 /* Set the unused DMA callbacks to NULL */
2246 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2247 hi2c->hdmatx->XferAbortCallback = NULL;
2248
2249 /* Enable the DMA stream */
2250 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
2251 hi2c->XferSize);
2252 }
2253 #ifdef HAL_MDMA_MODULE_ENABLED
2254 else if (hi2c->hmdmatx != NULL)
2255 {
2256 /* Set the I2C MDMA transfer complete callback */
2257 hi2c->hmdmatx->XferCpltCallback = I2C_MDMASlaveTransmitCplt;
2258
2259 /* Set the MDMA error callback */
2260 hi2c->hmdmatx->XferErrorCallback = I2C_MDMAError;
2261
2262 /* Set the unused MDMA callbacks to NULL */
2263 hi2c->hmdmatx->XferAbortCallback = NULL;
2264
2265 /* Enable the MDMA stream */
2266 dmaxferstatus = HAL_MDMA_Start_IT(hi2c->hmdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
2267 hi2c->XferSize, 1);
2268 }
2269 #endif /* HAL_MDMA_MODULE_ENABLED */
2270 else
2271 {
2272 /* Update I2C state */
2273 hi2c->State = HAL_I2C_STATE_LISTEN;
2274 hi2c->Mode = HAL_I2C_MODE_NONE;
2275
2276 /* Update I2C error code */
2277 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2278
2279 /* Process Unlocked */
2280 __HAL_UNLOCK(hi2c);
2281
2282 return HAL_ERROR;
2283 }
2284
2285 if (dmaxferstatus == HAL_OK)
2286 {
2287 /* Enable Address Acknowledge */
2288 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2289
2290 /* Process Unlocked */
2291 __HAL_UNLOCK(hi2c);
2292
2293 /* Note : The I2C interrupts must be enabled after unlocking current process
2294 to avoid the risk of I2C interrupt handle execution before current
2295 process unlock */
2296 /* Enable ERR, STOP, NACK, ADDR interrupts */
2297 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2298
2299 /* Enable DMA Request */
2300 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2301 }
2302 else
2303 {
2304 /* Update I2C state */
2305 hi2c->State = HAL_I2C_STATE_LISTEN;
2306 hi2c->Mode = HAL_I2C_MODE_NONE;
2307
2308 /* Update I2C error code */
2309 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2310
2311 /* Process Unlocked */
2312 __HAL_UNLOCK(hi2c);
2313
2314 return HAL_ERROR;
2315 }
2316
2317 return HAL_OK;
2318 }
2319 else
2320 {
2321 return HAL_BUSY;
2322 }
2323 }
2324
2325 /**
2326 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2327 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2328 * the configuration information for the specified I2C.
2329 * @param pData Pointer to data buffer
2330 * @param Size Amount of data to be sent
2331 * @retval HAL status
2332 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2333 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2334 {
2335 HAL_StatusTypeDef dmaxferstatus;
2336
2337 if (hi2c->State == HAL_I2C_STATE_READY)
2338 {
2339 if ((pData == NULL) || (Size == 0U))
2340 {
2341 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2342 return HAL_ERROR;
2343 }
2344 /* Process Locked */
2345 __HAL_LOCK(hi2c);
2346
2347 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2348 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2349 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2350
2351 /* Prepare transfer parameters */
2352 hi2c->pBuffPtr = pData;
2353 hi2c->XferCount = Size;
2354 hi2c->XferSize = hi2c->XferCount;
2355 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2356 hi2c->XferISR = I2C_Slave_ISR_DMA;
2357
2358 if (hi2c->hdmarx != NULL)
2359 {
2360 /* Set the I2C DMA transfer complete callback */
2361 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
2362
2363 /* Set the DMA error callback */
2364 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2365
2366 /* Set the unused DMA callbacks to NULL */
2367 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2368 hi2c->hdmarx->XferAbortCallback = NULL;
2369
2370 /* Enable the DMA stream */
2371 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2372 hi2c->XferSize);
2373 }
2374 #ifdef HAL_MDMA_MODULE_ENABLED
2375 else if (hi2c->hmdmarx != NULL)
2376 {
2377 /* Set the I2C MDMA transfer complete callback */
2378 hi2c->hmdmarx->XferCpltCallback = I2C_MDMASlaveReceiveCplt;
2379
2380 /* Set the MDMA error callback */
2381 hi2c->hmdmarx->XferErrorCallback = I2C_MDMAError;
2382
2383 /* Set the unused MDMA callbacks to NULL */
2384 hi2c->hmdmarx->XferAbortCallback = NULL;
2385
2386 /* Enable the MDMA stream */
2387 dmaxferstatus = HAL_MDMA_Start_IT(hi2c->hmdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2388 hi2c->XferSize, 1);
2389 }
2390 #endif /* HAL_MDMA_MODULE_ENABLED */
2391 else
2392 {
2393 /* Update I2C state */
2394 hi2c->State = HAL_I2C_STATE_LISTEN;
2395 hi2c->Mode = HAL_I2C_MODE_NONE;
2396
2397 /* Update I2C error code */
2398 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2399
2400 /* Process Unlocked */
2401 __HAL_UNLOCK(hi2c);
2402
2403 return HAL_ERROR;
2404 }
2405
2406 if (dmaxferstatus == HAL_OK)
2407 {
2408 /* Enable Address Acknowledge */
2409 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2410
2411 /* Process Unlocked */
2412 __HAL_UNLOCK(hi2c);
2413
2414 /* Note : The I2C interrupts must be enabled after unlocking current process
2415 to avoid the risk of I2C interrupt handle execution before current
2416 process unlock */
2417 /* Enable ERR, STOP, NACK, ADDR interrupts */
2418 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2419
2420 /* Enable DMA Request */
2421 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2422 }
2423 else
2424 {
2425 /* Update I2C state */
2426 hi2c->State = HAL_I2C_STATE_LISTEN;
2427 hi2c->Mode = HAL_I2C_MODE_NONE;
2428
2429 /* Update I2C error code */
2430 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2431
2432 /* Process Unlocked */
2433 __HAL_UNLOCK(hi2c);
2434
2435 return HAL_ERROR;
2436 }
2437
2438 return HAL_OK;
2439 }
2440 else
2441 {
2442 return HAL_BUSY;
2443 }
2444 }
2445 /**
2446 * @brief Write an amount of data in blocking mode to a specific memory address
2447 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2448 * the configuration information for the specified I2C.
2449 * @param DevAddress Target device address: The device 7 bits address value
2450 * in datasheet must be shifted to the left before calling the interface
2451 * @param MemAddress Internal memory address
2452 * @param MemAddSize Size of internal memory address
2453 * @param pData Pointer to data buffer
2454 * @param Size Amount of data to be sent
2455 * @param Timeout Timeout duration
2456 * @retval HAL status
2457 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2458 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2459 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2460 {
2461 uint32_t tickstart;
2462
2463 /* Check the parameters */
2464 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2465
2466 if (hi2c->State == HAL_I2C_STATE_READY)
2467 {
2468 if ((pData == NULL) || (Size == 0U))
2469 {
2470 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2471 return HAL_ERROR;
2472 }
2473
2474 /* Process Locked */
2475 __HAL_LOCK(hi2c);
2476
2477 /* Init tickstart for timeout management*/
2478 tickstart = HAL_GetTick();
2479
2480 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2481 {
2482 return HAL_ERROR;
2483 }
2484
2485 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2486 hi2c->Mode = HAL_I2C_MODE_MEM;
2487 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2488
2489 /* Prepare transfer parameters */
2490 hi2c->pBuffPtr = pData;
2491 hi2c->XferCount = Size;
2492 hi2c->XferISR = NULL;
2493
2494 /* Send Slave Address and Memory Address */
2495 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2496 {
2497 /* Process Unlocked */
2498 __HAL_UNLOCK(hi2c);
2499 return HAL_ERROR;
2500 }
2501
2502 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
2503 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2504 {
2505 hi2c->XferSize = MAX_NBYTE_SIZE;
2506 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
2507 }
2508 else
2509 {
2510 hi2c->XferSize = hi2c->XferCount;
2511 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
2512 }
2513
2514 do
2515 {
2516 /* Wait until TXIS flag is set */
2517 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2518 {
2519 return HAL_ERROR;
2520 }
2521
2522 /* Write data to TXDR */
2523 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2524
2525 /* Increment Buffer pointer */
2526 hi2c->pBuffPtr++;
2527
2528 hi2c->XferCount--;
2529 hi2c->XferSize--;
2530
2531 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2532 {
2533 /* Wait until TCR flag is set */
2534 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2535 {
2536 return HAL_ERROR;
2537 }
2538
2539 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2540 {
2541 hi2c->XferSize = MAX_NBYTE_SIZE;
2542 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2543 I2C_NO_STARTSTOP);
2544 }
2545 else
2546 {
2547 hi2c->XferSize = hi2c->XferCount;
2548 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2549 I2C_NO_STARTSTOP);
2550 }
2551 }
2552
2553 } while (hi2c->XferCount > 0U);
2554
2555 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2556 /* Wait until STOPF flag is reset */
2557 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2558 {
2559 return HAL_ERROR;
2560 }
2561
2562 /* Clear STOP Flag */
2563 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2564
2565 /* Clear Configuration Register 2 */
2566 I2C_RESET_CR2(hi2c);
2567
2568 hi2c->State = HAL_I2C_STATE_READY;
2569 hi2c->Mode = HAL_I2C_MODE_NONE;
2570
2571 /* Process Unlocked */
2572 __HAL_UNLOCK(hi2c);
2573
2574 return HAL_OK;
2575 }
2576 else
2577 {
2578 return HAL_BUSY;
2579 }
2580 }
2581
2582 /**
2583 * @brief Read an amount of data in blocking mode from a specific memory address
2584 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2585 * the configuration information for the specified I2C.
2586 * @param DevAddress Target device address: The device 7 bits address value
2587 * in datasheet must be shifted to the left before calling the interface
2588 * @param MemAddress Internal memory address
2589 * @param MemAddSize Size of internal memory address
2590 * @param pData Pointer to data buffer
2591 * @param Size Amount of data to be sent
2592 * @param Timeout Timeout duration
2593 * @retval HAL status
2594 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2595 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2596 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2597 {
2598 uint32_t tickstart;
2599
2600 /* Check the parameters */
2601 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2602
2603 if (hi2c->State == HAL_I2C_STATE_READY)
2604 {
2605 if ((pData == NULL) || (Size == 0U))
2606 {
2607 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2608 return HAL_ERROR;
2609 }
2610
2611 /* Process Locked */
2612 __HAL_LOCK(hi2c);
2613
2614 /* Init tickstart for timeout management*/
2615 tickstart = HAL_GetTick();
2616
2617 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2618 {
2619 return HAL_ERROR;
2620 }
2621
2622 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2623 hi2c->Mode = HAL_I2C_MODE_MEM;
2624 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2625
2626 /* Prepare transfer parameters */
2627 hi2c->pBuffPtr = pData;
2628 hi2c->XferCount = Size;
2629 hi2c->XferISR = NULL;
2630
2631 /* Send Slave Address and Memory Address */
2632 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2633 {
2634 /* Process Unlocked */
2635 __HAL_UNLOCK(hi2c);
2636 return HAL_ERROR;
2637 }
2638
2639 /* Send Slave Address */
2640 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2641 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2642 {
2643 hi2c->XferSize = MAX_NBYTE_SIZE;
2644 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2645 I2C_GENERATE_START_READ);
2646 }
2647 else
2648 {
2649 hi2c->XferSize = hi2c->XferCount;
2650 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2651 I2C_GENERATE_START_READ);
2652 }
2653
2654 do
2655 {
2656 /* Wait until RXNE flag is set */
2657 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
2658 {
2659 return HAL_ERROR;
2660 }
2661
2662 /* Read data from RXDR */
2663 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
2664
2665 /* Increment Buffer pointer */
2666 hi2c->pBuffPtr++;
2667
2668 hi2c->XferSize--;
2669 hi2c->XferCount--;
2670
2671 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2672 {
2673 /* Wait until TCR flag is set */
2674 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2675 {
2676 return HAL_ERROR;
2677 }
2678
2679 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2680 {
2681 hi2c->XferSize = MAX_NBYTE_SIZE;
2682 I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
2683 I2C_NO_STARTSTOP);
2684 }
2685 else
2686 {
2687 hi2c->XferSize = hi2c->XferCount;
2688 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2689 I2C_NO_STARTSTOP);
2690 }
2691 }
2692 } while (hi2c->XferCount > 0U);
2693
2694 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2695 /* Wait until STOPF flag is reset */
2696 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2697 {
2698 return HAL_ERROR;
2699 }
2700
2701 /* Clear STOP Flag */
2702 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2703
2704 /* Clear Configuration Register 2 */
2705 I2C_RESET_CR2(hi2c);
2706
2707 hi2c->State = HAL_I2C_STATE_READY;
2708 hi2c->Mode = HAL_I2C_MODE_NONE;
2709
2710 /* Process Unlocked */
2711 __HAL_UNLOCK(hi2c);
2712
2713 return HAL_OK;
2714 }
2715 else
2716 {
2717 return HAL_BUSY;
2718 }
2719 }
2720 /**
2721 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2722 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2723 * the configuration information for the specified I2C.
2724 * @param DevAddress Target device address: The device 7 bits address value
2725 * in datasheet must be shifted to the left before calling the interface
2726 * @param MemAddress Internal memory address
2727 * @param MemAddSize Size of internal memory address
2728 * @param pData Pointer to data buffer
2729 * @param Size Amount of data to be sent
2730 * @retval HAL status
2731 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2732 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2733 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2734 {
2735 uint32_t tickstart;
2736 uint32_t xfermode;
2737
2738 /* Check the parameters */
2739 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2740
2741 if (hi2c->State == HAL_I2C_STATE_READY)
2742 {
2743 if ((pData == NULL) || (Size == 0U))
2744 {
2745 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2746 return HAL_ERROR;
2747 }
2748
2749 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2750 {
2751 return HAL_BUSY;
2752 }
2753
2754 /* Process Locked */
2755 __HAL_LOCK(hi2c);
2756
2757 /* Init tickstart for timeout management*/
2758 tickstart = HAL_GetTick();
2759
2760 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2761 hi2c->Mode = HAL_I2C_MODE_MEM;
2762 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2763
2764 /* Prepare transfer parameters */
2765 hi2c->pBuffPtr = pData;
2766 hi2c->XferCount = Size;
2767 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2768 hi2c->XferISR = I2C_Master_ISR_IT;
2769
2770 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2771 {
2772 hi2c->XferSize = MAX_NBYTE_SIZE;
2773 xfermode = I2C_RELOAD_MODE;
2774 }
2775 else
2776 {
2777 hi2c->XferSize = hi2c->XferCount;
2778 xfermode = I2C_AUTOEND_MODE;
2779 }
2780
2781 /* Send Slave Address and Memory Address */
2782 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
2783 != HAL_OK)
2784 {
2785 /* Process Unlocked */
2786 __HAL_UNLOCK(hi2c);
2787 return HAL_ERROR;
2788 }
2789
2790 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2791 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
2792
2793 /* Process Unlocked */
2794 __HAL_UNLOCK(hi2c);
2795
2796 /* Note : The I2C interrupts must be enabled after unlocking current process
2797 to avoid the risk of I2C interrupt handle execution before current
2798 process unlock */
2799
2800 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2801 /* possible to enable all of these */
2802 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2803 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2804 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2805
2806 return HAL_OK;
2807 }
2808 else
2809 {
2810 return HAL_BUSY;
2811 }
2812 }
2813
2814 /**
2815 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2816 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2817 * the configuration information for the specified I2C.
2818 * @param DevAddress Target device address: The device 7 bits address value
2819 * in datasheet must be shifted to the left before calling the interface
2820 * @param MemAddress Internal memory address
2821 * @param MemAddSize Size of internal memory address
2822 * @param pData Pointer to data buffer
2823 * @param Size Amount of data to be sent
2824 * @retval HAL status
2825 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2826 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2827 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2828 {
2829 uint32_t tickstart;
2830 uint32_t xfermode;
2831
2832 /* Check the parameters */
2833 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2834
2835 if (hi2c->State == HAL_I2C_STATE_READY)
2836 {
2837 if ((pData == NULL) || (Size == 0U))
2838 {
2839 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2840 return HAL_ERROR;
2841 }
2842
2843 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2844 {
2845 return HAL_BUSY;
2846 }
2847
2848 /* Process Locked */
2849 __HAL_LOCK(hi2c);
2850
2851 /* Init tickstart for timeout management*/
2852 tickstart = HAL_GetTick();
2853
2854 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2855 hi2c->Mode = HAL_I2C_MODE_MEM;
2856 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2857
2858 /* Prepare transfer parameters */
2859 hi2c->pBuffPtr = pData;
2860 hi2c->XferCount = Size;
2861 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2862 hi2c->XferISR = I2C_Master_ISR_IT;
2863
2864 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2865 {
2866 hi2c->XferSize = MAX_NBYTE_SIZE;
2867 xfermode = I2C_RELOAD_MODE;
2868 }
2869 else
2870 {
2871 hi2c->XferSize = hi2c->XferCount;
2872 xfermode = I2C_AUTOEND_MODE;
2873 }
2874
2875 /* Send Slave Address and Memory Address */
2876 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
2877 {
2878 /* Process Unlocked */
2879 __HAL_UNLOCK(hi2c);
2880 return HAL_ERROR;
2881 }
2882
2883 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2884 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2885
2886 /* Process Unlocked */
2887 __HAL_UNLOCK(hi2c);
2888
2889 /* Note : The I2C interrupts must be enabled after unlocking current process
2890 to avoid the risk of I2C interrupt handle execution before current
2891 process unlock */
2892
2893 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
2894 /* possible to enable all of these */
2895 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2896 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2897 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
2898
2899 return HAL_OK;
2900 }
2901 else
2902 {
2903 return HAL_BUSY;
2904 }
2905 }
2906 /**
2907 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
2908 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2909 * the configuration information for the specified I2C.
2910 * @param DevAddress Target device address: The device 7 bits address value
2911 * in datasheet must be shifted to the left before calling the interface
2912 * @param MemAddress Internal memory address
2913 * @param MemAddSize Size of internal memory address
2914 * @param pData Pointer to data buffer
2915 * @param Size Amount of data to be sent
2916 * @retval HAL status
2917 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2918 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2919 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2920 {
2921 uint32_t tickstart;
2922 uint32_t xfermode;
2923 HAL_StatusTypeDef dmaxferstatus;
2924
2925 /* Check the parameters */
2926 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2927
2928 if (hi2c->State == HAL_I2C_STATE_READY)
2929 {
2930 if ((pData == NULL) || (Size == 0U))
2931 {
2932 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2933 return HAL_ERROR;
2934 }
2935
2936 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2937 {
2938 return HAL_BUSY;
2939 }
2940
2941 /* Process Locked */
2942 __HAL_LOCK(hi2c);
2943
2944 /* Init tickstart for timeout management*/
2945 tickstart = HAL_GetTick();
2946
2947 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2948 hi2c->Mode = HAL_I2C_MODE_MEM;
2949 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2950
2951 /* Prepare transfer parameters */
2952 hi2c->pBuffPtr = pData;
2953 hi2c->XferCount = Size;
2954 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2955 hi2c->XferISR = I2C_Master_ISR_DMA;
2956
2957 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2958 {
2959 hi2c->XferSize = MAX_NBYTE_SIZE;
2960 xfermode = I2C_RELOAD_MODE;
2961 }
2962 else
2963 {
2964 hi2c->XferSize = hi2c->XferCount;
2965 xfermode = I2C_AUTOEND_MODE;
2966 }
2967
2968 /* Send Slave Address and Memory Address */
2969 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
2970 != HAL_OK)
2971 {
2972 /* Process Unlocked */
2973 __HAL_UNLOCK(hi2c);
2974 return HAL_ERROR;
2975 }
2976
2977
2978 if (hi2c->hdmatx != NULL)
2979 {
2980 /* Set the I2C DMA transfer complete callback */
2981 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
2982
2983 /* Set the DMA error callback */
2984 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2985
2986 /* Set the unused DMA callbacks to NULL */
2987 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2988 hi2c->hdmatx->XferAbortCallback = NULL;
2989
2990 /* Enable the DMA stream */
2991 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
2992 hi2c->XferSize);
2993 }
2994 #ifdef HAL_MDMA_MODULE_ENABLED
2995 else if (hi2c->hmdmatx != NULL)
2996 {
2997 /* Set the I2C MDMA transfer complete callback */
2998 hi2c->hmdmatx->XferCpltCallback = I2C_MDMAMasterTransmitCplt;
2999
3000 /* Set the MDMA error callback */
3001 hi2c->hmdmatx->XferErrorCallback = I2C_MDMAError;
3002
3003 /* Set the unused MDMA callbacks to NULL */
3004 hi2c->hmdmatx->XferAbortCallback = NULL;
3005
3006 /* Enable the MDMA stream */
3007 dmaxferstatus = HAL_MDMA_Start_IT(hi2c->hmdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3008 hi2c->XferSize, 1);
3009 }
3010 #endif /* HAL_MDMA_MODULE_ENABLED */
3011 else
3012 {
3013 /* Update I2C state */
3014 hi2c->State = HAL_I2C_STATE_READY;
3015 hi2c->Mode = HAL_I2C_MODE_NONE;
3016
3017 /* Update I2C error code */
3018 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3019
3020 /* Process Unlocked */
3021 __HAL_UNLOCK(hi2c);
3022
3023 return HAL_ERROR;
3024 }
3025
3026 if (dmaxferstatus == HAL_OK)
3027 {
3028 /* Send Slave Address */
3029 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
3030 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
3031
3032 /* Update XferCount value */
3033 hi2c->XferCount -= hi2c->XferSize;
3034
3035 /* Process Unlocked */
3036 __HAL_UNLOCK(hi2c);
3037
3038 /* Note : The I2C interrupts must be enabled after unlocking current process
3039 to avoid the risk of I2C interrupt handle execution before current
3040 process unlock */
3041 /* Enable ERR and NACK interrupts */
3042 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3043
3044 /* Enable DMA Request */
3045 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
3046 }
3047 else
3048 {
3049 /* Update I2C state */
3050 hi2c->State = HAL_I2C_STATE_READY;
3051 hi2c->Mode = HAL_I2C_MODE_NONE;
3052
3053 /* Update I2C error code */
3054 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3055
3056 /* Process Unlocked */
3057 __HAL_UNLOCK(hi2c);
3058
3059 return HAL_ERROR;
3060 }
3061
3062 return HAL_OK;
3063 }
3064 else
3065 {
3066 return HAL_BUSY;
3067 }
3068 }
3069
3070 /**
3071 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3072 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3073 * the configuration information for the specified I2C.
3074 * @param DevAddress Target device address: The device 7 bits address value
3075 * in datasheet must be shifted to the left before calling the interface
3076 * @param MemAddress Internal memory address
3077 * @param MemAddSize Size of internal memory address
3078 * @param pData Pointer to data buffer
3079 * @param Size Amount of data to be read
3080 * @retval HAL status
3081 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3082 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
3083 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3084 {
3085 uint32_t tickstart;
3086 uint32_t xfermode;
3087 HAL_StatusTypeDef dmaxferstatus;
3088
3089 /* Check the parameters */
3090 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3091
3092 if (hi2c->State == HAL_I2C_STATE_READY)
3093 {
3094 if ((pData == NULL) || (Size == 0U))
3095 {
3096 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3097 return HAL_ERROR;
3098 }
3099
3100 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3101 {
3102 return HAL_BUSY;
3103 }
3104
3105 /* Process Locked */
3106 __HAL_LOCK(hi2c);
3107
3108 /* Init tickstart for timeout management*/
3109 tickstart = HAL_GetTick();
3110
3111 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3112 hi2c->Mode = HAL_I2C_MODE_MEM;
3113 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3114
3115 /* Prepare transfer parameters */
3116 hi2c->pBuffPtr = pData;
3117 hi2c->XferCount = Size;
3118 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3119 hi2c->XferISR = I2C_Master_ISR_DMA;
3120
3121 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3122 {
3123 hi2c->XferSize = MAX_NBYTE_SIZE;
3124 xfermode = I2C_RELOAD_MODE;
3125 }
3126 else
3127 {
3128 hi2c->XferSize = hi2c->XferCount;
3129 xfermode = I2C_AUTOEND_MODE;
3130 }
3131
3132 /* Send Slave Address and Memory Address */
3133 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3134 {
3135 /* Process Unlocked */
3136 __HAL_UNLOCK(hi2c);
3137 return HAL_ERROR;
3138 }
3139
3140 if (hi2c->hdmarx != NULL)
3141 {
3142 /* Set the I2C DMA transfer complete callback */
3143 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3144
3145 /* Set the DMA error callback */
3146 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3147
3148 /* Set the unused DMA callbacks to NULL */
3149 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3150 hi2c->hdmarx->XferAbortCallback = NULL;
3151
3152 /* Enable the DMA stream */
3153 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3154 hi2c->XferSize);
3155 }
3156 #ifdef HAL_MDMA_MODULE_ENABLED
3157 if (hi2c->hmdmarx != NULL)
3158 {
3159 /* Set the I2C MDMA transfer complete callback */
3160 hi2c->hmdmarx->XferCpltCallback = I2C_MDMAMasterReceiveCplt;
3161
3162 /* Set the MDMA error callback */
3163 hi2c->hmdmarx->XferErrorCallback = I2C_MDMAError;
3164
3165 /* Set the unused MDMA callbacks to NULL */
3166 hi2c->hmdmarx->XferAbortCallback = NULL;
3167
3168 /* Enable the MDMA stream */
3169 dmaxferstatus = HAL_MDMA_Start_IT(hi2c->hmdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3170 hi2c->XferSize, 1);
3171 }
3172 #endif /* HAL_MDMA_MODULE_ENABLED */
3173 else
3174 {
3175 /* Update I2C state */
3176 hi2c->State = HAL_I2C_STATE_READY;
3177 hi2c->Mode = HAL_I2C_MODE_NONE;
3178
3179 /* Update I2C error code */
3180 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3181
3182 /* Process Unlocked */
3183 __HAL_UNLOCK(hi2c);
3184
3185 return HAL_ERROR;
3186 }
3187
3188 if (dmaxferstatus == HAL_OK)
3189 {
3190 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
3191 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
3192
3193 /* Update XferCount value */
3194 hi2c->XferCount -= hi2c->XferSize;
3195
3196 /* Process Unlocked */
3197 __HAL_UNLOCK(hi2c);
3198
3199 /* Note : The I2C interrupts must be enabled after unlocking current process
3200 to avoid the risk of I2C interrupt handle execution before current
3201 process unlock */
3202 /* Enable ERR and NACK interrupts */
3203 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3204
3205 /* Enable DMA Request */
3206 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
3207 }
3208 else
3209 {
3210 /* Update I2C state */
3211 hi2c->State = HAL_I2C_STATE_READY;
3212 hi2c->Mode = HAL_I2C_MODE_NONE;
3213
3214 /* Update I2C error code */
3215 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3216
3217 /* Process Unlocked */
3218 __HAL_UNLOCK(hi2c);
3219
3220 return HAL_ERROR;
3221 }
3222
3223 return HAL_OK;
3224 }
3225 else
3226 {
3227 return HAL_BUSY;
3228 }
3229 }
3230
3231 /**
3232 * @brief Checks if target device is ready for communication.
3233 * @note This function is used with Memory devices
3234 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3235 * the configuration information for the specified I2C.
3236 * @param DevAddress Target device address: The device 7 bits address value
3237 * in datasheet must be shifted to the left before calling the interface
3238 * @param Trials Number of trials
3239 * @param Timeout Timeout duration
3240 * @retval HAL status
3241 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3242 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
3243 uint32_t Timeout)
3244 {
3245 uint32_t tickstart;
3246
3247 __IO uint32_t I2C_Trials = 0UL;
3248
3249 FlagStatus tmp1;
3250 FlagStatus tmp2;
3251
3252 if (hi2c->State == HAL_I2C_STATE_READY)
3253 {
3254 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3255 {
3256 return HAL_BUSY;
3257 }
3258
3259 /* Process Locked */
3260 __HAL_LOCK(hi2c);
3261
3262 hi2c->State = HAL_I2C_STATE_BUSY;
3263 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3264
3265 do
3266 {
3267 /* Generate Start */
3268 hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
3269
3270 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
3271 /* Wait until STOPF flag is set or a NACK flag is set*/
3272 tickstart = HAL_GetTick();
3273
3274 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3275 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3276
3277 while ((tmp1 == RESET) && (tmp2 == RESET))
3278 {
3279 if (Timeout != HAL_MAX_DELAY)
3280 {
3281 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3282 {
3283 /* Update I2C state */
3284 hi2c->State = HAL_I2C_STATE_READY;
3285
3286 /* Update I2C error code */
3287 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3288
3289 /* Process Unlocked */
3290 __HAL_UNLOCK(hi2c);
3291
3292 return HAL_ERROR;
3293 }
3294 }
3295
3296 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3297 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3298 }
3299
3300 /* Check if the NACKF flag has not been set */
3301 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
3302 {
3303 /* Wait until STOPF flag is reset */
3304 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3305 {
3306 return HAL_ERROR;
3307 }
3308
3309 /* Clear STOP Flag */
3310 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3311
3312 /* Device is ready */
3313 hi2c->State = HAL_I2C_STATE_READY;
3314
3315 /* Process Unlocked */
3316 __HAL_UNLOCK(hi2c);
3317
3318 return HAL_OK;
3319 }
3320 else
3321 {
3322 /* Wait until STOPF flag is reset */
3323 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3324 {
3325 return HAL_ERROR;
3326 }
3327
3328 /* Clear NACK Flag */
3329 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3330
3331 /* Clear STOP Flag, auto generated with autoend*/
3332 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3333 }
3334
3335 /* Check if the maximum allowed number of trials has been reached */
3336 if (I2C_Trials == Trials)
3337 {
3338 /* Generate Stop */
3339 hi2c->Instance->CR2 |= I2C_CR2_STOP;
3340
3341 /* Wait until STOPF flag is reset */
3342 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3343 {
3344 return HAL_ERROR;
3345 }
3346
3347 /* Clear STOP Flag */
3348 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3349 }
3350
3351 /* Increment Trials */
3352 I2C_Trials++;
3353 } while (I2C_Trials < Trials);
3354
3355 /* Update I2C state */
3356 hi2c->State = HAL_I2C_STATE_READY;
3357
3358 /* Update I2C error code */
3359 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3360
3361 /* Process Unlocked */
3362 __HAL_UNLOCK(hi2c);
3363
3364 return HAL_ERROR;
3365 }
3366 else
3367 {
3368 return HAL_BUSY;
3369 }
3370 }
3371
3372 /**
3373 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3374 * @note This interface allow to manage repeated start condition when a direction change during transfer
3375 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3376 * the configuration information for the specified I2C.
3377 * @param DevAddress Target device address: The device 7 bits address value
3378 * in datasheet must be shifted to the left before calling the interface
3379 * @param pData Pointer to data buffer
3380 * @param Size Amount of data to be sent
3381 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3382 * @retval HAL status
3383 */
HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3384 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3385 uint16_t Size, uint32_t XferOptions)
3386 {
3387 uint32_t xfermode;
3388 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3389
3390 /* Check the parameters */
3391 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3392
3393 if (hi2c->State == HAL_I2C_STATE_READY)
3394 {
3395 /* Process Locked */
3396 __HAL_LOCK(hi2c);
3397
3398 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3399 hi2c->Mode = HAL_I2C_MODE_MASTER;
3400 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3401
3402 /* Prepare transfer parameters */
3403 hi2c->pBuffPtr = pData;
3404 hi2c->XferCount = Size;
3405 hi2c->XferOptions = XferOptions;
3406 hi2c->XferISR = I2C_Master_ISR_IT;
3407
3408 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3409 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3410 {
3411 hi2c->XferSize = MAX_NBYTE_SIZE;
3412 xfermode = I2C_RELOAD_MODE;
3413 }
3414 else
3415 {
3416 hi2c->XferSize = hi2c->XferCount;
3417 xfermode = hi2c->XferOptions;
3418 }
3419
3420 /* If transfer direction not change and there is no request to start another frame,
3421 do not generate Restart Condition */
3422 /* Mean Previous state is same as current state */
3423 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3424 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3425 {
3426 xferrequest = I2C_NO_STARTSTOP;
3427 }
3428 else
3429 {
3430 /* Convert OTHER_xxx XferOptions if any */
3431 I2C_ConvertOtherXferOptions(hi2c);
3432
3433 /* Update xfermode accordingly if no reload is necessary */
3434 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3435 {
3436 xfermode = hi2c->XferOptions;
3437 }
3438 }
3439
3440 /* Send Slave Address and set NBYTES to write */
3441 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3442
3443 /* Process Unlocked */
3444 __HAL_UNLOCK(hi2c);
3445
3446 /* Note : The I2C interrupts must be enabled after unlocking current process
3447 to avoid the risk of I2C interrupt handle execution before current
3448 process unlock */
3449 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3450
3451 return HAL_OK;
3452 }
3453 else
3454 {
3455 return HAL_BUSY;
3456 }
3457 }
3458
3459 /**
3460 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3461 * @note This interface allow to manage repeated start condition when a direction change during transfer
3462 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3463 * the configuration information for the specified I2C.
3464 * @param DevAddress Target device address: The device 7 bits address value
3465 * in datasheet must be shifted to the left before calling the interface
3466 * @param pData Pointer to data buffer
3467 * @param Size Amount of data to be sent
3468 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3469 * @retval HAL status
3470 */
HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3471 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3472 uint16_t Size, uint32_t XferOptions)
3473 {
3474 uint32_t xfermode;
3475 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3476 HAL_StatusTypeDef dmaxferstatus;
3477
3478 /* Check the parameters */
3479 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3480
3481 if (hi2c->State == HAL_I2C_STATE_READY)
3482 {
3483 /* Process Locked */
3484 __HAL_LOCK(hi2c);
3485
3486 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3487 hi2c->Mode = HAL_I2C_MODE_MASTER;
3488 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3489
3490 /* Prepare transfer parameters */
3491 hi2c->pBuffPtr = pData;
3492 hi2c->XferCount = Size;
3493 hi2c->XferOptions = XferOptions;
3494 hi2c->XferISR = I2C_Master_ISR_DMA;
3495
3496 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3497 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3498 {
3499 hi2c->XferSize = MAX_NBYTE_SIZE;
3500 xfermode = I2C_RELOAD_MODE;
3501 }
3502 else
3503 {
3504 hi2c->XferSize = hi2c->XferCount;
3505 xfermode = hi2c->XferOptions;
3506 }
3507
3508 /* If transfer direction not change and there is no request to start another frame,
3509 do not generate Restart Condition */
3510 /* Mean Previous state is same as current state */
3511 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3512 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3513 {
3514 xferrequest = I2C_NO_STARTSTOP;
3515 }
3516 else
3517 {
3518 /* Convert OTHER_xxx XferOptions if any */
3519 I2C_ConvertOtherXferOptions(hi2c);
3520
3521 /* Update xfermode accordingly if no reload is necessary */
3522 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3523 {
3524 xfermode = hi2c->XferOptions;
3525 }
3526 }
3527
3528 if (hi2c->XferSize > 0U)
3529 {
3530 if (hi2c->hdmatx != NULL)
3531 {
3532 /* Set the I2C DMA transfer complete callback */
3533 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3534
3535 /* Set the DMA error callback */
3536 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3537
3538 /* Set the unused DMA callbacks to NULL */
3539 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3540 hi2c->hdmatx->XferAbortCallback = NULL;
3541
3542 /* Enable the DMA stream */
3543 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3544 hi2c->XferSize);
3545 }
3546 #ifdef HAL_MDMA_MODULE_ENABLED
3547 else if (hi2c->hmdmatx != NULL)
3548 {
3549 /* Set the I2C MDMA transfer complete callback */
3550 hi2c->hmdmatx->XferCpltCallback = I2C_MDMAMasterTransmitCplt;
3551
3552 /* Set the MDMA error callback */
3553 hi2c->hmdmatx->XferErrorCallback = I2C_MDMAError;
3554
3555 /* Set the unused MDMA callbacks to NULL */
3556 hi2c->hmdmatx->XferAbortCallback = NULL;
3557
3558 /* Enable the MDMA stream */
3559 dmaxferstatus = HAL_MDMA_Start_IT(hi2c->hmdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3560 hi2c->XferSize, 1);
3561 }
3562 #endif /* HAL_MDMA_MODULE_ENABLED */
3563 else
3564 {
3565 /* Update I2C state */
3566 hi2c->State = HAL_I2C_STATE_READY;
3567 hi2c->Mode = HAL_I2C_MODE_NONE;
3568
3569 /* Update I2C error code */
3570 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3571
3572 /* Process Unlocked */
3573 __HAL_UNLOCK(hi2c);
3574
3575 return HAL_ERROR;
3576 }
3577
3578 if (dmaxferstatus == HAL_OK)
3579 {
3580 /* Send Slave Address and set NBYTES to write */
3581 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3582
3583 /* Update XferCount value */
3584 hi2c->XferCount -= hi2c->XferSize;
3585
3586 /* Process Unlocked */
3587 __HAL_UNLOCK(hi2c);
3588
3589 /* Note : The I2C interrupts must be enabled after unlocking current process
3590 to avoid the risk of I2C interrupt handle execution before current
3591 process unlock */
3592 /* Enable ERR and NACK interrupts */
3593 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3594
3595 /* Enable DMA Request */
3596 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
3597 }
3598 else
3599 {
3600 /* Update I2C state */
3601 hi2c->State = HAL_I2C_STATE_READY;
3602 hi2c->Mode = HAL_I2C_MODE_NONE;
3603
3604 /* Update I2C error code */
3605 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3606
3607 /* Process Unlocked */
3608 __HAL_UNLOCK(hi2c);
3609
3610 return HAL_ERROR;
3611 }
3612 }
3613 else
3614 {
3615 /* Update Transfer ISR function pointer */
3616 hi2c->XferISR = I2C_Master_ISR_IT;
3617
3618 /* Send Slave Address */
3619 /* Set NBYTES to write and generate START condition */
3620 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
3621 I2C_GENERATE_START_WRITE);
3622
3623 /* Process Unlocked */
3624 __HAL_UNLOCK(hi2c);
3625
3626 /* Note : The I2C interrupts must be enabled after unlocking current process
3627 to avoid the risk of I2C interrupt handle execution before current
3628 process unlock */
3629 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3630 /* possible to enable all of these */
3631 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3632 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3633 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3634 }
3635
3636 return HAL_OK;
3637 }
3638 else
3639 {
3640 return HAL_BUSY;
3641 }
3642 }
3643
3644 /**
3645 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3646 * @note This interface allow to manage repeated start condition when a direction change during transfer
3647 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3648 * the configuration information for the specified I2C.
3649 * @param DevAddress Target device address: The device 7 bits address value
3650 * in datasheet must be shifted to the left before calling the interface
3651 * @param pData Pointer to data buffer
3652 * @param Size Amount of data to be sent
3653 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3654 * @retval HAL status
3655 */
HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3656 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3657 uint16_t Size, uint32_t XferOptions)
3658 {
3659 uint32_t xfermode;
3660 uint32_t xferrequest = I2C_GENERATE_START_READ;
3661
3662 /* Check the parameters */
3663 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3664
3665 if (hi2c->State == HAL_I2C_STATE_READY)
3666 {
3667 /* Process Locked */
3668 __HAL_LOCK(hi2c);
3669
3670 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3671 hi2c->Mode = HAL_I2C_MODE_MASTER;
3672 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3673
3674 /* Prepare transfer parameters */
3675 hi2c->pBuffPtr = pData;
3676 hi2c->XferCount = Size;
3677 hi2c->XferOptions = XferOptions;
3678 hi2c->XferISR = I2C_Master_ISR_IT;
3679
3680 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3681 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3682 {
3683 hi2c->XferSize = MAX_NBYTE_SIZE;
3684 xfermode = I2C_RELOAD_MODE;
3685 }
3686 else
3687 {
3688 hi2c->XferSize = hi2c->XferCount;
3689 xfermode = hi2c->XferOptions;
3690 }
3691
3692 /* If transfer direction not change and there is no request to start another frame,
3693 do not generate Restart Condition */
3694 /* Mean Previous state is same as current state */
3695 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3696 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3697 {
3698 xferrequest = I2C_NO_STARTSTOP;
3699 }
3700 else
3701 {
3702 /* Convert OTHER_xxx XferOptions if any */
3703 I2C_ConvertOtherXferOptions(hi2c);
3704
3705 /* Update xfermode accordingly if no reload is necessary */
3706 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3707 {
3708 xfermode = hi2c->XferOptions;
3709 }
3710 }
3711
3712 /* Send Slave Address and set NBYTES to read */
3713 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3714
3715 /* Process Unlocked */
3716 __HAL_UNLOCK(hi2c);
3717
3718 /* Note : The I2C interrupts must be enabled after unlocking current process
3719 to avoid the risk of I2C interrupt handle execution before current
3720 process unlock */
3721 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
3722
3723 return HAL_OK;
3724 }
3725 else
3726 {
3727 return HAL_BUSY;
3728 }
3729 }
3730
3731 /**
3732 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
3733 * @note This interface allow to manage repeated start condition when a direction change during transfer
3734 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3735 * the configuration information for the specified I2C.
3736 * @param DevAddress Target device address: The device 7 bits address value
3737 * in datasheet must be shifted to the left before calling the interface
3738 * @param pData Pointer to data buffer
3739 * @param Size Amount of data to be sent
3740 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3741 * @retval HAL status
3742 */
HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3743 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3744 uint16_t Size, uint32_t XferOptions)
3745 {
3746 uint32_t xfermode;
3747 uint32_t xferrequest = I2C_GENERATE_START_READ;
3748 HAL_StatusTypeDef dmaxferstatus;
3749
3750 /* Check the parameters */
3751 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3752
3753 if (hi2c->State == HAL_I2C_STATE_READY)
3754 {
3755 /* Process Locked */
3756 __HAL_LOCK(hi2c);
3757
3758 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3759 hi2c->Mode = HAL_I2C_MODE_MASTER;
3760 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3761
3762 /* Prepare transfer parameters */
3763 hi2c->pBuffPtr = pData;
3764 hi2c->XferCount = Size;
3765 hi2c->XferOptions = XferOptions;
3766 hi2c->XferISR = I2C_Master_ISR_DMA;
3767
3768 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3769 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3770 {
3771 hi2c->XferSize = MAX_NBYTE_SIZE;
3772 xfermode = I2C_RELOAD_MODE;
3773 }
3774 else
3775 {
3776 hi2c->XferSize = hi2c->XferCount;
3777 xfermode = hi2c->XferOptions;
3778 }
3779
3780 /* If transfer direction not change and there is no request to start another frame,
3781 do not generate Restart Condition */
3782 /* Mean Previous state is same as current state */
3783 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3784 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3785 {
3786 xferrequest = I2C_NO_STARTSTOP;
3787 }
3788 else
3789 {
3790 /* Convert OTHER_xxx XferOptions if any */
3791 I2C_ConvertOtherXferOptions(hi2c);
3792
3793 /* Update xfermode accordingly if no reload is necessary */
3794 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3795 {
3796 xfermode = hi2c->XferOptions;
3797 }
3798 }
3799
3800 if (hi2c->XferSize > 0U)
3801 {
3802 if (hi2c->hdmarx != NULL)
3803 {
3804 /* Set the I2C DMA transfer complete callback */
3805 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3806
3807 /* Set the DMA error callback */
3808 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3809
3810 /* Set the unused DMA callbacks to NULL */
3811 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3812 hi2c->hdmarx->XferAbortCallback = NULL;
3813
3814 /* Enable the DMA stream */
3815 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3816 hi2c->XferSize);
3817 }
3818 #ifdef HAL_MDMA_MODULE_ENABLED
3819 else if (hi2c->hmdmarx != NULL)
3820 {
3821 /* Set the I2C MDMA transfer complete callback */
3822 hi2c->hmdmarx->XferCpltCallback = I2C_MDMAMasterReceiveCplt;
3823
3824 /* Set the MDMA error callback */
3825 hi2c->hmdmarx->XferErrorCallback = I2C_MDMAError;
3826
3827 /* Set the unused MDMA callbacks to NULL */
3828 hi2c->hmdmarx->XferAbortCallback = NULL;
3829
3830 /* Enable the MDMA stream */
3831 dmaxferstatus = HAL_MDMA_Start_IT(hi2c->hmdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3832 hi2c->XferSize, 1);
3833 }
3834 #endif /* HAL_MDMA_MODULE_ENABLED */
3835 else
3836 {
3837 /* Update I2C state */
3838 hi2c->State = HAL_I2C_STATE_READY;
3839 hi2c->Mode = HAL_I2C_MODE_NONE;
3840
3841 /* Update I2C error code */
3842 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3843
3844 /* Process Unlocked */
3845 __HAL_UNLOCK(hi2c);
3846
3847 return HAL_ERROR;
3848 }
3849
3850 if (dmaxferstatus == HAL_OK)
3851 {
3852 /* Send Slave Address and set NBYTES to read */
3853 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3854
3855 /* Update XferCount value */
3856 hi2c->XferCount -= hi2c->XferSize;
3857
3858 /* Process Unlocked */
3859 __HAL_UNLOCK(hi2c);
3860
3861 /* Note : The I2C interrupts must be enabled after unlocking current process
3862 to avoid the risk of I2C interrupt handle execution before current
3863 process unlock */
3864 /* Enable ERR and NACK interrupts */
3865 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3866
3867 /* Enable DMA Request */
3868 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
3869 }
3870 else
3871 {
3872 /* Update I2C state */
3873 hi2c->State = HAL_I2C_STATE_READY;
3874 hi2c->Mode = HAL_I2C_MODE_NONE;
3875
3876 /* Update I2C error code */
3877 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3878
3879 /* Process Unlocked */
3880 __HAL_UNLOCK(hi2c);
3881
3882 return HAL_ERROR;
3883 }
3884 }
3885 else
3886 {
3887 /* Update Transfer ISR function pointer */
3888 hi2c->XferISR = I2C_Master_ISR_IT;
3889
3890 /* Send Slave Address */
3891 /* Set NBYTES to read and generate START condition */
3892 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
3893 I2C_GENERATE_START_READ);
3894
3895 /* Process Unlocked */
3896 __HAL_UNLOCK(hi2c);
3897
3898 /* Note : The I2C interrupts must be enabled after unlocking current process
3899 to avoid the risk of I2C interrupt handle execution before current
3900 process unlock */
3901 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3902 /* possible to enable all of these */
3903 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3904 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3905 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3906 }
3907
3908 return HAL_OK;
3909 }
3910 else
3911 {
3912 return HAL_BUSY;
3913 }
3914 }
3915
3916 /**
3917 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
3918 * @note This interface allow to manage repeated start condition when a direction change during transfer
3919 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3920 * the configuration information for the specified I2C.
3921 * @param pData Pointer to data buffer
3922 * @param Size Amount of data to be sent
3923 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3924 * @retval HAL status
3925 */
HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3926 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
3927 uint32_t XferOptions)
3928 {
3929 /* Check the parameters */
3930 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3931
3932 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
3933 {
3934 if ((pData == NULL) || (Size == 0U))
3935 {
3936 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3937 return HAL_ERROR;
3938 }
3939
3940 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
3941 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
3942
3943 /* Process Locked */
3944 __HAL_LOCK(hi2c);
3945
3946 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
3947 /* and then toggle the HAL slave RX state to TX state */
3948 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
3949 {
3950 /* Disable associated Interrupts */
3951 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
3952
3953 /* Abort DMA Xfer if any */
3954 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
3955 {
3956 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
3957
3958 if (hi2c->hdmarx != NULL)
3959 {
3960 /* Set the I2C DMA Abort callback :
3961 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3962 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
3963
3964 /* Abort DMA RX */
3965 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
3966 {
3967 /* Call Directly XferAbortCallback function in case of error */
3968 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
3969 }
3970 }
3971 #ifdef HAL_MDMA_MODULE_ENABLED
3972 else if (hi2c->hmdmarx != NULL)
3973 {
3974 /* Set the I2C DMA Abort callback :
3975 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3976 hi2c->hmdmarx->XferAbortCallback = I2C_MDMAAbort;
3977
3978 /* Abort MDMA RX */
3979 if (HAL_MDMA_Abort_IT(hi2c->hmdmarx) != HAL_OK)
3980 {
3981 /* Call Directly XferAbortCallback function in case of error */
3982 hi2c->hmdmarx->XferAbortCallback(hi2c->hmdmarx);
3983 }
3984 }
3985 else
3986 {
3987 /* Nothing to do */
3988 }
3989 #endif /* HAL_MDMA_MODULE_ENABLED */
3990 }
3991 }
3992
3993 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
3994 hi2c->Mode = HAL_I2C_MODE_SLAVE;
3995 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3996
3997 /* Enable Address Acknowledge */
3998 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
3999
4000 /* Prepare transfer parameters */
4001 hi2c->pBuffPtr = pData;
4002 hi2c->XferCount = Size;
4003 hi2c->XferSize = hi2c->XferCount;
4004 hi2c->XferOptions = XferOptions;
4005 hi2c->XferISR = I2C_Slave_ISR_IT;
4006
4007 if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
4008 {
4009 /* Clear ADDR flag after prepare the transfer parameters */
4010 /* This action will generate an acknowledge to the Master */
4011 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4012 }
4013
4014 /* Process Unlocked */
4015 __HAL_UNLOCK(hi2c);
4016
4017 /* Note : The I2C interrupts must be enabled after unlocking current process
4018 to avoid the risk of I2C interrupt handle execution before current
4019 process unlock */
4020 /* REnable ADDR interrupt */
4021 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
4022
4023 return HAL_OK;
4024 }
4025 else
4026 {
4027 return HAL_ERROR;
4028 }
4029 }
4030
4031 /**
4032 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
4033 * @note This interface allow to manage repeated start condition when a direction change during transfer
4034 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4035 * the configuration information for the specified I2C.
4036 * @param pData Pointer to data buffer
4037 * @param Size Amount of data to be sent
4038 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4039 * @retval HAL status
4040 */
HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4041 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4042 uint32_t XferOptions)
4043 {
4044 HAL_StatusTypeDef dmaxferstatus;
4045
4046 /* Check the parameters */
4047 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4048
4049 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4050 {
4051 if ((pData == NULL) || (Size == 0U))
4052 {
4053 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4054 return HAL_ERROR;
4055 }
4056
4057 /* Process Locked */
4058 __HAL_LOCK(hi2c);
4059
4060 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4061 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
4062
4063 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4064 /* and then toggle the HAL slave RX state to TX state */
4065 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4066 {
4067 /* Disable associated Interrupts */
4068 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4069
4070 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4071 {
4072 /* Abort DMA Xfer if any */
4073 if (hi2c->hdmarx != NULL)
4074 {
4075 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4076
4077 /* Set the I2C DMA Abort callback :
4078 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4079 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4080
4081 /* Abort DMA RX */
4082 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4083 {
4084 /* Call Directly XferAbortCallback function in case of error */
4085 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4086 }
4087 }
4088 #ifdef HAL_MDMA_MODULE_ENABLED
4089 else if (hi2c->hmdmarx != NULL)
4090 {
4091 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4092
4093 /* Set the I2C DMA Abort callback :
4094 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4095 hi2c->hmdmarx->XferAbortCallback = I2C_MDMAAbort;
4096
4097 /* Abort MDMA RX */
4098 if (HAL_MDMA_Abort_IT(hi2c->hmdmarx) != HAL_OK)
4099 {
4100 /* Call Directly XferAbortCallback function in case of error */
4101 hi2c->hmdmarx->XferAbortCallback(hi2c->hmdmarx);
4102 }
4103 }
4104 else
4105 {
4106 /* Nothing to do */
4107 }
4108 #endif /* HAL_MDMA_MODULE_ENABLED */
4109 }
4110 }
4111 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4112 {
4113 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4114 {
4115 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4116
4117 /* Abort DMA Xfer if any */
4118 if (hi2c->hdmatx != NULL)
4119 {
4120 /* Set the I2C DMA Abort callback :
4121 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4122 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4123
4124 /* Abort DMA TX */
4125 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4126 {
4127 /* Call Directly XferAbortCallback function in case of error */
4128 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4129 }
4130 }
4131 #ifdef HAL_MDMA_MODULE_ENABLED
4132 else if (hi2c->hmdmatx != NULL)
4133 {
4134 /* Set the I2C DMA Abort callback :
4135 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4136 hi2c->hmdmatx->XferAbortCallback = I2C_MDMAAbort;
4137
4138 /* Abort DMA TX */
4139 if (HAL_MDMA_Abort_IT(hi2c->hmdmatx) != HAL_OK)
4140 {
4141 /* Call Directly XferAbortCallback function in case of error */
4142 hi2c->hmdmatx->XferAbortCallback(hi2c->hmdmatx);
4143 }
4144 }
4145 else
4146 {
4147 /* Nothing to do */
4148 }
4149 #endif /* HAL_MDMA_MODULE_ENABLED */
4150 }
4151 }
4152 else
4153 {
4154 /* Nothing to do */
4155 }
4156
4157 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4158 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4159 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4160
4161 /* Enable Address Acknowledge */
4162 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4163
4164 /* Prepare transfer parameters */
4165 hi2c->pBuffPtr = pData;
4166 hi2c->XferCount = Size;
4167 hi2c->XferSize = hi2c->XferCount;
4168 hi2c->XferOptions = XferOptions;
4169 hi2c->XferISR = I2C_Slave_ISR_DMA;
4170
4171 if (hi2c->hdmatx != NULL)
4172 {
4173 /* Set the I2C DMA transfer complete callback */
4174 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
4175
4176 /* Set the DMA error callback */
4177 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
4178
4179 /* Set the unused DMA callbacks to NULL */
4180 hi2c->hdmatx->XferHalfCpltCallback = NULL;
4181 hi2c->hdmatx->XferAbortCallback = NULL;
4182
4183 /* Enable the DMA stream */
4184 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
4185 hi2c->XferSize);
4186 }
4187 #ifdef HAL_MDMA_MODULE_ENABLED
4188 else if (hi2c->hmdmatx != NULL)
4189 {
4190 /* Set the I2C MDMA transfer complete callback */
4191 hi2c->hmdmatx->XferCpltCallback = I2C_MDMASlaveTransmitCplt;
4192
4193 /* Set the MDMA error callback */
4194 hi2c->hmdmatx->XferErrorCallback = I2C_MDMAError;
4195
4196 /* Set the unused MDMA callbacks to NULL */
4197 hi2c->hmdmatx->XferAbortCallback = NULL;
4198
4199 /* Enable the MDMA stream */
4200 dmaxferstatus = HAL_MDMA_Start_IT(hi2c->hmdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
4201 hi2c->XferSize, 1);
4202 }
4203 #endif /* HAL_MDMA_MODULE_ENABLED */
4204 else
4205 {
4206 /* Update I2C state */
4207 hi2c->State = HAL_I2C_STATE_LISTEN;
4208 hi2c->Mode = HAL_I2C_MODE_NONE;
4209
4210 /* Update I2C error code */
4211 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4212
4213 /* Process Unlocked */
4214 __HAL_UNLOCK(hi2c);
4215
4216 return HAL_ERROR;
4217 }
4218
4219 if (dmaxferstatus == HAL_OK)
4220 {
4221 /* Update XferCount value */
4222 hi2c->XferCount -= hi2c->XferSize;
4223
4224 /* Reset XferSize */
4225 hi2c->XferSize = 0;
4226 }
4227 else
4228 {
4229 /* Update I2C state */
4230 hi2c->State = HAL_I2C_STATE_LISTEN;
4231 hi2c->Mode = HAL_I2C_MODE_NONE;
4232
4233 /* Update I2C error code */
4234 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4235
4236 /* Process Unlocked */
4237 __HAL_UNLOCK(hi2c);
4238
4239 return HAL_ERROR;
4240 }
4241
4242 if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
4243 {
4244 /* Clear ADDR flag after prepare the transfer parameters */
4245 /* This action will generate an acknowledge to the Master */
4246 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4247 }
4248
4249 /* Process Unlocked */
4250 __HAL_UNLOCK(hi2c);
4251
4252 /* Enable DMA Request */
4253 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
4254
4255 /* Note : The I2C interrupts must be enabled after unlocking current process
4256 to avoid the risk of I2C interrupt handle execution before current
4257 process unlock */
4258 /* Enable ERR, STOP, NACK, ADDR interrupts */
4259 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4260
4261 return HAL_OK;
4262 }
4263 else
4264 {
4265 return HAL_ERROR;
4266 }
4267 }
4268
4269 /**
4270 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
4271 * @note This interface allow to manage repeated start condition when a direction change during transfer
4272 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4273 * the configuration information for the specified I2C.
4274 * @param pData Pointer to data buffer
4275 * @param Size Amount of data to be sent
4276 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4277 * @retval HAL status
4278 */
HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4279 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4280 uint32_t XferOptions)
4281 {
4282 /* Check the parameters */
4283 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4284
4285 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4286 {
4287 if ((pData == NULL) || (Size == 0U))
4288 {
4289 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4290 return HAL_ERROR;
4291 }
4292
4293 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4294 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4295
4296 /* Process Locked */
4297 __HAL_LOCK(hi2c);
4298
4299 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4300 /* and then toggle the HAL slave TX state to RX state */
4301 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4302 {
4303 /* Disable associated Interrupts */
4304 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4305
4306 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4307 {
4308 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4309
4310 /* Abort DMA Xfer if any */
4311 if (hi2c->hdmatx != NULL)
4312 {
4313 /* Set the I2C DMA Abort callback :
4314 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4315 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4316
4317 /* Abort DMA TX */
4318 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4319 {
4320 /* Call Directly XferAbortCallback function in case of error */
4321 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4322 }
4323 }
4324 #ifdef HAL_MDMA_MODULE_ENABLED
4325 else if (hi2c->hmdmatx != NULL)
4326 {
4327 /* Set the I2C DMA Abort callback :
4328 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4329 hi2c->hmdmatx->XferAbortCallback = I2C_MDMAAbort;
4330
4331 /* Abort MDMA TX */
4332 if (HAL_MDMA_Abort_IT(hi2c->hmdmatx) != HAL_OK)
4333 {
4334 /* Call Directly XferAbortCallback function in case of error */
4335 hi2c->hmdmatx->XferAbortCallback(hi2c->hmdmatx);
4336 }
4337 }
4338 else
4339 {
4340 /* Nothing to do */
4341 }
4342 #endif /* HAL_MDMA_MODULE_ENABLED */
4343 }
4344 }
4345
4346 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4347 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4348 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4349
4350 /* Enable Address Acknowledge */
4351 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4352
4353 /* Prepare transfer parameters */
4354 hi2c->pBuffPtr = pData;
4355 hi2c->XferCount = Size;
4356 hi2c->XferSize = hi2c->XferCount;
4357 hi2c->XferOptions = XferOptions;
4358 hi2c->XferISR = I2C_Slave_ISR_IT;
4359
4360 if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
4361 {
4362 /* Clear ADDR flag after prepare the transfer parameters */
4363 /* This action will generate an acknowledge to the Master */
4364 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4365 }
4366
4367 /* Process Unlocked */
4368 __HAL_UNLOCK(hi2c);
4369
4370 /* Note : The I2C interrupts must be enabled after unlocking current process
4371 to avoid the risk of I2C interrupt handle execution before current
4372 process unlock */
4373 /* REnable ADDR interrupt */
4374 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4375
4376 return HAL_OK;
4377 }
4378 else
4379 {
4380 return HAL_ERROR;
4381 }
4382 }
4383
4384 /**
4385 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
4386 * @note This interface allow to manage repeated start condition when a direction change during transfer
4387 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4388 * the configuration information for the specified I2C.
4389 * @param pData Pointer to data buffer
4390 * @param Size Amount of data to be sent
4391 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4392 * @retval HAL status
4393 */
HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4394 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4395 uint32_t XferOptions)
4396 {
4397 HAL_StatusTypeDef dmaxferstatus;
4398
4399 /* Check the parameters */
4400 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4401
4402 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4403 {
4404 if ((pData == NULL) || (Size == 0U))
4405 {
4406 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4407 return HAL_ERROR;
4408 }
4409
4410 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4411 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4412
4413 /* Process Locked */
4414 __HAL_LOCK(hi2c);
4415
4416 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4417 /* and then toggle the HAL slave TX state to RX state */
4418 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4419 {
4420 /* Disable associated Interrupts */
4421 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4422
4423 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4424 {
4425 /* Abort DMA Xfer if any */
4426 if (hi2c->hdmatx != NULL)
4427 {
4428 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4429
4430 /* Set the I2C DMA Abort callback :
4431 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4432 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4433
4434 /* Abort DMA TX */
4435 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4436 {
4437 /* Call Directly XferAbortCallback function in case of error */
4438 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4439 }
4440 }
4441 #ifdef HAL_MDMA_MODULE_ENABLED
4442 else if (hi2c->hmdmatx != NULL)
4443 {
4444 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4445
4446 /* Set the I2C DMA Abort callback :
4447 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4448 hi2c->hmdmatx->XferAbortCallback = I2C_MDMAAbort;
4449
4450 /* Abort MDMA TX */
4451 if (HAL_MDMA_Abort_IT(hi2c->hmdmatx) != HAL_OK)
4452 {
4453 /* Call Directly XferAbortCallback function in case of error */
4454 hi2c->hmdmatx->XferAbortCallback(hi2c->hmdmatx);
4455 }
4456 }
4457 else
4458 {
4459 /* Nothing to do */
4460 }
4461 #endif /* HAL_MDMA_MODULE_ENABLED */
4462 }
4463 }
4464 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4465 {
4466 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4467 {
4468 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4469
4470 /* Abort DMA Xfer if any */
4471 if (hi2c->hdmarx != NULL)
4472 {
4473 /* Set the I2C DMA Abort callback :
4474 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4475 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4476
4477 /* Abort DMA RX */
4478 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4479 {
4480 /* Call Directly XferAbortCallback function in case of error */
4481 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4482 }
4483 }
4484 #ifdef HAL_MDMA_MODULE_ENABLED
4485 else if (hi2c->hmdmarx != NULL)
4486 {
4487 /* Set the I2C DMA Abort callback :
4488 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4489 hi2c->hmdmarx->XferAbortCallback = I2C_MDMAAbort;
4490
4491 /* Abort MDMA RX */
4492 if (HAL_MDMA_Abort_IT(hi2c->hmdmarx) != HAL_OK)
4493 {
4494 /* Call Directly XferAbortCallback function in case of error */
4495 hi2c->hmdmarx->XferAbortCallback(hi2c->hmdmarx);
4496 }
4497 }
4498 else
4499 {
4500 /* Nothing to do */
4501 }
4502 #endif /* HAL_MDMA_MODULE_ENABLED */
4503 }
4504 }
4505 else
4506 {
4507 /* Nothing to do */
4508 }
4509
4510 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4511 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4512 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4513
4514 /* Enable Address Acknowledge */
4515 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4516
4517 /* Prepare transfer parameters */
4518 hi2c->pBuffPtr = pData;
4519 hi2c->XferCount = Size;
4520 hi2c->XferSize = hi2c->XferCount;
4521 hi2c->XferOptions = XferOptions;
4522 hi2c->XferISR = I2C_Slave_ISR_DMA;
4523
4524 if (hi2c->hdmarx != NULL)
4525 {
4526 /* Set the I2C DMA transfer complete callback */
4527 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
4528
4529 /* Set the DMA error callback */
4530 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4531
4532 /* Set the unused DMA callbacks to NULL */
4533 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4534 hi2c->hdmarx->XferAbortCallback = NULL;
4535
4536 /* Enable the DMA stream */
4537 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
4538 (uint32_t)pData, hi2c->XferSize);
4539 }
4540 #ifdef HAL_MDMA_MODULE_ENABLED
4541 else if (hi2c->hmdmarx != NULL)
4542 {
4543 /* Set the I2C MDMA transfer complete callback */
4544 hi2c->hmdmarx->XferCpltCallback = I2C_MDMASlaveReceiveCplt;
4545
4546 /* Set the MDMA error callback */
4547 hi2c->hmdmarx->XferErrorCallback = I2C_MDMAError;
4548
4549 /* Set the unused MDMA callbacks to NULL */
4550 hi2c->hmdmarx->XferAbortCallback = NULL;
4551
4552 /* Enable the MDMA stream */
4553 dmaxferstatus = HAL_MDMA_Start_IT(hi2c->hmdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
4554 hi2c->XferSize, 1);
4555 }
4556 #endif /* HAL_MDMA_MODULE_ENABLED */
4557 else
4558 {
4559 /* Update I2C state */
4560 hi2c->State = HAL_I2C_STATE_LISTEN;
4561 hi2c->Mode = HAL_I2C_MODE_NONE;
4562
4563 /* Update I2C error code */
4564 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4565
4566 /* Process Unlocked */
4567 __HAL_UNLOCK(hi2c);
4568
4569 return HAL_ERROR;
4570 }
4571
4572 if (dmaxferstatus == HAL_OK)
4573 {
4574 /* Update XferCount value */
4575 hi2c->XferCount -= hi2c->XferSize;
4576
4577 /* Reset XferSize */
4578 hi2c->XferSize = 0;
4579 }
4580 else
4581 {
4582 /* Update I2C state */
4583 hi2c->State = HAL_I2C_STATE_LISTEN;
4584 hi2c->Mode = HAL_I2C_MODE_NONE;
4585
4586 /* Update I2C error code */
4587 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4588
4589 /* Process Unlocked */
4590 __HAL_UNLOCK(hi2c);
4591
4592 return HAL_ERROR;
4593 }
4594
4595 if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
4596 {
4597 /* Clear ADDR flag after prepare the transfer parameters */
4598 /* This action will generate an acknowledge to the Master */
4599 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4600 }
4601
4602 /* Process Unlocked */
4603 __HAL_UNLOCK(hi2c);
4604
4605 /* Enable DMA Request */
4606 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4607
4608 /* Note : The I2C interrupts must be enabled after unlocking current process
4609 to avoid the risk of I2C interrupt handle execution before current
4610 process unlock */
4611 /* REnable ADDR interrupt */
4612 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4613
4614 return HAL_OK;
4615 }
4616 else
4617 {
4618 return HAL_ERROR;
4619 }
4620 }
4621
4622 /**
4623 * @brief Enable the Address listen mode with Interrupt.
4624 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4625 * the configuration information for the specified I2C.
4626 * @retval HAL status
4627 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)4628 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4629 {
4630 if (hi2c->State == HAL_I2C_STATE_READY)
4631 {
4632 hi2c->State = HAL_I2C_STATE_LISTEN;
4633 hi2c->XferISR = I2C_Slave_ISR_IT;
4634
4635 /* Enable the Address Match interrupt */
4636 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4637
4638 return HAL_OK;
4639 }
4640 else
4641 {
4642 return HAL_BUSY;
4643 }
4644 }
4645
4646 /**
4647 * @brief Disable the Address listen mode with Interrupt.
4648 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4649 * the configuration information for the specified I2C
4650 * @retval HAL status
4651 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)4652 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4653 {
4654 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4655 uint32_t tmp;
4656
4657 /* Disable Address listen mode only if a transfer is not ongoing */
4658 if (hi2c->State == HAL_I2C_STATE_LISTEN)
4659 {
4660 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4661 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4662 hi2c->State = HAL_I2C_STATE_READY;
4663 hi2c->Mode = HAL_I2C_MODE_NONE;
4664 hi2c->XferISR = NULL;
4665
4666 /* Disable the Address Match interrupt */
4667 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4668
4669 return HAL_OK;
4670 }
4671 else
4672 {
4673 return HAL_BUSY;
4674 }
4675 }
4676
4677 /**
4678 * @brief Abort a master I2C IT or DMA process communication with Interrupt.
4679 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4680 * the configuration information for the specified I2C.
4681 * @param DevAddress Target device address: The device 7 bits address value
4682 * in datasheet must be shifted to the left before calling the interface
4683 * @retval HAL status
4684 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)4685 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4686 {
4687 if (hi2c->Mode == HAL_I2C_MODE_MASTER)
4688 {
4689 /* Process Locked */
4690 __HAL_LOCK(hi2c);
4691
4692 /* Disable Interrupts and Store Previous state */
4693 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
4694 {
4695 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4696 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
4697 }
4698 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
4699 {
4700 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4701 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
4702 }
4703 else
4704 {
4705 /* Do nothing */
4706 }
4707
4708 /* Set State at HAL_I2C_STATE_ABORT */
4709 hi2c->State = HAL_I2C_STATE_ABORT;
4710
4711 /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
4712 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
4713 I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
4714
4715 /* Process Unlocked */
4716 __HAL_UNLOCK(hi2c);
4717
4718 /* Note : The I2C interrupts must be enabled after unlocking current process
4719 to avoid the risk of I2C interrupt handle execution before current
4720 process unlock */
4721 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
4722
4723 return HAL_OK;
4724 }
4725 else
4726 {
4727 /* Wrong usage of abort function */
4728 /* This function should be used only in case of abort monitored by master device */
4729 return HAL_ERROR;
4730 }
4731 }
4732
4733 /**
4734 * @}
4735 */
4736
4737 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4738 * @{
4739 */
4740
4741 /**
4742 * @brief This function handles I2C event interrupt request.
4743 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4744 * the configuration information for the specified I2C.
4745 * @retval None
4746 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)4747 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
4748 {
4749 /* Get current IT Flags and IT sources value */
4750 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4751 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4752
4753 /* I2C events treatment -------------------------------------*/
4754 if (hi2c->XferISR != NULL)
4755 {
4756 hi2c->XferISR(hi2c, itflags, itsources);
4757 }
4758 }
4759
4760 /**
4761 * @brief This function handles I2C error interrupt request.
4762 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4763 * the configuration information for the specified I2C.
4764 * @retval None
4765 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)4766 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4767 {
4768 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4769 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4770 uint32_t tmperror;
4771
4772 /* I2C Bus error interrupt occurred ------------------------------------*/
4773 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
4774 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4775 {
4776 hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
4777
4778 /* Clear BERR flag */
4779 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4780 }
4781
4782 /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
4783 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
4784 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4785 {
4786 hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
4787
4788 /* Clear OVR flag */
4789 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
4790 }
4791
4792 /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
4793 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
4794 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4795 {
4796 hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
4797
4798 /* Clear ARLO flag */
4799 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4800 }
4801
4802 /* Store current volatile hi2c->ErrorCode, misra rule */
4803 tmperror = hi2c->ErrorCode;
4804
4805 /* Call the Error Callback in case of Error detected */
4806 if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
4807 {
4808 I2C_ITError(hi2c, tmperror);
4809 }
4810 }
4811
4812 /**
4813 * @brief Master Tx Transfer completed callback.
4814 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4815 * the configuration information for the specified I2C.
4816 * @retval None
4817 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)4818 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
4819 {
4820 /* Prevent unused argument(s) compilation warning */
4821 UNUSED(hi2c);
4822
4823 /* NOTE : This function should not be modified, when the callback is needed,
4824 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
4825 */
4826 }
4827
4828 /**
4829 * @brief Master Rx Transfer completed callback.
4830 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4831 * the configuration information for the specified I2C.
4832 * @retval None
4833 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)4834 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
4835 {
4836 /* Prevent unused argument(s) compilation warning */
4837 UNUSED(hi2c);
4838
4839 /* NOTE : This function should not be modified, when the callback is needed,
4840 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
4841 */
4842 }
4843
4844 /** @brief Slave Tx Transfer completed callback.
4845 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4846 * the configuration information for the specified I2C.
4847 * @retval None
4848 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)4849 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
4850 {
4851 /* Prevent unused argument(s) compilation warning */
4852 UNUSED(hi2c);
4853
4854 /* NOTE : This function should not be modified, when the callback is needed,
4855 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
4856 */
4857 }
4858
4859 /**
4860 * @brief Slave Rx Transfer completed callback.
4861 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4862 * the configuration information for the specified I2C.
4863 * @retval None
4864 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)4865 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
4866 {
4867 /* Prevent unused argument(s) compilation warning */
4868 UNUSED(hi2c);
4869
4870 /* NOTE : This function should not be modified, when the callback is needed,
4871 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
4872 */
4873 }
4874
4875 /**
4876 * @brief Slave Address Match callback.
4877 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4878 * the configuration information for the specified I2C.
4879 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
4880 * @param AddrMatchCode Address Match Code
4881 * @retval None
4882 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)4883 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
4884 {
4885 /* Prevent unused argument(s) compilation warning */
4886 UNUSED(hi2c);
4887 UNUSED(TransferDirection);
4888 UNUSED(AddrMatchCode);
4889
4890 /* NOTE : This function should not be modified, when the callback is needed,
4891 the HAL_I2C_AddrCallback() could be implemented in the user file
4892 */
4893 }
4894
4895 /**
4896 * @brief Listen Complete callback.
4897 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4898 * the configuration information for the specified I2C.
4899 * @retval None
4900 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)4901 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
4902 {
4903 /* Prevent unused argument(s) compilation warning */
4904 UNUSED(hi2c);
4905
4906 /* NOTE : This function should not be modified, when the callback is needed,
4907 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
4908 */
4909 }
4910
4911 /**
4912 * @brief Memory Tx Transfer completed callback.
4913 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4914 * the configuration information for the specified I2C.
4915 * @retval None
4916 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)4917 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
4918 {
4919 /* Prevent unused argument(s) compilation warning */
4920 UNUSED(hi2c);
4921
4922 /* NOTE : This function should not be modified, when the callback is needed,
4923 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
4924 */
4925 }
4926
4927 /**
4928 * @brief Memory Rx Transfer completed callback.
4929 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4930 * the configuration information for the specified I2C.
4931 * @retval None
4932 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)4933 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
4934 {
4935 /* Prevent unused argument(s) compilation warning */
4936 UNUSED(hi2c);
4937
4938 /* NOTE : This function should not be modified, when the callback is needed,
4939 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
4940 */
4941 }
4942
4943 /**
4944 * @brief I2C error callback.
4945 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4946 * the configuration information for the specified I2C.
4947 * @retval None
4948 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)4949 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
4950 {
4951 /* Prevent unused argument(s) compilation warning */
4952 UNUSED(hi2c);
4953
4954 /* NOTE : This function should not be modified, when the callback is needed,
4955 the HAL_I2C_ErrorCallback could be implemented in the user file
4956 */
4957 }
4958
4959 /**
4960 * @brief I2C abort callback.
4961 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4962 * the configuration information for the specified I2C.
4963 * @retval None
4964 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)4965 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
4966 {
4967 /* Prevent unused argument(s) compilation warning */
4968 UNUSED(hi2c);
4969
4970 /* NOTE : This function should not be modified, when the callback is needed,
4971 the HAL_I2C_AbortCpltCallback could be implemented in the user file
4972 */
4973 }
4974
4975 /**
4976 * @}
4977 */
4978
4979 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
4980 * @brief Peripheral State, Mode and Error functions
4981 *
4982 @verbatim
4983 ===============================================================================
4984 ##### Peripheral State, Mode and Error functions #####
4985 ===============================================================================
4986 [..]
4987 This subsection permit to get in run-time the status of the peripheral
4988 and the data flow.
4989
4990 @endverbatim
4991 * @{
4992 */
4993
4994 /**
4995 * @brief Return the I2C handle state.
4996 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4997 * the configuration information for the specified I2C.
4998 * @retval HAL state
4999 */
HAL_I2C_GetState(I2C_HandleTypeDef * hi2c)5000 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
5001 {
5002 /* Return I2C handle state */
5003 return hi2c->State;
5004 }
5005
5006 /**
5007 * @brief Returns the I2C Master, Slave, Memory or no mode.
5008 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5009 * the configuration information for I2C module
5010 * @retval HAL mode
5011 */
HAL_I2C_GetMode(I2C_HandleTypeDef * hi2c)5012 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
5013 {
5014 return hi2c->Mode;
5015 }
5016
5017 /**
5018 * @brief Return the I2C error code.
5019 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5020 * the configuration information for the specified I2C.
5021 * @retval I2C Error Code
5022 */
HAL_I2C_GetError(I2C_HandleTypeDef * hi2c)5023 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
5024 {
5025 return hi2c->ErrorCode;
5026 }
5027
5028 /**
5029 * @}
5030 */
5031
5032 /**
5033 * @}
5034 */
5035
5036 /** @addtogroup I2C_Private_Functions
5037 * @{
5038 */
5039
5040 /**
5041 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
5042 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5043 * the configuration information for the specified I2C.
5044 * @param ITFlags Interrupt flags to handle.
5045 * @param ITSources Interrupt sources enabled.
5046 * @retval HAL status
5047 */
I2C_Master_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5048 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5049 uint32_t ITSources)
5050 {
5051 uint16_t devaddress;
5052 uint32_t tmpITFlags = ITFlags;
5053
5054 /* Process Locked */
5055 __HAL_LOCK(hi2c);
5056
5057 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5058 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5059 {
5060 /* Clear NACK Flag */
5061 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5062
5063 /* Set corresponding Error Code */
5064 /* No need to generate STOP, it is automatically done */
5065 /* Error callback will be send during stop flag treatment */
5066 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5067
5068 /* Flush TX register */
5069 I2C_Flush_TXDR(hi2c);
5070 }
5071 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5072 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5073 {
5074 /* Remove RXNE flag on temporary variable as read done */
5075 tmpITFlags &= ~I2C_FLAG_RXNE;
5076
5077 /* Read data from RXDR */
5078 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5079
5080 /* Increment Buffer pointer */
5081 hi2c->pBuffPtr++;
5082
5083 hi2c->XferSize--;
5084 hi2c->XferCount--;
5085 }
5086 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5087 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5088 {
5089 /* Write data to TXDR */
5090 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5091
5092 /* Increment Buffer pointer */
5093 hi2c->pBuffPtr++;
5094
5095 hi2c->XferSize--;
5096 hi2c->XferCount--;
5097 }
5098 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
5099 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5100 {
5101 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
5102 {
5103 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5104
5105 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5106 {
5107 hi2c->XferSize = MAX_NBYTE_SIZE;
5108 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5109 }
5110 else
5111 {
5112 hi2c->XferSize = hi2c->XferCount;
5113 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5114 {
5115 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
5116 hi2c->XferOptions, I2C_NO_STARTSTOP);
5117 }
5118 else
5119 {
5120 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
5121 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5122 }
5123 }
5124 }
5125 else
5126 {
5127 /* Call TxCpltCallback() if no stop mode is set */
5128 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5129 {
5130 /* Call I2C Master Sequential complete process */
5131 I2C_ITMasterSeqCplt(hi2c);
5132 }
5133 else
5134 {
5135 /* Wrong size Status regarding TCR flag event */
5136 /* Call the corresponding callback to inform upper layer of End of Transfer */
5137 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5138 }
5139 }
5140 }
5141 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
5142 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5143 {
5144 if (hi2c->XferCount == 0U)
5145 {
5146 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5147 {
5148 /* Generate a stop condition in case of no transfer option */
5149 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5150 {
5151 /* Generate Stop */
5152 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5153 }
5154 else
5155 {
5156 /* Call I2C Master Sequential complete process */
5157 I2C_ITMasterSeqCplt(hi2c);
5158 }
5159 }
5160 }
5161 else
5162 {
5163 /* Wrong size Status regarding TC flag event */
5164 /* Call the corresponding callback to inform upper layer of End of Transfer */
5165 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5166 }
5167 }
5168 else
5169 {
5170 /* Nothing to do */
5171 }
5172
5173 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5174 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5175 {
5176 /* Call I2C Master complete process */
5177 I2C_ITMasterCplt(hi2c, tmpITFlags);
5178 }
5179
5180 /* Process Unlocked */
5181 __HAL_UNLOCK(hi2c);
5182
5183 return HAL_OK;
5184 }
5185
5186 /**
5187 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
5188 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5189 * the configuration information for the specified I2C.
5190 * @param ITFlags Interrupt flags to handle.
5191 * @param ITSources Interrupt sources enabled.
5192 * @retval HAL status
5193 */
I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5194 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5195 uint32_t ITSources)
5196 {
5197 uint32_t tmpoptions = hi2c->XferOptions;
5198 uint32_t tmpITFlags = ITFlags;
5199
5200 /* Process locked */
5201 __HAL_LOCK(hi2c);
5202
5203 /* Check if STOPF is set */
5204 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5205 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5206 {
5207 /* Call I2C Slave complete process */
5208 I2C_ITSlaveCplt(hi2c, tmpITFlags);
5209 }
5210
5211 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5212 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5213 {
5214 /* Check that I2C transfer finished */
5215 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5216 /* Mean XferCount == 0*/
5217 /* So clear Flag NACKF only */
5218 if (hi2c->XferCount == 0U)
5219 {
5220 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5221 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5222 Warning[Pa134]: left and right operands are identical */
5223 {
5224 /* Call I2C Listen complete process */
5225 I2C_ITListenCplt(hi2c, tmpITFlags);
5226 }
5227 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5228 {
5229 /* Clear NACK Flag */
5230 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5231
5232 /* Flush TX register */
5233 I2C_Flush_TXDR(hi2c);
5234
5235 /* Last Byte is Transmitted */
5236 /* Call I2C Slave Sequential complete process */
5237 I2C_ITSlaveSeqCplt(hi2c);
5238 }
5239 else
5240 {
5241 /* Clear NACK Flag */
5242 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5243 }
5244 }
5245 else
5246 {
5247 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5248 /* Clear NACK Flag */
5249 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5250
5251 /* Set ErrorCode corresponding to a Non-Acknowledge */
5252 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5253
5254 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5255 {
5256 /* Call the corresponding callback to inform upper layer of End of Transfer */
5257 I2C_ITError(hi2c, hi2c->ErrorCode);
5258 }
5259 }
5260 }
5261 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5262 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5263 {
5264 if (hi2c->XferCount > 0U)
5265 {
5266 /* Read data from RXDR */
5267 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5268
5269 /* Increment Buffer pointer */
5270 hi2c->pBuffPtr++;
5271
5272 hi2c->XferSize--;
5273 hi2c->XferCount--;
5274 }
5275
5276 if ((hi2c->XferCount == 0U) && \
5277 (tmpoptions != I2C_NO_OPTION_FRAME))
5278 {
5279 /* Call I2C Slave Sequential complete process */
5280 I2C_ITSlaveSeqCplt(hi2c);
5281 }
5282 }
5283 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
5284 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5285 {
5286 I2C_ITAddrCplt(hi2c, tmpITFlags);
5287 }
5288 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5289 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5290 {
5291 /* Write data to TXDR only if XferCount not reach "0" */
5292 /* A TXIS flag can be set, during STOP treatment */
5293 /* Check if all Data have already been sent */
5294 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
5295 if (hi2c->XferCount > 0U)
5296 {
5297 /* Write data to TXDR */
5298 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5299
5300 /* Increment Buffer pointer */
5301 hi2c->pBuffPtr++;
5302
5303 hi2c->XferCount--;
5304 hi2c->XferSize--;
5305 }
5306 else
5307 {
5308 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
5309 {
5310 /* Last Byte is Transmitted */
5311 /* Call I2C Slave Sequential complete process */
5312 I2C_ITSlaveSeqCplt(hi2c);
5313 }
5314 }
5315 }
5316 else
5317 {
5318 /* Nothing to do */
5319 }
5320
5321 /* Process Unlocked */
5322 __HAL_UNLOCK(hi2c);
5323
5324 return HAL_OK;
5325 }
5326
5327 /**
5328 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
5329 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5330 * the configuration information for the specified I2C.
5331 * @param ITFlags Interrupt flags to handle.
5332 * @param ITSources Interrupt sources enabled.
5333 * @retval HAL status
5334 */
I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5335 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5336 uint32_t ITSources)
5337 {
5338 uint16_t devaddress;
5339 uint32_t xfermode;
5340
5341 /* Process Locked */
5342 __HAL_LOCK(hi2c);
5343
5344 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5345 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5346 {
5347 /* Clear NACK Flag */
5348 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5349
5350 /* Set corresponding Error Code */
5351 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5352
5353 /* No need to generate STOP, it is automatically done */
5354 /* But enable STOP interrupt, to treat it */
5355 /* Error callback will be send during stop flag treatment */
5356 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5357
5358 /* Flush TX register */
5359 I2C_Flush_TXDR(hi2c);
5360 }
5361 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5362 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5363 {
5364 /* Disable TC interrupt */
5365 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
5366
5367 if (hi2c->XferCount != 0U)
5368 {
5369 /* Recover Slave address */
5370 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5371
5372 /* Prepare the new XferSize to transfer */
5373 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5374 {
5375 hi2c->XferSize = MAX_NBYTE_SIZE;
5376 xfermode = I2C_RELOAD_MODE;
5377 }
5378 else
5379 {
5380 hi2c->XferSize = hi2c->XferCount;
5381 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5382 {
5383 xfermode = hi2c->XferOptions;
5384 }
5385 else
5386 {
5387 xfermode = I2C_AUTOEND_MODE;
5388 }
5389 }
5390
5391 /* Set the new XferSize in Nbytes register */
5392 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
5393
5394 /* Update XferCount value */
5395 hi2c->XferCount -= hi2c->XferSize;
5396
5397 /* Enable DMA Request */
5398 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5399 {
5400 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5401 }
5402 else
5403 {
5404 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5405 }
5406 }
5407 else
5408 {
5409 /* Call TxCpltCallback() if no stop mode is set */
5410 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5411 {
5412 /* Call I2C Master Sequential complete process */
5413 I2C_ITMasterSeqCplt(hi2c);
5414 }
5415 else
5416 {
5417 /* Wrong size Status regarding TCR flag event */
5418 /* Call the corresponding callback to inform upper layer of End of Transfer */
5419 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5420 }
5421 }
5422 }
5423 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5424 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5425 {
5426 if (hi2c->XferCount == 0U)
5427 {
5428 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5429 {
5430 /* Generate a stop condition in case of no transfer option */
5431 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5432 {
5433 /* Generate Stop */
5434 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5435 }
5436 else
5437 {
5438 /* Call I2C Master Sequential complete process */
5439 I2C_ITMasterSeqCplt(hi2c);
5440 }
5441 }
5442 }
5443 else
5444 {
5445 /* Wrong size Status regarding TC flag event */
5446 /* Call the corresponding callback to inform upper layer of End of Transfer */
5447 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5448 }
5449 }
5450 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5451 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5452 {
5453 /* Call I2C Master complete process */
5454 I2C_ITMasterCplt(hi2c, ITFlags);
5455 }
5456 else
5457 {
5458 /* Nothing to do */
5459 }
5460
5461 /* Process Unlocked */
5462 __HAL_UNLOCK(hi2c);
5463
5464 return HAL_OK;
5465 }
5466
5467 /**
5468 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
5469 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5470 * the configuration information for the specified I2C.
5471 * @param ITFlags Interrupt flags to handle.
5472 * @param ITSources Interrupt sources enabled.
5473 * @retval HAL status
5474 */
I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5475 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5476 uint32_t ITSources)
5477 {
5478 uint32_t tmpoptions = hi2c->XferOptions;
5479 uint32_t treatdmanack = 0U;
5480 HAL_I2C_StateTypeDef tmpstate;
5481
5482 /* Process locked */
5483 __HAL_LOCK(hi2c);
5484
5485 /* Check if STOPF is set */
5486 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5487 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5488 {
5489 /* Call I2C Slave complete process */
5490 I2C_ITSlaveCplt(hi2c, ITFlags);
5491 }
5492
5493 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5494 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5495 {
5496 /* Check that I2C transfer finished */
5497 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5498 /* Mean XferCount == 0 */
5499 /* So clear Flag NACKF only */
5500 if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
5501 (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
5502 {
5503 /* Split check of hdmarx, for MISRA compliance */
5504 if (hi2c->hdmarx != NULL)
5505 {
5506 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
5507 {
5508 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
5509 {
5510 treatdmanack = 1U;
5511 }
5512 }
5513 }
5514
5515 /* Split check of hdmatx, for MISRA compliance */
5516 if (hi2c->hdmatx != NULL)
5517 {
5518 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
5519 {
5520 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
5521 {
5522 treatdmanack = 1U;
5523 }
5524 }
5525 }
5526
5527 #ifdef HAL_MDMA_MODULE_ENABLED
5528 if (hi2c->hmdmarx != NULL)
5529 {
5530 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
5531 {
5532 if (I2C_GET_MDMA_REMAIN_DATA_RX(hi2c) == 0U)
5533 {
5534 treatdmanack = 1U;
5535 }
5536 }
5537 }
5538
5539 if (hi2c->hmdmatx != NULL)
5540 {
5541 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
5542 {
5543 if (I2C_GET_MDMA_REMAIN_DATA_TX(hi2c) == 0U)
5544 {
5545 treatdmanack = 1U;
5546 }
5547 }
5548 }
5549 #endif /* HAL_MDMA_MODULE_ENABLED */
5550
5551 if (treatdmanack == 1U)
5552 {
5553 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5554 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5555 Warning[Pa134]: left and right operands are identical */
5556 {
5557 /* Call I2C Listen complete process */
5558 I2C_ITListenCplt(hi2c, ITFlags);
5559 }
5560 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5561 {
5562 /* Clear NACK Flag */
5563 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5564
5565 /* Flush TX register */
5566 I2C_Flush_TXDR(hi2c);
5567
5568 /* Last Byte is Transmitted */
5569 /* Call I2C Slave Sequential complete process */
5570 I2C_ITSlaveSeqCplt(hi2c);
5571 }
5572 else
5573 {
5574 /* Clear NACK Flag */
5575 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5576 }
5577 }
5578 else
5579 {
5580 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5581 /* Clear NACK Flag */
5582 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5583
5584 /* Set ErrorCode corresponding to a Non-Acknowledge */
5585 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5586
5587 /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
5588 tmpstate = hi2c->State;
5589
5590 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5591 {
5592 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
5593 {
5594 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
5595 }
5596 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
5597 {
5598 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
5599 }
5600 else
5601 {
5602 /* Do nothing */
5603 }
5604
5605 /* Call the corresponding callback to inform upper layer of End of Transfer */
5606 I2C_ITError(hi2c, hi2c->ErrorCode);
5607 }
5608 }
5609 }
5610 else
5611 {
5612 /* Only Clear NACK Flag, no DMA treatment is pending */
5613 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5614 }
5615 }
5616 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
5617 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5618 {
5619 I2C_ITAddrCplt(hi2c, ITFlags);
5620 }
5621 else
5622 {
5623 /* Nothing to do */
5624 }
5625
5626 /* Process Unlocked */
5627 __HAL_UNLOCK(hi2c);
5628
5629 return HAL_OK;
5630 }
5631
5632 /**
5633 * @brief Master sends target device address followed by internal memory address for write request.
5634 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5635 * the configuration information for the specified I2C.
5636 * @param DevAddress Target device address: The device 7 bits address value
5637 * in datasheet must be shifted to the left before calling the interface
5638 * @param MemAddress Internal memory address
5639 * @param MemAddSize Size of internal memory address
5640 * @param Timeout Timeout duration
5641 * @param Tickstart Tick start value
5642 * @retval HAL status
5643 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)5644 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
5645 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
5646 uint32_t Tickstart)
5647 {
5648 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
5649
5650 /* Wait until TXIS flag is set */
5651 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5652 {
5653 return HAL_ERROR;
5654 }
5655
5656 /* If Memory address size is 8Bit */
5657 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
5658 {
5659 /* Send Memory Address */
5660 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5661 }
5662 /* If Memory address size is 16Bit */
5663 else
5664 {
5665 /* Send MSB of Memory Address */
5666 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
5667
5668 /* Wait until TXIS flag is set */
5669 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5670 {
5671 return HAL_ERROR;
5672 }
5673
5674 /* Send LSB of Memory Address */
5675 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5676 }
5677
5678 /* Wait until TCR flag is set */
5679 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
5680 {
5681 return HAL_ERROR;
5682 }
5683
5684 return HAL_OK;
5685 }
5686
5687 /**
5688 * @brief Master sends target device address followed by internal memory address for read request.
5689 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5690 * the configuration information for the specified I2C.
5691 * @param DevAddress Target device address: The device 7 bits address value
5692 * in datasheet must be shifted to the left before calling the interface
5693 * @param MemAddress Internal memory address
5694 * @param MemAddSize Size of internal memory address
5695 * @param Timeout Timeout duration
5696 * @param Tickstart Tick start value
5697 * @retval HAL status
5698 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)5699 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
5700 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
5701 uint32_t Tickstart)
5702 {
5703 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
5704
5705 /* Wait until TXIS flag is set */
5706 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5707 {
5708 return HAL_ERROR;
5709 }
5710
5711 /* If Memory address size is 8Bit */
5712 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
5713 {
5714 /* Send Memory Address */
5715 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5716 }
5717 /* If Memory address size is 16Bit */
5718 else
5719 {
5720 /* Send MSB of Memory Address */
5721 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
5722
5723 /* Wait until TXIS flag is set */
5724 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5725 {
5726 return HAL_ERROR;
5727 }
5728
5729 /* Send LSB of Memory Address */
5730 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5731 }
5732
5733 /* Wait until TC flag is set */
5734 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
5735 {
5736 return HAL_ERROR;
5737 }
5738
5739 return HAL_OK;
5740 }
5741
5742 /**
5743 * @brief I2C Address complete process callback.
5744 * @param hi2c I2C handle.
5745 * @param ITFlags Interrupt flags to handle.
5746 * @retval None
5747 */
I2C_ITAddrCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)5748 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
5749 {
5750 uint8_t transferdirection;
5751 uint16_t slaveaddrcode;
5752 uint16_t ownadd1code;
5753 uint16_t ownadd2code;
5754
5755 /* Prevent unused argument(s) compilation warning */
5756 UNUSED(ITFlags);
5757
5758 /* In case of Listen state, need to inform upper layer of address match code event */
5759 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
5760 {
5761 transferdirection = I2C_GET_DIR(hi2c);
5762 slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
5763 ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
5764 ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
5765
5766 /* If 10bits addressing mode is selected */
5767 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
5768 {
5769 if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
5770 {
5771 slaveaddrcode = ownadd1code;
5772 hi2c->AddrEventCount++;
5773 if (hi2c->AddrEventCount == 2U)
5774 {
5775 /* Reset Address Event counter */
5776 hi2c->AddrEventCount = 0U;
5777
5778 /* Clear ADDR flag */
5779 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
5780
5781 /* Process Unlocked */
5782 __HAL_UNLOCK(hi2c);
5783
5784 /* Call Slave Addr callback */
5785 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5786 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5787 #else
5788 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5789 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5790 }
5791 }
5792 else
5793 {
5794 slaveaddrcode = ownadd2code;
5795
5796 /* Disable ADDR Interrupts */
5797 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
5798
5799 /* Process Unlocked */
5800 __HAL_UNLOCK(hi2c);
5801
5802 /* Call Slave Addr callback */
5803 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5804 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5805 #else
5806 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5807 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5808 }
5809 }
5810 /* else 7 bits addressing mode is selected */
5811 else
5812 {
5813 /* Disable ADDR Interrupts */
5814 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
5815
5816 /* Process Unlocked */
5817 __HAL_UNLOCK(hi2c);
5818
5819 /* Call Slave Addr callback */
5820 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5821 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5822 #else
5823 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5824 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5825 }
5826 }
5827 /* Else clear address flag only */
5828 else
5829 {
5830 /* Clear ADDR flag */
5831 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
5832
5833 /* Process Unlocked */
5834 __HAL_UNLOCK(hi2c);
5835 }
5836 }
5837
5838 /**
5839 * @brief I2C Master sequential complete process.
5840 * @param hi2c I2C handle.
5841 * @retval None
5842 */
I2C_ITMasterSeqCplt(I2C_HandleTypeDef * hi2c)5843 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
5844 {
5845 /* Reset I2C handle mode */
5846 hi2c->Mode = HAL_I2C_MODE_NONE;
5847
5848 /* No Generate Stop, to permit restart mode */
5849 /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
5850 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5851 {
5852 hi2c->State = HAL_I2C_STATE_READY;
5853 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5854 hi2c->XferISR = NULL;
5855
5856 /* Disable Interrupts */
5857 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5858
5859 /* Process Unlocked */
5860 __HAL_UNLOCK(hi2c);
5861
5862 /* Call the corresponding callback to inform upper layer of End of Transfer */
5863 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5864 hi2c->MasterTxCpltCallback(hi2c);
5865 #else
5866 HAL_I2C_MasterTxCpltCallback(hi2c);
5867 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5868 }
5869 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
5870 else
5871 {
5872 hi2c->State = HAL_I2C_STATE_READY;
5873 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5874 hi2c->XferISR = NULL;
5875
5876 /* Disable Interrupts */
5877 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
5878
5879 /* Process Unlocked */
5880 __HAL_UNLOCK(hi2c);
5881
5882 /* Call the corresponding callback to inform upper layer of End of Transfer */
5883 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5884 hi2c->MasterRxCpltCallback(hi2c);
5885 #else
5886 HAL_I2C_MasterRxCpltCallback(hi2c);
5887 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5888 }
5889 }
5890
5891 /**
5892 * @brief I2C Slave sequential complete process.
5893 * @param hi2c I2C handle.
5894 * @retval None
5895 */
I2C_ITSlaveSeqCplt(I2C_HandleTypeDef * hi2c)5896 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
5897 {
5898 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
5899
5900 /* Reset I2C handle mode */
5901 hi2c->Mode = HAL_I2C_MODE_NONE;
5902
5903 /* If a DMA is ongoing, Update handle size context */
5904 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
5905 {
5906 /* Disable DMA Request */
5907 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
5908 }
5909 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
5910 {
5911 /* Disable DMA Request */
5912 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
5913 }
5914 else
5915 {
5916 /* Do nothing */
5917 }
5918
5919 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
5920 {
5921 /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
5922 hi2c->State = HAL_I2C_STATE_LISTEN;
5923 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
5924
5925 /* Disable Interrupts */
5926 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5927
5928 /* Process Unlocked */
5929 __HAL_UNLOCK(hi2c);
5930
5931 /* Call the corresponding callback to inform upper layer of End of Transfer */
5932 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5933 hi2c->SlaveTxCpltCallback(hi2c);
5934 #else
5935 HAL_I2C_SlaveTxCpltCallback(hi2c);
5936 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5937 }
5938
5939 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
5940 {
5941 /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
5942 hi2c->State = HAL_I2C_STATE_LISTEN;
5943 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
5944
5945 /* Disable Interrupts */
5946 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
5947
5948 /* Process Unlocked */
5949 __HAL_UNLOCK(hi2c);
5950
5951 /* Call the corresponding callback to inform upper layer of End of Transfer */
5952 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5953 hi2c->SlaveRxCpltCallback(hi2c);
5954 #else
5955 HAL_I2C_SlaveRxCpltCallback(hi2c);
5956 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5957 }
5958 else
5959 {
5960 /* Nothing to do */
5961 }
5962 }
5963
5964 /**
5965 * @brief I2C Master complete process.
5966 * @param hi2c I2C handle.
5967 * @param ITFlags Interrupt flags to handle.
5968 * @retval None
5969 */
I2C_ITMasterCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)5970 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
5971 {
5972 uint32_t tmperror;
5973 uint32_t tmpITFlags = ITFlags;
5974 __IO uint32_t tmpreg;
5975
5976 /* Clear STOP Flag */
5977 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
5978
5979 /* Disable Interrupts and Store Previous state */
5980 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5981 {
5982 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5983 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5984 }
5985 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5986 {
5987 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
5988 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5989 }
5990 else
5991 {
5992 /* Do nothing */
5993 }
5994
5995 /* Clear Configuration Register 2 */
5996 I2C_RESET_CR2(hi2c);
5997
5998 /* Reset handle parameters */
5999 hi2c->XferISR = NULL;
6000 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6001
6002 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
6003 {
6004 /* Clear NACK Flag */
6005 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6006
6007 /* Set acknowledge error code */
6008 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6009 }
6010
6011 /* Fetch Last receive data if any */
6012 if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
6013 {
6014 /* Read data from RXDR */
6015 tmpreg = (uint8_t)hi2c->Instance->RXDR;
6016 UNUSED(tmpreg);
6017 }
6018
6019 /* Flush TX register */
6020 I2C_Flush_TXDR(hi2c);
6021
6022 /* Store current volatile hi2c->ErrorCode, misra rule */
6023 tmperror = hi2c->ErrorCode;
6024
6025 /* Call the corresponding callback to inform upper layer of End of Transfer */
6026 if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
6027 {
6028 /* Call the corresponding callback to inform upper layer of End of Transfer */
6029 I2C_ITError(hi2c, hi2c->ErrorCode);
6030 }
6031 /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
6032 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6033 {
6034 hi2c->State = HAL_I2C_STATE_READY;
6035 hi2c->PreviousState = I2C_STATE_NONE;
6036
6037 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6038 {
6039 hi2c->Mode = HAL_I2C_MODE_NONE;
6040
6041 /* Process Unlocked */
6042 __HAL_UNLOCK(hi2c);
6043
6044 /* Call the corresponding callback to inform upper layer of End of Transfer */
6045 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6046 hi2c->MemTxCpltCallback(hi2c);
6047 #else
6048 HAL_I2C_MemTxCpltCallback(hi2c);
6049 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6050 }
6051 else
6052 {
6053 hi2c->Mode = HAL_I2C_MODE_NONE;
6054
6055 /* Process Unlocked */
6056 __HAL_UNLOCK(hi2c);
6057
6058 /* Call the corresponding callback to inform upper layer of End of Transfer */
6059 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6060 hi2c->MasterTxCpltCallback(hi2c);
6061 #else
6062 HAL_I2C_MasterTxCpltCallback(hi2c);
6063 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6064 }
6065 }
6066 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6067 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6068 {
6069 hi2c->State = HAL_I2C_STATE_READY;
6070 hi2c->PreviousState = I2C_STATE_NONE;
6071
6072 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6073 {
6074 hi2c->Mode = HAL_I2C_MODE_NONE;
6075
6076 /* Process Unlocked */
6077 __HAL_UNLOCK(hi2c);
6078
6079 /* Call the corresponding callback to inform upper layer of End of Transfer */
6080 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6081 hi2c->MemRxCpltCallback(hi2c);
6082 #else
6083 HAL_I2C_MemRxCpltCallback(hi2c);
6084 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6085 }
6086 else
6087 {
6088 hi2c->Mode = HAL_I2C_MODE_NONE;
6089
6090 /* Process Unlocked */
6091 __HAL_UNLOCK(hi2c);
6092
6093 /* Call the corresponding callback to inform upper layer of End of Transfer */
6094 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6095 hi2c->MasterRxCpltCallback(hi2c);
6096 #else
6097 HAL_I2C_MasterRxCpltCallback(hi2c);
6098 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6099 }
6100 }
6101 else
6102 {
6103 /* Nothing to do */
6104 }
6105 }
6106
6107 /**
6108 * @brief I2C Slave complete process.
6109 * @param hi2c I2C handle.
6110 * @param ITFlags Interrupt flags to handle.
6111 * @retval None
6112 */
I2C_ITSlaveCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6113 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6114 {
6115 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6116 uint32_t tmpITFlags = ITFlags;
6117 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6118
6119 /* Clear STOP Flag */
6120 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6121
6122 /* Disable Interrupts and Store Previous state */
6123 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
6124 {
6125 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
6126 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6127 }
6128 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6129 {
6130 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
6131 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6132 }
6133 else
6134 {
6135 /* Do nothing */
6136 }
6137
6138 /* Disable Address Acknowledge */
6139 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6140
6141 /* Clear Configuration Register 2 */
6142 I2C_RESET_CR2(hi2c);
6143
6144 /* Flush TX register */
6145 I2C_Flush_TXDR(hi2c);
6146
6147 /* If a DMA is ongoing, Update handle size context */
6148 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6149 {
6150 /* Disable DMA Request */
6151 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6152
6153 if (hi2c->hdmatx != NULL)
6154 {
6155 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
6156 }
6157 #ifdef HAL_MDMA_MODULE_ENABLED
6158 else if (hi2c->hmdmatx != NULL)
6159 {
6160 hi2c->XferCount = I2C_GET_MDMA_REMAIN_DATA_TX(hi2c);
6161 }
6162 #endif /* HAL_MDMA_MODULE_ENABLED */
6163 }
6164 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6165 {
6166 /* Disable DMA Request */
6167 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6168
6169 if (hi2c->hdmarx != NULL)
6170 {
6171 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
6172 }
6173 #ifdef HAL_MDMA_MODULE_ENABLED
6174 else if (hi2c->hmdmarx != NULL)
6175 {
6176 hi2c->XferCount = I2C_GET_MDMA_REMAIN_DATA_RX(hi2c);
6177 }
6178 #endif /* HAL_MDMA_MODULE_ENABLED */
6179 }
6180 else
6181 {
6182 /* Do nothing */
6183 }
6184
6185 /* Store Last receive data if any */
6186 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
6187 {
6188 /* Remove RXNE flag on temporary variable as read done */
6189 tmpITFlags &= ~I2C_FLAG_RXNE;
6190
6191 /* Read data from RXDR */
6192 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6193
6194 /* Increment Buffer pointer */
6195 hi2c->pBuffPtr++;
6196
6197 if ((hi2c->XferSize > 0U))
6198 {
6199 hi2c->XferSize--;
6200 hi2c->XferCount--;
6201 }
6202 }
6203
6204 /* All data are not transferred, so set error code accordingly */
6205 if (hi2c->XferCount != 0U)
6206 {
6207 /* Set ErrorCode corresponding to a Non-Acknowledge */
6208 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6209 }
6210
6211 hi2c->Mode = HAL_I2C_MODE_NONE;
6212 hi2c->XferISR = NULL;
6213
6214 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6215 {
6216 /* Call the corresponding callback to inform upper layer of End of Transfer */
6217 I2C_ITError(hi2c, hi2c->ErrorCode);
6218
6219 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6220 if (hi2c->State == HAL_I2C_STATE_LISTEN)
6221 {
6222 /* Call I2C Listen complete process */
6223 I2C_ITListenCplt(hi2c, tmpITFlags);
6224 }
6225 }
6226 else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
6227 {
6228 /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
6229 I2C_ITSlaveSeqCplt(hi2c);
6230
6231 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6232 hi2c->State = HAL_I2C_STATE_READY;
6233 hi2c->PreviousState = I2C_STATE_NONE;
6234
6235 /* Process Unlocked */
6236 __HAL_UNLOCK(hi2c);
6237
6238 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6239 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6240 hi2c->ListenCpltCallback(hi2c);
6241 #else
6242 HAL_I2C_ListenCpltCallback(hi2c);
6243 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6244 }
6245 /* Call the corresponding callback to inform upper layer of End of Transfer */
6246 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6247 {
6248 hi2c->State = HAL_I2C_STATE_READY;
6249 hi2c->PreviousState = I2C_STATE_NONE;
6250
6251 /* Process Unlocked */
6252 __HAL_UNLOCK(hi2c);
6253
6254 /* Call the corresponding callback to inform upper layer of End of Transfer */
6255 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6256 hi2c->SlaveRxCpltCallback(hi2c);
6257 #else
6258 HAL_I2C_SlaveRxCpltCallback(hi2c);
6259 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6260 }
6261 else
6262 {
6263 hi2c->State = HAL_I2C_STATE_READY;
6264 hi2c->PreviousState = I2C_STATE_NONE;
6265
6266 /* Process Unlocked */
6267 __HAL_UNLOCK(hi2c);
6268
6269 /* Call the corresponding callback to inform upper layer of End of Transfer */
6270 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6271 hi2c->SlaveTxCpltCallback(hi2c);
6272 #else
6273 HAL_I2C_SlaveTxCpltCallback(hi2c);
6274 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6275 }
6276 }
6277
6278 /**
6279 * @brief I2C Listen complete process.
6280 * @param hi2c I2C handle.
6281 * @param ITFlags Interrupt flags to handle.
6282 * @retval None
6283 */
I2C_ITListenCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6284 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6285 {
6286 /* Reset handle parameters */
6287 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6288 hi2c->PreviousState = I2C_STATE_NONE;
6289 hi2c->State = HAL_I2C_STATE_READY;
6290 hi2c->Mode = HAL_I2C_MODE_NONE;
6291 hi2c->XferISR = NULL;
6292
6293 /* Store Last receive data if any */
6294 if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
6295 {
6296 /* Read data from RXDR */
6297 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6298
6299 /* Increment Buffer pointer */
6300 hi2c->pBuffPtr++;
6301
6302 if ((hi2c->XferSize > 0U))
6303 {
6304 hi2c->XferSize--;
6305 hi2c->XferCount--;
6306
6307 /* Set ErrorCode corresponding to a Non-Acknowledge */
6308 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6309 }
6310 }
6311
6312 /* Disable all Interrupts*/
6313 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6314
6315 /* Clear NACK Flag */
6316 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6317
6318 /* Process Unlocked */
6319 __HAL_UNLOCK(hi2c);
6320
6321 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6322 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6323 hi2c->ListenCpltCallback(hi2c);
6324 #else
6325 HAL_I2C_ListenCpltCallback(hi2c);
6326 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6327 }
6328
6329 /**
6330 * @brief I2C interrupts error process.
6331 * @param hi2c I2C handle.
6332 * @param ErrorCode Error code to handle.
6333 * @retval None
6334 */
I2C_ITError(I2C_HandleTypeDef * hi2c,uint32_t ErrorCode)6335 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
6336 {
6337 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6338 uint32_t tmppreviousstate;
6339
6340 /* Reset handle parameters */
6341 hi2c->Mode = HAL_I2C_MODE_NONE;
6342 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6343 hi2c->XferCount = 0U;
6344
6345 /* Set new error code */
6346 hi2c->ErrorCode |= ErrorCode;
6347
6348 /* Disable Interrupts */
6349 if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
6350 (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
6351 (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6352 {
6353 /* Disable all interrupts, except interrupts related to LISTEN state */
6354 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6355
6356 /* keep HAL_I2C_STATE_LISTEN if set */
6357 hi2c->State = HAL_I2C_STATE_LISTEN;
6358 hi2c->XferISR = I2C_Slave_ISR_IT;
6359 }
6360 else
6361 {
6362 /* Disable all interrupts */
6363 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6364
6365 /* If state is an abort treatment on going, don't change state */
6366 /* This change will be do later */
6367 if (hi2c->State != HAL_I2C_STATE_ABORT)
6368 {
6369 /* Set HAL_I2C_STATE_READY */
6370 hi2c->State = HAL_I2C_STATE_READY;
6371 }
6372 hi2c->XferISR = NULL;
6373 }
6374
6375 /* Abort DMA TX transfer if any */
6376 tmppreviousstate = hi2c->PreviousState;
6377 #ifdef HAL_MDMA_MODULE_ENABLED
6378 if (((hi2c->hdmatx != NULL) || (hi2c->hmdmatx != NULL)) && \
6379 ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
6380 #else
6381 if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
6382 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
6383 #endif /* HAL_MDMA_MODULE_ENABLED */
6384 {
6385 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
6386 {
6387 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6388 }
6389
6390 if ((hi2c->hdmatx != NULL) && (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY))
6391 {
6392 /* Set the I2C DMA Abort callback :
6393 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6394 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6395
6396 /* Process Unlocked */
6397 __HAL_UNLOCK(hi2c);
6398
6399 /* Abort DMA TX */
6400 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6401 {
6402 /* Call Directly XferAbortCallback function in case of error */
6403 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6404 }
6405 }
6406 #ifdef HAL_MDMA_MODULE_ENABLED
6407 else if ((hi2c->hmdmatx != NULL) && (HAL_MDMA_GetState(hi2c->hmdmatx) != HAL_MDMA_STATE_READY))
6408 {
6409 /* Set the I2C MDMA Abort callback :
6410 will lead to call HAL_I2C_ErrorCallback() at end of MDMA abort procedure */
6411 hi2c->hmdmatx->XferAbortCallback = I2C_MDMAAbort;
6412
6413 /* Process Unlocked */
6414 __HAL_UNLOCK(hi2c);
6415
6416 /* Abort MDMA TX */
6417 if (HAL_MDMA_Abort_IT(hi2c->hmdmatx) != HAL_OK)
6418 {
6419 /* Call Directly XferAbortCallback function in case of error */
6420 hi2c->hmdmatx->XferAbortCallback(hi2c->hmdmatx);
6421 }
6422 }
6423 #endif /* HAL_MDMA_MODULE_ENABLED */
6424 else
6425 {
6426 I2C_TreatErrorCallback(hi2c);
6427 }
6428 }
6429 /* Abort DMA RX transfer if any */
6430 #ifdef HAL_MDMA_MODULE_ENABLED
6431 else if (((hi2c->hdmarx != NULL) || (hi2c->hmdmarx != NULL)) && \
6432 ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
6433 #else
6434 else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
6435 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
6436 #endif /* HAL_MDMA_MODULE_ENABLED */
6437 {
6438 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
6439 {
6440 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6441 }
6442
6443 if ((hi2c->hdmarx != NULL) && (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY))
6444 {
6445 /* Set the I2C DMA Abort callback :
6446 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6447 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6448
6449 /* Process Unlocked */
6450 __HAL_UNLOCK(hi2c);
6451
6452 /* Abort DMA RX */
6453 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6454 {
6455 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6456 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6457 }
6458 }
6459 #ifdef HAL_MDMA_MODULE_ENABLED
6460 else if ((hi2c->hmdmarx != NULL) && (HAL_MDMA_GetState(hi2c->hmdmarx) != HAL_MDMA_STATE_READY))
6461 {
6462 /* Set the I2C MDMA Abort callback :
6463 will lead to call HAL_I2C_ErrorCallback() at end of MDMA abort procedure */
6464 hi2c->hmdmarx->XferAbortCallback = I2C_MDMAAbort;
6465
6466 /* Process Unlocked */
6467 __HAL_UNLOCK(hi2c);
6468
6469 /* Abort MDMA RX */
6470 if (HAL_MDMA_Abort_IT(hi2c->hmdmarx) != HAL_OK)
6471 {
6472 /* Call Directly hi2c->hmdmarx->XferAbortCallback function in case of error */
6473 hi2c->hmdmarx->XferAbortCallback(hi2c->hmdmarx);
6474 }
6475 }
6476 #endif /* HAL_MDMA_MODULE_ENABLED */
6477 else
6478 {
6479 I2C_TreatErrorCallback(hi2c);
6480 }
6481 }
6482 else
6483 {
6484 I2C_TreatErrorCallback(hi2c);
6485 }
6486 }
6487
6488 /**
6489 * @brief I2C Error callback treatment.
6490 * @param hi2c I2C handle.
6491 * @retval None
6492 */
I2C_TreatErrorCallback(I2C_HandleTypeDef * hi2c)6493 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
6494 {
6495 if (hi2c->State == HAL_I2C_STATE_ABORT)
6496 {
6497 hi2c->State = HAL_I2C_STATE_READY;
6498 hi2c->PreviousState = I2C_STATE_NONE;
6499
6500 /* Process Unlocked */
6501 __HAL_UNLOCK(hi2c);
6502
6503 /* Call the corresponding callback to inform upper layer of End of Transfer */
6504 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6505 hi2c->AbortCpltCallback(hi2c);
6506 #else
6507 HAL_I2C_AbortCpltCallback(hi2c);
6508 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6509 }
6510 else
6511 {
6512 hi2c->PreviousState = I2C_STATE_NONE;
6513
6514 /* Process Unlocked */
6515 __HAL_UNLOCK(hi2c);
6516
6517 /* Call the corresponding callback to inform upper layer of End of Transfer */
6518 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6519 hi2c->ErrorCallback(hi2c);
6520 #else
6521 HAL_I2C_ErrorCallback(hi2c);
6522 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6523 }
6524 }
6525
6526 /**
6527 * @brief I2C Tx data register flush process.
6528 * @param hi2c I2C handle.
6529 * @retval None
6530 */
I2C_Flush_TXDR(I2C_HandleTypeDef * hi2c)6531 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
6532 {
6533 /* If a pending TXIS flag is set */
6534 /* Write a dummy data in TXDR to clear it */
6535 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
6536 {
6537 hi2c->Instance->TXDR = 0x00U;
6538 }
6539
6540 /* Flush TX register if not empty */
6541 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
6542 {
6543 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
6544 }
6545 }
6546
6547 /**
6548 * @brief DMA I2C master transmit process complete callback.
6549 * @param hdma DMA handle
6550 * @retval None
6551 */
I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef * hdma)6552 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
6553 {
6554 /* Derogation MISRAC2012-Rule-11.5 */
6555 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6556
6557 /* Disable DMA Request */
6558 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6559
6560 /* If last transfer, enable STOP interrupt */
6561 if (hi2c->XferCount == 0U)
6562 {
6563 /* Enable STOP interrupt */
6564 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6565 }
6566 /* else prepare a new DMA transfer and enable TCReload interrupt */
6567 else
6568 {
6569 /* Update Buffer pointer */
6570 hi2c->pBuffPtr += hi2c->XferSize;
6571
6572 /* Set the XferSize to transfer */
6573 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6574 {
6575 hi2c->XferSize = MAX_NBYTE_SIZE;
6576 }
6577 else
6578 {
6579 hi2c->XferSize = hi2c->XferCount;
6580 }
6581
6582 /* Enable the DMA stream */
6583 if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
6584 hi2c->XferSize) != HAL_OK)
6585 {
6586 /* Call the corresponding callback to inform upper layer of End of Transfer */
6587 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6588 }
6589 else
6590 {
6591 /* Enable TC interrupts */
6592 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6593 }
6594 }
6595 }
6596 #ifdef HAL_MDMA_MODULE_ENABLED
6597
6598 /**
6599 * @brief MDMA I2C master transmit process complete callback.
6600 * @param hmdma MDMA handle
6601 * @retval None
6602 */
I2C_MDMAMasterTransmitCplt(MDMA_HandleTypeDef * hmdma)6603 static void I2C_MDMAMasterTransmitCplt(MDMA_HandleTypeDef *hmdma)
6604 {
6605 /* Derogation MISRAC2012-Rule-11.5 */
6606 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((MDMA_HandleTypeDef *)hmdma)->Parent);
6607
6608 /* Disable MDMA Request */
6609 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6610
6611 /* If last transfer, enable STOP interrupt */
6612 if (hi2c->XferCount == 0U)
6613 {
6614 /* Enable STOP interrupt */
6615 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6616 }
6617 /* else prepare a new MDMA transfer and enable TCReload interrupt */
6618 else
6619 {
6620 /* Update Buffer pointer */
6621 hi2c->pBuffPtr += hi2c->XferSize;
6622
6623 /* Set the XferSize to transfer */
6624 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6625 {
6626 hi2c->XferSize = MAX_NBYTE_SIZE;
6627 }
6628 else
6629 {
6630 hi2c->XferSize = hi2c->XferCount;
6631 }
6632
6633 /* Enable the MDMA stream */
6634 if (HAL_MDMA_Start_IT(hi2c->hmdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
6635 hi2c->XferSize, 1) != HAL_OK)
6636 {
6637 /* Call the corresponding callback to inform upper layer of End of Transfer */
6638 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6639 }
6640 else
6641 {
6642 /* Enable TC interrupts */
6643 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6644 }
6645 }
6646 }
6647 #endif /* HAL_MDMA_MODULE_ENABLED */
6648
6649 /**
6650 * @brief DMA I2C slave transmit process complete callback.
6651 * @param hdma DMA handle
6652 * @retval None
6653 */
I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef * hdma)6654 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
6655 {
6656 /* Derogation MISRAC2012-Rule-11.5 */
6657 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6658 uint32_t tmpoptions = hi2c->XferOptions;
6659
6660 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
6661 {
6662 /* Disable DMA Request */
6663 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6664
6665 /* Last Byte is Transmitted */
6666 /* Call I2C Slave Sequential complete process */
6667 I2C_ITSlaveSeqCplt(hi2c);
6668 }
6669 else
6670 {
6671 /* No specific action, Master fully manage the generation of STOP condition */
6672 /* Mean that this generation can arrive at any time, at the end or during DMA process */
6673 /* So STOP condition should be manage through Interrupt treatment */
6674 }
6675 }
6676 #ifdef HAL_MDMA_MODULE_ENABLED
6677
6678 /**
6679 * @brief MDMA I2C slave transmit process complete callback.
6680 * @param hmdma MDMA handle
6681 * @retval None
6682 */
I2C_MDMASlaveTransmitCplt(MDMA_HandleTypeDef * hmdma)6683 static void I2C_MDMASlaveTransmitCplt(MDMA_HandleTypeDef *hmdma)
6684 {
6685 /* Derogation MISRAC2012-Rule-11.5 */
6686 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((MDMA_HandleTypeDef *)hmdma)->Parent);
6687
6688 if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
6689 {
6690 /* Disable DMA Request */
6691 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6692
6693 /* Last Byte is Transmitted */
6694 /* Call I2C Slave Sequential complete process */
6695 I2C_ITSlaveSeqCplt(hi2c);
6696 }
6697 else
6698 {
6699 /* No specific action, Master fully manage the generation of STOP condition */
6700 /* Mean that this generation can arrive at any time, at the end or during MDMA process */
6701 /* So STOP condition should be manage through Interrupt treatment */
6702 }
6703 }
6704 #endif /* HAL_MDMA_MODULE_ENABLED */
6705
6706 /**
6707 * @brief DMA I2C master receive process complete callback.
6708 * @param hdma DMA handle
6709 * @retval None
6710 */
I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef * hdma)6711 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
6712 {
6713 /* Derogation MISRAC2012-Rule-11.5 */
6714 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6715
6716 /* Disable DMA Request */
6717 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6718
6719 /* If last transfer, enable STOP interrupt */
6720 if (hi2c->XferCount == 0U)
6721 {
6722 /* Enable STOP interrupt */
6723 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6724 }
6725 /* else prepare a new DMA transfer and enable TCReload interrupt */
6726 else
6727 {
6728 /* Update Buffer pointer */
6729 hi2c->pBuffPtr += hi2c->XferSize;
6730
6731 /* Set the XferSize to transfer */
6732 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6733 {
6734 hi2c->XferSize = MAX_NBYTE_SIZE;
6735 }
6736 else
6737 {
6738 hi2c->XferSize = hi2c->XferCount;
6739 }
6740
6741 /* Enable the DMA stream */
6742 if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
6743 hi2c->XferSize) != HAL_OK)
6744 {
6745 /* Call the corresponding callback to inform upper layer of End of Transfer */
6746 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6747 }
6748 else
6749 {
6750 /* Enable TC interrupts */
6751 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6752 }
6753 }
6754 }
6755 #ifdef HAL_MDMA_MODULE_ENABLED
6756
6757 /**
6758 * @brief MDMA I2C master receive process complete callback.
6759 * @param hmdma MDMA handle
6760 * @retval None
6761 */
I2C_MDMAMasterReceiveCplt(MDMA_HandleTypeDef * hmdma)6762 static void I2C_MDMAMasterReceiveCplt(MDMA_HandleTypeDef *hmdma)
6763 {
6764 /* Derogation MISRAC2012-Rule-11.5 */
6765 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((MDMA_HandleTypeDef *)hmdma)->Parent);
6766
6767 /* Disable MDMA Request */
6768 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6769
6770 /* If last transfer, enable STOP interrupt */
6771 if (hi2c->XferCount == 0U)
6772 {
6773 /* Enable STOP interrupt */
6774 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6775 }
6776 /* else prepare a new MDMA transfer and enable TCReload interrupt */
6777 else
6778 {
6779 /* Update Buffer pointer */
6780 hi2c->pBuffPtr += hi2c->XferSize;
6781
6782 /* Set the XferSize to transfer */
6783 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6784 {
6785 hi2c->XferSize = MAX_NBYTE_SIZE;
6786 }
6787 else
6788 {
6789 hi2c->XferSize = hi2c->XferCount;
6790 }
6791
6792 /* Enable the MDMA stream */
6793 if (HAL_MDMA_Start_IT(hi2c->hmdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
6794 hi2c->XferSize, 1) != HAL_OK)
6795 {
6796 /* Call the corresponding callback to inform upper layer of End of Transfer */
6797 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6798 }
6799 else
6800 {
6801 /* Enable TC interrupts */
6802 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6803 }
6804 }
6805 }
6806 #endif /* HAL_MDMA_MODULE_ENABLED */
6807
6808 /**
6809 * @brief DMA I2C slave receive process complete callback.
6810 * @param hdma DMA handle
6811 * @retval None
6812 */
I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef * hdma)6813 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
6814 {
6815 /* Derogation MISRAC2012-Rule-11.5 */
6816 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6817 uint32_t tmpoptions = hi2c->XferOptions;
6818
6819 if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
6820 (tmpoptions != I2C_NO_OPTION_FRAME))
6821 {
6822 /* Disable DMA Request */
6823 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6824
6825 /* Call I2C Slave Sequential complete process */
6826 I2C_ITSlaveSeqCplt(hi2c);
6827 }
6828 else
6829 {
6830 /* No specific action, Master fully manage the generation of STOP condition */
6831 /* Mean that this generation can arrive at any time, at the end or during DMA process */
6832 /* So STOP condition should be manage through Interrupt treatment */
6833 }
6834 }
6835 #ifdef HAL_MDMA_MODULE_ENABLED
6836
6837 /**
6838 * @brief MDMA I2C slave receive process complete callback.
6839 * @param hmdma MDMA handle
6840 * @retval None
6841 */
I2C_MDMASlaveReceiveCplt(MDMA_HandleTypeDef * hmdma)6842 static void I2C_MDMASlaveReceiveCplt(MDMA_HandleTypeDef *hmdma)
6843 {
6844 /* Derogation MISRAC2012-Rule-11.5 */
6845 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((MDMA_HandleTypeDef *)hmdma)->Parent);
6846
6847 if ((I2C_GET_MDMA_REMAIN_DATA_RX(hi2c) == 0U) && \
6848 (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
6849 {
6850 /* Disable DMA Request */
6851 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6852
6853 /* Call I2C Slave Sequential complete process */
6854 I2C_ITSlaveSeqCplt(hi2c);
6855 }
6856 else
6857 {
6858 /* No specific action, Master fully manage the generation of STOP condition */
6859 /* Mean that this generation can arrive at any time, at the end or during MDMA process */
6860 /* So STOP condition should be manage through Interrupt treatment */
6861 }
6862 }
6863 #endif /* HAL_MDMA_MODULE_ENABLED */
6864
6865 /**
6866 * @brief DMA I2C communication error callback.
6867 * @param hdma DMA handle
6868 * @retval None
6869 */
I2C_DMAError(DMA_HandleTypeDef * hdma)6870 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
6871 {
6872 uint32_t treatdmaerror = 0U;
6873 /* Derogation MISRAC2012-Rule-11.5 */
6874 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6875
6876 if (hi2c->hdmatx != NULL)
6877 {
6878 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
6879 {
6880 treatdmaerror = 1U;
6881 }
6882 }
6883
6884 if (hi2c->hdmarx != NULL)
6885 {
6886 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
6887 {
6888 treatdmaerror = 1U;
6889 }
6890 }
6891
6892 /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */
6893 if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U))
6894 {
6895 /* Disable Acknowledge */
6896 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6897
6898 /* Call the corresponding callback to inform upper layer of End of Transfer */
6899 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6900 }
6901 }
6902 #ifdef HAL_MDMA_MODULE_ENABLED
6903
6904 /**
6905 * @brief MDMA I2C communication error callback.
6906 * @param hmdma MDMA handle
6907 * @retval None
6908 */
I2C_MDMAError(MDMA_HandleTypeDef * hmdma)6909 static void I2C_MDMAError(MDMA_HandleTypeDef *hmdma)
6910 {
6911 /* Derogation MISRAC2012-Rule-11.5 */
6912 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((MDMA_HandleTypeDef *)hmdma)->Parent);
6913
6914 /* Disable Acknowledge */
6915 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6916
6917 /* Call the corresponding callback to inform upper layer of End of Transfer */
6918 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6919 }
6920 #endif /* HAL_MDMA_MODULE_ENABLED */
6921
6922 /**
6923 * @brief DMA I2C communication abort callback
6924 * (To be called at end of DMA Abort procedure).
6925 * @param hdma DMA handle.
6926 * @retval None
6927 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)6928 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
6929 {
6930 /* Derogation MISRAC2012-Rule-11.5 */
6931 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6932
6933 /* Reset AbortCpltCallback */
6934 if (hi2c->hdmatx != NULL)
6935 {
6936 hi2c->hdmatx->XferAbortCallback = NULL;
6937 }
6938 if (hi2c->hdmarx != NULL)
6939 {
6940 hi2c->hdmarx->XferAbortCallback = NULL;
6941 }
6942
6943 I2C_TreatErrorCallback(hi2c);
6944 }
6945 #ifdef HAL_MDMA_MODULE_ENABLED
6946
6947 /**
6948 * @brief MDMA I2C communication abort callback
6949 * (To be called at end of MDMA Abort procedure).
6950 * @param hmdma MDMA handle.
6951 * @retval None
6952 */
I2C_MDMAAbort(MDMA_HandleTypeDef * hmdma)6953 static void I2C_MDMAAbort(MDMA_HandleTypeDef *hmdma)
6954 {
6955 /* Derogation MISRAC2012-Rule-11.5 */
6956 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((MDMA_HandleTypeDef *)hmdma)->Parent);
6957
6958 /* Disable Acknowledge */
6959 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6960
6961 /* Reset AbortCpltCallback */
6962 if (hi2c->hmdmatx != NULL)
6963 {
6964 hi2c->hmdmatx->XferAbortCallback = NULL;
6965 }
6966 if (hi2c->hmdmarx != NULL)
6967 {
6968 hi2c->hmdmarx->XferAbortCallback = NULL;
6969 }
6970
6971 I2C_TreatErrorCallback(hi2c);
6972 }
6973 #endif /* HAL_MDMA_MODULE_ENABLED */
6974
6975 /**
6976 * @brief This function handles I2C Communication Timeout. It waits
6977 * until a flag is no longer in the specified status.
6978 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6979 * the configuration information for the specified I2C.
6980 * @param Flag Specifies the I2C flag to check.
6981 * @param Status The actual Flag status (SET or RESET).
6982 * @param Timeout Timeout duration
6983 * @param Tickstart Tick start value
6984 * @retval HAL status
6985 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)6986 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
6987 uint32_t Timeout, uint32_t Tickstart)
6988 {
6989 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
6990 {
6991 /* Check for the Timeout */
6992 if (Timeout != HAL_MAX_DELAY)
6993 {
6994 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6995 {
6996 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6997 hi2c->State = HAL_I2C_STATE_READY;
6998 hi2c->Mode = HAL_I2C_MODE_NONE;
6999
7000 /* Process Unlocked */
7001 __HAL_UNLOCK(hi2c);
7002 return HAL_ERROR;
7003 }
7004 }
7005 }
7006 return HAL_OK;
7007 }
7008
7009 /**
7010 * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
7011 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7012 * the configuration information for the specified I2C.
7013 * @param Timeout Timeout duration
7014 * @param Tickstart Tick start value
7015 * @retval HAL status
7016 */
I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7017 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7018 uint32_t Tickstart)
7019 {
7020 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
7021 {
7022 /* Check if an error is detected */
7023 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7024 {
7025 return HAL_ERROR;
7026 }
7027
7028 /* Check for the Timeout */
7029 if (Timeout != HAL_MAX_DELAY)
7030 {
7031 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7032 {
7033 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7034 hi2c->State = HAL_I2C_STATE_READY;
7035 hi2c->Mode = HAL_I2C_MODE_NONE;
7036
7037 /* Process Unlocked */
7038 __HAL_UNLOCK(hi2c);
7039
7040 return HAL_ERROR;
7041 }
7042 }
7043 }
7044 return HAL_OK;
7045 }
7046
7047 /**
7048 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
7049 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7050 * the configuration information for the specified I2C.
7051 * @param Timeout Timeout duration
7052 * @param Tickstart Tick start value
7053 * @retval HAL status
7054 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7055 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7056 uint32_t Tickstart)
7057 {
7058 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7059 {
7060 /* Check if an error is detected */
7061 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7062 {
7063 return HAL_ERROR;
7064 }
7065
7066 /* Check for the Timeout */
7067 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7068 {
7069 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7070 hi2c->State = HAL_I2C_STATE_READY;
7071 hi2c->Mode = HAL_I2C_MODE_NONE;
7072
7073 /* Process Unlocked */
7074 __HAL_UNLOCK(hi2c);
7075
7076 return HAL_ERROR;
7077 }
7078 }
7079 return HAL_OK;
7080 }
7081
7082 /**
7083 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
7084 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7085 * the configuration information for the specified I2C.
7086 * @param Timeout Timeout duration
7087 * @param Tickstart Tick start value
7088 * @retval HAL status
7089 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7090 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7091 uint32_t Tickstart)
7092 {
7093 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
7094 {
7095 /* Check if an error is detected */
7096 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7097 {
7098 return HAL_ERROR;
7099 }
7100
7101 /* Check if a STOPF is detected */
7102 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
7103 {
7104 /* Check if an RXNE is pending */
7105 /* Store Last receive data if any */
7106 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
7107 {
7108 /* Return HAL_OK */
7109 /* The Reading of data from RXDR will be done in caller function */
7110 return HAL_OK;
7111 }
7112 else
7113 {
7114 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7115 {
7116 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7117 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
7118 }
7119 else
7120 {
7121 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
7122 }
7123
7124 /* Clear STOP Flag */
7125 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7126
7127 /* Clear Configuration Register 2 */
7128 I2C_RESET_CR2(hi2c);
7129
7130 hi2c->State = HAL_I2C_STATE_READY;
7131 hi2c->Mode = HAL_I2C_MODE_NONE;
7132
7133 /* Process Unlocked */
7134 __HAL_UNLOCK(hi2c);
7135
7136 return HAL_ERROR;
7137 }
7138 }
7139
7140 /* Check for the Timeout */
7141 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7142 {
7143 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7144 hi2c->State = HAL_I2C_STATE_READY;
7145
7146 /* Process Unlocked */
7147 __HAL_UNLOCK(hi2c);
7148
7149 return HAL_ERROR;
7150 }
7151 }
7152 return HAL_OK;
7153 }
7154
7155 /**
7156 * @brief This function handles errors detection during an I2C Communication.
7157 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7158 * the configuration information for the specified I2C.
7159 * @param Timeout Timeout duration
7160 * @param Tickstart Tick start value
7161 * @retval HAL status
7162 */
I2C_IsErrorOccurred(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7163 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7164 {
7165 HAL_StatusTypeDef status = HAL_OK;
7166 uint32_t itflag = hi2c->Instance->ISR;
7167 uint32_t error_code = 0;
7168 uint32_t tickstart = Tickstart;
7169 uint32_t tmp1;
7170 HAL_I2C_ModeTypeDef tmp2;
7171
7172 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
7173 {
7174 /* Clear NACKF Flag */
7175 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7176
7177 /* Wait until STOP Flag is set or timeout occurred */
7178 /* AutoEnd should be initiate after AF */
7179 while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
7180 {
7181 /* Check for the Timeout */
7182 if (Timeout != HAL_MAX_DELAY)
7183 {
7184 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7185 {
7186 tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
7187 tmp2 = hi2c->Mode;
7188
7189 /* In case of I2C still busy, try to regenerate a STOP manually */
7190 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
7191 (tmp1 != I2C_CR2_STOP) && \
7192 (tmp2 != HAL_I2C_MODE_SLAVE))
7193 {
7194 /* Generate Stop */
7195 hi2c->Instance->CR2 |= I2C_CR2_STOP;
7196
7197 /* Update Tick with new reference */
7198 tickstart = HAL_GetTick();
7199 }
7200
7201 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7202 {
7203 /* Check for the Timeout */
7204 if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
7205 {
7206 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7207 hi2c->State = HAL_I2C_STATE_READY;
7208 hi2c->Mode = HAL_I2C_MODE_NONE;
7209
7210 /* Process Unlocked */
7211 __HAL_UNLOCK(hi2c);
7212
7213 status = HAL_ERROR;
7214 }
7215 }
7216 }
7217 }
7218 }
7219
7220 /* In case STOP Flag is detected, clear it */
7221 if (status == HAL_OK)
7222 {
7223 /* Clear STOP Flag */
7224 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7225 }
7226
7227 error_code |= HAL_I2C_ERROR_AF;
7228
7229 status = HAL_ERROR;
7230 }
7231
7232 /* Refresh Content of Status register */
7233 itflag = hi2c->Instance->ISR;
7234
7235 /* Then verify if an additional errors occurs */
7236 /* Check if a Bus error occurred */
7237 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
7238 {
7239 error_code |= HAL_I2C_ERROR_BERR;
7240
7241 /* Clear BERR flag */
7242 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
7243
7244 status = HAL_ERROR;
7245 }
7246
7247 /* Check if an Over-Run/Under-Run error occurred */
7248 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
7249 {
7250 error_code |= HAL_I2C_ERROR_OVR;
7251
7252 /* Clear OVR flag */
7253 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
7254
7255 status = HAL_ERROR;
7256 }
7257
7258 /* Check if an Arbitration Loss error occurred */
7259 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
7260 {
7261 error_code |= HAL_I2C_ERROR_ARLO;
7262
7263 /* Clear ARLO flag */
7264 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
7265
7266 status = HAL_ERROR;
7267 }
7268
7269 if (status != HAL_OK)
7270 {
7271 /* Flush TX register */
7272 I2C_Flush_TXDR(hi2c);
7273
7274 /* Clear Configuration Register 2 */
7275 I2C_RESET_CR2(hi2c);
7276
7277 hi2c->ErrorCode |= error_code;
7278 hi2c->State = HAL_I2C_STATE_READY;
7279 hi2c->Mode = HAL_I2C_MODE_NONE;
7280
7281 /* Process Unlocked */
7282 __HAL_UNLOCK(hi2c);
7283 }
7284
7285 return status;
7286 }
7287
7288 /**
7289 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
7290 * @param hi2c I2C handle.
7291 * @param DevAddress Specifies the slave address to be programmed.
7292 * @param Size Specifies the number of bytes to be programmed.
7293 * This parameter must be a value between 0 and 255.
7294 * @param Mode New state of the I2C START condition generation.
7295 * This parameter can be one of the following values:
7296 * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
7297 * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
7298 * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
7299 * @param Request New state of the I2C START condition generation.
7300 * This parameter can be one of the following values:
7301 * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
7302 * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
7303 * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
7304 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
7305 * @retval None
7306 */
I2C_TransferConfig(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t Size,uint32_t Mode,uint32_t Request)7307 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
7308 uint32_t Request)
7309 {
7310 /* Check the parameters */
7311 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
7312 assert_param(IS_TRANSFER_MODE(Mode));
7313 assert_param(IS_TRANSFER_REQUEST(Request));
7314
7315 /* Declaration of tmp to prevent undefined behavior of volatile usage */
7316 uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
7317 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
7318 (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
7319
7320 /* update CR2 register */
7321 MODIFY_REG(hi2c->Instance->CR2, \
7322 ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
7323 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
7324 I2C_CR2_START | I2C_CR2_STOP)), tmp);
7325 }
7326
7327 /**
7328 * @brief Manage the enabling of Interrupts.
7329 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7330 * the configuration information for the specified I2C.
7331 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7332 * @retval None
7333 */
I2C_Enable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7334 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7335 {
7336 uint32_t tmpisr = 0U;
7337
7338 if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
7339 (hi2c->XferISR == I2C_Slave_ISR_DMA))
7340 {
7341 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7342 {
7343 /* Enable ERR, STOP, NACK and ADDR interrupts */
7344 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7345 }
7346
7347 if (InterruptRequest == I2C_XFER_ERROR_IT)
7348 {
7349 /* Enable ERR and NACK interrupts */
7350 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7351 }
7352
7353 if (InterruptRequest == I2C_XFER_CPLT_IT)
7354 {
7355 /* Enable STOP interrupts */
7356 tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
7357 }
7358
7359 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7360 {
7361 /* Enable TC interrupts */
7362 tmpisr |= I2C_IT_TCI;
7363 }
7364 }
7365 else
7366 {
7367 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7368 {
7369 /* Enable ERR, STOP, NACK, and ADDR interrupts */
7370 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7371 }
7372
7373 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7374 {
7375 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7376 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7377 }
7378
7379 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7380 {
7381 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7382 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7383 }
7384
7385 if (InterruptRequest == I2C_XFER_CPLT_IT)
7386 {
7387 /* Enable STOP interrupts */
7388 tmpisr |= I2C_IT_STOPI;
7389 }
7390 }
7391
7392 /* Enable interrupts only at the end */
7393 /* to avoid the risk of I2C interrupt handle execution before */
7394 /* all interrupts requested done */
7395 __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
7396 }
7397
7398 /**
7399 * @brief Manage the disabling of Interrupts.
7400 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7401 * the configuration information for the specified I2C.
7402 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7403 * @retval None
7404 */
I2C_Disable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7405 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7406 {
7407 uint32_t tmpisr = 0U;
7408
7409 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7410 {
7411 /* Disable TC and TXI interrupts */
7412 tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
7413
7414 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7415 {
7416 /* Disable NACK and STOP interrupts */
7417 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7418 }
7419 }
7420
7421 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7422 {
7423 /* Disable TC and RXI interrupts */
7424 tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
7425
7426 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7427 {
7428 /* Disable NACK and STOP interrupts */
7429 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7430 }
7431 }
7432
7433 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7434 {
7435 /* Disable ADDR, NACK and STOP interrupts */
7436 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7437 }
7438
7439 if (InterruptRequest == I2C_XFER_ERROR_IT)
7440 {
7441 /* Enable ERR and NACK interrupts */
7442 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7443 }
7444
7445 if (InterruptRequest == I2C_XFER_CPLT_IT)
7446 {
7447 /* Enable STOP interrupts */
7448 tmpisr |= I2C_IT_STOPI;
7449 }
7450
7451 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7452 {
7453 /* Enable TC interrupts */
7454 tmpisr |= I2C_IT_TCI;
7455 }
7456
7457 /* Disable interrupts only at the end */
7458 /* to avoid a breaking situation like at "t" time */
7459 /* all disable interrupts request are not done */
7460 __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
7461 }
7462
7463 /**
7464 * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
7465 * @param hi2c I2C handle.
7466 * @retval None
7467 */
I2C_ConvertOtherXferOptions(I2C_HandleTypeDef * hi2c)7468 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7469 {
7470 /* if user set XferOptions to I2C_OTHER_FRAME */
7471 /* it request implicitly to generate a restart condition */
7472 /* set XferOptions to I2C_FIRST_FRAME */
7473 if (hi2c->XferOptions == I2C_OTHER_FRAME)
7474 {
7475 hi2c->XferOptions = I2C_FIRST_FRAME;
7476 }
7477 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7478 /* it request implicitly to generate a restart condition */
7479 /* then generate a stop condition at the end of transfer */
7480 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7481 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7482 {
7483 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7484 }
7485 else
7486 {
7487 /* Nothing to do */
7488 }
7489 }
7490
7491 /**
7492 * @}
7493 */
7494
7495 #endif /* HAL_I2C_MODULE_ENABLED */
7496 /**
7497 * @}
7498 */
7499
7500 /**
7501 * @}
7502 */
7503
