1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_hal_cortex.c
4 * @author MCD Application Team
5 * @brief CORTEX HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the CORTEX:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2019 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 @verbatim
23 ==============================================================================
24 ##### How to use this driver #####
25 ==============================================================================
26
27 [..]
28 *** How to configure Interrupts using CORTEX HAL driver ***
29 ===========================================================
30 [..]
31 This section provides functions allowing to configure the NVIC interrupts (IRQ).
32 The Cortex-M exceptions are managed by CMSIS functions.
33
34 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
35 function according to the following table.
36 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
37 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
38 (#) please refer to programming manual for details in how to configure priority.
39
40 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
41 The pending IRQ priority will be managed only by the sub priority.
42
43 -@- IRQ priority order (sorted by highest to lowest priority):
44 (+@) Lowest preemption priority
45 (+@) Lowest sub priority
46 (+@) Lowest hardware priority (IRQ number)
47
48 [..]
49 *** How to configure Systick using CORTEX HAL driver ***
50 ========================================================
51 [..]
52 Setup SysTick Timer for time base.
53
54 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
55 is a CMSIS function that:
56 (++) Configures the SysTick Reload register with value passed as function parameter.
57 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
58 (++) Resets the SysTick Counter register.
59 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
60 (++) Enables the SysTick Interrupt.
61 (++) Starts the SysTick Counter.
62
63 (+) You can change the SysTick IRQ priority by calling the
64 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
65 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
66
67 (+) To adjust the SysTick time base, use the following formula:
68
69 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
70 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
71 (++) Reload Value should not exceed 0xFFFFFF
72
73 @endverbatim
74 ******************************************************************************
75 */
76
77 /* Includes ------------------------------------------------------------------*/
78 #include "stm32mp1xx_hal.h"
79
80 /** @addtogroup STM32MP1xx_HAL_Driver
81 * @{
82 */
83
84 /** @defgroup CORTEX CORTEX
85 * @brief CORTEX HAL module driver
86 * @{
87 */
88
89 #ifdef HAL_CORTEX_MODULE_ENABLED
90
91 /* Private types -------------------------------------------------------------*/
92 /* Private variables ---------------------------------------------------------*/
93 /* Private constants ---------------------------------------------------------*/
94 /* Private macros ------------------------------------------------------------*/
95 /* Private functions ---------------------------------------------------------*/
96 /* Exported functions --------------------------------------------------------*/
97
98 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
99 * @{
100 */
101
102
103 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
104 * @brief Initialization and Configuration functions
105 *
106 @verbatim
107 ==============================================================================
108 ##### Initialization and de-initialization functions #####
109 ==============================================================================
110 [..]
111 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
112 Systick functionalities
113
114 @endverbatim
115 * @{
116 */
117
118
119 /**
120 * @brief Sets the priority grouping field (preemption priority and subpriority)
121 * using the required unlock sequence.
122 * @param PriorityGroup: The priority grouping bits length.
123 * This parameter can be one of the following values:
124 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
125 * 4 bits for subpriority
126 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
127 * 3 bits for subpriority
128 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
129 * 2 bits for subpriority
130 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
131 * 1 bits for subpriority
132 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
133 * 0 bits for subpriority
134 * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
135 * The pending IRQ priority will be managed only by the subpriority.
136 * @retval None
137 */
HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)138 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
139 {
140 /* Check the parameters */
141 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
142
143 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
144 NVIC_SetPriorityGrouping(PriorityGroup);
145 }
146
147 /**
148 * @brief Sets the priority of an interrupt.
149 * @param IRQn: External interrupt number.
150 * This parameter can be an enumerator of IRQn_Type enumeration
151 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32mp1xxxx.h))
152 * @param PreemptPriority: The preemption priority for the IRQn channel.
153 * This parameter can be a value between 0 and 15
154 * A lower priority value indicates a higher priority
155 * @param SubPriority: the subpriority level for the IRQ channel.
156 * This parameter can be a value between 0 and 15
157 * A lower priority value indicates a higher priority.
158 * @retval None
159 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)160 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
161 {
162 uint32_t prioritygroup = 0x00;
163
164 /* Check the parameters */
165 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
166 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
167
168 prioritygroup = NVIC_GetPriorityGrouping();
169
170 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
171 }
172
173 /**
174 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
175 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
176 * function should be called before.
177 * @param IRQn External interrupt number.
178 * This parameter can be an enumerator of IRQn_Type enumeration
179 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32mp1xxxx.h))
180 * @retval None
181 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)182 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
183 {
184 /* Check the parameters */
185 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
186
187 /* Enable interrupt */
188 NVIC_EnableIRQ(IRQn);
189 }
190
191 /**
192 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
193 * @param IRQn External interrupt number.
194 * This parameter can be an enumerator of IRQn_Type enumeration
195 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32mp1xxxx.h))
196 * @retval None
197 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)198 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
199 {
200 /* Check the parameters */
201 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
202
203 /* Disable interrupt */
204 NVIC_DisableIRQ(IRQn);
205 }
206
207 /**
208 * @brief Initiates a system reset request to reset the MCU.
209 * @retval None
210 */
HAL_NVIC_SystemReset(void)211 void HAL_NVIC_SystemReset(void)
212 {
213 /* System Reset */
214 NVIC_SystemReset();
215 }
216
217 /**
218 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
219 * Counter is in free running mode to generate periodic interrupts.
220 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
221 * @retval status: - 0 Function succeeded.
222 * - 1 Function failed.
223 */
HAL_SYSTICK_Config(uint32_t TicksNumb)224 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
225 {
226 return SysTick_Config(TicksNumb);
227 }
228 /**
229 * @}
230 */
231
232 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
233 * @brief Cortex control functions
234 *
235 @verbatim
236 ==============================================================================
237 ##### Peripheral Control functions #####
238 ==============================================================================
239 [..]
240 This subsection provides a set of functions allowing to control the CORTEX
241 (NVIC, SYSTICK, MPU) functionalities.
242
243
244 @endverbatim
245 * @{
246 */
247 #if (__MPU_PRESENT == 1)
248 /**
249 * @brief Initializes and configures the Region and the memory to be protected.
250 * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
251 * the initialization and configuration information.
252 * @retval None
253 */
HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef * MPU_Init)254 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
255 {
256 /* Check the parameters */
257 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
258 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
259
260 /* Set the Region number */
261 MPU->RNR = MPU_Init->Number;
262
263 if ((MPU_Init->Enable) != RESET)
264 {
265 /* Check the parameters */
266 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
267 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
268 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
269 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
270 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
271 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
272 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
273 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
274
275 MPU->RBAR = MPU_Init->BaseAddress;
276 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
277 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
278 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
279 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
280 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
281 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
282 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
283 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
284 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
285 }
286 else
287 {
288 MPU->RBAR = 0x00;
289 MPU->RASR = 0x00;
290 }
291 }
292 #endif /* __MPU_PRESENT */
293
294 /**
295 * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
296 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
297 */
HAL_NVIC_GetPriorityGrouping(void)298 uint32_t HAL_NVIC_GetPriorityGrouping(void)
299 {
300 /* Get the PRIGROUP[10:8] field value */
301 return NVIC_GetPriorityGrouping();
302 }
303
304 /**
305 * @brief Gets the priority of an interrupt.
306 * @param IRQn: External interrupt number.
307 * This parameter can be an enumerator of IRQn_Type enumeration
308 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32mp1xxxx.h))
309 * @param PriorityGroup: the priority grouping bits length.
310 * This parameter can be one of the following values:
311 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
312 * 4 bits for subpriority
313 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
314 * 3 bits for subpriority
315 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
316 * 2 bits for subpriority
317 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
318 * 1 bits for subpriority
319 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
320 * 0 bits for subpriority
321 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
322 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
323 * @retval None
324 */
HAL_NVIC_GetPriority(IRQn_Type IRQn,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)325 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
326 {
327 /* Check the parameters */
328 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
329 /* Get priority for Cortex-M system or device specific interrupts */
330 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
331 }
332
333 /**
334 * @brief Sets Pending bit of an external interrupt.
335 * @param IRQn External interrupt number
336 * This parameter can be an enumerator of IRQn_Type enumeration
337 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32mp1xxxx.h))
338 * @retval None
339 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)340 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
341 {
342 /* Check the parameters */
343 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
344
345 /* Set interrupt pending */
346 NVIC_SetPendingIRQ(IRQn);
347 }
348
349 /**
350 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
351 * and returns the pending bit for the specified interrupt).
352 * @param IRQn External interrupt number.
353 * This parameter can be an enumerator of IRQn_Type enumeration
354 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32mp1xxxx.h))
355 * @retval status: - 0 Interrupt status is not pending.
356 * - 1 Interrupt status is pending.
357 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)358 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
359 {
360 /* Check the parameters */
361 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
362
363 /* Return 1 if pending else 0 */
364 return NVIC_GetPendingIRQ(IRQn);
365 }
366
367 /**
368 * @brief Clears the pending bit of an external interrupt.
369 * @param IRQn External interrupt number.
370 * This parameter can be an enumerator of IRQn_Type enumeration
371 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32mp1xxxx.h))
372 * @retval None
373 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)374 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
375 {
376 /* Check the parameters */
377 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
378
379 /* Clear pending interrupt */
380 NVIC_ClearPendingIRQ(IRQn);
381 }
382
383 /**
384 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
385 * @param IRQn External interrupt number
386 * This parameter can be an enumerator of IRQn_Type enumeration
387 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32mp1xxxx.h))
388 * @retval status: - 0 Interrupt status is not pending.
389 * - 1 Interrupt status is pending.
390 */
HAL_NVIC_GetActive(IRQn_Type IRQn)391 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
392 {
393 /* Check the parameters */
394 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
395
396 /* Return 1 if active else 0 */
397 return NVIC_GetActive(IRQn);
398 }
399
400
401 /**
402 * @brief This function handles SYSTICK interrupt request.
403 * @retval None
404 */
HAL_SYSTICK_IRQHandler(void)405 void HAL_SYSTICK_IRQHandler(void)
406 {
407 HAL_SYSTICK_Callback();
408 }
409
410 /**
411 * @brief SYSTICK callback.
412 * @retval None
413 */
HAL_SYSTICK_Callback(void)414 __weak void HAL_SYSTICK_Callback(void)
415 {
416 /* NOTE : This function Should not be modified, when the callback is needed,
417 the HAL_SYSTICK_Callback could be implemented in the user file
418 */
419 }
420
421
422 /**
423 * @}
424 */
425
426 /**
427 * @}
428 */
429
430 #endif /* HAL_CORTEX_MODULE_ENABLED */
431 /**
432 * @}
433 */
434
435 /**
436 * @}
437 */
438
439
