1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_ll_utils.h
4 * @author MCD Application Team
5 * @brief Header file of UTILS LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL UTILS driver contains a set of generic APIs that can be
12 used by user:
13 (+) Device electronic signature
14 (+) Timing functions
15 (+) PLL configuration functions
16
17 @endverbatim
18 ******************************************************************************
19 * @attention
20 *
21 * Copyright (c) 2019 STMicroelectronics.
22 * All rights reserved.
23 *
24 * This software is licensed under terms that can be found in the LICENSE file
25 * in the root directory of this software component.
26 * If no LICENSE file comes with this software, it is provided AS-IS.
27 *
28 ******************************************************************************
29 */
30
31 /* Define to prevent recursive inclusion -------------------------------------*/
32 #ifndef STM32MP1xx_LL_UTILS_H
33 #define STM32MP1xx_LL_UTILS_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32mp1xx.h"
41
42 /** @addtogroup STM32MP1xx_LL_Driver
43 * @{
44 */
45
46 /** @defgroup UTILS_LL UTILS
47 * @{
48 */
49
50 /* Private types -------------------------------------------------------------*/
51 /* Private variables ---------------------------------------------------------*/
52
53 /* Private constants ---------------------------------------------------------*/
54 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
55 * @{
56 */
57
58 /* Max delay can be used in LL_mDelay */
59 #define LL_MAX_DELAY 0xFFFFFFFFU
60
61 /**
62 * @brief Unique device ID register base address
63 */
64 #define UID_BASE_ADDRESS UID_BASE
65
66 /**
67 * @brief Package data register base address
68 */
69 #define PACKAGE_BASE_ADDRESS PACKAGE_BASE
70
71 /**
72 * @}
73 */
74
75 /* Private macros ------------------------------------------------------------*/
76 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
77 * @{
78 */
79 /**
80 * @}
81 */
82 /* Exported types ------------------------------------------------------------*/
83 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
84 * @{
85 */
86 /**
87 * @brief UTILS PLL structure definition
88 */
89 typedef struct
90 {
91 uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
92 This parameter can be a value between 1 and 64 */
93
94 uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
95 This parameter must be a number between 4 and 512 */
96
97 uint32_t PLLP; /*!< Division for the P divider
98 This parameter can be a value between 1 and 128
99
100 This feature can be modified afterwards using unitary
101 functions @ref LL_RCC_PLL1_SetP, @ref LL_RCC_PLL2_SetP,
102 @ref LL_RCC_PLL3_SetP and @ref LL_RCC_PLL4_SetP */
103
104 uint32_t PLLQ; /*!< Division for the Q divider
105 This parameter can be a value between 1 and 128
106
107 This feature can be modified afterwards using unitary
108 functions @ref LL_RCC_PLL2_SetQ, @ref LL_RCC_PLL3_SetQ
109 and @ref LL_RCC_PLL4_SetQ*/
110
111 uint32_t PLLR; /*!< Division for the R divider
112 This parameter can be a value between 1 and 128
113
114 This feature can be modified afterwards using unitary
115 functions @ref LL_RCC_PLL2_SetR, @ref LL_RCC_PLL3_SetR
116 and @ref LL_RCC_PLL4_SetR */
117
118 uint32_t PLLFRACV; /*!< Fractional part of the multiplication factor for PLLx VCO.
119 This parameter can be a value between 0 and 8191 (0x1FFF) */
120 } LL_UTILS_PLLTypeDef;
121
122 /**
123 * @brief UTILS PLLs system structure definition
124 */
125 typedef struct
126 {
127 LL_UTILS_PLLTypeDef PLL1; /*!< PLL1 structure parameters */
128
129 LL_UTILS_PLLTypeDef PLL2; /*!< PLL2 structure parameters */
130
131 LL_UTILS_PLLTypeDef PLL3; /*!< PLL3 structure parameters */
132
133 LL_UTILS_PLLTypeDef PLL4; /*!< PLL4 structure parameters */
134
135 } LL_UTILS_PLLsInitTypeDef;
136
137 /**
138 * @brief UTILS System, AHB and APB buses clock configuration structure definition
139 */
140 typedef struct
141 {
142 uint32_t MPUDivider; /*!< The MPU divider. This clock is derived from the CK_PLL1_P clock.
143 This parameter can be a value of @ref RCC_LL_EC_MPU_DIV
144
145 This feature can be modified afterwards using unitary function
146 @ref LL_RCC_SetMPUPrescaler(). */
147
148 uint32_t AXIDivider; /*!< The AXI divider. This clock is derived from the AXISSRC clock.
149 This parameter can be a value of @ref RCC_LL_EC_AXI_DIV
150
151 This feature can be modified afterwards using unitary function
152 @ref LL_RCC_SetACLKPrescaler(). */
153
154 uint32_t MCUDivider; /*!< The MCU divider. This clock is derived from the MCUSSRC muxer.
155 This parameter can be a value of @ref RCC_LL_EC_MCU_DIV
156
157 This feature can be modified afterwards using unitary function
158 @ref LL_RCC_SetMLHCLKPrescaler(). */
159
160 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the MCU divider.
161 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
162
163 This feature can be modified afterwards using unitary function
164 @ref LL_RCC_SetAPB1Prescaler(). */
165
166 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the MCU divider.
167 This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
168
169 This feature can be modified afterwards using unitary function
170 @ref LL_RCC_SetAPB2Prescaler(). */
171
172 uint32_t APB3CLKDivider; /*!< The APB2 clock (PCLK3) divider. This clock is derived from the MCU divider.
173 This parameter can be a value of @ref RCC_LL_EC_APB3_DIV
174
175 This feature can be modified afterwards using unitary function
176 @ref LL_RCC_SetAPB3Prescaler(). */
177
178 uint32_t APB4CLKDivider; /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AXIDIV divider.
179 This parameter can be a value of @ref RCC_LL_EC_APB4_DIV
180
181 This feature can be modified afterwards using unitary function
182 @ref LL_RCC_SetAPB4Prescaler(). */
183
184 uint32_t APB5CLKDivider; /*!< The APB5 clock (PCLK5) divider. This clock is derived from the AXIDIV divider.
185 This parameter can be a value of @ref RCC_LL_EC_APB5_DIV
186
187 This feature can be modified afterwards using unitary function
188 @ref LL_RCC_SetAPB5Prescaler(). */
189 } LL_UTILS_ClkInitTypeDef;
190
191 /**
192 * @}
193 */
194
195 /* Exported constants --------------------------------------------------------*/
196 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
197 * @{
198 */
199
200 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
201 * @{
202 */
203 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is disabled */
204 #define LL_UTILS_HSEBYPASS_ON RCC_OCENSETR_HSEBYP /*!< HSE Bypass is enabled */
205 #define LL_UTILS_HSEBYPASSDIG_ON RCC_OCENSETR_DIGBYP /*!< HSE Bypass Digital is enabled */
206
207 /**
208 * @}
209 */
210
211 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
212 * @{
213 */
214 #define LL_UTILS_PACKAGETYPE_TFBGA257 1U /*!< TFBGA257 package type */
215 #define LL_UTILS_PACKAGETYPE_TFBGA361 2U /*!< TFBGA361 package type */
216 #define LL_UTILS_PACKAGETYPE_LFBGA354 3U /*!< LFBGA354 package type */
217 #define LL_UTILS_PACKAGETYPE_LFBGA448 4U /*!< LFBGA448 package type */
218
219 /**
220 * @}
221 */
222
223 /** @defgroup UTILS_EC_RPN DEVICE PART NUMBER
224 * @{
225 */
226 #define LL_UTILS_RPN_STM32MP157Cxx 0U /*!< STM32MP157Cxx Part Number */
227 #define LL_UTILS_RPN_STM32MP157Axx 1U /*!< STM32MP157Axx Part Number */
228 #define LL_UTILS_RPN_STM32MP157Fxx 128U /*!< STM32MP157Fxx Part Number */
229 #define LL_UTILS_RPN_STM32MP157Dxx 129U /*!< STM32MP157Dxx Part Number */
230
231 /**
232 * @}
233 */
234
235 /** @defgroup UTILS_EC_DV DEVICE ID VERSION
236 * @{
237 */
238 #define LL_UTILS_DV_ID_STM32MP15xxx 0x500U /*!< STM32MP15xxx Device ID */
239
240 /**
241 * @}
242 */
243
244 /**
245 * @}
246 */
247
248 /* Exported macro ------------------------------------------------------------*/
249
250 /* Exported functions --------------------------------------------------------*/
251 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
252 * @{
253 */
254
255 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
256 * @{
257 */
258
259 /**
260 * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
261 * @retval UID[31:0]
262 */
LL_GetUID_Word0(void)263 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
264 {
265 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
266 }
267
268 /**
269 * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
270 * @retval UID[63:32]
271 */
LL_GetUID_Word1(void)272 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
273 {
274 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
275 }
276
277 /**
278 * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
279 * @retval UID[95:64]
280 */
LL_GetUID_Word2(void)281 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
282 {
283 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
284 }
285
286 /**
287 * @brief Get Package type
288 * @retval Returned value can be one of the following values:
289 * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA257
290 * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA361
291 * @arg @ref LL_UTILS_PACKAGETYPE_LFBGA354
292 * @arg @ref LL_UTILS_PACKAGETYPE_LFBGA448
293 */
LL_GetPackageType(void)294 __STATIC_INLINE uint32_t LL_GetPackageType(void)
295 {
296 return (uint32_t)(READ_BIT(*(uint32_t *)PACKAGE_BASE_ADDRESS, PKG_ID) >> PKG_ID_Pos);
297 }
298
299 /**
300 * @brief Get Device Part Number
301 * @retval Returned value can be one of the following values:
302 * @arg @ref LL_UTILS_RPN_STM32MP157Cxx
303 * @arg @ref LL_UTILS_RPN_STM32MP157Axx
304 * @arg @ref LL_UTILS_RPN_STM32MP157Fxx
305 * @arg @ref LL_UTILS_RPN_STM32MP157Dxx
306 */
LL_GetDevicePartNumber(void)307 __STATIC_INLINE uint32_t LL_GetDevicePartNumber(void)
308 {
309 return (uint32_t)(READ_BIT(*(uint32_t *)RPN_BASE, RPN_ID) >> RPN_ID_Pos);
310 }
311
312 /**
313 * @brief Get Device Version ID
314 * @retval Returned value can be one of the following values:
315 * @arg @ref LL_UTILS_DV_ID_STM32MP15xxx
316 */
LL_GetDeviceVersionDevID(void)317 __STATIC_INLINE uint32_t LL_GetDeviceVersionDevID(void)
318 {
319 return (uint32_t)(READ_BIT(*(uint32_t *)DV_BASE, DV_DEV_ID) >> DV_DEV_ID_Pos);
320 }
321
322 /**
323 * @brief Get Device Version Rev ID
324 * @retval Returned value is Silicon version
325 */
LL_GetDeviceVersionRevID(void)326 __STATIC_INLINE uint32_t LL_GetDeviceVersionRevID(void)
327 {
328 return (uint32_t)(READ_BIT(*(uint32_t *)DV_BASE, DV_REV_ID) >> DV_REV_ID_Pos);
329 }
330
331 /**
332 * @}
333 */
334
335 /** @defgroup UTILS_LL_EF_DELAY DELAY
336 * @{
337 */
338 #if defined(CORE_CM4)
339 /**
340 * @brief This function configures the Cortex-M SysTick source of the time base.
341 * @param CPU_Frequency Core frequency in Hz. It can be calculated thanks to RCC
342 * helper macro or function @ref LL_RCC_GetSystemClocksFreq
343 * - Use MCU_Frequency structure element returned by function above
344 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
345 * configuration by calling this function, for a delay use rather osDelay RTOS service.
346 * @param Ticks Number of ticks
347 * @retval None
348 */
LL_InitTick(uint32_t CPU_Frequency,uint32_t Ticks)349 __STATIC_INLINE void LL_InitTick(uint32_t CPU_Frequency, uint32_t Ticks)
350 {
351 /* Configure the SysTick to have interrupt in 1ms time base */
352 SysTick->LOAD = (uint32_t)((CPU_Frequency / Ticks) - 1UL); /* set reload register */
353 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
354 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
355 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
356 }
357
358 void LL_Init1msTick(uint32_t CPU_Frequency);
359 void LL_mDelay(uint32_t Delay);
360 #endif /* CORE_CM4 */
361
362 /**
363 * @}
364 */
365
366 /** @defgroup UTILS_EF_SYSTEM SYSTEM
367 * @{
368 */
369
370 void LL_SetSystemCoreClock(uint32_t CPU_Frequency);
371 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,
372 uint32_t HSEBypass,
373 LL_UTILS_PLLsInitTypeDef *UTILS_PLLInitStruct,
374 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
375
376 /**
377 * @}
378 */
379
380 /**
381 * @}
382 */
383
384 /**
385 * @}
386 */
387
388 /**
389 * @}
390 */
391
392 #ifdef __cplusplus
393 }
394 #endif
395
396 #endif /* STM32MP1xx_LL_UTILS_H */
397
398
