1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32MP1xx_LL_TIM_H
21 #define __STM32MP1xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32mp1xx.h"
29
30 /** @addtogroup STM32MP1xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined(TIM12) | defined (TIM13) | defined (TIM14) | defined (TIM15) || defined (TIM16) || defined (TIM17)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x3CU, /* 7: TIMx_CH5 */
55 0x3CU /* 8: TIMx_CH6 */
56 };
57
58 static const uint8_t SHIFT_TAB_OCxx[] =
59 {
60 0U, /* 0: OC1M, OC1FE, OC1PE */
61 0U, /* 1: - NA */
62 8U, /* 2: OC2M, OC2FE, OC2PE */
63 0U, /* 3: - NA */
64 0U, /* 4: OC3M, OC3FE, OC3PE */
65 0U, /* 5: - NA */
66 8U, /* 6: OC4M, OC4FE, OC4PE */
67 0U, /* 7: OC5M, OC5FE, OC5PE */
68 8U /* 8: OC6M, OC6FE, OC6PE */
69 };
70
71 static const uint8_t SHIFT_TAB_ICxx[] =
72 {
73 0U, /* 0: CC1S, IC1PSC, IC1F */
74 0U, /* 1: - NA */
75 8U, /* 2: CC2S, IC2PSC, IC2F */
76 0U, /* 3: - NA */
77 0U, /* 4: CC3S, IC3PSC, IC3F */
78 0U, /* 5: - NA */
79 8U, /* 6: CC4S, IC4PSC, IC4F */
80 0U, /* 7: - NA */
81 0U /* 8: - NA */
82 };
83
84 static const uint8_t SHIFT_TAB_CCxP[] =
85 {
86 0U, /* 0: CC1P */
87 2U, /* 1: CC1NP */
88 4U, /* 2: CC2P */
89 6U, /* 3: CC2NP */
90 8U, /* 4: CC3P */
91 10U, /* 5: CC3NP */
92 12U, /* 6: CC4P */
93 16U, /* 7: CC5P */
94 20U /* 8: CC6P */
95 };
96
97 static const uint8_t SHIFT_TAB_OISx[] =
98 {
99 0U, /* 0: OIS1 */
100 1U, /* 1: OIS1N */
101 2U, /* 2: OIS2 */
102 3U, /* 3: OIS2N */
103 4U, /* 4: OIS3 */
104 5U, /* 5: OIS3N */
105 6U, /* 6: OIS4 */
106 8U, /* 7: OIS5 */
107 10U /* 8: OIS6 */
108 };
109 /**
110 * @}
111 */
112
113 /* Private constants ---------------------------------------------------------*/
114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
115 * @{
116 */
117
118 /* Defines used for the bit position in the register and perform offsets */
119 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
120
121 /* Generic bit definitions for TIMx_AF1 register */
122 #define TIMx_AF1_BKINE TIM1_AF1_BKINE /*!< BRK BKINE input enable */
123 #if defined(DFSDM1_Channel0)
124 #define TIMx_AF1_BKDFBKE TIM1_AF1_BKDF1BK0E /*!< BRK DFSDM1_BREAK[0] enable */
125 #endif /* DFSDM1_Channel0 */
126 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
127 /* Generic bit definitions for TIMx_AF2 register */
128 #define TIMx_AF2_BK2INE TIM1_AF2_BK2INE /*!< BRK B2KINE input enable */
129 #if defined(DFSDM1_Channel0)
130 #define TIMx_AF2_BK2DFBKE TIM1_AF2_BK2DF1BK1E /*!< BRK DFSDM_BREAK[0] enable */
131 #endif /* DFSDM1_Channel0 */
132 #define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /*!< BRK BK2IN input polarity */
133 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
134
135
136 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
137 #define DT_DELAY_1 ((uint8_t)0x7F)
138 #define DT_DELAY_2 ((uint8_t)0x3F)
139 #define DT_DELAY_3 ((uint8_t)0x1F)
140 #define DT_DELAY_4 ((uint8_t)0x1F)
141
142 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
143 #define DT_RANGE_1 ((uint8_t)0x00)
144 #define DT_RANGE_2 ((uint8_t)0x80)
145 #define DT_RANGE_3 ((uint8_t)0xC0)
146 #define DT_RANGE_4 ((uint8_t)0xE0)
147
148 /** Legacy definitions for compatibility purpose
149 @cond 0
150 */
151 #define TIMx_AF1_BKDFBK0E TIMx_AF1_BKDF1BK0E
152 #define TIMx_AF2_BK2DFBK1E TIMx_AF2_BK2DF1BK1E
153 /**
154 @endcond
155 */
156
157 #define OCREF_CLEAR_SELECT_Pos (16U)
158 #define OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos) /*!< 0x00010000 */
159 /**
160 * @}
161 */
162
163 /* Private macros ------------------------------------------------------------*/
164 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
165 * @{
166 */
167 /** @brief Convert channel id into channel index.
168 * @param __CHANNEL__ This parameter can be one of the following values:
169 * @arg @ref LL_TIM_CHANNEL_CH1
170 * @arg @ref LL_TIM_CHANNEL_CH1N
171 * @arg @ref LL_TIM_CHANNEL_CH2
172 * @arg @ref LL_TIM_CHANNEL_CH2N
173 * @arg @ref LL_TIM_CHANNEL_CH3
174 * @arg @ref LL_TIM_CHANNEL_CH3N
175 * @arg @ref LL_TIM_CHANNEL_CH4
176 * @arg @ref LL_TIM_CHANNEL_CH5
177 * @arg @ref LL_TIM_CHANNEL_CH6
178 * @retval none
179 */
180 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
181 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
182 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
183 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
184 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
185 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
186 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
187 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
188 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
189
190 /** @brief Calculate the deadtime sampling period(in ps).
191 * @param __TIMCLK__ timer input clock frequency (in Hz).
192 * @param __CKD__ This parameter can be one of the following values:
193 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
194 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
195 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
196 * @retval none
197 */
198 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
199 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
200 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
201 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
202 /**
203 * @}
204 */
205
206
207 /* Exported types ------------------------------------------------------------*/
208 #if defined(USE_FULL_LL_DRIVER)
209 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
210 * @{
211 */
212
213 /**
214 * @brief TIM Time Base configuration structure definition.
215 */
216 typedef struct
217 {
218 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
219 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
220
221 This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
222
223 uint32_t CounterMode; /*!< Specifies the counter mode.
224 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
225
226 This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
227
228 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
229 Auto-Reload Register at the next update event.
230 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
231 Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
232
233 This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
234
235 uint32_t ClockDivision; /*!< Specifies the clock division.
236 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
237
238 This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
239
240 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
241 reaches zero, an update event is generated and counting restarts
242 from the RCR value (N).
243 This means in PWM mode that (N+1) corresponds to:
244 - the number of PWM periods in edge-aligned mode
245 - the number of half PWM period in center-aligned mode
246 GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
247 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
248
249 This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
250 } LL_TIM_InitTypeDef;
251
252 /**
253 * @brief TIM Output Compare configuration structure definition.
254 */
255 typedef struct
256 {
257 uint32_t OCMode; /*!< Specifies the output mode.
258 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
259
260 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
261
262 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
263 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
264
265 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
266
267 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
268 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
269
270 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
271
272 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
273 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
274
275 This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
276
277 uint32_t OCPolarity; /*!< Specifies the output polarity.
278 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
279
280 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
281
282 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
283 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
284
285 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
286
287
288 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
289 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
290
291 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
292
293 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
294 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
295
296 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
297 } LL_TIM_OC_InitTypeDef;
298
299 /**
300 * @brief TIM Input Capture configuration structure definition.
301 */
302
303 typedef struct
304 {
305
306 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
307 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
308
309 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
310
311 uint32_t ICActiveInput; /*!< Specifies the input.
312 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
313
314 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
315
316 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
317 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
318
319 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
320
321 uint32_t ICFilter; /*!< Specifies the input capture filter.
322 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
323
324 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
325 } LL_TIM_IC_InitTypeDef;
326
327
328 /**
329 * @brief TIM Encoder interface configuration structure definition.
330 */
331 typedef struct
332 {
333 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
334 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
335
336 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
337
338 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
339 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
340
341 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
342
343 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
344 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
345
346 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
347
348 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
349 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
350
351 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
352
353 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
354 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
355
356 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
357
358 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
359 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
360
361 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
362
363 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
364 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
365
366 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
367
368 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
369 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
370
371 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
372
373 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
374 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
375
376 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
377
378 } LL_TIM_ENCODER_InitTypeDef;
379
380 /**
381 * @brief TIM Hall sensor interface configuration structure definition.
382 */
383 typedef struct
384 {
385
386 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
387 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
388
389 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
390
391 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
392 Prescaler must be set to get a maximum counter period longer than the
393 time interval between 2 consecutive changes on the Hall inputs.
394 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
395
396 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
397
398 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
399 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
400
401 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
402
403 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
404 A positive pulse (TRGO event) is generated with a programmable delay every time
405 a change occurs on the Hall inputs.
406 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
407
408 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
409 } LL_TIM_HALLSENSOR_InitTypeDef;
410
411 /**
412 * @brief BDTR (Break and Dead Time) structure definition
413 */
414 typedef struct
415 {
416 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
417 This parameter can be a value of @ref TIM_LL_EC_OSSR
418
419 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
420
421 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
422
423 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
424 This parameter can be a value of @ref TIM_LL_EC_OSSI
425
426 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
427
428 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
429
430 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
431 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
432
433 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
434 has been written, their content is frozen until the next reset.*/
435
436 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
437 switching-on of the outputs.
438 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
439
440 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
441
442 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
443
444 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
445 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
446
447 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
448
449 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
450
451 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
452 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
453
454 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
455
456 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
457
458 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
459 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
460
461 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
462
463 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
464
465 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
466 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
467
468 This feature can be modified afterwards using unitary functions @ref LL_TIM_ConfigBRK()
469
470 @note Bidirectional break input is only supported by advanced timers instances.
471
472 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
473
474 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
475 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
476
477 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
478
479 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
480
481 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
482 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
483
484 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
485
486 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
487
488 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
489 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
490
491 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
492
493 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
494
495 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
496 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
497
498 This feature can be modified afterwards using unitary functions @ref LL_TIM_ConfigBRK2()
499
500 @note Bidirectional break input is only supported by advanced timers instances.
501
502 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
503
504 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
505 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
506
507 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
508
509 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
510 } LL_TIM_BDTR_InitTypeDef;
511
512 /**
513 * @}
514 */
515 #endif /* USE_FULL_LL_DRIVER */
516
517 /* Exported constants --------------------------------------------------------*/
518 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
519 * @{
520 */
521
522 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
523 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
524 * @{
525 */
526 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
527 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
528 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
529 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
530 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
531 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
532 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
533 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
534 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
535 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
536 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
537 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
538 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
539 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
540 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
541 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
542 /**
543 * @}
544 */
545
546 #if defined(USE_FULL_LL_DRIVER)
547 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
548 * @{
549 */
550 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
551 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
552 /**
553 * @}
554 */
555
556 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
557 * @{
558 */
559 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
560 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
561 /**
562 * @}
563 */
564
565 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
566 * @{
567 */
568 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
569 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
570 /**
571 * @}
572 */
573 #endif /* USE_FULL_LL_DRIVER */
574
575 /** @defgroup TIM_LL_EC_IT IT Defines
576 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
577 * @{
578 */
579 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
580 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
581 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
582 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
583 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
584 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
585 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
586 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
587 /**
588 * @}
589 */
590
591 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
592 * @{
593 */
594 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
595 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
596 /**
597 * @}
598 */
599
600 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
601 * @{
602 */
603 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
604 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
605 /**
606 * @}
607 */
608
609 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
610 * @{
611 */
612 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
613 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
614 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
615 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up. */
616 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
617 /**
618 * @}
619 */
620
621 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
622 * @{
623 */
624 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
625 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
626 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
627 /**
628 * @}
629 */
630
631 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
632 * @{
633 */
634 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
635 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
636 /**
637 * @}
638 */
639
640 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
641 * @{
642 */
643 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
644 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
645 /**
646 * @}
647 */
648
649 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
650 * @{
651 */
652 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
653 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
654 /**
655 * @}
656 */
657
658 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
659 * @{
660 */
661 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
662 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
663 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
664 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
665 /**
666 * @}
667 */
668
669 /** @defgroup TIM_LL_EC_CHANNEL Channel
670 * @{
671 */
672 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
673 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
674 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
675 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
676 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
677 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
678 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
679 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
680 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
681 /**
682 * @}
683 */
684
685 #if defined(USE_FULL_LL_DRIVER)
686 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
687 * @{
688 */
689 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
690 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
691 /**
692 * @}
693 */
694 #endif /* USE_FULL_LL_DRIVER */
695
696 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
697 * @{
698 */
699 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
700 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
701 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
702 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
703 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
704 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
705 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
706 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
707 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
708 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
709 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
710 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
711 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
712 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
713 /**
714 * @}
715 */
716
717 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
718 * @{
719 */
720 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
721 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
722 /**
723 * @}
724 */
725
726 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
727 * @{
728 */
729 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
730 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
731 /**
732 * @}
733 */
734
735 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
736 * @{
737 */
738 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
739 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
740 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
741 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
742 /**
743 * @}
744 */
745
746 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
747 * @{
748 */
749 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
750 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
751 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
752 /**
753 * @}
754 */
755
756 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
757 * @{
758 */
759 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
760 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
761 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
762 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
763 /**
764 * @}
765 */
766
767 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
768 * @{
769 */
770 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
771 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
772 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
773 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
774 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
775 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
776 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
777 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
778 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
779 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
780 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
781 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
782 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
783 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
784 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
785 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
786 /**
787 * @}
788 */
789
790 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
791 * @{
792 */
793 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
794 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
795 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
796 /**
797 * @}
798 */
799
800 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
801 * @{
802 */
803 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
804 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
805 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
806 /**
807 * @}
808 */
809
810 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
811 * @{
812 */
813 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
814 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
815 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
816 /**
817 * @}
818 */
819
820 /** @defgroup TIM_LL_EC_TRGO Trigger Output
821 * @{
822 */
823 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
824 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
825 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
826 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
827 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
828 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
829 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
830 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
831 /**
832 * @}
833 */
834
835 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
836 * @{
837 */
838 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
839 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
840 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
841 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
842 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
843 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
844 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
845 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
846 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
847 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
848 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
849 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
850 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
851 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
852 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
853 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
854 /**
855 * @}
856 */
857
858 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
859 * @{
860 */
861 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
862 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
863 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
864 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
865 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
866 /**
867 * @}
868 */
869
870 /** @defgroup TIM_LL_EC_TS Trigger Selection
871 * @{
872 */
873 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
874 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
875 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
876 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
877 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
878 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
879 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
880 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
881 /**
882 * @}
883 */
884
885 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
886 * @{
887 */
888 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
889 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
890 /**
891 * @}
892 */
893
894 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
895 * @{
896 */
897 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
898 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
899 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
900 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
901 /**
902 * @}
903 */
904
905 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
906 * @{
907 */
908 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
909 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
910 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
911 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
912 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
913 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
914 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
915 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
916 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
917 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
918 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
919 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
920 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
921 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
922 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
923 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
924 /**
925 * @}
926 */
927
928 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
929 * @{
930 */
931 #define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
932 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 1 */
933 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to ADC1 analog watchdog 2 */
934 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 3 */
935 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to ADC2 analog watchdog 1 */
936 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC2 analog watchdog 2 */
937 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3) /*!< ETR input is connected to ADC2 analog watchdog 3 */
938
939 #define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
940 #define LL_TIM_TIM8_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 1 */
941 #define LL_TIM_TIM8_ETRSOURCE_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to ADC1 analog watchdog 2 */
942 #define LL_TIM_TIM8_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 3 */
943 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to ADC2 analog watchdog 1 */
944 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC2 analog watchdog 2 */
945 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3) /*!< ETR input is connected to ADC2 analog watchdog 3 */
946
947 #define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
948 #define LL_TIM_TIM2_ETRSOURCE_RCC_LSE (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to RCC LSE */
949 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to SAI1 FS_A */
950 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to SAI1 FS_B */
951 #define LL_TIM_TIM2_ETRSOURCE_ETH_PPS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to ETH PPS */
952
953 #define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
954 #define LL_TIM_TIM3_ETRSOURCE_ETH_PPS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to ETH PPS */
955
956 #define LL_TIM_TIM4_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
957
958 #define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
959 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to SAI2 FS_A */
960 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to SAI2 FS_B */
961 #define LL_TIM_TIM5_ETRSOURCE_OTG_SOF (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to OTG SOF */
962 /**
963 * @}
964 */
965
966 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
967 * @{
968 */
969 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
970 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
971 /**
972 * @}
973 */
974
975 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
976 * @{
977 */
978 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
979 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
980 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
981 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
982 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
983 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
984 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
985 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
986 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
987 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
988 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
989 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
990 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
991 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
992 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
993 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
994 /**
995 * @}
996 */
997
998 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
999 * @{
1000 */
1001 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1002 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1003 /**
1004 * @}
1005 */
1006
1007 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1008 * @{
1009 */
1010 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1011 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1012 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1013 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1014 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1015 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1016 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1017 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1018 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1019 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1020 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1021 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1022 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1023 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1024 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1025 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1026 /**
1027 * @}
1028 */
1029
1030 /** @defgroup TIM_LL_EC_OSSI OSSI
1031 * @{
1032 */
1033 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1034 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1035 /**
1036 * @}
1037 */
1038
1039 /** @defgroup TIM_LL_EC_OSSR OSSR
1040 * @{
1041 */
1042 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1043 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1044 /**
1045 * @}
1046 */
1047
1048 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1049 * @{
1050 */
1051 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1052 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1053 /**
1054 * @}
1055 */
1056
1057 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1058 * @{
1059 */
1060 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1061 #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_AF1_BKDF1BK0E /*!< internal signal: DFSDM1 break output */
1062 /**
1063 * @}
1064 */
1065
1066 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1067 * @{
1068 */
1069 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1070 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1071 /**
1072 * @}
1073 */
1074
1075 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1076 * @{
1077 */
1078 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1079 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1080 /**
1081 * @}
1082 */
1083
1084 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1085 * @{
1086 */
1087 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1088 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1089 /**
1090 * @}
1091 */
1092
1093 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1094 * @{
1095 */
1096 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1097 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1098 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1099 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1100 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1101 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1102 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1103 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1104 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1105 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1106 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1107 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1108 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1109 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1110 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1111 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1112 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1113 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1114 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1115 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1116 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1117 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1118 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1119 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1120 /**
1121 * @}
1122 */
1123
1124 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1125 * @{
1126 */
1127 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1128 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1129 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1130 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1131 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1132 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1133 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1134 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1135 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1136 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1137 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1138 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1139 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1140 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1141 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1142 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1143 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1144 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1145 /**
1146 * @}
1147 */
1148
1149 /** @defgroup TIM_LL_EC_TIM1_TIx_RMP TIM1 Timer Input Chx Remap
1150 * @{
1151 */
1152 #define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /*!< TIM1 input 1 is connected to GPIO */
1153 #define LL_TIM_TIM1_TI2_RMP_GPIO 0x00000000U /*!< TIM1 input 2 is connected to GPIO */
1154 #define LL_TIM_TIM1_TI3_RMP_GPIO 0x00000000U /*!< TIM1 input 3 is connected to GPIO */
1155 #define LL_TIM_TIM1_TI4_RMP_GPIO 0x00000000U /*!< TIM1 input 4 is connected to GPIO */
1156 /**
1157 * @}
1158 */
1159 /** @defgroup TIM_LL_EC_TIM8_TIx_RMP TIM8 Timer Input Chx Remap
1160 * @{
1161 */
1162 #define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000U /*!< TIM8 input 1 is connected to GPIO */
1163 #define LL_TIM_TIM8_TI2_RMP_GPIO 0x00000000U /*!< TIM8 input 2 is connected to GPIO */
1164 #define LL_TIM_TIM8_TI3_RMP_GPIO 0x00000000U /*!< TIM8 input 3 is connected to GPIO */
1165 #define LL_TIM_TIM8_TI4_RMP_GPIO 0x00000000U /*!< TIM8 input 4 is connected to GPIO */
1166 /**
1167 * @}
1168 */
1169 /** @defgroup TIM_LL_EC_TIM2_TIx_RMP TIM2 Timer Input Chx Remap
1170 * @{
1171 */
1172 #define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000U /*!< TIM2 input 1 is connected to GPIO */
1173 #define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000U /*!< TIM2 input 2 is connected to GPIO */
1174 #define LL_TIM_TIM2_TI3_RMP_GPIO 0x00000000U /*!< TIM2 input 3 is connected to GPIO */
1175 #define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000U /*!< TIM2 input 4 is connected to GPIO */
1176 /**
1177 * @}
1178 */
1179 /** @defgroup TIM_LL_EC_TIM3_TIx_RMP TIM3 Timer Input Chx Remap
1180 * @{
1181 */
1182 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /*!< TIM3 input 1 is connected to GPIO */
1183 #define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000U /*!< TIM3 input 2 is connected to GPIO */
1184 #define LL_TIM_TIM3_TI3_RMP_GPIO 0x00000000U /*!< TIM3 input 3 is connected to GPIO */
1185 #define LL_TIM_TIM3_TI4_RMP_GPIO 0x00000000U /*!< TIM3 input 4 is connected to GPIO */
1186 /**
1187 * @}
1188 */
1189 /** @defgroup TIM_LL_EC_TIM4_TIx_RMP TIM4 Timer Input Chx Remap
1190 * @{
1191 */
1192 #define LL_TIM_TIM4_TI1_RMP_GPIO 0x00000000U /*!< TIM4 input 1 is connected to GPIO */
1193 #define LL_TIM_TIM4_TI2_RMP_GPIO 0x00000000U /*!< TIM4 input 2 is connected to GPIO */
1194 #define LL_TIM_TIM4_TI3_RMP_GPIO 0x00000000U /*!< TIM4 input 3 is connected to GPIO */
1195 #define LL_TIM_TIM4_TI4_RMP_GPIO 0x00000000U /*!< TIM4 input 4 is connected to GPIO */
1196 /**
1197 * @}
1198 */
1199 /** @defgroup TIM_LL_EC_TIM5_TIx_RMP TIM5 Timer Input Chx Remap
1200 * @{
1201 */
1202 #define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000U /*!< TIM5 input 1 is connected to GPIO */
1203 #define LL_TIM_TIM5_TI1_RMP_FDCAN1_TMP TIM_TISEL_TI1SEL_0 /*!< TIM5 input 1 is connected to FDCAN1_TMP */
1204 #define LL_TIM_TIM5_TI1_RMP_FDCAN1_RTP TIM_TISEL_TI1SEL_1 /*!< TIM5 input 1 is connected to FDCAN1_RTP */
1205 #define LL_TIM_TIM5_TI2_RMP_GPIO 0x00000000U /*!< TIM5 input 2 is connected to GPIO */
1206 #define LL_TIM_TIM5_TI3_RMP_GPIO 0x00000000U /*!< TIM5 input 3 is connected to GPIO */
1207 #define LL_TIM_TIM5_TI4_RMP_GPIO 0x00000000U /*!< TIM5 input 4 is connected to GPIO */
1208 /**
1209 * @}
1210 */
1211 /** @defgroup TIM_LL_EC_TIM12_TIx_RMP TIM12 Timer Input Chx Remap
1212 * @{
1213 */
1214 #define LL_TIM_TIM12_TI1_RMP_GPIO 0x00000000U /*!< TIM12 input 1 is connected to GPIO */
1215 #define LL_TIM_TIM12_TI1_RMP_HSI_CAL_CK TIM_TISEL_TI1SEL_0 /*!< TIM12 input 1 is connected to HSI_CAL_CK */
1216 #define LL_TIM_TIM12_TI1_RMP_CSI_CAL_CK TIM_TISEL_TI1SEL_1 /*!< TIM12 input 1 is connected to CSI_CAL_CK */
1217 #define LL_TIM_TIM12_TI2_RMP_GPIO 0x00000000U /*!< TIM12 input 2 is connected to GPIO */
1218 /**
1219 * @}
1220 */
1221 /** @defgroup TIM_LL_EC_TIM13_TIx_RMP TIM13 Timer Input Chx Remap
1222 * @{
1223 */
1224 #define LL_TIM_TIM13_TI1_RMP_GPIO 0x00000000U /*!< TIM13 input 1 is connected to GPIO */
1225 /**
1226 * @}
1227 */
1228 /** @defgroup TIM_LL_EC_TIM14_TIx_RMP TIM14 Timer Input Chx Remap
1229 * @{
1230 */
1231 #define LL_TIM_TIM14_TI1_RMP_GPIO 0x00000000U /*!< TIM14 input 1 is connected to GPIO */
1232 /**
1233 * @}
1234 */
1235 /** @defgroup TIM_LL_EC_TIM15_TIx_RMP TIM15 Timer Input Chx Remap
1236 * @{
1237 */
1238 #define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /*!< TIM15 input 1 is connected to GPIO */
1239 #define LL_TIM_TIM15_TI1_RMP_TIM2_CH1 TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to TIM2_CH1 */
1240 #define LL_TIM_TIM15_TI1_RMP_TIM3_CH1 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to TIM3_CH1 */
1241 #define LL_TIM_TIM15_TI1_RMP_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM15 input 1 is connected to TIM4_CH1 */
1242 #define LL_TIM_TIM15_TI1_RMP_RCC_LSE TIM_TISEL_TI1SEL_2 /*!< TIM15 input 1 is connected to RCC_LSE */
1243 #define LL_TIM_TIM15_TI1_RMP_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to RCC_CSI */
1244 #define LL_TIM_TIM15_TI1_RMP_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM15 input 1 is connected to RCC_MCO2 */
1245 #define LL_TIM_TIM15_TI1_RMP_HSI_CAL_CK (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to HSI_CAL_CK */
1246 #define LL_TIM_TIM15_TI1_RMP_CSI_CAL_CK TIM_TISEL_TI1SEL_3 /*!< TIM15 input 1 is connected to CSI_CAL_CK */
1247 #define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /*!< TIM15 input 2 is connected to GPIO */
1248 #define LL_TIM_TIM15_TI2_RMP_TIM2_CH2 TIM_TISEL_TI1SEL_0 /*!< TIM15 input 2 is connected to TIM2_CH2 */
1249 #define LL_TIM_TIM15_TI2_RMP_TIM3_CH2 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 2 is connected to TIM3_CH2 */
1250 #define LL_TIM_TIM15_TI2_RMP_TIM4_CH2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM15 input 2 is connected to TIM4_CH2 */
1251 /**
1252 * @}
1253 */
1254 /** @defgroup TIM_LL_EC_TIM16_TIx_RMP TIM16 Timer Input Chx Remap
1255 * @{
1256 */
1257 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input 1 is connected to GPIO */
1258 #define LL_TIM_TIM16_TI1_RMP_RCC_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to RCC_LSI */
1259 #define LL_TIM_TIM16_TI1_RMP_RCC_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to RCC_LSE */
1260 #define LL_TIM_TIM16_TI1_RMP_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to WKUP_IT */
1261 /**
1262 * @}
1263 */
1264 /** @defgroup TIM_LL_EC_TIM17_TIx_RMP TIM17 Timer Input Chx Remap
1265 * @{
1266 */
1267 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /*!< TIM17 input 1 is connected to GPIO */
1268 #define LL_TIM_TIM17_TI1_RMP_SPDIFRX_FS TIM_TISEL_TI1SEL_0 /*!< TIM17 input 1 is connected to SPDIF_FS */
1269 #define LL_TIM_TIM17_TI1_RMP_RCC_HSE_RTC TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to RCC_HSE_RTC */
1270 #define LL_TIM_TIM17_TI1_RMP_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to RCC_MCO1 */
1271 /**
1272 * @}
1273 */
1274
1275 /** Legacy definitions for compatibility purpose
1276 @cond 0
1277 */
1278 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1279 /**
1280 @endcond
1281 */
1282 /**
1283 * @}
1284 */
1285
1286 /* Exported macro ------------------------------------------------------------*/
1287 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1288 * @{
1289 */
1290
1291 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1292 * @{
1293 */
1294 /**
1295 * @brief Write a value in TIM register.
1296 * @param __INSTANCE__ TIM Instance
1297 * @param __REG__ Register to be written
1298 * @param __VALUE__ Value to be written in the register
1299 * @retval None
1300 */
1301 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1302
1303 /**
1304 * @brief Read a value in TIM register.
1305 * @param __INSTANCE__ TIM Instance
1306 * @param __REG__ Register to be read
1307 * @retval Register value
1308 */
1309 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1310 /**
1311 * @}
1312 */
1313
1314 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
1315 * @{
1316 */
1317
1318 /**
1319 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1320 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1321 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1322 * to TIMx_CNT register bit 31)
1323 * @param __CNT__ Counter value
1324 * @retval UIF status bit
1325 */
1326 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1327 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1328
1329 /**
1330 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1331 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1332 * @param __TIMCLK__ timer input clock frequency (in Hz)
1333 * @param __CKD__ This parameter can be one of the following values:
1334 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1335 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1336 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1337 * @param __DT__ deadtime duration (in ns)
1338 * @retval DTG[0:7]
1339 */
1340 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1341 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1342 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1343 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1344 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1345 0U)
1346
1347 /**
1348 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1349 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1350 * @param __TIMCLK__ timer input clock frequency (in Hz)
1351 * @param __CNTCLK__ counter clock frequency (in Hz)
1352 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1353 */
1354 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1355 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
1356
1357 /**
1358 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1359 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1360 * @param __TIMCLK__ timer input clock frequency (in Hz)
1361 * @param __PSC__ prescaler
1362 * @param __FREQ__ output signal frequency (in Hz)
1363 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1364 */
1365 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1366 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1367
1368 /**
1369 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
1370 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1371 * @param __TIMCLK__ timer input clock frequency (in Hz)
1372 * @param __PSC__ prescaler
1373 * @param __DELAY__ timer output compare active/inactive delay (in us)
1374 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1375 */
1376 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1377 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1378 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1379
1380 /**
1381 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
1382 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1383 * @param __TIMCLK__ timer input clock frequency (in Hz)
1384 * @param __PSC__ prescaler
1385 * @param __DELAY__ timer output compare active/inactive delay (in us)
1386 * @param __PULSE__ pulse duration (in us)
1387 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1388 */
1389 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1390 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1391 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1392
1393 /**
1394 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1395 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1396 * @param __ICPSC__ This parameter can be one of the following values:
1397 * @arg @ref LL_TIM_ICPSC_DIV1
1398 * @arg @ref LL_TIM_ICPSC_DIV2
1399 * @arg @ref LL_TIM_ICPSC_DIV4
1400 * @arg @ref LL_TIM_ICPSC_DIV8
1401 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1402 */
1403 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1404 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1405
1406
1407 /**
1408 * @}
1409 */
1410
1411
1412 /**
1413 * @}
1414 */
1415
1416 /* Exported functions --------------------------------------------------------*/
1417 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1418 * @{
1419 */
1420
1421 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1422 * @{
1423 */
1424 /**
1425 * @brief Enable timer counter.
1426 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1427 * @param TIMx Timer instance
1428 * @retval None
1429 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1430 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1431 {
1432 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1433 }
1434
1435 /**
1436 * @brief Disable timer counter.
1437 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1438 * @param TIMx Timer instance
1439 * @retval None
1440 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1441 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1442 {
1443 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1444 }
1445
1446 /**
1447 * @brief Indicates whether the timer counter is enabled.
1448 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1449 * @param TIMx Timer instance
1450 * @retval State of bit (1 or 0).
1451 */
LL_TIM_IsEnabledCounter(TIM_TypeDef * TIMx)1452 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
1453 {
1454 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1455 }
1456
1457 /**
1458 * @brief Enable update event generation.
1459 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1460 * @param TIMx Timer instance
1461 * @retval None
1462 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1463 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1464 {
1465 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1466 }
1467
1468 /**
1469 * @brief Disable update event generation.
1470 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1471 * @param TIMx Timer instance
1472 * @retval None
1473 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1474 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1475 {
1476 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1477 }
1478
1479 /**
1480 * @brief Indicates whether update event generation is enabled.
1481 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1482 * @param TIMx Timer instance
1483 * @retval Inverted state of bit (0 or 1).
1484 */
LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef * TIMx)1485 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
1486 {
1487 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1488 }
1489
1490 /**
1491 * @brief Set update event source
1492 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1493 * generate an update interrupt or DMA request if enabled:
1494 * - Counter overflow/underflow
1495 * - Setting the UG bit
1496 * - Update generation through the slave mode controller
1497 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1498 * overflow/underflow generates an update interrupt or DMA request if enabled.
1499 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1500 * @param TIMx Timer instance
1501 * @param UpdateSource This parameter can be one of the following values:
1502 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1503 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1504 * @retval None
1505 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1506 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1507 {
1508 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1509 }
1510
1511 /**
1512 * @brief Get actual event update source
1513 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1514 * @param TIMx Timer instance
1515 * @retval Returned value can be one of the following values:
1516 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1517 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1518 */
LL_TIM_GetUpdateSource(TIM_TypeDef * TIMx)1519 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
1520 {
1521 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1522 }
1523
1524 /**
1525 * @brief Set one pulse mode (one shot v.s. repetitive).
1526 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1527 * @param TIMx Timer instance
1528 * @param OnePulseMode This parameter can be one of the following values:
1529 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1530 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1531 * @retval None
1532 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1533 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1534 {
1535 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1536 }
1537
1538 /**
1539 * @brief Get actual one pulse mode.
1540 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1541 * @param TIMx Timer instance
1542 * @retval Returned value can be one of the following values:
1543 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1544 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1545 */
LL_TIM_GetOnePulseMode(TIM_TypeDef * TIMx)1546 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
1547 {
1548 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1549 }
1550
1551 /**
1552 * @brief Set the timer counter counting mode.
1553 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1554 * check whether or not the counter mode selection feature is supported
1555 * by a timer instance.
1556 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1557 * requires a timer reset to avoid unexpected direction
1558 * due to DIR bit readonly in center aligned mode.
1559 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1560 * CR1 CMS LL_TIM_SetCounterMode
1561 * @param TIMx Timer instance
1562 * @param CounterMode This parameter can be one of the following values:
1563 * @arg @ref LL_TIM_COUNTERMODE_UP
1564 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1565 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1566 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1567 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1568 * @retval None
1569 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1570 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1571 {
1572 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1573 }
1574
1575 /**
1576 * @brief Get actual counter mode.
1577 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1578 * check whether or not the counter mode selection feature is supported
1579 * by a timer instance.
1580 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1581 * CR1 CMS LL_TIM_GetCounterMode
1582 * @param TIMx Timer instance
1583 * @retval Returned value can be one of the following values:
1584 * @arg @ref LL_TIM_COUNTERMODE_UP
1585 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1586 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1587 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1588 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1589 */
LL_TIM_GetCounterMode(TIM_TypeDef * TIMx)1590 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
1591 {
1592 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
1593 }
1594
1595 /**
1596 * @brief Enable auto-reload (ARR) preload.
1597 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1598 * @param TIMx Timer instance
1599 * @retval None
1600 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1601 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1602 {
1603 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1604 }
1605
1606 /**
1607 * @brief Disable auto-reload (ARR) preload.
1608 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1609 * @param TIMx Timer instance
1610 * @retval None
1611 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1612 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1613 {
1614 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1615 }
1616
1617 /**
1618 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1619 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1620 * @param TIMx Timer instance
1621 * @retval State of bit (1 or 0).
1622 */
LL_TIM_IsEnabledARRPreload(TIM_TypeDef * TIMx)1623 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
1624 {
1625 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1626 }
1627
1628 /**
1629 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1630 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1631 * whether or not the clock division feature is supported by the timer
1632 * instance.
1633 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1634 * @param TIMx Timer instance
1635 * @param ClockDivision This parameter can be one of the following values:
1636 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1637 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1638 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1639 * @retval None
1640 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1641 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1642 {
1643 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1644 }
1645
1646 /**
1647 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1648 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1649 * whether or not the clock division feature is supported by the timer
1650 * instance.
1651 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1652 * @param TIMx Timer instance
1653 * @retval Returned value can be one of the following values:
1654 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1655 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1656 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1657 */
LL_TIM_GetClockDivision(TIM_TypeDef * TIMx)1658 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
1659 {
1660 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1661 }
1662
1663 /**
1664 * @brief Set the counter value.
1665 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1666 * whether or not a timer instance supports a 32 bits counter.
1667 * @rmtoll CNT CNT LL_TIM_SetCounter
1668 * @param TIMx Timer instance
1669 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1670 * @retval None
1671 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1672 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1673 {
1674 WRITE_REG(TIMx->CNT, Counter);
1675 }
1676
1677 /**
1678 * @brief Get the counter value.
1679 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1680 * whether or not a timer instance supports a 32 bits counter.
1681 * @rmtoll CNT CNT LL_TIM_GetCounter
1682 * @param TIMx Timer instance
1683 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1684 */
LL_TIM_GetCounter(TIM_TypeDef * TIMx)1685 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
1686 {
1687 return (uint32_t)(READ_REG(TIMx->CNT));
1688 }
1689
1690 /**
1691 * @brief Get the current direction of the counter
1692 * @rmtoll CR1 DIR LL_TIM_GetDirection
1693 * @param TIMx Timer instance
1694 * @retval Returned value can be one of the following values:
1695 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1696 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1697 */
LL_TIM_GetDirection(TIM_TypeDef * TIMx)1698 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
1699 {
1700 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1701 }
1702
1703 /**
1704 * @brief Set the prescaler value.
1705 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1706 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1707 * prescaler ratio is taken into account at the next update event.
1708 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1709 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1710 * @param TIMx Timer instance
1711 * @param Prescaler between Min_Data=0 and Max_Data=65535
1712 * @retval None
1713 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1714 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1715 {
1716 WRITE_REG(TIMx->PSC, Prescaler);
1717 }
1718
1719 /**
1720 * @brief Get the prescaler value.
1721 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1722 * @param TIMx Timer instance
1723 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1724 */
LL_TIM_GetPrescaler(TIM_TypeDef * TIMx)1725 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
1726 {
1727 return (uint32_t)(READ_REG(TIMx->PSC));
1728 }
1729
1730 /**
1731 * @brief Set the auto-reload value.
1732 * @note The counter is blocked while the auto-reload value is null.
1733 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1734 * whether or not a timer instance supports a 32 bits counter.
1735 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1736 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1737 * @param TIMx Timer instance
1738 * @param AutoReload between Min_Data=0 and Max_Data=65535
1739 * @retval None
1740 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1741 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1742 {
1743 WRITE_REG(TIMx->ARR, AutoReload);
1744 }
1745
1746 /**
1747 * @brief Get the auto-reload value.
1748 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1749 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1750 * whether or not a timer instance supports a 32 bits counter.
1751 * @param TIMx Timer instance
1752 * @retval Auto-reload value
1753 */
LL_TIM_GetAutoReload(TIM_TypeDef * TIMx)1754 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
1755 {
1756 return (uint32_t)(READ_REG(TIMx->ARR));
1757 }
1758
1759 /**
1760 * @brief Set the repetition counter value.
1761 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1762 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1763 * whether or not a timer instance supports a repetition counter.
1764 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1765 * @param TIMx Timer instance
1766 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1767 * @retval None
1768 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1769 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1770 {
1771 WRITE_REG(TIMx->RCR, RepetitionCounter);
1772 }
1773
1774 /**
1775 * @brief Get the repetition counter value.
1776 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1777 * whether or not a timer instance supports a repetition counter.
1778 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1779 * @param TIMx Timer instance
1780 * @retval Repetition counter value
1781 */
LL_TIM_GetRepetitionCounter(TIM_TypeDef * TIMx)1782 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
1783 {
1784 return (uint32_t)(READ_REG(TIMx->RCR));
1785 }
1786
1787 /**
1788 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1789 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
1790 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1791 * @param TIMx Timer instance
1792 * @retval None
1793 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1794 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1795 {
1796 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1797 }
1798
1799 /**
1800 * @brief Disable update interrupt flag (UIF) remapping.
1801 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1802 * @param TIMx Timer instance
1803 * @retval None
1804 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1805 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1806 {
1807 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1808 }
1809
1810 /**
1811 * @}
1812 */
1813
1814 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1815 * @{
1816 */
1817 /**
1818 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1819 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1820 * they are updated only when a commutation event (COM) occurs.
1821 * @note Only on channels that have a complementary output.
1822 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1823 * whether or not a timer instance is able to generate a commutation event.
1824 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1825 * @param TIMx Timer instance
1826 * @retval None
1827 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1828 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1829 {
1830 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1831 }
1832
1833 /**
1834 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1835 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1836 * whether or not a timer instance is able to generate a commutation event.
1837 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1838 * @param TIMx Timer instance
1839 * @retval None
1840 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1841 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1842 {
1843 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1844 }
1845
1846 /**
1847 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1848 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1849 * whether or not a timer instance is able to generate a commutation event.
1850 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1851 * @param TIMx Timer instance
1852 * @param CCUpdateSource This parameter can be one of the following values:
1853 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1854 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1855 * @retval None
1856 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1857 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1858 {
1859 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1860 }
1861
1862 /**
1863 * @brief Set the trigger of the capture/compare DMA request.
1864 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1865 * @param TIMx Timer instance
1866 * @param DMAReqTrigger This parameter can be one of the following values:
1867 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1868 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1869 * @retval None
1870 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1871 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1872 {
1873 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1874 }
1875
1876 /**
1877 * @brief Get actual trigger of the capture/compare DMA request.
1878 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1879 * @param TIMx Timer instance
1880 * @retval Returned value can be one of the following values:
1881 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1882 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1883 */
LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef * TIMx)1884 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
1885 {
1886 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1887 }
1888
1889 /**
1890 * @brief Set the lock level to freeze the
1891 * configuration of several capture/compare parameters.
1892 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1893 * the lock mechanism is supported by a timer instance.
1894 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1895 * @param TIMx Timer instance
1896 * @param LockLevel This parameter can be one of the following values:
1897 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1898 * @arg @ref LL_TIM_LOCKLEVEL_1
1899 * @arg @ref LL_TIM_LOCKLEVEL_2
1900 * @arg @ref LL_TIM_LOCKLEVEL_3
1901 * @retval None
1902 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1903 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1904 {
1905 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1906 }
1907
1908 /**
1909 * @brief Enable capture/compare channels.
1910 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1911 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1912 * CCER CC2E LL_TIM_CC_EnableChannel\n
1913 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1914 * CCER CC3E LL_TIM_CC_EnableChannel\n
1915 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1916 * CCER CC4E LL_TIM_CC_EnableChannel\n
1917 * CCER CC5E LL_TIM_CC_EnableChannel\n
1918 * CCER CC6E LL_TIM_CC_EnableChannel
1919 * @param TIMx Timer instance
1920 * @param Channels This parameter can be a combination of the following values:
1921 * @arg @ref LL_TIM_CHANNEL_CH1
1922 * @arg @ref LL_TIM_CHANNEL_CH1N
1923 * @arg @ref LL_TIM_CHANNEL_CH2
1924 * @arg @ref LL_TIM_CHANNEL_CH2N
1925 * @arg @ref LL_TIM_CHANNEL_CH3
1926 * @arg @ref LL_TIM_CHANNEL_CH3N
1927 * @arg @ref LL_TIM_CHANNEL_CH4
1928 * @arg @ref LL_TIM_CHANNEL_CH5
1929 * @arg @ref LL_TIM_CHANNEL_CH6
1930 * @retval None
1931 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1932 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1933 {
1934 SET_BIT(TIMx->CCER, Channels);
1935 }
1936
1937 /**
1938 * @brief Disable capture/compare channels.
1939 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1940 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1941 * CCER CC2E LL_TIM_CC_DisableChannel\n
1942 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1943 * CCER CC3E LL_TIM_CC_DisableChannel\n
1944 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1945 * CCER CC4E LL_TIM_CC_DisableChannel\n
1946 * CCER CC5E LL_TIM_CC_DisableChannel\n
1947 * CCER CC6E LL_TIM_CC_DisableChannel
1948 * @param TIMx Timer instance
1949 * @param Channels This parameter can be a combination of the following values:
1950 * @arg @ref LL_TIM_CHANNEL_CH1
1951 * @arg @ref LL_TIM_CHANNEL_CH1N
1952 * @arg @ref LL_TIM_CHANNEL_CH2
1953 * @arg @ref LL_TIM_CHANNEL_CH2N
1954 * @arg @ref LL_TIM_CHANNEL_CH3
1955 * @arg @ref LL_TIM_CHANNEL_CH3N
1956 * @arg @ref LL_TIM_CHANNEL_CH4
1957 * @arg @ref LL_TIM_CHANNEL_CH5
1958 * @arg @ref LL_TIM_CHANNEL_CH6
1959 * @retval None
1960 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1961 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1962 {
1963 CLEAR_BIT(TIMx->CCER, Channels);
1964 }
1965
1966 /**
1967 * @brief Indicate whether channel(s) is(are) enabled.
1968 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1969 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1970 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1971 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1972 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1973 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1974 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
1975 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
1976 * CCER CC6E LL_TIM_CC_IsEnabledChannel
1977 * @param TIMx Timer instance
1978 * @param Channels This parameter can be a combination of the following values:
1979 * @arg @ref LL_TIM_CHANNEL_CH1
1980 * @arg @ref LL_TIM_CHANNEL_CH1N
1981 * @arg @ref LL_TIM_CHANNEL_CH2
1982 * @arg @ref LL_TIM_CHANNEL_CH2N
1983 * @arg @ref LL_TIM_CHANNEL_CH3
1984 * @arg @ref LL_TIM_CHANNEL_CH3N
1985 * @arg @ref LL_TIM_CHANNEL_CH4
1986 * @arg @ref LL_TIM_CHANNEL_CH5
1987 * @arg @ref LL_TIM_CHANNEL_CH6
1988 * @retval State of bit (1 or 0).
1989 */
LL_TIM_CC_IsEnabledChannel(TIM_TypeDef * TIMx,uint32_t Channels)1990 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1991 {
1992 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
1993 }
1994
1995 /**
1996 * @}
1997 */
1998
1999 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2000 * @{
2001 */
2002 /**
2003 * @brief Configure an output channel.
2004 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2005 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2006 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2007 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2008 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2009 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2010 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2011 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2012 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2013 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2014 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2015 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2016 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2017 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2018 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2019 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2020 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2021 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2022 * @param TIMx Timer instance
2023 * @param Channel This parameter can be one of the following values:
2024 * @arg @ref LL_TIM_CHANNEL_CH1
2025 * @arg @ref LL_TIM_CHANNEL_CH2
2026 * @arg @ref LL_TIM_CHANNEL_CH3
2027 * @arg @ref LL_TIM_CHANNEL_CH4
2028 * @arg @ref LL_TIM_CHANNEL_CH5
2029 * @arg @ref LL_TIM_CHANNEL_CH6
2030 * @param Configuration This parameter must be a combination of all the following values:
2031 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2032 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2033 * @retval None
2034 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2035 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2036 {
2037 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2038 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2039 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2040 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2041 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2042 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2043 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2044 }
2045
2046 /**
2047 * @brief Define the behavior of the output reference signal OCxREF from which
2048 * OCx and OCxN (when relevant) are derived.
2049 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2050 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2051 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2052 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2053 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2054 * CCMR3 OC6M LL_TIM_OC_SetMode
2055 * @param TIMx Timer instance
2056 * @param Channel This parameter can be one of the following values:
2057 * @arg @ref LL_TIM_CHANNEL_CH1
2058 * @arg @ref LL_TIM_CHANNEL_CH2
2059 * @arg @ref LL_TIM_CHANNEL_CH3
2060 * @arg @ref LL_TIM_CHANNEL_CH4
2061 * @arg @ref LL_TIM_CHANNEL_CH5
2062 * @arg @ref LL_TIM_CHANNEL_CH6
2063 * @param Mode This parameter can be one of the following values:
2064 * @arg @ref LL_TIM_OCMODE_FROZEN
2065 * @arg @ref LL_TIM_OCMODE_ACTIVE
2066 * @arg @ref LL_TIM_OCMODE_INACTIVE
2067 * @arg @ref LL_TIM_OCMODE_TOGGLE
2068 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2069 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2070 * @arg @ref LL_TIM_OCMODE_PWM1
2071 * @arg @ref LL_TIM_OCMODE_PWM2
2072 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2073 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2074 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2075 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2076 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2077 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2078 * @retval None
2079 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2080 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2081 {
2082 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2083 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2084 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2085 }
2086
2087 /**
2088 * @brief Get the output compare mode of an output channel.
2089 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2090 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2091 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2092 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2093 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2094 * CCMR3 OC6M LL_TIM_OC_GetMode
2095 * @param TIMx Timer instance
2096 * @param Channel This parameter can be one of the following values:
2097 * @arg @ref LL_TIM_CHANNEL_CH1
2098 * @arg @ref LL_TIM_CHANNEL_CH2
2099 * @arg @ref LL_TIM_CHANNEL_CH3
2100 * @arg @ref LL_TIM_CHANNEL_CH4
2101 * @arg @ref LL_TIM_CHANNEL_CH5
2102 * @arg @ref LL_TIM_CHANNEL_CH6
2103 * @retval Returned value can be one of the following values:
2104 * @arg @ref LL_TIM_OCMODE_FROZEN
2105 * @arg @ref LL_TIM_OCMODE_ACTIVE
2106 * @arg @ref LL_TIM_OCMODE_INACTIVE
2107 * @arg @ref LL_TIM_OCMODE_TOGGLE
2108 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2109 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2110 * @arg @ref LL_TIM_OCMODE_PWM1
2111 * @arg @ref LL_TIM_OCMODE_PWM2
2112 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2113 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2114 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2115 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2116 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2117 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2118 */
LL_TIM_OC_GetMode(TIM_TypeDef * TIMx,uint32_t Channel)2119 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
2120 {
2121 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2122 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2123 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2124 }
2125
2126 /**
2127 * @brief Set the polarity of an output channel.
2128 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2129 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2130 * CCER CC2P LL_TIM_OC_SetPolarity\n
2131 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2132 * CCER CC3P LL_TIM_OC_SetPolarity\n
2133 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2134 * CCER CC4P LL_TIM_OC_SetPolarity\n
2135 * CCER CC5P LL_TIM_OC_SetPolarity\n
2136 * CCER CC6P LL_TIM_OC_SetPolarity
2137 * @param TIMx Timer instance
2138 * @param Channel This parameter can be one of the following values:
2139 * @arg @ref LL_TIM_CHANNEL_CH1
2140 * @arg @ref LL_TIM_CHANNEL_CH1N
2141 * @arg @ref LL_TIM_CHANNEL_CH2
2142 * @arg @ref LL_TIM_CHANNEL_CH2N
2143 * @arg @ref LL_TIM_CHANNEL_CH3
2144 * @arg @ref LL_TIM_CHANNEL_CH3N
2145 * @arg @ref LL_TIM_CHANNEL_CH4
2146 * @arg @ref LL_TIM_CHANNEL_CH5
2147 * @arg @ref LL_TIM_CHANNEL_CH6
2148 * @param Polarity This parameter can be one of the following values:
2149 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2150 * @arg @ref LL_TIM_OCPOLARITY_LOW
2151 * @retval None
2152 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2153 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2154 {
2155 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2156 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2157 }
2158
2159 /**
2160 * @brief Get the polarity of an output channel.
2161 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2162 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2163 * CCER CC2P LL_TIM_OC_GetPolarity\n
2164 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2165 * CCER CC3P LL_TIM_OC_GetPolarity\n
2166 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2167 * CCER CC4P LL_TIM_OC_GetPolarity\n
2168 * CCER CC5P LL_TIM_OC_GetPolarity\n
2169 * CCER CC6P LL_TIM_OC_GetPolarity
2170 * @param TIMx Timer instance
2171 * @param Channel This parameter can be one of the following values:
2172 * @arg @ref LL_TIM_CHANNEL_CH1
2173 * @arg @ref LL_TIM_CHANNEL_CH1N
2174 * @arg @ref LL_TIM_CHANNEL_CH2
2175 * @arg @ref LL_TIM_CHANNEL_CH2N
2176 * @arg @ref LL_TIM_CHANNEL_CH3
2177 * @arg @ref LL_TIM_CHANNEL_CH3N
2178 * @arg @ref LL_TIM_CHANNEL_CH4
2179 * @arg @ref LL_TIM_CHANNEL_CH5
2180 * @arg @ref LL_TIM_CHANNEL_CH6
2181 * @retval Returned value can be one of the following values:
2182 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2183 * @arg @ref LL_TIM_OCPOLARITY_LOW
2184 */
LL_TIM_OC_GetPolarity(TIM_TypeDef * TIMx,uint32_t Channel)2185 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2186 {
2187 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2188 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2189 }
2190
2191 /**
2192 * @brief Set the IDLE state of an output channel
2193 * @note This function is significant only for the timer instances
2194 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2195 * can be used to check whether or not a timer instance provides
2196 * a break input.
2197 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2198 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2199 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2200 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2201 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2202 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2203 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2204 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2205 * CR2 OIS6 LL_TIM_OC_SetIdleState
2206 * @param TIMx Timer instance
2207 * @param Channel This parameter can be one of the following values:
2208 * @arg @ref LL_TIM_CHANNEL_CH1
2209 * @arg @ref LL_TIM_CHANNEL_CH1N
2210 * @arg @ref LL_TIM_CHANNEL_CH2
2211 * @arg @ref LL_TIM_CHANNEL_CH2N
2212 * @arg @ref LL_TIM_CHANNEL_CH3
2213 * @arg @ref LL_TIM_CHANNEL_CH3N
2214 * @arg @ref LL_TIM_CHANNEL_CH4
2215 * @arg @ref LL_TIM_CHANNEL_CH5
2216 * @arg @ref LL_TIM_CHANNEL_CH6
2217 * @param IdleState This parameter can be one of the following values:
2218 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2219 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2220 * @retval None
2221 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2222 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2223 {
2224 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2225 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2226 }
2227
2228 /**
2229 * @brief Get the IDLE state of an output channel
2230 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2231 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2232 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2233 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2234 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2235 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2236 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2237 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2238 * CR2 OIS6 LL_TIM_OC_GetIdleState
2239 * @param TIMx Timer instance
2240 * @param Channel This parameter can be one of the following values:
2241 * @arg @ref LL_TIM_CHANNEL_CH1
2242 * @arg @ref LL_TIM_CHANNEL_CH1N
2243 * @arg @ref LL_TIM_CHANNEL_CH2
2244 * @arg @ref LL_TIM_CHANNEL_CH2N
2245 * @arg @ref LL_TIM_CHANNEL_CH3
2246 * @arg @ref LL_TIM_CHANNEL_CH3N
2247 * @arg @ref LL_TIM_CHANNEL_CH4
2248 * @arg @ref LL_TIM_CHANNEL_CH5
2249 * @arg @ref LL_TIM_CHANNEL_CH6
2250 * @retval Returned value can be one of the following values:
2251 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2252 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2253 */
LL_TIM_OC_GetIdleState(TIM_TypeDef * TIMx,uint32_t Channel)2254 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
2255 {
2256 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2257 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2258 }
2259
2260 /**
2261 * @brief Enable fast mode for the output channel.
2262 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2263 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2264 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2265 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2266 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2267 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2268 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2269 * @param TIMx Timer instance
2270 * @param Channel This parameter can be one of the following values:
2271 * @arg @ref LL_TIM_CHANNEL_CH1
2272 * @arg @ref LL_TIM_CHANNEL_CH2
2273 * @arg @ref LL_TIM_CHANNEL_CH3
2274 * @arg @ref LL_TIM_CHANNEL_CH4
2275 * @arg @ref LL_TIM_CHANNEL_CH5
2276 * @arg @ref LL_TIM_CHANNEL_CH6
2277 * @retval None
2278 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2279 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2280 {
2281 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2282 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2283 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2284
2285 }
2286
2287 /**
2288 * @brief Disable fast mode for the output channel.
2289 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2290 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2291 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2292 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2293 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2294 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2295 * @param TIMx Timer instance
2296 * @param Channel This parameter can be one of the following values:
2297 * @arg @ref LL_TIM_CHANNEL_CH1
2298 * @arg @ref LL_TIM_CHANNEL_CH2
2299 * @arg @ref LL_TIM_CHANNEL_CH3
2300 * @arg @ref LL_TIM_CHANNEL_CH4
2301 * @arg @ref LL_TIM_CHANNEL_CH5
2302 * @arg @ref LL_TIM_CHANNEL_CH6
2303 * @retval None
2304 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2305 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2306 {
2307 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2308 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2309 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2310
2311 }
2312
2313 /**
2314 * @brief Indicates whether fast mode is enabled for the output channel.
2315 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2316 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2317 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2318 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2319 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2320 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2321 * @param TIMx Timer instance
2322 * @param Channel This parameter can be one of the following values:
2323 * @arg @ref LL_TIM_CHANNEL_CH1
2324 * @arg @ref LL_TIM_CHANNEL_CH2
2325 * @arg @ref LL_TIM_CHANNEL_CH3
2326 * @arg @ref LL_TIM_CHANNEL_CH4
2327 * @arg @ref LL_TIM_CHANNEL_CH5
2328 * @arg @ref LL_TIM_CHANNEL_CH6
2329 * @retval State of bit (1 or 0).
2330 */
LL_TIM_OC_IsEnabledFast(TIM_TypeDef * TIMx,uint32_t Channel)2331 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
2332 {
2333 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2334 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2335 register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2336 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2337 }
2338
2339 /**
2340 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2341 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2342 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2343 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2344 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2345 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2346 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2347 * @param TIMx Timer instance
2348 * @param Channel This parameter can be one of the following values:
2349 * @arg @ref LL_TIM_CHANNEL_CH1
2350 * @arg @ref LL_TIM_CHANNEL_CH2
2351 * @arg @ref LL_TIM_CHANNEL_CH3
2352 * @arg @ref LL_TIM_CHANNEL_CH4
2353 * @arg @ref LL_TIM_CHANNEL_CH5
2354 * @arg @ref LL_TIM_CHANNEL_CH6
2355 * @retval None
2356 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2357 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2358 {
2359 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2360 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2361 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2362 }
2363
2364 /**
2365 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2366 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2367 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2368 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2369 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2370 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2371 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2372 * @param TIMx Timer instance
2373 * @param Channel This parameter can be one of the following values:
2374 * @arg @ref LL_TIM_CHANNEL_CH1
2375 * @arg @ref LL_TIM_CHANNEL_CH2
2376 * @arg @ref LL_TIM_CHANNEL_CH3
2377 * @arg @ref LL_TIM_CHANNEL_CH4
2378 * @arg @ref LL_TIM_CHANNEL_CH5
2379 * @arg @ref LL_TIM_CHANNEL_CH6
2380 * @retval None
2381 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2382 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2383 {
2384 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2385 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2386 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2387 }
2388
2389 /**
2390 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2391 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2392 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2393 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2394 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2395 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2396 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2397 * @param TIMx Timer instance
2398 * @param Channel This parameter can be one of the following values:
2399 * @arg @ref LL_TIM_CHANNEL_CH1
2400 * @arg @ref LL_TIM_CHANNEL_CH2
2401 * @arg @ref LL_TIM_CHANNEL_CH3
2402 * @arg @ref LL_TIM_CHANNEL_CH4
2403 * @arg @ref LL_TIM_CHANNEL_CH5
2404 * @arg @ref LL_TIM_CHANNEL_CH6
2405 * @retval State of bit (1 or 0).
2406 */
LL_TIM_OC_IsEnabledPreload(TIM_TypeDef * TIMx,uint32_t Channel)2407 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
2408 {
2409 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2410 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2411 register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2412 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2413 }
2414
2415 /**
2416 * @brief Enable clearing the output channel on an external event.
2417 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2418 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2419 * or not a timer instance can clear the OCxREF signal on an external event.
2420 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2421 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2422 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2423 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2424 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2425 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2426 * @param TIMx Timer instance
2427 * @param Channel This parameter can be one of the following values:
2428 * @arg @ref LL_TIM_CHANNEL_CH1
2429 * @arg @ref LL_TIM_CHANNEL_CH2
2430 * @arg @ref LL_TIM_CHANNEL_CH3
2431 * @arg @ref LL_TIM_CHANNEL_CH4
2432 * @arg @ref LL_TIM_CHANNEL_CH5
2433 * @arg @ref LL_TIM_CHANNEL_CH6
2434 * @retval None
2435 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2436 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2437 {
2438 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2439 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2440 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2441 }
2442
2443 /**
2444 * @brief Disable clearing the output channel on an external event.
2445 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2446 * or not a timer instance can clear the OCxREF signal on an external event.
2447 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2448 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2449 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2450 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2451 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2452 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2453 * @param TIMx Timer instance
2454 * @param Channel This parameter can be one of the following values:
2455 * @arg @ref LL_TIM_CHANNEL_CH1
2456 * @arg @ref LL_TIM_CHANNEL_CH2
2457 * @arg @ref LL_TIM_CHANNEL_CH3
2458 * @arg @ref LL_TIM_CHANNEL_CH4
2459 * @arg @ref LL_TIM_CHANNEL_CH5
2460 * @arg @ref LL_TIM_CHANNEL_CH6
2461 * @retval None
2462 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2463 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2464 {
2465 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2466 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2467 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2468 }
2469
2470 /**
2471 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2472 * @note This function enables clearing the output channel on an external event.
2473 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2474 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2475 * or not a timer instance can clear the OCxREF signal on an external event.
2476 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2477 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2478 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2479 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2480 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2481 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2482 * @param TIMx Timer instance
2483 * @param Channel This parameter can be one of the following values:
2484 * @arg @ref LL_TIM_CHANNEL_CH1
2485 * @arg @ref LL_TIM_CHANNEL_CH2
2486 * @arg @ref LL_TIM_CHANNEL_CH3
2487 * @arg @ref LL_TIM_CHANNEL_CH4
2488 * @arg @ref LL_TIM_CHANNEL_CH5
2489 * @arg @ref LL_TIM_CHANNEL_CH6
2490 * @retval State of bit (1 or 0).
2491 */
LL_TIM_OC_IsEnabledClear(TIM_TypeDef * TIMx,uint32_t Channel)2492 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
2493 {
2494 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2495 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2496 register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2497 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2498 }
2499
2500 /**
2501 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
2502 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2503 * dead-time insertion feature is supported by a timer instance.
2504 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2505 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2506 * @param TIMx Timer instance
2507 * @param DeadTime between Min_Data=0 and Max_Data=255
2508 * @retval None
2509 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2510 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2511 {
2512 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2513 }
2514
2515 /**
2516 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2517 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2518 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2519 * whether or not a timer instance supports a 32 bits counter.
2520 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2521 * output channel 1 is supported by a timer instance.
2522 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2523 * @param TIMx Timer instance
2524 * @param CompareValue between Min_Data=0 and Max_Data=65535
2525 * @retval None
2526 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2527 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2528 {
2529 WRITE_REG(TIMx->CCR1, CompareValue);
2530 }
2531
2532 /**
2533 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2534 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2535 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2536 * whether or not a timer instance supports a 32 bits counter.
2537 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2538 * output channel 2 is supported by a timer instance.
2539 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2540 * @param TIMx Timer instance
2541 * @param CompareValue between Min_Data=0 and Max_Data=65535
2542 * @retval None
2543 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2544 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2545 {
2546 WRITE_REG(TIMx->CCR2, CompareValue);
2547 }
2548
2549 /**
2550 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2551 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2552 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2553 * whether or not a timer instance supports a 32 bits counter.
2554 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2555 * output channel is supported by a timer instance.
2556 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2557 * @param TIMx Timer instance
2558 * @param CompareValue between Min_Data=0 and Max_Data=65535
2559 * @retval None
2560 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2561 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2562 {
2563 WRITE_REG(TIMx->CCR3, CompareValue);
2564 }
2565
2566 /**
2567 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2568 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2569 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2570 * whether or not a timer instance supports a 32 bits counter.
2571 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2572 * output channel 4 is supported by a timer instance.
2573 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2574 * @param TIMx Timer instance
2575 * @param CompareValue between Min_Data=0 and Max_Data=65535
2576 * @retval None
2577 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2578 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2579 {
2580 WRITE_REG(TIMx->CCR4, CompareValue);
2581 }
2582
2583 /**
2584 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2585 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2586 * output channel 5 is supported by a timer instance.
2587 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2588 * @param TIMx Timer instance
2589 * @param CompareValue between Min_Data=0 and Max_Data=65535
2590 * @retval None
2591 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2592 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2593 {
2594 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2595 }
2596
2597 /**
2598 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2599 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2600 * output channel 6 is supported by a timer instance.
2601 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2602 * @param TIMx Timer instance
2603 * @param CompareValue between Min_Data=0 and Max_Data=65535
2604 * @retval None
2605 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2606 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2607 {
2608 WRITE_REG(TIMx->CCR6, CompareValue);
2609 }
2610
2611 /**
2612 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2613 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2614 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2615 * whether or not a timer instance supports a 32 bits counter.
2616 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2617 * output channel 1 is supported by a timer instance.
2618 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2619 * @param TIMx Timer instance
2620 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2621 */
LL_TIM_OC_GetCompareCH1(TIM_TypeDef * TIMx)2622 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
2623 {
2624 return (uint32_t)(READ_REG(TIMx->CCR1));
2625 }
2626
2627 /**
2628 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2629 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2630 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2631 * whether or not a timer instance supports a 32 bits counter.
2632 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2633 * output channel 2 is supported by a timer instance.
2634 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2635 * @param TIMx Timer instance
2636 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2637 */
LL_TIM_OC_GetCompareCH2(TIM_TypeDef * TIMx)2638 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
2639 {
2640 return (uint32_t)(READ_REG(TIMx->CCR2));
2641 }
2642
2643 /**
2644 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2645 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2646 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2647 * whether or not a timer instance supports a 32 bits counter.
2648 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2649 * output channel 3 is supported by a timer instance.
2650 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2651 * @param TIMx Timer instance
2652 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2653 */
LL_TIM_OC_GetCompareCH3(TIM_TypeDef * TIMx)2654 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
2655 {
2656 return (uint32_t)(READ_REG(TIMx->CCR3));
2657 }
2658
2659 /**
2660 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2661 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2662 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2663 * whether or not a timer instance supports a 32 bits counter.
2664 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2665 * output channel 4 is supported by a timer instance.
2666 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2667 * @param TIMx Timer instance
2668 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2669 */
LL_TIM_OC_GetCompareCH4(TIM_TypeDef * TIMx)2670 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
2671 {
2672 return (uint32_t)(READ_REG(TIMx->CCR4));
2673 }
2674
2675 /**
2676 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2677 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2678 * output channel 5 is supported by a timer instance.
2679 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2680 * @param TIMx Timer instance
2681 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2682 */
LL_TIM_OC_GetCompareCH5(TIM_TypeDef * TIMx)2683 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
2684 {
2685 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2686 }
2687
2688 /**
2689 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2690 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2691 * output channel 6 is supported by a timer instance.
2692 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2693 * @param TIMx Timer instance
2694 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2695 */
LL_TIM_OC_GetCompareCH6(TIM_TypeDef * TIMx)2696 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
2697 {
2698 return (uint32_t)(READ_REG(TIMx->CCR6));
2699 }
2700
2701 /**
2702 * @brief Select on which reference signal the OC5REF is combined to.
2703 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2704 * whether or not a timer instance supports the combined 3-phase PWM mode.
2705 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2706 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2707 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2708 * @param TIMx Timer instance
2709 * @param GroupCH5 This parameter can be a combination of the following values:
2710 * @arg @ref LL_TIM_GROUPCH5_NONE
2711 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2712 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2713 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2714 * @retval None
2715 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2716 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2717 {
2718 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2719 }
2720
2721 /**
2722 * @}
2723 */
2724
2725 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2726 * @{
2727 */
2728 /**
2729 * @brief Configure input channel.
2730 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2731 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2732 * CCMR1 IC1F LL_TIM_IC_Config\n
2733 * CCMR1 CC2S LL_TIM_IC_Config\n
2734 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2735 * CCMR1 IC2F LL_TIM_IC_Config\n
2736 * CCMR2 CC3S LL_TIM_IC_Config\n
2737 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2738 * CCMR2 IC3F LL_TIM_IC_Config\n
2739 * CCMR2 CC4S LL_TIM_IC_Config\n
2740 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2741 * CCMR2 IC4F LL_TIM_IC_Config\n
2742 * CCER CC1P LL_TIM_IC_Config\n
2743 * CCER CC1NP LL_TIM_IC_Config\n
2744 * CCER CC2P LL_TIM_IC_Config\n
2745 * CCER CC2NP LL_TIM_IC_Config\n
2746 * CCER CC3P LL_TIM_IC_Config\n
2747 * CCER CC3NP LL_TIM_IC_Config\n
2748 * CCER CC4P LL_TIM_IC_Config\n
2749 * CCER CC4NP LL_TIM_IC_Config
2750 * @param TIMx Timer instance
2751 * @param Channel This parameter can be one of the following values:
2752 * @arg @ref LL_TIM_CHANNEL_CH1
2753 * @arg @ref LL_TIM_CHANNEL_CH2
2754 * @arg @ref LL_TIM_CHANNEL_CH3
2755 * @arg @ref LL_TIM_CHANNEL_CH4
2756 * @param Configuration This parameter must be a combination of all the following values:
2757 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2758 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2759 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2760 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2761 * @retval None
2762 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2763 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2764 {
2765 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2766 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2767 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2768 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
2769 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2770 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2771 }
2772
2773 /**
2774 * @brief Set the active input.
2775 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2776 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2777 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2778 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2779 * @param TIMx Timer instance
2780 * @param Channel This parameter can be one of the following values:
2781 * @arg @ref LL_TIM_CHANNEL_CH1
2782 * @arg @ref LL_TIM_CHANNEL_CH2
2783 * @arg @ref LL_TIM_CHANNEL_CH3
2784 * @arg @ref LL_TIM_CHANNEL_CH4
2785 * @param ICActiveInput This parameter can be one of the following values:
2786 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2787 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2788 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2789 * @retval None
2790 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2791 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2792 {
2793 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2794 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2795 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2796 }
2797
2798 /**
2799 * @brief Get the current active input.
2800 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2801 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2802 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2803 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2804 * @param TIMx Timer instance
2805 * @param Channel This parameter can be one of the following values:
2806 * @arg @ref LL_TIM_CHANNEL_CH1
2807 * @arg @ref LL_TIM_CHANNEL_CH2
2808 * @arg @ref LL_TIM_CHANNEL_CH3
2809 * @arg @ref LL_TIM_CHANNEL_CH4
2810 * @retval Returned value can be one of the following values:
2811 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2812 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2813 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2814 */
LL_TIM_IC_GetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel)2815 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
2816 {
2817 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2818 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2819 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2820 }
2821
2822 /**
2823 * @brief Set the prescaler of input channel.
2824 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2825 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2826 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2827 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2828 * @param TIMx Timer instance
2829 * @param Channel This parameter can be one of the following values:
2830 * @arg @ref LL_TIM_CHANNEL_CH1
2831 * @arg @ref LL_TIM_CHANNEL_CH2
2832 * @arg @ref LL_TIM_CHANNEL_CH3
2833 * @arg @ref LL_TIM_CHANNEL_CH4
2834 * @param ICPrescaler This parameter can be one of the following values:
2835 * @arg @ref LL_TIM_ICPSC_DIV1
2836 * @arg @ref LL_TIM_ICPSC_DIV2
2837 * @arg @ref LL_TIM_ICPSC_DIV4
2838 * @arg @ref LL_TIM_ICPSC_DIV8
2839 * @retval None
2840 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2841 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2842 {
2843 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2844 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2845 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2846 }
2847
2848 /**
2849 * @brief Get the current prescaler value acting on an input channel.
2850 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2851 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2852 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2853 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2854 * @param TIMx Timer instance
2855 * @param Channel This parameter can be one of the following values:
2856 * @arg @ref LL_TIM_CHANNEL_CH1
2857 * @arg @ref LL_TIM_CHANNEL_CH2
2858 * @arg @ref LL_TIM_CHANNEL_CH3
2859 * @arg @ref LL_TIM_CHANNEL_CH4
2860 * @retval Returned value can be one of the following values:
2861 * @arg @ref LL_TIM_ICPSC_DIV1
2862 * @arg @ref LL_TIM_ICPSC_DIV2
2863 * @arg @ref LL_TIM_ICPSC_DIV4
2864 * @arg @ref LL_TIM_ICPSC_DIV8
2865 */
LL_TIM_IC_GetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel)2866 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
2867 {
2868 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2869 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2870 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2871 }
2872
2873 /**
2874 * @brief Set the input filter duration.
2875 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2876 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2877 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2878 * CCMR2 IC4F LL_TIM_IC_SetFilter
2879 * @param TIMx Timer instance
2880 * @param Channel This parameter can be one of the following values:
2881 * @arg @ref LL_TIM_CHANNEL_CH1
2882 * @arg @ref LL_TIM_CHANNEL_CH2
2883 * @arg @ref LL_TIM_CHANNEL_CH3
2884 * @arg @ref LL_TIM_CHANNEL_CH4
2885 * @param ICFilter This parameter can be one of the following values:
2886 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2887 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2888 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2889 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2890 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2891 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2892 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2893 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2894 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2895 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2896 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2897 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2898 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2899 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2900 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2901 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2902 * @retval None
2903 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2904 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2905 {
2906 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2907 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2908 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2909 }
2910
2911 /**
2912 * @brief Get the input filter duration.
2913 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2914 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2915 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2916 * CCMR2 IC4F LL_TIM_IC_GetFilter
2917 * @param TIMx Timer instance
2918 * @param Channel This parameter can be one of the following values:
2919 * @arg @ref LL_TIM_CHANNEL_CH1
2920 * @arg @ref LL_TIM_CHANNEL_CH2
2921 * @arg @ref LL_TIM_CHANNEL_CH3
2922 * @arg @ref LL_TIM_CHANNEL_CH4
2923 * @retval Returned value can be one of the following values:
2924 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2925 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2926 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2927 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2928 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2929 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2930 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2931 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2932 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2933 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2934 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2935 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2936 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2937 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2938 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2939 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2940 */
LL_TIM_IC_GetFilter(TIM_TypeDef * TIMx,uint32_t Channel)2941 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
2942 {
2943 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2944 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2945 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2946 }
2947
2948 /**
2949 * @brief Set the input channel polarity.
2950 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2951 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2952 * CCER CC2P LL_TIM_IC_SetPolarity\n
2953 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2954 * CCER CC3P LL_TIM_IC_SetPolarity\n
2955 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2956 * CCER CC4P LL_TIM_IC_SetPolarity\n
2957 * CCER CC4NP LL_TIM_IC_SetPolarity
2958 * @param TIMx Timer instance
2959 * @param Channel This parameter can be one of the following values:
2960 * @arg @ref LL_TIM_CHANNEL_CH1
2961 * @arg @ref LL_TIM_CHANNEL_CH2
2962 * @arg @ref LL_TIM_CHANNEL_CH3
2963 * @arg @ref LL_TIM_CHANNEL_CH4
2964 * @param ICPolarity This parameter can be one of the following values:
2965 * @arg @ref LL_TIM_IC_POLARITY_RISING
2966 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2967 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2968 * @retval None
2969 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)2970 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2971 {
2972 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2973 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2974 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2975 }
2976
2977 /**
2978 * @brief Get the current input channel polarity.
2979 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2980 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2981 * CCER CC2P LL_TIM_IC_GetPolarity\n
2982 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2983 * CCER CC3P LL_TIM_IC_GetPolarity\n
2984 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2985 * CCER CC4P LL_TIM_IC_GetPolarity\n
2986 * CCER CC4NP LL_TIM_IC_GetPolarity
2987 * @param TIMx Timer instance
2988 * @param Channel This parameter can be one of the following values:
2989 * @arg @ref LL_TIM_CHANNEL_CH1
2990 * @arg @ref LL_TIM_CHANNEL_CH2
2991 * @arg @ref LL_TIM_CHANNEL_CH3
2992 * @arg @ref LL_TIM_CHANNEL_CH4
2993 * @retval Returned value can be one of the following values:
2994 * @arg @ref LL_TIM_IC_POLARITY_RISING
2995 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2996 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2997 */
LL_TIM_IC_GetPolarity(TIM_TypeDef * TIMx,uint32_t Channel)2998 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2999 {
3000 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3001 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3002 SHIFT_TAB_CCxP[iChannel]);
3003 }
3004
3005 /**
3006 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3007 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3008 * a timer instance provides an XOR input.
3009 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3010 * @param TIMx Timer instance
3011 * @retval None
3012 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3013 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3014 {
3015 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3016 }
3017
3018 /**
3019 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3020 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3021 * a timer instance provides an XOR input.
3022 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3023 * @param TIMx Timer instance
3024 * @retval None
3025 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3026 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3027 {
3028 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3029 }
3030
3031 /**
3032 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3033 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3034 * a timer instance provides an XOR input.
3035 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3036 * @param TIMx Timer instance
3037 * @retval State of bit (1 or 0).
3038 */
LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef * TIMx)3039 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
3040 {
3041 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3042 }
3043
3044 /**
3045 * @brief Get captured value for input channel 1.
3046 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3047 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3048 * whether or not a timer instance supports a 32 bits counter.
3049 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3050 * input channel 1 is supported by a timer instance.
3051 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3052 * @param TIMx Timer instance
3053 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3054 */
LL_TIM_IC_GetCaptureCH1(TIM_TypeDef * TIMx)3055 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
3056 {
3057 return (uint32_t)(READ_REG(TIMx->CCR1));
3058 }
3059
3060 /**
3061 * @brief Get captured value for input channel 2.
3062 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3063 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3064 * whether or not a timer instance supports a 32 bits counter.
3065 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3066 * input channel 2 is supported by a timer instance.
3067 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3068 * @param TIMx Timer instance
3069 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3070 */
LL_TIM_IC_GetCaptureCH2(TIM_TypeDef * TIMx)3071 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
3072 {
3073 return (uint32_t)(READ_REG(TIMx->CCR2));
3074 }
3075
3076 /**
3077 * @brief Get captured value for input channel 3.
3078 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3079 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3080 * whether or not a timer instance supports a 32 bits counter.
3081 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3082 * input channel 3 is supported by a timer instance.
3083 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3084 * @param TIMx Timer instance
3085 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3086 */
LL_TIM_IC_GetCaptureCH3(TIM_TypeDef * TIMx)3087 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
3088 {
3089 return (uint32_t)(READ_REG(TIMx->CCR3));
3090 }
3091
3092 /**
3093 * @brief Get captured value for input channel 4.
3094 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3095 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3096 * whether or not a timer instance supports a 32 bits counter.
3097 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3098 * input channel 4 is supported by a timer instance.
3099 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3100 * @param TIMx Timer instance
3101 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3102 */
LL_TIM_IC_GetCaptureCH4(TIM_TypeDef * TIMx)3103 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
3104 {
3105 return (uint32_t)(READ_REG(TIMx->CCR4));
3106 }
3107
3108 /**
3109 * @}
3110 */
3111
3112 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3113 * @{
3114 */
3115 /**
3116 * @brief Enable external clock mode 2.
3117 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3118 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3119 * whether or not a timer instance supports external clock mode2.
3120 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3121 * @param TIMx Timer instance
3122 * @retval None
3123 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3124 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3125 {
3126 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3127 }
3128
3129 /**
3130 * @brief Disable external clock mode 2.
3131 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3132 * whether or not a timer instance supports external clock mode2.
3133 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3134 * @param TIMx Timer instance
3135 * @retval None
3136 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3137 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3138 {
3139 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3140 }
3141
3142 /**
3143 * @brief Indicate whether external clock mode 2 is enabled.
3144 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3145 * whether or not a timer instance supports external clock mode2.
3146 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3147 * @param TIMx Timer instance
3148 * @retval State of bit (1 or 0).
3149 */
LL_TIM_IsEnabledExternalClock(TIM_TypeDef * TIMx)3150 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
3151 {
3152 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3153 }
3154
3155 /**
3156 * @brief Set the clock source of the counter clock.
3157 * @note when selected clock source is external clock mode 1, the timer input
3158 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3159 * function. This timer input must be configured by calling
3160 * the @ref LL_TIM_IC_Config() function.
3161 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3162 * whether or not a timer instance supports external clock mode1.
3163 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3164 * whether or not a timer instance supports external clock mode2.
3165 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3166 * SMCR ECE LL_TIM_SetClockSource
3167 * @param TIMx Timer instance
3168 * @param ClockSource This parameter can be one of the following values:
3169 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3170 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3171 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3172 * @retval None
3173 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3174 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3175 {
3176 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3177 }
3178
3179 /**
3180 * @brief Set the encoder interface mode.
3181 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3182 * whether or not a timer instance supports the encoder mode.
3183 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3184 * @param TIMx Timer instance
3185 * @param EncoderMode This parameter can be one of the following values:
3186 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3187 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3188 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3189 * @retval None
3190 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3191 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3192 {
3193 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3194 }
3195
3196 /**
3197 * @}
3198 */
3199
3200 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3201 * @{
3202 */
3203 /**
3204 * @brief Set the trigger output (TRGO) used for timer synchronization .
3205 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3206 * whether or not a timer instance can operate as a master timer.
3207 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3208 * @param TIMx Timer instance
3209 * @param TimerSynchronization This parameter can be one of the following values:
3210 * @arg @ref LL_TIM_TRGO_RESET
3211 * @arg @ref LL_TIM_TRGO_ENABLE
3212 * @arg @ref LL_TIM_TRGO_UPDATE
3213 * @arg @ref LL_TIM_TRGO_CC1IF
3214 * @arg @ref LL_TIM_TRGO_OC1REF
3215 * @arg @ref LL_TIM_TRGO_OC2REF
3216 * @arg @ref LL_TIM_TRGO_OC3REF
3217 * @arg @ref LL_TIM_TRGO_OC4REF
3218 * @retval None
3219 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3220 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3221 {
3222 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3223 }
3224
3225 /**
3226 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3227 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3228 * whether or not a timer instance can be used for ADC synchronization.
3229 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3230 * @param TIMx Timer Instance
3231 * @param ADCSynchronization This parameter can be one of the following values:
3232 * @arg @ref LL_TIM_TRGO2_RESET
3233 * @arg @ref LL_TIM_TRGO2_ENABLE
3234 * @arg @ref LL_TIM_TRGO2_UPDATE
3235 * @arg @ref LL_TIM_TRGO2_CC1F
3236 * @arg @ref LL_TIM_TRGO2_OC1
3237 * @arg @ref LL_TIM_TRGO2_OC2
3238 * @arg @ref LL_TIM_TRGO2_OC3
3239 * @arg @ref LL_TIM_TRGO2_OC4
3240 * @arg @ref LL_TIM_TRGO2_OC5
3241 * @arg @ref LL_TIM_TRGO2_OC6
3242 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3243 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3244 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3245 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3246 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3247 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3248 * @retval None
3249 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3250 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3251 {
3252 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3253 }
3254
3255 /**
3256 * @brief Set the synchronization mode of a slave timer.
3257 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3258 * a timer instance can operate as a slave timer.
3259 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3260 * @param TIMx Timer instance
3261 * @param SlaveMode This parameter can be one of the following values:
3262 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3263 * @arg @ref LL_TIM_SLAVEMODE_RESET
3264 * @arg @ref LL_TIM_SLAVEMODE_GATED
3265 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3266 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3267 * @retval None
3268 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3269 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3270 {
3271 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3272 }
3273
3274 /**
3275 * @brief Set the selects the trigger input to be used to synchronize the counter.
3276 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3277 * a timer instance can operate as a slave timer.
3278 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3279 * @param TIMx Timer instance
3280 * @param TriggerInput This parameter can be one of the following values:
3281 * @arg @ref LL_TIM_TS_ITR0
3282 * @arg @ref LL_TIM_TS_ITR1
3283 * @arg @ref LL_TIM_TS_ITR2
3284 * @arg @ref LL_TIM_TS_ITR3
3285 * @arg @ref LL_TIM_TS_TI1F_ED
3286 * @arg @ref LL_TIM_TS_TI1FP1
3287 * @arg @ref LL_TIM_TS_TI2FP2
3288 * @arg @ref LL_TIM_TS_ETRF
3289 * @retval None
3290 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3291 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3292 {
3293 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3294 }
3295
3296 /**
3297 * @brief Enable the Master/Slave mode.
3298 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3299 * a timer instance can operate as a slave timer.
3300 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3301 * @param TIMx Timer instance
3302 * @retval None
3303 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3304 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3305 {
3306 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3307 }
3308
3309 /**
3310 * @brief Disable the Master/Slave mode.
3311 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3312 * a timer instance can operate as a slave timer.
3313 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3314 * @param TIMx Timer instance
3315 * @retval None
3316 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3317 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3318 {
3319 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3320 }
3321
3322 /**
3323 * @brief Indicates whether the Master/Slave mode is enabled.
3324 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3325 * a timer instance can operate as a slave timer.
3326 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3327 * @param TIMx Timer instance
3328 * @retval State of bit (1 or 0).
3329 */
LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef * TIMx)3330 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
3331 {
3332 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3333 }
3334
3335 /**
3336 * @brief Configure the external trigger (ETR) input.
3337 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3338 * a timer instance provides an external trigger input.
3339 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3340 * SMCR ETPS LL_TIM_ConfigETR\n
3341 * SMCR ETF LL_TIM_ConfigETR
3342 * @param TIMx Timer instance
3343 * @param ETRPolarity This parameter can be one of the following values:
3344 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3345 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3346 * @param ETRPrescaler This parameter can be one of the following values:
3347 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3348 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3349 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3350 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3351 * @param ETRFilter This parameter can be one of the following values:
3352 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3353 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3354 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3355 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3356 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3357 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3358 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3359 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3360 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3361 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3362 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3363 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3364 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3365 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3366 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3367 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3368 * @retval None
3369 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3370 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3371 uint32_t ETRFilter)
3372 {
3373 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3374 }
3375
3376 /**
3377 * @brief Select the external trigger (ETR) input source.
3378 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3379 * not a timer instance supports ETR source selection.
3380 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3381 * @param TIMx Timer instance
3382 * @param ETRSource This parameter can be one of the following values:
3383 * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
3384 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
3385 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
3386 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
3387 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD1
3388 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD2
3389 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3
3390 * @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO
3391 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC1_AWD1
3392 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC1_AWD2
3393 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC1_AWD3
3394 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1
3395 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2
3396 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3
3397 * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
3398 * @arg @ref LL_TIM_TIM2_ETRSOURCE_RCC_LSE
3399 * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSA
3400 * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSB
3401 * @arg @ref LL_TIM_TIM2_ETRSOURCE_ETH_PPS
3402 * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
3403 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ETH_PPS
3404 * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO
3405 * @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO
3406 * @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSA
3407 * @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSB
3408 * @arg @ref LL_TIM_TIM5_ETRSOURCE_OTG_SOF
3409
3410 * @retval None
3411 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3412 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3413 {
3414
3415 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3416 }
3417
3418 /**
3419 * @}
3420 */
3421
3422 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3423 * @{
3424 */
3425 /**
3426 * @brief Enable the break function.
3427 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3428 * a timer instance provides a break input.
3429 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3430 * @param TIMx Timer instance
3431 * @retval None
3432 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3433 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3434 {
3435 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3436 }
3437
3438 /**
3439 * @brief Disable the break function.
3440 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3441 * @param TIMx Timer instance
3442 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3443 * a timer instance provides a break input.
3444 * @retval None
3445 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3446 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3447 {
3448 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3449 }
3450
3451 /**
3452 * @brief Configure the break input.
3453 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3454 * a timer instance provides a break input.
3455 * @note Bidirectional mode is only supported by advanced timer instances.
3456 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3457 * a timer instance is an advanced-control timer.
3458 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
3459 * in input mode and in open drain output mode. Any active Break event will
3460 * assert a low logic level on the Break input to indicate an internal break
3461 * event to external devices.
3462 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
3463 * LL_TIM_BREAK_AFMODE_INPUT.
3464 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3465 * BDTR BKF LL_TIM_ConfigBRK\n
3466 * BDTR BKBID LL_TIM_ConfigBRK
3467 * @param TIMx Timer instance
3468 * @param BreakPolarity This parameter can be one of the following values:
3469 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3470 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3471 * @param BreakFilter This parameter can be one of the following values:
3472 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3473 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3474 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3475 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3476 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3477 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3478 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3479 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3480 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3481 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3482 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3483 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3484 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3485 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3486 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3487 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3488 * @param BreakAFMode This parameter can be one of the following values:
3489 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
3490 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
3491 * @retval None
3492 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)3493 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
3494 uint32_t BreakAFMode)
3495 {
3496 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
3497 }
3498
3499 /**
3500 * @brief Disarm the break input (when it operates in bidirectional mode).
3501 * @note The break input can be disarmed only when it is configured in
3502 * bidirectional mode and when when MOE is reset.
3503 * @note Purpose is to be able to have the input voltage back to high-state,
3504 * whatever the time constant on the output .
3505 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
3506 * @param TIMx Timer instance
3507 * @retval None
3508 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)3509 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
3510 {
3511 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3512 }
3513
3514 /**
3515 * @brief Re-arm the break input (when it operates in bidirectional mode).
3516 * @note The Break input is automatically armed as soon as MOE bit is set.
3517 * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
3518 * @param TIMx Timer instance
3519 * @retval None
3520 */
LL_TIM_ReArmBRK(TIM_TypeDef * TIMx)3521 __STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
3522 {
3523 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3524 }
3525
3526 /**
3527 * @brief Enable the break 2 function.
3528 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3529 * a timer instance provides a second break input.
3530 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3531 * @param TIMx Timer instance
3532 * @retval None
3533 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3534 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3535 {
3536 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3537 }
3538
3539 /**
3540 * @brief Disable the break 2 function.
3541 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3542 * a timer instance provides a second break input.
3543 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3544 * @param TIMx Timer instance
3545 * @retval None
3546 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3547 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3548 {
3549 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3550 }
3551
3552 /**
3553 * @brief Configure the break 2 input.
3554 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3555 * a timer instance provides a second break input.
3556 * @note Bidirectional mode is only supported by advanced timer instances.
3557 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3558 * a timer instance is an advanced-control timer.
3559 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
3560 * in input mode and in open drain output mode. Any active Break event will
3561 * assert a low logic level on the Break 2 input to indicate an internal break
3562 * event to external devices.
3563 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
3564 * LL_TIM_BREAK2_AFMODE_INPUT.
3565 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3566 * BDTR BK2F LL_TIM_ConfigBRK2\n
3567 * BDTR BK2BID LL_TIM_ConfigBRK2
3568 * @param TIMx Timer instance
3569 * @param Break2Polarity This parameter can be one of the following values:
3570 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3571 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3572 * @param Break2Filter This parameter can be one of the following values:
3573 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3574 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3575 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3576 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3577 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3578 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3579 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3580 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3581 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3582 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3583 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3584 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3585 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3586 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3587 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3588 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3589 * @param Break2AFMode This parameter can be one of the following values:
3590 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
3591 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
3592 * @retval None
3593 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)3594 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
3595 uint32_t Break2AFMode)
3596 {
3597 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
3598 }
3599
3600 /**
3601 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
3602 * @note The break 2 input can be disarmed only when it is configured in
3603 * bidirectional mode and when when MOE is reset.
3604 * @note Purpose is to be able to have the input voltage back to high-state,
3605 * whatever the time constant on the output.
3606 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
3607 * @param TIMx Timer instance
3608 * @retval None
3609 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)3610 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
3611 {
3612 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3613 }
3614
3615 /**
3616 * @brief Re-arm the break 2 input (when it operates in bidirectional mode).
3617 * @note The Break 2 input is automatically armed as soon as MOE bit is set.
3618 * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
3619 * @param TIMx Timer instance
3620 * @retval None
3621 */
LL_TIM_ReArmBRK2(TIM_TypeDef * TIMx)3622 __STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
3623 {
3624 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3625 }
3626
3627 /**
3628 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3629 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3630 * a timer instance provides a break input.
3631 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3632 * BDTR OSSR LL_TIM_SetOffStates
3633 * @param TIMx Timer instance
3634 * @param OffStateIdle This parameter can be one of the following values:
3635 * @arg @ref LL_TIM_OSSI_DISABLE
3636 * @arg @ref LL_TIM_OSSI_ENABLE
3637 * @param OffStateRun This parameter can be one of the following values:
3638 * @arg @ref LL_TIM_OSSR_DISABLE
3639 * @arg @ref LL_TIM_OSSR_ENABLE
3640 * @retval None
3641 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3642 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3643 {
3644 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3645 }
3646
3647 /**
3648 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3649 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3650 * a timer instance provides a break input.
3651 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3652 * @param TIMx Timer instance
3653 * @retval None
3654 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3655 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3656 {
3657 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3658 }
3659
3660 /**
3661 * @brief Disable automatic output (MOE can be set only by software).
3662 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3663 * a timer instance provides a break input.
3664 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3665 * @param TIMx Timer instance
3666 * @retval None
3667 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3668 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3669 {
3670 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3671 }
3672
3673 /**
3674 * @brief Indicate whether automatic output is enabled.
3675 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3676 * a timer instance provides a break input.
3677 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3678 * @param TIMx Timer instance
3679 * @retval State of bit (1 or 0).
3680 */
LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef * TIMx)3681 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
3682 {
3683 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3684 }
3685
3686 /**
3687 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3688 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3689 * software and is reset in case of break or break2 event
3690 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3691 * a timer instance provides a break input.
3692 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3693 * @param TIMx Timer instance
3694 * @retval None
3695 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3696 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3697 {
3698 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3699 }
3700
3701 /**
3702 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3703 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3704 * software and is reset in case of break or break2 event.
3705 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3706 * a timer instance provides a break input.
3707 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3708 * @param TIMx Timer instance
3709 * @retval None
3710 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3711 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3712 {
3713 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3714 }
3715
3716 /**
3717 * @brief Indicates whether outputs are enabled.
3718 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3719 * a timer instance provides a break input.
3720 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3721 * @param TIMx Timer instance
3722 * @retval State of bit (1 or 0).
3723 */
LL_TIM_IsEnabledAllOutputs(TIM_TypeDef * TIMx)3724 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
3725 {
3726 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3727 }
3728
3729 /**
3730 * @brief Enable the signals connected to the designated timer break input.
3731 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3732 * or not a timer instance allows for break input selection.
3733 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
3734 * AF1 BKDF1BK0E LL_TIM_EnableBreakInputSource\n
3735 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
3736 * AF2 BK2DF1BK1E LL_TIM_EnableBreakInputSource
3737 * @param TIMx Timer instance
3738 * @param BreakInput This parameter can be one of the following values:
3739 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3740 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3741 * @param Source This parameter can be one of the following values:
3742 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3743 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3744 * @retval None
3745 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3746 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3747 {
3748 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3749 SET_BIT(*pReg, Source);
3750 }
3751
3752 /**
3753 * @brief Disable the signals connected to the designated timer break input.
3754 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3755 * or not a timer instance allows for break input selection.
3756 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
3757 * AF1 BKDF1BK0E LL_TIM_DisableBreakInputSource\n
3758 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
3759 * AF2 BK2DF1BK1E LL_TIM_DisableBreakInputSource
3760 * @param TIMx Timer instance
3761 * @param BreakInput This parameter can be one of the following values:
3762 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3763 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3764 * @param Source This parameter can be one of the following values:
3765 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3766 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3767 * @retval None
3768 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3769 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3770 {
3771 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3772 CLEAR_BIT(*pReg, Source);
3773 }
3774
3775 /**
3776 * @brief Set the polarity of the break signal for the timer break input.
3777 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3778 * or not a timer instance allows for break input selection.
3779 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3780 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3781 * @param TIMx Timer instance
3782 * @param BreakInput This parameter can be one of the following values:
3783 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3784 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3785 * @param Source This parameter can be one of the following values:
3786 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3787 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3788 * @param Polarity This parameter can be one of the following values:
3789 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
3790 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3791 * @retval None
3792 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)3793 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3794 uint32_t Polarity)
3795 {
3796 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3797 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
3798 }
3799 /**
3800 * @}
3801 */
3802
3803 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3804 * @{
3805 */
3806 /**
3807 * @brief Configures the timer DMA burst feature.
3808 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3809 * not a timer instance supports the DMA burst mode.
3810 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3811 * DCR DBA LL_TIM_ConfigDMABurst
3812 * @param TIMx Timer instance
3813 * @param DMABurstBaseAddress This parameter can be one of the following values:
3814 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3815 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3816 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3817 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3818 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3819 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3820 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3821 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3822 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3823 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3824 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3825 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3826 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3827 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3828 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3829 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3830 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3831 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3832 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3833 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3834 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3835 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
3836 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
3837 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
3838 * @param DMABurstLength This parameter can be one of the following values:
3839 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3840 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3841 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3842 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3843 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3844 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3845 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3846 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3847 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3848 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3849 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3850 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3851 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3852 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3853 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3854 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3855 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3856 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3857 * @retval None
3858 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3859 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3860 {
3861 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3862 }
3863
3864 /**
3865 * @}
3866 */
3867
3868 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3869 * @{
3870 */
3871 /**
3872 * @brief Remap TIM inputs (input channel, internal/external triggers).
3873 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3874 * a some timer inputs can be remapped.
3875 * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
3876 * TIM1_TISEL TI2SEL LL_TIM_SetRemap\n
3877 * TIM1_TISEL TI3SEL LL_TIM_SetRemap\n
3878 * TIM1_TISEL TI4SEL LL_TIM_SetRemap\n
3879 * TIM8_TISEL TI1SEL LL_TIM_SetRemap\n
3880 * TIM8_TISEL TI2SEL LL_TIM_SetRemap\n
3881 * TIM8_TISEL TI3SEL LL_TIM_SetRemap\n
3882 * TIM8_TISEL TI4SEL LL_TIM_SetRemap\n
3883 * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
3884 * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
3885 * TIM2_TISEL TI3SEL LL_TIM_SetRemap\n
3886 * TIM2_TISEL TI4SEL LL_TIM_SetRemap\n
3887 * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
3888 * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
3889 * TIM3_TISEL TI3SEL LL_TIM_SetRemap\n
3890 * TIM4_TISEL TI1SEL LL_TIM_SetRemap\n
3891 * TIM4_TISEL TI2SEL LL_TIM_SetRemap\n
3892 * TIM4_TISEL TI3SEL LL_TIM_SetRemap\n
3893 * TIM4_TISEL TI4SEL LL_TIM_SetRemap\n
3894 * TIM5_TISEL TI1SEL LL_TIM_SetRemap\n
3895 * TIM5_TISEL TI2SEL LL_TIM_SetRemap\n
3896 * TIM5_TISEL TI3SEL LL_TIM_SetRemap\n
3897 * TIM5_TISEL TI4SEL LL_TIM_SetRemap\n
3898 * TIM12_TISEL TI1SEL LL_TIM_SetRemap\n
3899 * TIM12_TISEL TI2SEL LL_TIM_SetRemap\n
3900 * TIM13_TISEL TI1SEL LL_TIM_SetRemap\n
3901 * TIM14_TISEL TI1SEL LL_TIM_SetRemap\n
3902 * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n
3903 * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
3904 * TIM17_TISEL TI1SEL LL_TIM_SetRemap
3905 * @param TIMx Timer instance
3906 * @param Remap Remap param depends on the TIMx. Description available only
3907 * in CHM version of the User Manual (not in .pdf).
3908 * Otherwise see Reference Manual description of TISEL registers.
3909 *
3910 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3911 *
3912 * TIM1: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
3913 *
3914 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
3915 * @arg @ref LL_TIM_TIM1_TI2_RMP_GPIO
3916 * @arg @ref LL_TIM_TIM1_TI3_RMP_GPIO
3917 * @arg @ref LL_TIM_TIM1_TI4_RMP_GPIO
3918 *
3919 * TIM8: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
3920 *
3921 * @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
3922 * @arg @ref LL_TIM_TIM8_TI2_RMP_GPIO
3923 * @arg @ref LL_TIM_TIM8_TI3_RMP_GPIO
3924 * @arg @ref LL_TIM_TIM8_TI4_RMP_GPIO
3925 *
3926 * TIM2: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
3927 *
3928 * @arg @ref LL_TIM_TIM2_TI1_RMP_GPIO
3929 * @arg @ref LL_TIM_TIM2_TI2_RMP_GPIO
3930 * @arg @ref LL_TIM_TIM2_TI3_RMP_GPIO
3931 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
3932 *
3933 * TIM3: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
3934 *
3935 * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
3936 * @arg @ref LL_TIM_TIM3_TI2_RMP_GPIO
3937 * @arg @ref LL_TIM_TIM3_TI3_RMP_GPIO
3938 * @arg @ref LL_TIM_TIM3_TI4_RMP_GPIO
3939 *
3940 * TIM4: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
3941 *
3942 * @arg @ref LL_TIM_TIM4_TI1_RMP_GPIO
3943 * @arg @ref LL_TIM_TIM4_TI2_RMP_GPIO
3944 * @arg @ref LL_TIM_TIM4_TI3_RMP_GPIO
3945 * @arg @ref LL_TIM_TIM4_TI4_RMP_GPIO
3946 *
3947 *
3948 * TIM5: any combination of TI1_RMP and TI2_RMP, TI3_RMP and TI4_RMP where
3949 *
3950 * . . TI1_RMP can be one of the following values
3951 * @arg @ref LL_TIM_TIM5_TI1_RMP_GPIO
3952 * @arg @ref LL_TIM_TIM5_TI1_RMP_FDCAN1_TMP
3953 * @arg @ref LL_TIM_TIM5_TI1_RMP_FDCAN1_RTP
3954 *
3955 * . . TI2_RMP can be one of the following values
3956 * @arg @ref LL_TIM_TIM5_TI2_RMP_GPIO
3957 *
3958 * . . TI3_RMP can be one of the following values
3959 * @arg @ref LL_TIM_TIM5_TI3_RMP_GPIO
3960 *
3961 * . . TI4_RMP can be one of the following values
3962 * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
3963 *
3964 * TIM12: any combination of TI1_RMP and TI2_RMP where
3965 *
3966 * @arg @ref LL_TIM_TIM12_TI1_RMP_GPIO
3967 * @arg @ref LL_TIM_TIM12_TI1_RMP_HSI_CAL_CK
3968 * @arg @ref LL_TIM_TIM12_TI1_RMP_CSI_CAL_CK
3969 * @arg @ref LL_TIM_TIM12_TI2_RMP_GPIO
3970 *
3971 * TIM13: any combination of TI1_RMP where
3972 *
3973 * @arg @ref LL_TIM_TIM13_TI1_RMP_GPIO
3974 *
3975 * TIM14: any combination of TI1_RMP where
3976 *
3977 * @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO
3978 *
3979 * TIM15: any combination of TI1_RMP and TI2_RMP where
3980 *
3981 * . . TI1_RMP can be one of the following values
3982 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
3983 * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM2_CH1
3984 * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM3_CH1
3985 * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM4_CH1
3986 * @arg @ref LL_TIM_TIM15_TI1_RMP_RCC_LSE
3987 * @arg @ref LL_TIM_TIM15_TI1_RMP_RCC_CSI
3988 * @arg @ref LL_TIM_TIM15_TI1_RMP_RCC_MCO2
3989 * @arg @ref LL_TIM_TIM15_TI1_RMP_HSI_CAL_CK
3990 * @arg @ref LL_TIM_TIM15_TI1_RMP_CSI_CAL_CK
3991 *
3992 * . . TI2_RMP can be one of the following values
3993 * @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO
3994 * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM2_CH2
3995 * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM3_CH2
3996 * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM4_CH2
3997 *
3998 * TIM16: one of the following values
3999 *
4000 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
4001 * @arg @ref LL_TIM_TIM16_TI1_RMP_RCC_LSI
4002 * @arg @ref LL_TIM_TIM16_TI1_RMP_RCC_LSE
4003 * @arg @ref LL_TIM_TIM16_TI1_RMP_WKUP_IT
4004 *
4005 * TIM17: one of the following values
4006 *
4007 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
4008 * @arg @ref LL_TIM_TIM17_TI1_RMP_SPDIFRX_FS
4009 * @arg @ref LL_TIM_TIM17_TI1_RMP_RCC_HSE_RTC
4010 * @arg @ref LL_TIM_TIM17_TI1_RMP_RCC_MCO1
4011 *
4012 *
4013 * @retval None
4014 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)4015 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
4016 {
4017 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
4018 }
4019
4020 /**
4021 * @}
4022 */
4023
4024 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4025 * @{
4026 */
4027 /**
4028 * @brief Clear the update interrupt flag (UIF).
4029 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
4030 * @param TIMx Timer instance
4031 * @retval None
4032 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)4033 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
4034 {
4035 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
4036 }
4037
4038 /**
4039 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
4040 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
4041 * @param TIMx Timer instance
4042 * @retval State of bit (1 or 0).
4043 */
LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef * TIMx)4044 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
4045 {
4046 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
4047 }
4048
4049 /**
4050 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
4051 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
4052 * @param TIMx Timer instance
4053 * @retval None
4054 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)4055 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
4056 {
4057 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
4058 }
4059
4060 /**
4061 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
4062 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
4063 * @param TIMx Timer instance
4064 * @retval State of bit (1 or 0).
4065 */
LL_TIM_IsActiveFlag_CC1(TIM_TypeDef * TIMx)4066 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
4067 {
4068 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
4069 }
4070
4071 /**
4072 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4073 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4074 * @param TIMx Timer instance
4075 * @retval None
4076 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)4077 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4078 {
4079 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4080 }
4081
4082 /**
4083 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4084 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4085 * @param TIMx Timer instance
4086 * @retval State of bit (1 or 0).
4087 */
LL_TIM_IsActiveFlag_CC2(TIM_TypeDef * TIMx)4088 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
4089 {
4090 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
4091 }
4092
4093 /**
4094 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4095 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4096 * @param TIMx Timer instance
4097 * @retval None
4098 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)4099 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4100 {
4101 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4102 }
4103
4104 /**
4105 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4106 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4107 * @param TIMx Timer instance
4108 * @retval State of bit (1 or 0).
4109 */
LL_TIM_IsActiveFlag_CC3(TIM_TypeDef * TIMx)4110 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
4111 {
4112 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4113 }
4114
4115 /**
4116 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4117 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4118 * @param TIMx Timer instance
4119 * @retval None
4120 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)4121 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4122 {
4123 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4124 }
4125
4126 /**
4127 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4128 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4129 * @param TIMx Timer instance
4130 * @retval State of bit (1 or 0).
4131 */
LL_TIM_IsActiveFlag_CC4(TIM_TypeDef * TIMx)4132 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
4133 {
4134 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4135 }
4136
4137 /**
4138 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4139 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4140 * @param TIMx Timer instance
4141 * @retval None
4142 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4143 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4144 {
4145 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4146 }
4147
4148 /**
4149 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4150 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4151 * @param TIMx Timer instance
4152 * @retval State of bit (1 or 0).
4153 */
LL_TIM_IsActiveFlag_CC5(TIM_TypeDef * TIMx)4154 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
4155 {
4156 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4157 }
4158
4159 /**
4160 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4161 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4162 * @param TIMx Timer instance
4163 * @retval None
4164 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4165 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4166 {
4167 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4168 }
4169
4170 /**
4171 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4172 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4173 * @param TIMx Timer instance
4174 * @retval State of bit (1 or 0).
4175 */
LL_TIM_IsActiveFlag_CC6(TIM_TypeDef * TIMx)4176 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
4177 {
4178 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4179 }
4180
4181 /**
4182 * @brief Clear the commutation interrupt flag (COMIF).
4183 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4184 * @param TIMx Timer instance
4185 * @retval None
4186 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4187 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4188 {
4189 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4190 }
4191
4192 /**
4193 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4194 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4195 * @param TIMx Timer instance
4196 * @retval State of bit (1 or 0).
4197 */
LL_TIM_IsActiveFlag_COM(TIM_TypeDef * TIMx)4198 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
4199 {
4200 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4201 }
4202
4203 /**
4204 * @brief Clear the trigger interrupt flag (TIF).
4205 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4206 * @param TIMx Timer instance
4207 * @retval None
4208 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)4209 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4210 {
4211 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4212 }
4213
4214 /**
4215 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4216 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4217 * @param TIMx Timer instance
4218 * @retval State of bit (1 or 0).
4219 */
LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef * TIMx)4220 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
4221 {
4222 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4223 }
4224
4225 /**
4226 * @brief Clear the break interrupt flag (BIF).
4227 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4228 * @param TIMx Timer instance
4229 * @retval None
4230 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)4231 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4232 {
4233 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4234 }
4235
4236 /**
4237 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4238 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4239 * @param TIMx Timer instance
4240 * @retval State of bit (1 or 0).
4241 */
LL_TIM_IsActiveFlag_BRK(TIM_TypeDef * TIMx)4242 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
4243 {
4244 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4245 }
4246
4247 /**
4248 * @brief Clear the break 2 interrupt flag (B2IF).
4249 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4250 * @param TIMx Timer instance
4251 * @retval None
4252 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)4253 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4254 {
4255 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4256 }
4257
4258 /**
4259 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4260 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4261 * @param TIMx Timer instance
4262 * @retval State of bit (1 or 0).
4263 */
LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef * TIMx)4264 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
4265 {
4266 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4267 }
4268
4269 /**
4270 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4271 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4272 * @param TIMx Timer instance
4273 * @retval None
4274 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)4275 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4276 {
4277 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4278 }
4279
4280 /**
4281 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
4282 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4283 * @param TIMx Timer instance
4284 * @retval State of bit (1 or 0).
4285 */
LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef * TIMx)4286 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
4287 {
4288 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4289 }
4290
4291 /**
4292 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4293 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4294 * @param TIMx Timer instance
4295 * @retval None
4296 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)4297 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4298 {
4299 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4300 }
4301
4302 /**
4303 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
4304 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4305 * @param TIMx Timer instance
4306 * @retval State of bit (1 or 0).
4307 */
LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef * TIMx)4308 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
4309 {
4310 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4311 }
4312
4313 /**
4314 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4315 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4316 * @param TIMx Timer instance
4317 * @retval None
4318 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)4319 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4320 {
4321 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4322 }
4323
4324 /**
4325 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
4326 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4327 * @param TIMx Timer instance
4328 * @retval State of bit (1 or 0).
4329 */
LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef * TIMx)4330 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
4331 {
4332 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4333 }
4334
4335 /**
4336 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4337 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4338 * @param TIMx Timer instance
4339 * @retval None
4340 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)4341 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4342 {
4343 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4344 }
4345
4346 /**
4347 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
4348 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4349 * @param TIMx Timer instance
4350 * @retval State of bit (1 or 0).
4351 */
LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef * TIMx)4352 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
4353 {
4354 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4355 }
4356
4357 /**
4358 * @brief Clear the system break interrupt flag (SBIF).
4359 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4360 * @param TIMx Timer instance
4361 * @retval None
4362 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)4363 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4364 {
4365 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4366 }
4367
4368 /**
4369 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4370 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4371 * @param TIMx Timer instance
4372 * @retval State of bit (1 or 0).
4373 */
LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef * TIMx)4374 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
4375 {
4376 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4377 }
4378
4379 /**
4380 * @}
4381 */
4382
4383 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4384 * @{
4385 */
4386 /**
4387 * @brief Enable update interrupt (UIE).
4388 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4389 * @param TIMx Timer instance
4390 * @retval None
4391 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)4392 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4393 {
4394 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4395 }
4396
4397 /**
4398 * @brief Disable update interrupt (UIE).
4399 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4400 * @param TIMx Timer instance
4401 * @retval None
4402 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)4403 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4404 {
4405 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4406 }
4407
4408 /**
4409 * @brief Indicates whether the update interrupt (UIE) is enabled.
4410 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4411 * @param TIMx Timer instance
4412 * @retval State of bit (1 or 0).
4413 */
LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef * TIMx)4414 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
4415 {
4416 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4417 }
4418
4419 /**
4420 * @brief Enable capture/compare 1 interrupt (CC1IE).
4421 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4422 * @param TIMx Timer instance
4423 * @retval None
4424 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4425 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4426 {
4427 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4428 }
4429
4430 /**
4431 * @brief Disable capture/compare 1 interrupt (CC1IE).
4432 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4433 * @param TIMx Timer instance
4434 * @retval None
4435 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4436 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4437 {
4438 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4439 }
4440
4441 /**
4442 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4443 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4444 * @param TIMx Timer instance
4445 * @retval State of bit (1 or 0).
4446 */
LL_TIM_IsEnabledIT_CC1(TIM_TypeDef * TIMx)4447 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
4448 {
4449 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4450 }
4451
4452 /**
4453 * @brief Enable capture/compare 2 interrupt (CC2IE).
4454 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4455 * @param TIMx Timer instance
4456 * @retval None
4457 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4458 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4459 {
4460 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4461 }
4462
4463 /**
4464 * @brief Disable capture/compare 2 interrupt (CC2IE).
4465 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4466 * @param TIMx Timer instance
4467 * @retval None
4468 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4469 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4470 {
4471 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4472 }
4473
4474 /**
4475 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4476 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4477 * @param TIMx Timer instance
4478 * @retval State of bit (1 or 0).
4479 */
LL_TIM_IsEnabledIT_CC2(TIM_TypeDef * TIMx)4480 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
4481 {
4482 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4483 }
4484
4485 /**
4486 * @brief Enable capture/compare 3 interrupt (CC3IE).
4487 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4488 * @param TIMx Timer instance
4489 * @retval None
4490 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4491 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4492 {
4493 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4494 }
4495
4496 /**
4497 * @brief Disable capture/compare 3 interrupt (CC3IE).
4498 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4499 * @param TIMx Timer instance
4500 * @retval None
4501 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4502 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4503 {
4504 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4505 }
4506
4507 /**
4508 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4509 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4510 * @param TIMx Timer instance
4511 * @retval State of bit (1 or 0).
4512 */
LL_TIM_IsEnabledIT_CC3(TIM_TypeDef * TIMx)4513 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
4514 {
4515 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4516 }
4517
4518 /**
4519 * @brief Enable capture/compare 4 interrupt (CC4IE).
4520 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4521 * @param TIMx Timer instance
4522 * @retval None
4523 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4524 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4525 {
4526 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4527 }
4528
4529 /**
4530 * @brief Disable capture/compare 4 interrupt (CC4IE).
4531 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4532 * @param TIMx Timer instance
4533 * @retval None
4534 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4535 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4536 {
4537 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4538 }
4539
4540 /**
4541 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4542 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4543 * @param TIMx Timer instance
4544 * @retval State of bit (1 or 0).
4545 */
LL_TIM_IsEnabledIT_CC4(TIM_TypeDef * TIMx)4546 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
4547 {
4548 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4549 }
4550
4551 /**
4552 * @brief Enable commutation interrupt (COMIE).
4553 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4554 * @param TIMx Timer instance
4555 * @retval None
4556 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4557 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4558 {
4559 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4560 }
4561
4562 /**
4563 * @brief Disable commutation interrupt (COMIE).
4564 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4565 * @param TIMx Timer instance
4566 * @retval None
4567 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4568 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4569 {
4570 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4571 }
4572
4573 /**
4574 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4575 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4576 * @param TIMx Timer instance
4577 * @retval State of bit (1 or 0).
4578 */
LL_TIM_IsEnabledIT_COM(TIM_TypeDef * TIMx)4579 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
4580 {
4581 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4582 }
4583
4584 /**
4585 * @brief Enable trigger interrupt (TIE).
4586 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4587 * @param TIMx Timer instance
4588 * @retval None
4589 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4590 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4591 {
4592 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4593 }
4594
4595 /**
4596 * @brief Disable trigger interrupt (TIE).
4597 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4598 * @param TIMx Timer instance
4599 * @retval None
4600 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4601 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4602 {
4603 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4604 }
4605
4606 /**
4607 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4608 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4609 * @param TIMx Timer instance
4610 * @retval State of bit (1 or 0).
4611 */
LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef * TIMx)4612 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
4613 {
4614 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4615 }
4616
4617 /**
4618 * @brief Enable break interrupt (BIE).
4619 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4620 * @param TIMx Timer instance
4621 * @retval None
4622 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4623 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4624 {
4625 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4626 }
4627
4628 /**
4629 * @brief Disable break interrupt (BIE).
4630 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4631 * @param TIMx Timer instance
4632 * @retval None
4633 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4634 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4635 {
4636 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4637 }
4638
4639 /**
4640 * @brief Indicates whether the break interrupt (BIE) is enabled.
4641 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4642 * @param TIMx Timer instance
4643 * @retval State of bit (1 or 0).
4644 */
LL_TIM_IsEnabledIT_BRK(TIM_TypeDef * TIMx)4645 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
4646 {
4647 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4648 }
4649
4650 /**
4651 * @}
4652 */
4653
4654 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management
4655 * @{
4656 */
4657 /**
4658 * @brief Enable update DMA request (UDE).
4659 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4660 * @param TIMx Timer instance
4661 * @retval None
4662 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4663 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4664 {
4665 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4666 }
4667
4668 /**
4669 * @brief Disable update DMA request (UDE).
4670 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4671 * @param TIMx Timer instance
4672 * @retval None
4673 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4674 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4675 {
4676 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4677 }
4678
4679 /**
4680 * @brief Indicates whether the update DMA request (UDE) is enabled.
4681 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4682 * @param TIMx Timer instance
4683 * @retval State of bit (1 or 0).
4684 */
LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef * TIMx)4685 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
4686 {
4687 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4688 }
4689
4690 /**
4691 * @brief Enable capture/compare 1 DMA request (CC1DE).
4692 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4693 * @param TIMx Timer instance
4694 * @retval None
4695 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4696 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4697 {
4698 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4699 }
4700
4701 /**
4702 * @brief Disable capture/compare 1 DMA request (CC1DE).
4703 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4704 * @param TIMx Timer instance
4705 * @retval None
4706 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4707 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4708 {
4709 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4710 }
4711
4712 /**
4713 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4714 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4715 * @param TIMx Timer instance
4716 * @retval State of bit (1 or 0).
4717 */
LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef * TIMx)4718 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
4719 {
4720 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4721 }
4722
4723 /**
4724 * @brief Enable capture/compare 2 DMA request (CC2DE).
4725 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4726 * @param TIMx Timer instance
4727 * @retval None
4728 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4729 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4730 {
4731 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4732 }
4733
4734 /**
4735 * @brief Disable capture/compare 2 DMA request (CC2DE).
4736 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4737 * @param TIMx Timer instance
4738 * @retval None
4739 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4740 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4741 {
4742 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4743 }
4744
4745 /**
4746 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4747 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4748 * @param TIMx Timer instance
4749 * @retval State of bit (1 or 0).
4750 */
LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef * TIMx)4751 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
4752 {
4753 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4754 }
4755
4756 /**
4757 * @brief Enable capture/compare 3 DMA request (CC3DE).
4758 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4759 * @param TIMx Timer instance
4760 * @retval None
4761 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4762 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4763 {
4764 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4765 }
4766
4767 /**
4768 * @brief Disable capture/compare 3 DMA request (CC3DE).
4769 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4770 * @param TIMx Timer instance
4771 * @retval None
4772 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)4773 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4774 {
4775 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4776 }
4777
4778 /**
4779 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4780 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4781 * @param TIMx Timer instance
4782 * @retval State of bit (1 or 0).
4783 */
LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef * TIMx)4784 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
4785 {
4786 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4787 }
4788
4789 /**
4790 * @brief Enable capture/compare 4 DMA request (CC4DE).
4791 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4792 * @param TIMx Timer instance
4793 * @retval None
4794 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)4795 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4796 {
4797 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4798 }
4799
4800 /**
4801 * @brief Disable capture/compare 4 DMA request (CC4DE).
4802 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4803 * @param TIMx Timer instance
4804 * @retval None
4805 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)4806 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4807 {
4808 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4809 }
4810
4811 /**
4812 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4813 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4814 * @param TIMx Timer instance
4815 * @retval State of bit (1 or 0).
4816 */
LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef * TIMx)4817 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
4818 {
4819 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4820 }
4821
4822 /**
4823 * @brief Enable commutation DMA request (COMDE).
4824 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4825 * @param TIMx Timer instance
4826 * @retval None
4827 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)4828 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4829 {
4830 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4831 }
4832
4833 /**
4834 * @brief Disable commutation DMA request (COMDE).
4835 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4836 * @param TIMx Timer instance
4837 * @retval None
4838 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)4839 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4840 {
4841 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4842 }
4843
4844 /**
4845 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4846 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4847 * @param TIMx Timer instance
4848 * @retval State of bit (1 or 0).
4849 */
LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef * TIMx)4850 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
4851 {
4852 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4853 }
4854
4855 /**
4856 * @brief Enable trigger interrupt (TDE).
4857 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4858 * @param TIMx Timer instance
4859 * @retval None
4860 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)4861 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4862 {
4863 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4864 }
4865
4866 /**
4867 * @brief Disable trigger interrupt (TDE).
4868 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4869 * @param TIMx Timer instance
4870 * @retval None
4871 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)4872 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4873 {
4874 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4875 }
4876
4877 /**
4878 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4879 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4880 * @param TIMx Timer instance
4881 * @retval State of bit (1 or 0).
4882 */
LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef * TIMx)4883 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
4884 {
4885 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4886 }
4887
4888 /**
4889 * @}
4890 */
4891
4892 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4893 * @{
4894 */
4895 /**
4896 * @brief Generate an update event.
4897 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4898 * @param TIMx Timer instance
4899 * @retval None
4900 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)4901 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4902 {
4903 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4904 }
4905
4906 /**
4907 * @brief Generate Capture/Compare 1 event.
4908 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4909 * @param TIMx Timer instance
4910 * @retval None
4911 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)4912 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4913 {
4914 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4915 }
4916
4917 /**
4918 * @brief Generate Capture/Compare 2 event.
4919 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4920 * @param TIMx Timer instance
4921 * @retval None
4922 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)4923 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4924 {
4925 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4926 }
4927
4928 /**
4929 * @brief Generate Capture/Compare 3 event.
4930 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4931 * @param TIMx Timer instance
4932 * @retval None
4933 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4934 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4935 {
4936 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4937 }
4938
4939 /**
4940 * @brief Generate Capture/Compare 4 event.
4941 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4942 * @param TIMx Timer instance
4943 * @retval None
4944 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4945 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4946 {
4947 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4948 }
4949
4950 /**
4951 * @brief Generate commutation event.
4952 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4953 * @param TIMx Timer instance
4954 * @retval None
4955 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)4956 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4957 {
4958 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4959 }
4960
4961 /**
4962 * @brief Generate trigger event.
4963 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4964 * @param TIMx Timer instance
4965 * @retval None
4966 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)4967 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4968 {
4969 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4970 }
4971
4972 /**
4973 * @brief Generate break event.
4974 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4975 * @param TIMx Timer instance
4976 * @retval None
4977 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)4978 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4979 {
4980 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4981 }
4982
4983 /**
4984 * @brief Generate break 2 event.
4985 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
4986 * @param TIMx Timer instance
4987 * @retval None
4988 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)4989 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
4990 {
4991 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
4992 }
4993
4994 /**
4995 * @}
4996 */
4997
4998 #if defined(USE_FULL_LL_DRIVER)
4999 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
5000 * @{
5001 */
5002
5003 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
5004 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
5005 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
5006 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
5007 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
5008 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
5009 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
5010 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5011 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5012 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5013 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5014 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5015 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5016 /**
5017 * @}
5018 */
5019 #endif /* USE_FULL_LL_DRIVER */
5020
5021 /**
5022 * @}
5023 */
5024
5025 /**
5026 * @}
5027 */
5028
5029 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */
5030
5031 /**
5032 * @}
5033 */
5034
5035 #ifdef __cplusplus
5036 }
5037 #endif
5038
5039 #endif /* __STM32MP1xx_LL_TIM_H */
5040
