1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_ll_fmc.h 4 * @author MCD Application Team 5 * @brief Header file of FMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32MP1xx_LL_FMC_H 21 #define STM32MP1xx_LL_FMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32mp1xx_hal_def.h" 29 30 /** @addtogroup STM32MP1xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FMC_LL 35 * @{ 36 */ 37 38 /** @addtogroup FMC_LL_Private_Macros 39 * @{ 40 */ 41 42 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ 43 ((__BANK__) == FMC_NORSRAM_BANK2) || \ 44 ((__BANK__) == FMC_NORSRAM_BANK3) || \ 45 ((__BANK__) == FMC_NORSRAM_BANK4)) 46 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ 47 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) 48 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ 49 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ 50 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) 51 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 52 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16)) 53 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ 54 ((__SIZE__) == FMC_PAGE_SIZE_128) || \ 55 ((__SIZE__) == FMC_PAGE_SIZE_256) || \ 56 ((__SIZE__) == FMC_PAGE_SIZE_512) || \ 57 ((__SIZE__) == FMC_PAGE_SIZE_1024)) 58 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ 59 ((__MODE__) == FMC_ACCESS_MODE_B) || \ 60 ((__MODE__) == FMC_ACCESS_MODE_C) || \ 61 ((__MODE__) == FMC_ACCESS_MODE_D)) 62 #define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \ 63 ((__NBL__) == FMC_NBL_SETUPTIME_1) || \ 64 ((__NBL__) == FMC_NBL_SETUPTIME_2) || \ 65 ((__NBL__) == FMC_NBL_SETUPTIME_3)) 66 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ 67 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) 68 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ 69 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) 70 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ 71 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) 72 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ 73 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) 74 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ 75 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) 76 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ 77 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) 78 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 79 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) 80 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) 81 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ 82 ((__BURST__) == FMC_WRITE_BURST_ENABLE)) 83 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 84 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 85 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) 86 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) 87 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) 88 #define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) 89 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) 90 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) 91 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) 92 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) 93 #define IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(__TIME__) (((__TIME__) >= 1U) && ((__TIME__) <= 65535U)) 94 95 96 /** 97 * @} 98 */ 99 100 /* Exported typedef ----------------------------------------------------------*/ 101 102 /** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types 103 * @{ 104 */ 105 106 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef 107 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef 108 109 #define FMC_NORSRAM_DEVICE FMC_Bank1_R 110 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R 111 112 /** 113 * @brief FMC NORSRAM Configuration Structure definition 114 */ 115 typedef struct 116 { 117 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 118 This parameter can be a value of @ref FMC_NORSRAM_Bank */ 119 120 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 121 multiplexed on the data bus or not. 122 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ 123 124 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 125 the corresponding memory device. 126 This parameter can be a value of @ref FMC_Memory_Type */ 127 128 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 129 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ 130 131 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 132 valid only with synchronous burst Flash memories. 133 This parameter can be a value of @ref FMC_Burst_Access_Mode */ 134 135 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 136 the Flash memory in burst mode. 137 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ 138 139 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 140 clock cycle before the wait state or during the wait state, 141 valid only when accessing memories in burst mode. 142 This parameter can be a value of @ref FMC_Wait_Timing */ 143 144 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. 145 This parameter can be a value of @ref FMC_Write_Operation */ 146 147 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 148 signal, valid for Flash memory access in burst mode. 149 This parameter can be a value of @ref FMC_Wait_Signal */ 150 151 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 152 This parameter can be a value of @ref FMC_Extended_Mode */ 153 154 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 155 valid only with asynchronous Flash memories. 156 This parameter can be a value of @ref FMC_AsynchronousWait */ 157 158 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 159 This parameter can be a value of @ref FMC_Write_Burst */ 160 161 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. 162 This parameter is only enabled through the FMC_BCR1 register, and don't care 163 through FMC_BCR2..4 registers. 164 This parameter can be a value of @ref FMC_Continous_Clock */ 165 166 uint32_t PageSize; /*!< Specifies the memory page size. 167 This parameter can be a value of @ref FMC_Page_Size */ 168 169 uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number 170 This parameter can be a value of @ref FMC_Byte_Lane */ 171 172 FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this NSBank 173 for PSRAM refresh. 174 This parameter can be set to ENABLE or DISABLE */ 175 176 uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for synchronous 177 accesses and in HCLK cycles for asynchronous accesses, 178 valid only if MaxChipSelectPulse is ENABLE. 179 This parameter can be a value between Min_Data = 1 and Max_Data = 65535. 180 @note: This parameter is common to all NSBank. */ 181 }FMC_NORSRAM_InitTypeDef; 182 183 /** 184 * @brief FMC NORSRAM Timing parameters structure definition 185 */ 186 typedef struct 187 { 188 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 189 the duration of the address setup time. 190 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 191 @note This parameter is not used with synchronous NOR Flash memories. */ 192 193 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 194 the duration of the address hold time. 195 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 196 @note This parameter is not used with synchronous NOR Flash memories. */ 197 198 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 199 the duration of the data setup time. 200 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 201 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 202 NOR Flash memories. */ 203 204 uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure 205 the duration of the data hold time. 206 This parameter can be a value between Min_Data = 0 and Max_Data = 3. 207 @note This parameter is used for used in asynchronous accesses. */ 208 209 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 210 the duration of the bus turnaround. 211 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 212 @note This parameter is only used for multiplexed NOR Flash memories. */ 213 214 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 215 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. 216 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 217 accesses. */ 218 219 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 220 to the memory before getting the first data. 221 The parameter value depends on the memory type as shown below: 222 - It must be set to 0 in case of a CRAM 223 - It is don't care in asynchronous NOR, SRAM or ROM accesses 224 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories 225 with synchronous burst mode enable */ 226 227 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 228 This parameter can be a value of @ref FMC_Access_Mode */ 229 }FMC_NORSRAM_TimingTypeDef; 230 231 232 233 234 /** 235 * @} 236 */ 237 238 /* Exported constants --------------------------------------------------------*/ 239 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants 240 * @{ 241 */ 242 243 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller 244 * @{ 245 */ 246 247 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank 248 * @{ 249 */ 250 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U) 251 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U) 252 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U) 253 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U) 254 /** 255 * @} 256 */ 257 258 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing 259 * @{ 260 */ 261 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U) 262 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U) 263 /** 264 * @} 265 */ 266 267 /** @defgroup FMC_Memory_Type FMC Memory Type 268 * @{ 269 */ 270 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U) 271 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U) 272 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U) 273 /** 274 * @} 275 */ 276 277 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width 278 * @{ 279 */ 280 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) 281 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) 282 /** 283 * @} 284 */ 285 286 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access 287 * @{ 288 */ 289 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U) 290 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U) 291 /** 292 * @} 293 */ 294 295 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode 296 * @{ 297 */ 298 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U) 299 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U) 300 /** 301 * @} 302 */ 303 304 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity 305 * @{ 306 */ 307 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U) 308 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U) 309 /** 310 * @} 311 */ 312 313 /** @defgroup FMC_Wait_Timing FMC Wait Timing 314 * @{ 315 */ 316 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U) 317 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U) 318 /** 319 * @} 320 */ 321 322 /** @defgroup FMC_Write_Operation FMC Write Operation 323 * @{ 324 */ 325 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U) 326 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U) 327 /** 328 * @} 329 */ 330 331 /** @defgroup FMC_Wait_Signal FMC Wait Signal 332 * @{ 333 */ 334 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U) 335 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U) 336 /** 337 * @} 338 */ 339 340 /** @defgroup FMC_Extended_Mode FMC Extended Mode 341 * @{ 342 */ 343 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U) 344 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U) 345 /** 346 * @} 347 */ 348 349 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait 350 * @{ 351 */ 352 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U) 353 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U) 354 /** 355 * @} 356 */ 357 358 /** @defgroup FMC_Page_Size FMC Page Size 359 * @{ 360 */ 361 #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U) 362 #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0) 363 #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1) 364 #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1)) 365 #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2) 366 /** 367 * @} 368 */ 369 370 /** @defgroup FMC_Write_Burst FMC Write Burst 371 * @{ 372 */ 373 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U) 374 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U) 375 /** 376 * @} 377 */ 378 379 /** @defgroup FMC_Continous_Clock FMC Continuous Clock 380 * @{ 381 */ 382 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U) 383 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U) 384 /** 385 * @} 386 */ 387 388 /** @defgroup FMC_Access_Mode FMC Access Mode 389 * @{ 390 */ 391 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U) 392 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U) 393 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U) 394 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000U) 395 /** 396 * @} 397 */ 398 399 /** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup 400 * @{ 401 */ 402 #define FMC_NBL_SETUPTIME_0 ((uint32_t)0x00000000U) 403 #define FMC_NBL_SETUPTIME_1 ((uint32_t)0x00400000U) 404 #define FMC_NBL_SETUPTIME_2 ((uint32_t)0x00800000U) 405 #define FMC_NBL_SETUPTIME_3 ((uint32_t)0x00C00000U) 406 /** 407 * @} 408 */ 409 410 /** 411 * @} 412 */ 413 414 415 416 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition 417 * @{ 418 */ 419 /** 420 * @} 421 */ 422 423 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition 424 * @{ 425 */ 426 /** 427 * @} 428 */ 429 430 /** 431 * @} 432 */ 433 434 /** 435 * @} 436 */ 437 438 /* Private macro -------------------------------------------------------------*/ 439 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros 440 * @{ 441 */ 442 /** 443 * @brief Enable the FMC Peripheral. 444 * @retval None 445 */ 446 #define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN) 447 448 /** 449 * @brief Disable the FMC Peripheral. 450 * @retval None 451 */ 452 #define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN) 453 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros 454 * @brief macros to handle NOR device enable/disable and read/write operations 455 * @{ 456 */ 457 458 /** 459 * @brief Enable the NORSRAM device access. 460 * @param __INSTANCE__ FMC_NORSRAM Instance 461 * @param __BANK__ FMC_NORSRAM Bank 462 * @retval None 463 */ 464 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN) 465 466 /** 467 * @brief Disable the NORSRAM device access. 468 * @param __INSTANCE__ FMC_NORSRAM Instance 469 * @param __BANK__ FMC_NORSRAM Bank 470 * @retval None 471 */ 472 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN) 473 474 /** 475 * @} 476 */ 477 478 479 480 481 /** 482 * @} 483 */ 484 485 /** 486 * @} 487 */ 488 489 /* Private functions ---------------------------------------------------------*/ 490 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions 491 * @{ 492 */ 493 494 /** @defgroup FMC_LL_NORSRAM NOR SRAM 495 * @{ 496 */ 497 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 498 * @{ 499 */ 500 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); 501 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 502 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); 503 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 504 /** 505 * @} 506 */ 507 508 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 509 * @{ 510 */ 511 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 512 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 513 /** 514 * @} 515 */ 516 /** 517 * @} 518 */ 519 520 521 522 523 /** 524 * @} 525 */ 526 527 /** 528 * @} 529 */ 530 531 /** 532 * @} 533 */ 534 535 #ifdef __cplusplus 536 } 537 #endif 538 539 #endif /* STM32MP1xx_LL_FMC_H */ 540 541
