1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_ll_dmamux.h
4 * @author MCD Application Team
5 * @brief Header file of DMAMUX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32MP1xx_LL_DMAMUX_H
21 #define STM32MP1xx_LL_DMAMUX_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32mp1xx.h"
29
30 /** @addtogroup STM32MP1xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DMAMUX1) || defined (DMAMUX2)
35
36 /** @defgroup DMAMUX_LL DMAMUX
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
44 * @{
45 */
46 /* Define used to get DMAMUX CCR register size */
47 #define DMAMUX_CCR_SIZE 0x00000004U
48
49 /* Define used to get DMAMUX RGCR register size */
50 #define DMAMUX_RGCR_SIZE 0x00000004U
51
52 /* Define used to get DMAMUX RequestGenerator offset */
53 #define DMAMUX_REQ_GEN_OFFSET (DMAMUX1_RequestGenerator0_BASE - DMAMUX1_BASE)
54 /* Define used to get DMAMUX Channel Status offset */
55 #define DMAMUX_CH_STATUS_OFFSET (DMAMUX1_ChannelStatus_BASE - DMAMUX1_BASE)
56 /* Define used to get DMAMUX RequestGenerator status offset */
57 #define DMAMUX_REQ_GEN_STATUS_OFFSET (DMAMUX1_RequestGenStatus_BASE - DMAMUX1_BASE)
58
59 /**
60 * @}
61 */
62
63 /* Private macros ------------------------------------------------------------*/
64 /* Exported types ------------------------------------------------------------*/
65 /* Exported constants --------------------------------------------------------*/
66 /** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
67 * @{
68 */
69 /** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
70 * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function
71 * @{
72 */
73 #define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
74 #define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
75 #define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
76 #define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
77 #define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
78 #define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
79 #define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
80 #define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
81 #define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
82 #define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
83 #define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
84 #define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
85 #define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
86 #define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
87 #define LL_DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14 /*!< Synchronization Event Overrun Flag Channel 14 */
88 #define LL_DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15 /*!< Synchronization Event Overrun Flag Channel 15 */
89 #define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
90 #define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
91 #define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
92 #define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
93 #define LL_DMAMUX_RGCFR_RGCOF4 DMAMUX_RGCFR_COF4 /*!< Request Generator 4 Trigger Event Overrun Flag */
94 #define LL_DMAMUX_RGCFR_RGCOF5 DMAMUX_RGCFR_COF5 /*!< Request Generator 5 Trigger Event Overrun Flag */
95 #define LL_DMAMUX_RGCFR_RGCOF6 DMAMUX_RGCFR_COF6 /*!< Request Generator 6 Trigger Event Overrun Flag */
96 #define LL_DMAMUX_RGCFR_RGCOF7 DMAMUX_RGCFR_COF7 /*!< Request Generator 7 Trigger Event Overrun Flag */
97 /**
98 * @}
99 */
100
101 /** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
102 * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function
103 * @{
104 */
105 #define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
106 #define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
107 #define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
108 #define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
109 #define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
110 #define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
111 #define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
112 #define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
113 #define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
114 #define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
115 #define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
116 #define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
117 #define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
118 #define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
119 #define LL_DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14 /*!< Synchronization Event Overrun Flag Channel 14 */
120 #define LL_DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15 /*!< Synchronization Event Overrun Flag Channel 15 */
121 #define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
122 #define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
123 #define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
124 #define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
125 #define LL_DMAMUX_RGSR_RGOF4 DMAMUX_RGSR_OF4 /*!< Request Generator 4 Trigger Event Overrun Flag */
126 #define LL_DMAMUX_RGSR_RGOF5 DMAMUX_RGSR_OF5 /*!< Request Generator 5 Trigger Event Overrun Flag */
127 #define LL_DMAMUX_RGSR_RGOF6 DMAMUX_RGSR_OF6 /*!< Request Generator 6 Trigger Event Overrun Flag */
128 #define LL_DMAMUX_RGSR_RGOF7 DMAMUX_RGSR_OF7 /*!< Request Generator 7 Trigger Event Overrun Flag */
129 /**
130 * @}
131 */
132
133 /** @defgroup DMAMUX_LL_EC_IT IT Defines
134 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions
135 * @{
136 */
137 #define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */
138 #define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */
139 /**
140 * @}
141 */
142
143 /** @defgroup DMAMUX_LL_EC_REQUEST DMAMUX1 Request
144 * @{
145 */
146 #define LL_DMAMUX1_REQ_MEM2MEM 0U /*!< memory to memory transfer */
147 #define LL_DMAMUX1_REQ_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */
148 #define LL_DMAMUX1_REQ_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */
149 #define LL_DMAMUX1_REQ_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */
150 #define LL_DMAMUX1_REQ_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */
151 #define LL_DMAMUX1_REQ_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */
152 #define LL_DMAMUX1_REQ_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */
153 #define LL_DMAMUX1_REQ_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */
154 #define LL_DMAMUX1_REQ_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */
155 #define LL_DMAMUX1_REQ_ADC1 9U /*!< DMAMUX1 ADC1 request */
156 #define LL_DMAMUX1_REQ_ADC2 10U /*!< DMAMUX1 ADC2 request */
157 #define LL_DMAMUX1_REQ_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */
158 #define LL_DMAMUX1_REQ_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */
159 #define LL_DMAMUX1_REQ_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */
160 #define LL_DMAMUX1_REQ_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */
161 #define LL_DMAMUX1_REQ_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */
162 #define LL_DMAMUX1_REQ_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */
163 #define LL_DMAMUX1_REQ_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */
164 #define LL_DMAMUX1_REQ_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */
165 #define LL_DMAMUX1_REQ_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */
166 #define LL_DMAMUX1_REQ_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */
167 #define LL_DMAMUX1_REQ_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */
168 #define LL_DMAMUX1_REQ_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */
169 #define LL_DMAMUX1_REQ_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */
170 #define LL_DMAMUX1_REQ_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */
171 #define LL_DMAMUX1_REQ_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */
172 #define LL_DMAMUX1_REQ_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */
173 #define LL_DMAMUX1_REQ_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */
174 #define LL_DMAMUX1_REQ_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */
175 #define LL_DMAMUX1_REQ_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */
176 #define LL_DMAMUX1_REQ_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */
177 #define LL_DMAMUX1_REQ_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */
178 #define LL_DMAMUX1_REQ_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */
179 #define LL_DMAMUX1_REQ_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */
180 #define LL_DMAMUX1_REQ_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */
181 #define LL_DMAMUX1_REQ_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */
182 #define LL_DMAMUX1_REQ_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */
183 #define LL_DMAMUX1_REQ_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */
184 #define LL_DMAMUX1_REQ_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */
185 #define LL_DMAMUX1_REQ_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */
186 #define LL_DMAMUX1_REQ_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */
187 #define LL_DMAMUX1_REQ_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */
188 #define LL_DMAMUX1_REQ_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */
189 #define LL_DMAMUX1_REQ_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */
190 #define LL_DMAMUX1_REQ_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */
191 #define LL_DMAMUX1_REQ_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */
192 #define LL_DMAMUX1_REQ_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */
193 #define LL_DMAMUX1_REQ_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */
194 #define LL_DMAMUX1_REQ_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */
195 #define LL_DMAMUX1_REQ_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */
196 #define LL_DMAMUX1_REQ_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */
197 #define LL_DMAMUX1_REQ_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */
198 #define LL_DMAMUX1_REQ_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */
199 #define LL_DMAMUX1_REQ_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */
200 #define LL_DMAMUX1_REQ_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */
201 #define LL_DMAMUX1_REQ_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */
202 #define LL_DMAMUX1_REQ_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */
203 #define LL_DMAMUX1_REQ_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */
204 #define LL_DMAMUX1_REQ_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */
205 #define LL_DMAMUX1_REQ_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */
206 #define LL_DMAMUX1_REQ_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */
207 #define LL_DMAMUX1_REQ_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */
208 #define LL_DMAMUX1_REQ_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */
209 #define LL_DMAMUX1_REQ_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */
210 #if defined (DAC1)
211 #define LL_DMAMUX1_REQ_DAC1 67U /*!< DMAMUX1 DAC1 request */
212 #define LL_DMAMUX1_REQ_DAC2 68U /*!< DMAMUX1 DAC2 request */
213 #endif
214 #define LL_DMAMUX1_REQ_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */
215 #define LL_DMAMUX1_REQ_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */
216 #define LL_DMAMUX1_REQ_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */
217 #define LL_DMAMUX1_REQ_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */
218 #define LL_DMAMUX1_REQ_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */
219 #define LL_DMAMUX1_REQ_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */
220 #if defined (DCMI)
221 #define LL_DMAMUX1_REQ_DCMI 75U /*!< DMAMUX1 DCMI request */
222 #endif
223 #if defined(CRYP2)
224 #define LL_DMAMUX1_REQ_CRYP2_IN 76U /*!< DMAMUX1 CRYP2 IN request */
225 #define LL_DMAMUX1_REQ_CRYP2_OUT 77U /*!< DMAMUX1 CRYP2 OUT request */
226 #endif
227 #if defined (HASH2)
228 #define LL_DMAMUX1_REQ_HASH2_IN 78U /*!< DMAMUX1 HASH2 IN request */
229 #endif
230 #define LL_DMAMUX1_REQ_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */
231 #define LL_DMAMUX1_REQ_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */
232 #define LL_DMAMUX1_REQ_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */
233 #define LL_DMAMUX1_REQ_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */
234 #define LL_DMAMUX1_REQ_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */
235 #define LL_DMAMUX1_REQ_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */
236 #define LL_DMAMUX1_REQ_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */
237 #define LL_DMAMUX1_REQ_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */
238 #define LL_DMAMUX1_REQ_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */
239 #define LL_DMAMUX1_REQ_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */
240 #define LL_DMAMUX1_REQ_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */
241 #define LL_DMAMUX1_REQ_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */
242 #define LL_DMAMUX1_REQ_DFSDM1_FLT4 91U /*!< DMAMUX1 DFSDM1 Filter4 request */
243 #define LL_DMAMUX1_REQ_DFSDM1_FLT5 92U /*!< DMAMUX1 DFSDM1 Filter5 request */
244 #define LL_DMAMUX1_REQ_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request*/
245 #define LL_DMAMUX1_REQ_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request*/
246 #if defined (SAI4)
247 #define LL_DMAMUX1_REQ_SAI4_A 99U /*!< DMAMUX1 SAI4 A request */
248 #define LL_DMAMUX1_REQ_SAI4_B 100U /*!< DMAMUX1 SAI4 B request */
249 #endif
250 #define LL_DMAMUX1_REQ_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */
251 #define LL_DMAMUX1_REQ_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM Filter1 request */
252 #define LL_DMAMUX1_REQ_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM Filter2 request */
253 #define LL_DMAMUX1_REQ_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM Filter3 request */
254 #define LL_DMAMUX1_REQ_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */
255 #define LL_DMAMUX1_REQ_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */
256 #define LL_DMAMUX1_REQ_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */
257 #define LL_DMAMUX1_REQ_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */
258 #define LL_DMAMUX1_REQ_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */
259 #define LL_DMAMUX1_REQ_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */
260 #define LL_DMAMUX1_REQ_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */
261 #define LL_DMAMUX1_REQ_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */
262 #if defined (SAI3)
263 #define LL_DMAMUX1_REQ_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */
264 #define LL_DMAMUX1_REQ_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */
265 #endif
266 #define LL_DMAMUX1_REQ_I2C5_RX 115U /*!< DMAMUX1 I2C5 RX request */
267 #define LL_DMAMUX1_REQ_I2C5_TX 116U /*!< DMAMUX1 I2C5 TX request */
268 /**
269 * @}
270 */
271
272
273 /** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
274 * @{
275 */
276 #define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX1 Channel 0 connected to DMA1 Channel 0 */
277 #define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX1 Channel 1 connected to DMA1 Channel 1 */
278 #define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX1 Channel 2 connected to DMA1 Channel 2 */
279 #define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX1 Channel 3 connected to DMA1 Channel 3 */
280 #define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX1 Channel 4 connected to DMA1 Channel 4 */
281 #define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX1 Channel 5 connected to DMA1 Channel 5 */
282 #define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX1 Channel 6 connected to DMA1 Channel 6 */
283 #define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX1 Channel 7 connected to DMA1 Channel 7 */
284 #define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX1 Channel 8 connected to DMA2 Channel 0 */
285 #define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX1 Channel 9 connected to DMA2 Channel 1 */
286 #define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX1 Channel 10 connected to DMA2 Channel 2 */
287 #define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX1 Channel 11 connected to DMA2 Channel 3 */
288 #define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX1 Channel 12 connected to DMA2 Channel 4 */
289 #define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX1 Channel 13 connected to DMA2 Channel 5 */
290 #define LL_DMAMUX_CHANNEL_14 0x0000000EU /*!< DMAMUX1 Channel 14 connected to DMA2 Channel 6 */
291 #define LL_DMAMUX_CHANNEL_15 0x0000000FU /*!< DMAMUX1 Channel 15 connected to DMA2 Channel 7 */
292 /**
293 * @}
294 */
295
296 /** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
297 * @{
298 */
299 #define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */
300 #define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */
301 #define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */
302 #define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
303 /**
304 * @}
305 */
306
307 /** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
308 * @{
309 */
310 #define LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0x00000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */
311 #define LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 0x01000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */
312 #define LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 0x02000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */
313 #define LL_DMAMUX1_SYNC_LPTIM1_OUT 0x03000000U /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT */
314 #define LL_DMAMUX1_SYNC_LPTIM2_OUT 0x04000000U /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT */
315 #define LL_DMAMUX1_SYNC_LPTIM3_OUT 0x05000000U /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT */
316 #define LL_DMAMUX1_SYNC_EXTI0 0x06000000U /*!< DMAMUX1 synchronization Signal is EXTI0 IT */
317 #define LL_DMAMUX1_SYNC_TIM12_TRGO 0x07000000U /*!< DMAMUX1 synchronization Signal is TIM12 TRGO */
318 /**
319 * @}
320 */
321
322 /** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
323 * @{
324 */
325 #define LL_DMAMUX_REQ_GEN_0 0x00000000U
326 #define LL_DMAMUX_REQ_GEN_1 0x00000001U
327 #define LL_DMAMUX_REQ_GEN_2 0x00000002U
328 #define LL_DMAMUX_REQ_GEN_3 0x00000003U
329 #define LL_DMAMUX_REQ_GEN_4 0x00000004U
330 #define LL_DMAMUX_REQ_GEN_5 0x00000005U
331 #define LL_DMAMUX_REQ_GEN_6 0x00000006U
332 #define LL_DMAMUX_REQ_GEN_7 0x00000007U
333 /**
334 * @}
335 */
336
337 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
338 * @{
339 */
340 #define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */
341 #define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */
342 #define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */
343 #define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */
344 /**
345 * @}
346 */
347
348 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
349 * @{
350 */
351 #define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */
352 #define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */
353 #define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */
354 #define LL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT */
355 #define LL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT */
356 #define LL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT */
357 #define LL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< DMAMUX1 Request generator Signal is EXTI0 IT */
358 #define LL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< DMAMUX1 Request generator Signal is TIM12 TRGO */
359 /**
360 * @}
361 */
362
363 /**
364 * @}
365 */
366
367 /* Exported macro ------------------------------------------------------------*/
368 /** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
369 * @{
370 */
371
372 /** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
373 * @{
374 */
375 /**
376 * @brief Write a value in DMAMUX register
377 * @param __INSTANCE__ DMAMUX Instance
378 * @param __REG__ Register to be written
379 * @param __VALUE__ Value to be written in the register
380 * @retval None
381 */
382 #define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
383
384 /**
385 * @brief Read a value in DMAMUX register
386 * @param __INSTANCE__ DMAMUX Instance
387 * @param __REG__ Register to be read
388 * @retval Register value
389 */
390 #define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
391 /**
392 * @}
393 */
394
395 /**
396 * @}
397 */
398
399 /* Exported functions --------------------------------------------------------*/
400 /** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
401 * @{
402 */
403
404 /** @defgroup DMAMUX_LL_EF_Configuration Configuration
405 * @{
406 */
407 /**
408 * @brief Set DMAMUX request ID for DMAMUX Channel x.
409 * @note DMAMUX channel 0 to 7 are mapped to DMA1 channel 0 to 7.
410 * DMAMUX channel 8 to 15 are mapped to DMA2 channel 0 to 7.
411 * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID
412 * @param DMAMUXx DMAMUXx Instance
413 * @param Channel This parameter can be one of the following values:
414 * @arg @ref LL_DMAMUX_CHANNEL_0
415 * @arg @ref LL_DMAMUX_CHANNEL_1
416 * @arg @ref LL_DMAMUX_CHANNEL_2
417 * @arg @ref LL_DMAMUX_CHANNEL_3
418 * @arg @ref LL_DMAMUX_CHANNEL_4
419 * @arg @ref LL_DMAMUX_CHANNEL_5
420 * @arg @ref LL_DMAMUX_CHANNEL_6
421 * @arg @ref LL_DMAMUX_CHANNEL_7
422 * @arg @ref LL_DMAMUX_CHANNEL_8
423 * @arg @ref LL_DMAMUX_CHANNEL_9
424 * @arg @ref LL_DMAMUX_CHANNEL_10
425 * @arg @ref LL_DMAMUX_CHANNEL_11
426 * @arg @ref LL_DMAMUX_CHANNEL_12
427 * @arg @ref LL_DMAMUX_CHANNEL_13
428 * @arg @ref LL_DMAMUX_CHANNEL_14
429 * @arg @ref LL_DMAMUX_CHANNEL_15
430 * @param Request This parameter can be one of the following values:
431 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
432 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
433 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
434 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
435 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
436 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
437 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
438 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
439 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
440 * @arg @ref LL_DMAMUX1_REQ_ADC1
441 * @arg @ref LL_DMAMUX1_REQ_ADC2
442 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
443 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
444 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
445 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
446 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
447 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
448 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
449 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
450 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
451 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
452 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
453 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
454 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
455 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
456 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
457 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
458 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
459 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
460 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
461 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
462 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
463 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
464 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
465 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
466 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
467 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
468 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
469 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
470 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
471 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
472 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
473 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
474 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
475 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
476 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
477 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
478 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
479 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
480 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
481 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
482 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
483 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
484 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
485 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
486 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
487 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
488 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
489 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
490 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
491 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
492 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
493 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
494 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
495 * @arg @ref LL_DMAMUX1_REQ_DAC1
496 * @arg @ref LL_DMAMUX1_REQ_DAC2
497 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
498 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
499 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
500 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
501 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
502 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
503 * @arg @ref LL_DMAMUX1_REQ_DCMI
504 * @arg @ref LL_DMAMUX1_REQ_CRYP2_IN
505 * @arg @ref LL_DMAMUX1_REQ_CRYP2_OUT
506 * @arg @ref LL_DMAMUX1_REQ_HASH2_IN
507 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
508 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
509 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
510 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
511 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
512 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
513 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
514 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
515 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
516 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
517 * @arg @ref LL_DMAMUX1_REQ_SAI2_A
518 * @arg @ref LL_DMAMUX1_REQ_SAI2_B
519 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT4
520 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT5
521 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
522 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
523 * @arg @ref LL_DMAMUX1_REQ_SAI4_A
524 * @arg @ref LL_DMAMUX1_REQ_SAI4_B
525 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
526 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
527 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
528 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
529 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
530 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
531 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
532 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
533 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
534 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
535 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
536 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
537 * @arg @ref LL_DMAMUX1_REQ_SAI3_A
538 * @arg @ref LL_DMAMUX1_REQ_SAI3_B
539 * @arg @ref LL_DMAMUX1_REQ_I2C5_RX
540 * @arg @ref LL_DMAMUX1_REQ_I2C5_TX
541 * @retval None
542 */
LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t Request)543 __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
544 {
545 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
546
547 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
548 }
549
550 /**
551 * @brief Get DMAMUX request ID for DMAMUX Channel x.
552 * @note DMAMUX channel 0 to 7 are mapped to DMA1 channel 0 to 7.
553 * DMAMUX channel 8 to 15 are mapped to DMA2 channel 0 to 7.
554 * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID
555 * @param DMAMUXx DMAMUXx Instance
556 * @param Channel This parameter can be one of the following values:
557 * @arg @ref LL_DMAMUX_CHANNEL_0
558 * @arg @ref LL_DMAMUX_CHANNEL_1
559 * @arg @ref LL_DMAMUX_CHANNEL_2
560 * @arg @ref LL_DMAMUX_CHANNEL_3
561 * @arg @ref LL_DMAMUX_CHANNEL_4
562 * @arg @ref LL_DMAMUX_CHANNEL_5
563 * @arg @ref LL_DMAMUX_CHANNEL_6
564 * @arg @ref LL_DMAMUX_CHANNEL_7
565 * @arg @ref LL_DMAMUX_CHANNEL_8
566 * @arg @ref LL_DMAMUX_CHANNEL_9
567 * @arg @ref LL_DMAMUX_CHANNEL_10
568 * @arg @ref LL_DMAMUX_CHANNEL_11
569 * @arg @ref LL_DMAMUX_CHANNEL_12
570 * @arg @ref LL_DMAMUX_CHANNEL_13
571 * @arg @ref LL_DMAMUX_CHANNEL_14
572 * @arg @ref LL_DMAMUX_CHANNEL_15
573 * @retval Returned value can be one of the following values:
574 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
575 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
576 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
577 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
578 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
579 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
580 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
581 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
582 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
583 * @arg @ref LL_DMAMUX1_REQ_ADC1
584 * @arg @ref LL_DMAMUX1_REQ_ADC2
585 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
586 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
587 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
588 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
589 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
590 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
591 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
592 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
593 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
594 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
595 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
596 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
597 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
598 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
599 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
600 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
601 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
602 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
603 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
604 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
605 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
606 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
607 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
608 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
609 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
610 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
611 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
612 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
613 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
614 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
615 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
616 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
617 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
618 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
619 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
620 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
621 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
622 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
623 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
624 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
625 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
626 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
627 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
628 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
629 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
630 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
631 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
632 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
633 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
634 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
635 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
636 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
637 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
638 * @arg @ref LL_DMAMUX1_REQ_DAC1
639 * @arg @ref LL_DMAMUX1_REQ_DAC2
640 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
641 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
642 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
643 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
644 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
645 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
646 * @arg @ref LL_DMAMUX1_REQ_DCMI
647 * @arg @ref LL_DMAMUX1_REQ_CRYP2_IN
648 * @arg @ref LL_DMAMUX1_REQ_CRYP2_OUT
649 * @arg @ref LL_DMAMUX1_REQ_HASH2_IN
650 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
651 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
652 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
653 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
654 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
655 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
656 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
657 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
658 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
659 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
660 * @arg @ref LL_DMAMUX1_REQ_SAI2_A
661 * @arg @ref LL_DMAMUX1_REQ_SAI2_B
662 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT4
663 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT5
664 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
665 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
666 * @arg @ref LL_DMAMUX1_REQ_SAI4_A
667 * @arg @ref LL_DMAMUX1_REQ_SAI4_B
668 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
669 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
670 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
671 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
672 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
673 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
674 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
675 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
676 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
677 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
678 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
679 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
680 * @arg @ref LL_DMAMUX1_REQ_SAI3_A
681 * @arg @ref LL_DMAMUX1_REQ_SAI3_B
682 * @arg @ref LL_DMAMUX1_REQ_I2C5_RX
683 * @arg @ref LL_DMAMUX1_REQ_I2C5_TX
684 */
LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)685 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
686 {
687 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
688
689 return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
690 }
691
692 /**
693 * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
694 * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb
695 * @param DMAMUXx DMAMUXx Instance
696 * @param Channel This parameter can be one of the following values:
697 * @arg @ref LL_DMAMUX_CHANNEL_0
698 * @arg @ref LL_DMAMUX_CHANNEL_1
699 * @arg @ref LL_DMAMUX_CHANNEL_2
700 * @arg @ref LL_DMAMUX_CHANNEL_3
701 * @arg @ref LL_DMAMUX_CHANNEL_4
702 * @arg @ref LL_DMAMUX_CHANNEL_5
703 * @arg @ref LL_DMAMUX_CHANNEL_6
704 * @arg @ref LL_DMAMUX_CHANNEL_7
705 * @arg @ref LL_DMAMUX_CHANNEL_8
706 * @arg @ref LL_DMAMUX_CHANNEL_9
707 * @arg @ref LL_DMAMUX_CHANNEL_10
708 * @arg @ref LL_DMAMUX_CHANNEL_11
709 * @arg @ref LL_DMAMUX_CHANNEL_12
710 * @arg @ref LL_DMAMUX_CHANNEL_13
711 * @arg @ref LL_DMAMUX_CHANNEL_14
712 * @arg @ref LL_DMAMUX_CHANNEL_15
713 * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
714 * @retval None
715 */
LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t RequestNb)716 __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
717 {
718 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
719
720 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ, (RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos);
721 }
722
723 /**
724 * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
725 * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb
726 * @param DMAMUXx DMAMUXx Instance
727 * @param Channel This parameter can be one of the following values:
728 * @arg @ref LL_DMAMUX_CHANNEL_0
729 * @arg @ref LL_DMAMUX_CHANNEL_1
730 * @arg @ref LL_DMAMUX_CHANNEL_2
731 * @arg @ref LL_DMAMUX_CHANNEL_3
732 * @arg @ref LL_DMAMUX_CHANNEL_4
733 * @arg @ref LL_DMAMUX_CHANNEL_5
734 * @arg @ref LL_DMAMUX_CHANNEL_6
735 * @arg @ref LL_DMAMUX_CHANNEL_7
736 * @arg @ref LL_DMAMUX_CHANNEL_8
737 * @arg @ref LL_DMAMUX_CHANNEL_9
738 * @arg @ref LL_DMAMUX_CHANNEL_10
739 * @arg @ref LL_DMAMUX_CHANNEL_11
740 * @arg @ref LL_DMAMUX_CHANNEL_12
741 * @arg @ref LL_DMAMUX_CHANNEL_13
742 * @arg @ref LL_DMAMUX_CHANNEL_14
743 * @arg @ref LL_DMAMUX_CHANNEL_15
744 * @retval Between Min_Data = 1 and Max_Data = 32
745 */
LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)746 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
747 {
748 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
749
750 return (uint32_t)((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
751 }
752
753 /**
754 * @brief Set the polarity of the signal on which the DMA request is synchronized.
755 * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity
756 * @param DMAMUXx DMAMUXx Instance
757 * @param Channel This parameter can be one of the following values:
758 * @arg @ref LL_DMAMUX_CHANNEL_0
759 * @arg @ref LL_DMAMUX_CHANNEL_1
760 * @arg @ref LL_DMAMUX_CHANNEL_2
761 * @arg @ref LL_DMAMUX_CHANNEL_3
762 * @arg @ref LL_DMAMUX_CHANNEL_4
763 * @arg @ref LL_DMAMUX_CHANNEL_5
764 * @arg @ref LL_DMAMUX_CHANNEL_6
765 * @arg @ref LL_DMAMUX_CHANNEL_7
766 * @arg @ref LL_DMAMUX_CHANNEL_8
767 * @arg @ref LL_DMAMUX_CHANNEL_9
768 * @arg @ref LL_DMAMUX_CHANNEL_10
769 * @arg @ref LL_DMAMUX_CHANNEL_11
770 * @arg @ref LL_DMAMUX_CHANNEL_12
771 * @arg @ref LL_DMAMUX_CHANNEL_13
772 * @arg @ref LL_DMAMUX_CHANNEL_14
773 * @arg @ref LL_DMAMUX_CHANNEL_15
774 * @param Polarity This parameter can be one of the following values:
775 * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
776 * @arg @ref LL_DMAMUX_SYNC_POL_RISING
777 * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
778 * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
779 * @retval None
780 */
LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t Polarity)781 __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
782 {
783 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
784
785 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL, Polarity);
786 }
787
788 /**
789 * @brief Get the polarity of the signal on which the DMA request is synchronized.
790 * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity
791 * @param DMAMUXx DMAMUXx Instance
792 * @param Channel This parameter can be one of the following values:
793 * @arg @ref LL_DMAMUX_CHANNEL_0
794 * @arg @ref LL_DMAMUX_CHANNEL_1
795 * @arg @ref LL_DMAMUX_CHANNEL_2
796 * @arg @ref LL_DMAMUX_CHANNEL_3
797 * @arg @ref LL_DMAMUX_CHANNEL_4
798 * @arg @ref LL_DMAMUX_CHANNEL_5
799 * @arg @ref LL_DMAMUX_CHANNEL_6
800 * @arg @ref LL_DMAMUX_CHANNEL_7
801 * @arg @ref LL_DMAMUX_CHANNEL_8
802 * @arg @ref LL_DMAMUX_CHANNEL_9
803 * @arg @ref LL_DMAMUX_CHANNEL_10
804 * @arg @ref LL_DMAMUX_CHANNEL_11
805 * @arg @ref LL_DMAMUX_CHANNEL_12
806 * @arg @ref LL_DMAMUX_CHANNEL_13
807 * @arg @ref LL_DMAMUX_CHANNEL_14
808 * @arg @ref LL_DMAMUX_CHANNEL_15
809 * @retval Returned value can be one of the following values:
810 * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
811 * @arg @ref LL_DMAMUX_SYNC_POL_RISING
812 * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
813 * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
814 */
LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)815 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
816 {
817 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
818
819 return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL));
820 }
821
822 /**
823 * @brief Enable the Event Generation on DMAMUX channel x.
824 * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration
825 * @param DMAMUXx DMAMUXx Instance
826 * @param Channel This parameter can be one of the following values:
827 * @arg @ref LL_DMAMUX_CHANNEL_0
828 * @arg @ref LL_DMAMUX_CHANNEL_1
829 * @arg @ref LL_DMAMUX_CHANNEL_2
830 * @arg @ref LL_DMAMUX_CHANNEL_3
831 * @arg @ref LL_DMAMUX_CHANNEL_4
832 * @arg @ref LL_DMAMUX_CHANNEL_5
833 * @arg @ref LL_DMAMUX_CHANNEL_6
834 * @arg @ref LL_DMAMUX_CHANNEL_7
835 * @arg @ref LL_DMAMUX_CHANNEL_8
836 * @arg @ref LL_DMAMUX_CHANNEL_9
837 * @arg @ref LL_DMAMUX_CHANNEL_10
838 * @arg @ref LL_DMAMUX_CHANNEL_11
839 * @arg @ref LL_DMAMUX_CHANNEL_12
840 * @arg @ref LL_DMAMUX_CHANNEL_13
841 * @arg @ref LL_DMAMUX_CHANNEL_14
842 * @arg @ref LL_DMAMUX_CHANNEL_15
843 * @retval None
844 */
LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)845 __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
846 {
847 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
848
849 SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
850 }
851
852 /**
853 * @brief Disable the Event Generation on DMAMUX channel x.
854 * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration
855 * @param DMAMUXx DMAMUXx Instance
856 * @param Channel This parameter can be one of the following values:
857 * @arg @ref LL_DMAMUX_CHANNEL_0
858 * @arg @ref LL_DMAMUX_CHANNEL_1
859 * @arg @ref LL_DMAMUX_CHANNEL_2
860 * @arg @ref LL_DMAMUX_CHANNEL_3
861 * @arg @ref LL_DMAMUX_CHANNEL_4
862 * @arg @ref LL_DMAMUX_CHANNEL_5
863 * @arg @ref LL_DMAMUX_CHANNEL_6
864 * @arg @ref LL_DMAMUX_CHANNEL_7
865 * @arg @ref LL_DMAMUX_CHANNEL_8
866 * @arg @ref LL_DMAMUX_CHANNEL_9
867 * @arg @ref LL_DMAMUX_CHANNEL_10
868 * @arg @ref LL_DMAMUX_CHANNEL_11
869 * @arg @ref LL_DMAMUX_CHANNEL_12
870 * @arg @ref LL_DMAMUX_CHANNEL_13
871 * @arg @ref LL_DMAMUX_CHANNEL_14
872 * @arg @ref LL_DMAMUX_CHANNEL_15
873 * @retval None
874 */
LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)875 __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
876 {
877 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
878
879 CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
880 }
881
882 /**
883 * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled.
884 * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration
885 * @param DMAMUXx DMAMUXx Instance
886 * @param Channel This parameter can be one of the following values:
887 * @arg @ref LL_DMAMUX_CHANNEL_0
888 * @arg @ref LL_DMAMUX_CHANNEL_1
889 * @arg @ref LL_DMAMUX_CHANNEL_2
890 * @arg @ref LL_DMAMUX_CHANNEL_3
891 * @arg @ref LL_DMAMUX_CHANNEL_4
892 * @arg @ref LL_DMAMUX_CHANNEL_5
893 * @arg @ref LL_DMAMUX_CHANNEL_6
894 * @arg @ref LL_DMAMUX_CHANNEL_7
895 * @arg @ref LL_DMAMUX_CHANNEL_8
896 * @arg @ref LL_DMAMUX_CHANNEL_9
897 * @arg @ref LL_DMAMUX_CHANNEL_10
898 * @arg @ref LL_DMAMUX_CHANNEL_11
899 * @arg @ref LL_DMAMUX_CHANNEL_12
900 * @arg @ref LL_DMAMUX_CHANNEL_13
901 * @arg @ref LL_DMAMUX_CHANNEL_14
902 * @arg @ref LL_DMAMUX_CHANNEL_15
903 * @retval State of bit (1 or 0).
904 */
LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)905 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
906 {
907 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
908
909 return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
910 }
911
912 /**
913 * @brief Enable the synchronization mode.
914 * @rmtoll CxCR SE LL_DMAMUX_EnableSync
915 * @param DMAMUXx DMAMUXx Instance
916 * @param Channel This parameter can be one of the following values:
917 * @arg @ref LL_DMAMUX_CHANNEL_0
918 * @arg @ref LL_DMAMUX_CHANNEL_1
919 * @arg @ref LL_DMAMUX_CHANNEL_2
920 * @arg @ref LL_DMAMUX_CHANNEL_3
921 * @arg @ref LL_DMAMUX_CHANNEL_4
922 * @arg @ref LL_DMAMUX_CHANNEL_5
923 * @arg @ref LL_DMAMUX_CHANNEL_6
924 * @arg @ref LL_DMAMUX_CHANNEL_7
925 * @arg @ref LL_DMAMUX_CHANNEL_8
926 * @arg @ref LL_DMAMUX_CHANNEL_9
927 * @arg @ref LL_DMAMUX_CHANNEL_10
928 * @arg @ref LL_DMAMUX_CHANNEL_11
929 * @arg @ref LL_DMAMUX_CHANNEL_12
930 * @arg @ref LL_DMAMUX_CHANNEL_13
931 * @arg @ref LL_DMAMUX_CHANNEL_14
932 * @arg @ref LL_DMAMUX_CHANNEL_15
933 * @retval None
934 */
LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)935 __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
936 {
937 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
938
939 SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
940 }
941
942 /**
943 * @brief Disable the synchronization mode.
944 * @rmtoll CxCR SE LL_DMAMUX_DisableSync
945 * @param DMAMUXx DMAMUXx Instance
946 * @param Channel This parameter can be one of the following values:
947 * @arg @ref LL_DMAMUX_CHANNEL_0
948 * @arg @ref LL_DMAMUX_CHANNEL_1
949 * @arg @ref LL_DMAMUX_CHANNEL_2
950 * @arg @ref LL_DMAMUX_CHANNEL_3
951 * @arg @ref LL_DMAMUX_CHANNEL_4
952 * @arg @ref LL_DMAMUX_CHANNEL_5
953 * @arg @ref LL_DMAMUX_CHANNEL_6
954 * @arg @ref LL_DMAMUX_CHANNEL_7
955 * @arg @ref LL_DMAMUX_CHANNEL_8
956 * @arg @ref LL_DMAMUX_CHANNEL_9
957 * @arg @ref LL_DMAMUX_CHANNEL_10
958 * @arg @ref LL_DMAMUX_CHANNEL_11
959 * @arg @ref LL_DMAMUX_CHANNEL_12
960 * @arg @ref LL_DMAMUX_CHANNEL_13
961 * @arg @ref LL_DMAMUX_CHANNEL_14
962 * @arg @ref LL_DMAMUX_CHANNEL_15
963 * @retval None
964 */
LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)965 __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
966 {
967 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
968
969 CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
970 }
971
972 /**
973 * @brief Check if the synchronization mode is enabled or disabled.
974 * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync
975 * @param DMAMUXx DMAMUXx Instance
976 * @param Channel This parameter can be one of the following values:
977 * @arg @ref LL_DMAMUX_CHANNEL_0
978 * @arg @ref LL_DMAMUX_CHANNEL_1
979 * @arg @ref LL_DMAMUX_CHANNEL_2
980 * @arg @ref LL_DMAMUX_CHANNEL_3
981 * @arg @ref LL_DMAMUX_CHANNEL_4
982 * @arg @ref LL_DMAMUX_CHANNEL_5
983 * @arg @ref LL_DMAMUX_CHANNEL_6
984 * @arg @ref LL_DMAMUX_CHANNEL_7
985 * @arg @ref LL_DMAMUX_CHANNEL_8
986 * @arg @ref LL_DMAMUX_CHANNEL_9
987 * @arg @ref LL_DMAMUX_CHANNEL_10
988 * @arg @ref LL_DMAMUX_CHANNEL_11
989 * @arg @ref LL_DMAMUX_CHANNEL_12
990 * @arg @ref LL_DMAMUX_CHANNEL_13
991 * @arg @ref LL_DMAMUX_CHANNEL_14
992 * @arg @ref LL_DMAMUX_CHANNEL_15
993 * @retval State of bit (1 or 0).
994 */
LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)995 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
996 {
997 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
998
999 return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
1000 }
1001
1002 /**
1003 * @brief Set DMAMUX synchronization ID on DMAMUX Channel x.
1004 * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID
1005 * @param DMAMUXx DMAMUXx Instance
1006 * @param Channel This parameter can be one of the following values:
1007 * @arg @ref LL_DMAMUX_CHANNEL_0
1008 * @arg @ref LL_DMAMUX_CHANNEL_1
1009 * @arg @ref LL_DMAMUX_CHANNEL_2
1010 * @arg @ref LL_DMAMUX_CHANNEL_3
1011 * @arg @ref LL_DMAMUX_CHANNEL_4
1012 * @arg @ref LL_DMAMUX_CHANNEL_5
1013 * @arg @ref LL_DMAMUX_CHANNEL_6
1014 * @arg @ref LL_DMAMUX_CHANNEL_7
1015 * @arg @ref LL_DMAMUX_CHANNEL_8
1016 * @arg @ref LL_DMAMUX_CHANNEL_9
1017 * @arg @ref LL_DMAMUX_CHANNEL_10
1018 * @arg @ref LL_DMAMUX_CHANNEL_11
1019 * @arg @ref LL_DMAMUX_CHANNEL_12
1020 * @arg @ref LL_DMAMUX_CHANNEL_13
1021 * @arg @ref LL_DMAMUX_CHANNEL_14
1022 * @arg @ref LL_DMAMUX_CHANNEL_15
1023 * @param SyncID This parameter can be one of the following values:
1024 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
1025 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
1026 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
1027 * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
1028 * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
1029 * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
1030 * @arg @ref LL_DMAMUX1_SYNC_EXTI0
1031 * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
1032 * @retval None
1033 */
LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t SyncID)1034 __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
1035 {
1036 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1037
1038 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
1039 }
1040
1041 /**
1042 * @brief Get DMAMUX synchronization ID on DMAMUX Channel x.
1043 * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID
1044 * @param DMAMUXx DMAMUXx Instance
1045 * @param Channel This parameter can be one of the following values:
1046 * @arg @ref LL_DMAMUX_CHANNEL_0
1047 * @arg @ref LL_DMAMUX_CHANNEL_1
1048 * @arg @ref LL_DMAMUX_CHANNEL_2
1049 * @arg @ref LL_DMAMUX_CHANNEL_3
1050 * @arg @ref LL_DMAMUX_CHANNEL_4
1051 * @arg @ref LL_DMAMUX_CHANNEL_5
1052 * @arg @ref LL_DMAMUX_CHANNEL_6
1053 * @arg @ref LL_DMAMUX_CHANNEL_7
1054 * @arg @ref LL_DMAMUX_CHANNEL_8
1055 * @arg @ref LL_DMAMUX_CHANNEL_9
1056 * @arg @ref LL_DMAMUX_CHANNEL_10
1057 * @arg @ref LL_DMAMUX_CHANNEL_11
1058 * @arg @ref LL_DMAMUX_CHANNEL_12
1059 * @arg @ref LL_DMAMUX_CHANNEL_13
1060 * @arg @ref LL_DMAMUX_CHANNEL_14
1061 * @arg @ref LL_DMAMUX_CHANNEL_15
1062 * @retval Returned value can be one of the following values:
1063 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
1064 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
1065 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
1066 * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
1067 * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
1068 * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
1069 * @arg @ref LL_DMAMUX1_SYNC_EXTI0
1070 * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
1071 */
LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)1072 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1073 {
1074 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1075
1076 return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID));
1077 }
1078
1079 /**
1080 * @brief Enable the Request Generator.
1081 * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen
1082 * @param DMAMUXx DMAMUXx Instance
1083 * @param RequestGenChannel This parameter can be one of the following values:
1084 * @arg @ref LL_DMAMUX_REQ_GEN_0
1085 * @arg @ref LL_DMAMUX_REQ_GEN_1
1086 * @arg @ref LL_DMAMUX_REQ_GEN_2
1087 * @arg @ref LL_DMAMUX_REQ_GEN_3
1088 * @arg @ref LL_DMAMUX_REQ_GEN_4
1089 * @arg @ref LL_DMAMUX_REQ_GEN_5
1090 * @arg @ref LL_DMAMUX_REQ_GEN_6
1091 * @arg @ref LL_DMAMUX_REQ_GEN_7
1092 * @retval None
1093 */
LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1094 __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1095 {
1096 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1097
1098 SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
1099 }
1100
1101 /**
1102 * @brief Disable the Request Generator.
1103 * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen
1104 * @param DMAMUXx DMAMUXx Instance
1105 * @param RequestGenChannel This parameter can be one of the following values:
1106 * @arg @ref LL_DMAMUX_REQ_GEN_0
1107 * @arg @ref LL_DMAMUX_REQ_GEN_1
1108 * @arg @ref LL_DMAMUX_REQ_GEN_2
1109 * @arg @ref LL_DMAMUX_REQ_GEN_3
1110 * @retval None
1111 */
LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1112 __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1113 {
1114 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1115
1116 CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
1117 }
1118
1119 /**
1120 * @brief Check if the Request Generator is enabled or disabled.
1121 * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen
1122 * @param DMAMUXx DMAMUXx Instance
1123 * @param RequestGenChannel This parameter can be one of the following values:
1124 * @arg @ref LL_DMAMUX_REQ_GEN_0
1125 * @arg @ref LL_DMAMUX_REQ_GEN_1
1126 * @arg @ref LL_DMAMUX_REQ_GEN_2
1127 * @arg @ref LL_DMAMUX_REQ_GEN_3
1128 * @arg @ref LL_DMAMUX_REQ_GEN_4
1129 * @arg @ref LL_DMAMUX_REQ_GEN_5
1130 * @arg @ref LL_DMAMUX_REQ_GEN_6
1131 * @arg @ref LL_DMAMUX_REQ_GEN_7
1132 * @retval State of bit (1 or 0).
1133 */
LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1134 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1135 {
1136 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1137
1138 return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
1139 }
1140
1141 /**
1142 * @brief Set the polarity of the signal on which the DMA request is generated.
1143 * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity
1144 * @param DMAMUXx DMAMUXx Instance
1145 * @param RequestGenChannel This parameter can be one of the following values:
1146 * @arg @ref LL_DMAMUX_REQ_GEN_0
1147 * @arg @ref LL_DMAMUX_REQ_GEN_1
1148 * @arg @ref LL_DMAMUX_REQ_GEN_2
1149 * @arg @ref LL_DMAMUX_REQ_GEN_3
1150 * @arg @ref LL_DMAMUX_REQ_GEN_4
1151 * @arg @ref LL_DMAMUX_REQ_GEN_5
1152 * @arg @ref LL_DMAMUX_REQ_GEN_6
1153 * @arg @ref LL_DMAMUX_REQ_GEN_7
1154 * @param Polarity This parameter can be one of the following values:
1155 * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
1156 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
1157 * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
1158 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
1159 * @retval None
1160 */
LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel,uint32_t Polarity)1161 __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
1162 {
1163 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1164
1165 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
1166 }
1167
1168 /**
1169 * @brief Get the polarity of the signal on which the DMA request is generated.
1170 * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity
1171 * @param DMAMUXx DMAMUXx Instance
1172 * @param RequestGenChannel This parameter can be one of the following values:
1173 * @arg @ref LL_DMAMUX_REQ_GEN_0
1174 * @arg @ref LL_DMAMUX_REQ_GEN_1
1175 * @arg @ref LL_DMAMUX_REQ_GEN_2
1176 * @arg @ref LL_DMAMUX_REQ_GEN_3
1177 * @arg @ref LL_DMAMUX_REQ_GEN_4
1178 * @arg @ref LL_DMAMUX_REQ_GEN_5
1179 * @arg @ref LL_DMAMUX_REQ_GEN_6
1180 * @arg @ref LL_DMAMUX_REQ_GEN_7
1181 * @retval Returned value can be one of the following values:
1182 * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
1183 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
1184 * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
1185 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
1186 */
LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1187 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1188 {
1189 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1190
1191 return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL));
1192 }
1193
1194 /**
1195 * @brief Set the number of DMA request that will be autorized after a generation event.
1196 * @note This field can only be written when Generator is disabled.
1197 * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb
1198 * @param DMAMUXx DMAMUXx Instance
1199 * @param RequestGenChannel This parameter can be one of the following values:
1200 * @arg @ref LL_DMAMUX_REQ_GEN_0
1201 * @arg @ref LL_DMAMUX_REQ_GEN_1
1202 * @arg @ref LL_DMAMUX_REQ_GEN_2
1203 * @arg @ref LL_DMAMUX_REQ_GEN_3
1204 * @arg @ref LL_DMAMUX_REQ_GEN_4
1205 * @arg @ref LL_DMAMUX_REQ_GEN_5
1206 * @arg @ref LL_DMAMUX_REQ_GEN_6
1207 * @arg @ref LL_DMAMUX_REQ_GEN_7
1208 * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
1209 * @retval None
1210 */
LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel,uint32_t RequestNb)1211 __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
1212 {
1213 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1214
1215 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
1216 }
1217
1218 /**
1219 * @brief Get the number of DMA request that will be autorized after a generation event.
1220 * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb
1221 * @param DMAMUXx DMAMUXx Instance
1222 * @param RequestGenChannel This parameter can be one of the following values:
1223 * @arg @ref LL_DMAMUX_REQ_GEN_0
1224 * @arg @ref LL_DMAMUX_REQ_GEN_1
1225 * @arg @ref LL_DMAMUX_REQ_GEN_2
1226 * @arg @ref LL_DMAMUX_REQ_GEN_3
1227 * @arg @ref LL_DMAMUX_REQ_GEN_4
1228 * @arg @ref LL_DMAMUX_REQ_GEN_5
1229 * @arg @ref LL_DMAMUX_REQ_GEN_6
1230 * @arg @ref LL_DMAMUX_REQ_GEN_7
1231 * @retval Between Min_Data = 1 and Max_Data = 32
1232 */
LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1233 __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1234 {
1235 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1236
1237 return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
1238 }
1239
1240 /**
1241 * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
1242 * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID
1243 * @param DMAMUXx DMAMUXx Instance
1244 * @param RequestGenChannel This parameter can be one of the following values:
1245 * @arg @ref LL_DMAMUX_REQ_GEN_0
1246 * @arg @ref LL_DMAMUX_REQ_GEN_1
1247 * @arg @ref LL_DMAMUX_REQ_GEN_2
1248 * @arg @ref LL_DMAMUX_REQ_GEN_3
1249 * @arg @ref LL_DMAMUX_REQ_GEN_4
1250 * @arg @ref LL_DMAMUX_REQ_GEN_5
1251 * @arg @ref LL_DMAMUX_REQ_GEN_6
1252 * @arg @ref LL_DMAMUX_REQ_GEN_7
1253 * @param RequestSignalID This parameter can be one of the following values:
1254 * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
1255 * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
1256 * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
1257 * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM1_OUT
1258 * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM2_OUT
1259 * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM3_OUT
1260 * @arg @ref LL_DMAMUX1_REQ_GEN_EXTI0
1261 * @arg @ref LL_DMAMUX1_REQ_GEN_TIM12_TRGO
1262 * @retval None
1263 */
LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel,uint32_t RequestSignalID)1264 __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
1265 {
1266 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1267
1268 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
1269 }
1270
1271 /**
1272 * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
1273 * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID
1274 * @param DMAMUXx DMAMUXx Instance
1275 * @param RequestGenChannel This parameter can be one of the following values:
1276 * @arg @ref LL_DMAMUX_REQ_GEN_0
1277 * @arg @ref LL_DMAMUX_REQ_GEN_1
1278 * @arg @ref LL_DMAMUX_REQ_GEN_2
1279 * @arg @ref LL_DMAMUX_REQ_GEN_3
1280 * @arg @ref LL_DMAMUX_REQ_GEN_4
1281 * @arg @ref LL_DMAMUX_REQ_GEN_5
1282 * @arg @ref LL_DMAMUX_REQ_GEN_6
1283 * @arg @ref LL_DMAMUX_REQ_GEN_7
1284 * @retval Returned value can be one of the following values:
1285 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
1286 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
1287 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
1288 * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
1289 * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
1290 * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
1291 * @arg @ref LL_DMAMUX1_SYNC_EXTI0
1292 * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
1293 */
LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1294 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1295 {
1296 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1297
1298 return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID));
1299 }
1300
1301 /**
1302 * @}
1303 */
1304
1305 /** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
1306 * @{
1307 */
1308
1309 /**
1310 * @brief Get Synchronization Event Overrun Flag Channel 0.
1311 * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0
1312 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1313 * @retval State of bit (1 or 0).
1314 */
LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef * DMAMUXx)1315 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1316 {
1317 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1318
1319 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
1320 }
1321
1322 /**
1323 * @brief Get Synchronization Event Overrun Flag Channel 1.
1324 * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1
1325 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1326 * @retval State of bit (1 or 0).
1327 */
LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef * DMAMUXx)1328 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1329 {
1330 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1331
1332 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
1333 }
1334
1335 /**
1336 * @brief Get Synchronization Event Overrun Flag Channel 2.
1337 * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2
1338 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1339 * @retval State of bit (1 or 0).
1340 */
LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef * DMAMUXx)1341 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1342 {
1343 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1344
1345 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
1346 }
1347
1348 /**
1349 * @brief Get Synchronization Event Overrun Flag Channel 3.
1350 * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3
1351 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1352 * @retval State of bit (1 or 0).
1353 */
LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef * DMAMUXx)1354 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1355 {
1356 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1357
1358 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
1359 }
1360
1361 /**
1362 * @brief Get Synchronization Event Overrun Flag Channel 4.
1363 * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4
1364 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1365 * @retval State of bit (1 or 0).
1366 */
LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef * DMAMUXx)1367 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
1368 {
1369 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1370
1371 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
1372 }
1373
1374 /**
1375 * @brief Get Synchronization Event Overrun Flag Channel 5.
1376 * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5
1377 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1378 * @retval State of bit (1 or 0).
1379 */
LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef * DMAMUXx)1380 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
1381 {
1382 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1383
1384 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
1385 }
1386
1387 /**
1388 * @brief Get Synchronization Event Overrun Flag Channel 6.
1389 * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6
1390 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1391 * @retval State of bit (1 or 0).
1392 */
LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef * DMAMUXx)1393 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
1394 {
1395 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1396
1397 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
1398 }
1399
1400 /**
1401 * @brief Get Synchronization Event Overrun Flag Channel 7.
1402 * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7
1403 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1404 * @retval State of bit (1 or 0).
1405 */
LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef * DMAMUXx)1406 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
1407 {
1408 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1409
1410 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
1411 }
1412
1413 /**
1414 * @brief Get Synchronization Event Overrun Flag Channel 8.
1415 * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8
1416 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1417 * @retval State of bit (1 or 0).
1418 */
LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef * DMAMUXx)1419 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
1420 {
1421 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1422
1423 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
1424 }
1425
1426 /**
1427 * @brief Get Synchronization Event Overrun Flag Channel 9.
1428 * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9
1429 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1430 * @retval State of bit (1 or 0).
1431 */
LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef * DMAMUXx)1432 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
1433 {
1434 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1435
1436 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
1437 }
1438
1439 /**
1440 * @brief Get Synchronization Event Overrun Flag Channel 10.
1441 * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10
1442 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1443 * @retval State of bit (1 or 0).
1444 */
LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef * DMAMUXx)1445 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
1446 {
1447 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1448
1449 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
1450 }
1451
1452 /**
1453 * @brief Get Synchronization Event Overrun Flag Channel 11.
1454 * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11
1455 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1456 * @retval State of bit (1 or 0).
1457 */
LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef * DMAMUXx)1458 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
1459 {
1460 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1461
1462 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
1463 }
1464
1465 /**
1466 * @brief Get Synchronization Event Overrun Flag Channel 12.
1467 * @rmtoll CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12
1468 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1469 * @retval State of bit (1 or 0).
1470 */
LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef * DMAMUXx)1471 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
1472 {
1473 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1474
1475 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL);
1476 }
1477
1478 /**
1479 * @brief Get Synchronization Event Overrun Flag Channel 13.
1480 * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13
1481 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1482 * @retval State of bit (1 or 0).
1483 */
LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef * DMAMUXx)1484 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
1485 {
1486 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1487
1488 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL);
1489 }
1490
1491 /**
1492 * @brief Get Synchronization Event Overrun Flag Channel 14.
1493 * @rmtoll CSR SOF14 LL_DMAMUX_IsActiveFlag_SO14
1494 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1495 * @retval State of bit (1 or 0).
1496 */
LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef * DMAMUXx)1497 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
1498 {
1499 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1500
1501 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL);
1502 }
1503
1504 /**
1505 * @brief Get Synchronization Event Overrun Flag Channel 15.
1506 * @rmtoll CSR SOF15 LL_DMAMUX_IsActiveFlag_SO15
1507 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1508 * @retval State of bit (1 or 0).
1509 */
LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef * DMAMUXx)1510 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
1511 {
1512 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1513
1514 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL);
1515 }
1516
1517 /**
1518 * @brief Get Request Generator 0 Trigger Event Overrun Flag.
1519 * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0
1520 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1521 * @retval State of bit (1 or 0).
1522 */
LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef * DMAMUXx)1523 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1524 {
1525 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1526
1527 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
1528 }
1529
1530 /**
1531 * @brief Get Request Generator 1 Trigger Event Overrun Flag.
1532 * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1
1533 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1534 * @retval State of bit (1 or 0).
1535 */
LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef * DMAMUXx)1536 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1537 {
1538 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1539
1540 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
1541 }
1542
1543 /**
1544 * @brief Get Request Generator 2 Trigger Event Overrun Flag.
1545 * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2
1546 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1547 * @retval State of bit (1 or 0).
1548 */
LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef * DMAMUXx)1549 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1550 {
1551 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1552
1553 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
1554 }
1555
1556 /**
1557 * @brief Get Request Generator 3 Trigger Event Overrun Flag.
1558 * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3
1559 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1560 * @retval State of bit (1 or 0).
1561 */
LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef * DMAMUXx)1562 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1563 {
1564 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1565
1566 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
1567 }
1568
1569 /**
1570 * @brief Get Request Generator 4 Trigger Event Overrun Flag.
1571 * @rmtoll RGSR OF4 LL_DMAMUX_IsActiveFlag_RGO4
1572 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1573 * @retval State of bit (1 or 0).
1574 */
LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef * DMAMUXx)1575 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
1576 {
1577 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1578
1579 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF4) == (DMAMUX_RGSR_OF4)) ? 1UL : 0UL);
1580 }
1581
1582 /**
1583 * @brief Get Request Generator 5 Trigger Event Overrun Flag.
1584 * @rmtoll RGSR OF5 LL_DMAMUX_IsActiveFlag_RGO5
1585 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1586 * @retval State of bit (1 or 0).
1587 */
LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef * DMAMUXx)1588 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
1589 {
1590 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1591
1592 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF5) == (DMAMUX_RGSR_OF5)) ? 1UL : 0UL);
1593 }
1594
1595 /**
1596 * @brief Get Request Generator 6 Trigger Event Overrun Flag.
1597 * @rmtoll RGSR OF6 LL_DMAMUX_IsActiveFlag_RGO6
1598 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1599 * @retval State of bit (1 or 0).
1600 */
LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef * DMAMUXx)1601 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
1602 {
1603 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1604
1605 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF6) == (DMAMUX_RGSR_OF6)) ? 1UL : 0UL);
1606 }
1607
1608 /**
1609 * @brief Get Request Generator 7 Trigger Event Overrun Flag.
1610 * @rmtoll RGSR OF7 LL_DMAMUX_IsActiveFlag_RGO7
1611 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1612 * @retval State of bit (1 or 0).
1613 */
LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef * DMAMUXx)1614 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
1615 {
1616 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1617
1618 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF7) == (DMAMUX_RGSR_OF7)) ? 1UL : 0UL);
1619 }
1620
1621 /**
1622 * @brief Clear Synchronization Event Overrun Flag Channel 0.
1623 * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0
1624 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1625 * @retval None
1626 */
LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef * DMAMUXx)1627 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1628 {
1629 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1630
1631 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF0);
1632 }
1633
1634 /**
1635 * @brief Clear Synchronization Event Overrun Flag Channel 1.
1636 * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1
1637 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1638 * @retval None
1639 */
LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef * DMAMUXx)1640 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1641 {
1642 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1643
1644 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF1);
1645 }
1646
1647 /**
1648 * @brief Clear Synchronization Event Overrun Flag Channel 2.
1649 * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2
1650 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1651 * @retval None
1652 */
LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef * DMAMUXx)1653 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1654 {
1655 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1656
1657 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF2);
1658 }
1659
1660 /**
1661 * @brief Clear Synchronization Event Overrun Flag Channel 3.
1662 * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3
1663 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1664 * @retval None
1665 */
LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef * DMAMUXx)1666 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1667 {
1668 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1669
1670 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF3);
1671 }
1672
1673 /**
1674 * @brief Clear Synchronization Event Overrun Flag Channel 4.
1675 * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4
1676 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1677 * @retval None
1678 */
LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef * DMAMUXx)1679 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
1680 {
1681 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1682
1683 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF4);
1684 }
1685
1686 /**
1687 * @brief Clear Synchronization Event Overrun Flag Channel 5.
1688 * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5
1689 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1690 * @retval None
1691 */
LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef * DMAMUXx)1692 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
1693 {
1694 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1695
1696 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF5);
1697 }
1698
1699 /**
1700 * @brief Clear Synchronization Event Overrun Flag Channel 6.
1701 * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6
1702 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1703 * @retval None
1704 */
LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef * DMAMUXx)1705 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
1706 {
1707 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1708
1709 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF6);
1710 }
1711
1712 /**
1713 * @brief Clear Synchronization Event Overrun Flag Channel 7.
1714 * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7
1715 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1716 * @retval None
1717 */
LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef * DMAMUXx)1718 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
1719 {
1720 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1721
1722 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF7);
1723 }
1724
1725 /**
1726 * @brief Clear Synchronization Event Overrun Flag Channel 8.
1727 * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8
1728 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1729 * @retval None
1730 */
LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef * DMAMUXx)1731 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
1732 {
1733 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1734
1735 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF8);
1736 }
1737
1738 /**
1739 * @brief Clear Synchronization Event Overrun Flag Channel 9.
1740 * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9
1741 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1742 * @retval None
1743 */
LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef * DMAMUXx)1744 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
1745 {
1746 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1747
1748 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF9);
1749 }
1750
1751 /**
1752 * @brief Clear Synchronization Event Overrun Flag Channel 10.
1753 * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10
1754 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1755 * @retval None
1756 */
LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef * DMAMUXx)1757 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
1758 {
1759 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1760
1761 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF10);
1762 }
1763
1764 /**
1765 * @brief Clear Synchronization Event Overrun Flag Channel 11.
1766 * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11
1767 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1768 * @retval None
1769 */
LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef * DMAMUXx)1770 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
1771 {
1772 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1773
1774 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF11);
1775 }
1776
1777 /**
1778 * @brief Clear Synchronization Event Overrun Flag Channel 12.
1779 * @rmtoll CFR CSOF12 LL_DMAMUX_ClearFlag_SO12
1780 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1781 * @retval None
1782 */
LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef * DMAMUXx)1783 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
1784 {
1785 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1786
1787 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF12);
1788 }
1789
1790 /**
1791 * @brief Clear Synchronization Event Overrun Flag Channel 13.
1792 * @rmtoll CFR CSOF13 LL_DMAMUX_ClearFlag_SO13
1793 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1794 * @retval None
1795 */
LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef * DMAMUXx)1796 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
1797 {
1798 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1799
1800 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF13);
1801 }
1802
1803 /**
1804 * @brief Clear Synchronization Event Overrun Flag Channel 14.
1805 * @rmtoll CFR CSOF14 LL_DMAMUX_ClearFlag_SO14
1806 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1807 * @retval None
1808 */
LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef * DMAMUXx)1809 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
1810 {
1811 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1812
1813 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF14);
1814 }
1815
1816 /**
1817 * @brief Clear Synchronization Event Overrun Flag Channel 15.
1818 * @rmtoll CFR CSOF15 LL_DMAMUX_ClearFlag_SO15
1819 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1820 * @retval None
1821 */
LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef * DMAMUXx)1822 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
1823 {
1824 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1825
1826 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF15);
1827 }
1828
1829 /**
1830 * @brief Clear Request Generator 0 Trigger Event Overrun Flag.
1831 * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0
1832 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1833 * @retval None
1834 */
LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef * DMAMUXx)1835 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1836 {
1837 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1838
1839 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF0);
1840 }
1841
1842 /**
1843 * @brief Clear Request Generator 1 Trigger Event Overrun Flag.
1844 * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1
1845 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1846 * @retval None
1847 */
LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef * DMAMUXx)1848 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1849 {
1850 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1851
1852 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF1);
1853 }
1854
1855 /**
1856 * @brief Clear Request Generator 2 Trigger Event Overrun Flag.
1857 * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2
1858 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1859 * @retval None
1860 */
LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef * DMAMUXx)1861 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1862 {
1863 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1864
1865 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF2);
1866 }
1867
1868 /**
1869 * @brief Clear Request Generator 3 Trigger Event Overrun Flag.
1870 * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3
1871 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1872 * @retval None
1873 */
LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef * DMAMUXx)1874 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1875 {
1876 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1877
1878 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF3);
1879 }
1880
1881 /**
1882 * @brief Clear Request Generator 4 Trigger Event Overrun Flag.
1883 * @rmtoll RGCFR COF4 LL_DMAMUX_ClearFlag_RGO4
1884 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1885 * @retval None
1886 */
LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef * DMAMUXx)1887 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
1888 {
1889 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1890
1891 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF4);
1892 }
1893
1894 /**
1895 * @brief Clear Request Generator 5 Trigger Event Overrun Flag.
1896 * @rmtoll RGCFR COF5 LL_DMAMUX_ClearFlag_RGO5
1897 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1898 * @retval None
1899 */
LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef * DMAMUXx)1900 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
1901 {
1902 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1903
1904 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF5);
1905 }
1906
1907 /**
1908 * @brief Clear Request Generator 6 Trigger Event Overrun Flag.
1909 * @rmtoll RGCFR COF6 LL_DMAMUX_ClearFlag_RGO6
1910 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1911 * @retval None
1912 */
LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef * DMAMUXx)1913 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
1914 {
1915 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1916
1917 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF6);
1918 }
1919
1920 /**
1921 * @brief Clear Request Generator 7 Trigger Event Overrun Flag.
1922 * @rmtoll RGCFR COF7 LL_DMAMUX_ClearFlag_RGO7
1923 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1924 * @retval None
1925 */
LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef * DMAMUXx)1926 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
1927 {
1928 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1929
1930 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF7);
1931 }
1932
1933 /**
1934 * @}
1935 */
1936
1937 /** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
1938 * @{
1939 */
1940
1941 /**
1942 * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
1943 * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO
1944 * @param DMAMUXx DMAMUXx Instance
1945 * @param Channel This parameter can be one of the following values:
1946 * @arg @ref LL_DMAMUX_CHANNEL_0
1947 * @arg @ref LL_DMAMUX_CHANNEL_1
1948 * @arg @ref LL_DMAMUX_CHANNEL_2
1949 * @arg @ref LL_DMAMUX_CHANNEL_3
1950 * @arg @ref LL_DMAMUX_CHANNEL_4
1951 * @arg @ref LL_DMAMUX_CHANNEL_5
1952 * @arg @ref LL_DMAMUX_CHANNEL_6
1953 * @arg @ref LL_DMAMUX_CHANNEL_7
1954 * @arg @ref LL_DMAMUX_CHANNEL_8
1955 * @arg @ref LL_DMAMUX_CHANNEL_9
1956 * @arg @ref LL_DMAMUX_CHANNEL_10
1957 * @arg @ref LL_DMAMUX_CHANNEL_11
1958 * @arg @ref LL_DMAMUX_CHANNEL_12
1959 * @arg @ref LL_DMAMUX_CHANNEL_13
1960 * @arg @ref LL_DMAMUX_CHANNEL_14
1961 * @arg @ref LL_DMAMUX_CHANNEL_15
1962 * @retval None
1963 */
LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)1964 __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1965 {
1966 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1967
1968 SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
1969 }
1970
1971 /**
1972 * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
1973 * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO
1974 * @param DMAMUXx DMAMUXx Instance
1975 * @param Channel This parameter can be one of the following values:
1976 * @arg @ref LL_DMAMUX_CHANNEL_0
1977 * @arg @ref LL_DMAMUX_CHANNEL_1
1978 * @arg @ref LL_DMAMUX_CHANNEL_2
1979 * @arg @ref LL_DMAMUX_CHANNEL_3
1980 * @arg @ref LL_DMAMUX_CHANNEL_4
1981 * @arg @ref LL_DMAMUX_CHANNEL_5
1982 * @arg @ref LL_DMAMUX_CHANNEL_6
1983 * @arg @ref LL_DMAMUX_CHANNEL_7
1984 * @arg @ref LL_DMAMUX_CHANNEL_8
1985 * @arg @ref LL_DMAMUX_CHANNEL_9
1986 * @arg @ref LL_DMAMUX_CHANNEL_10
1987 * @arg @ref LL_DMAMUX_CHANNEL_11
1988 * @arg @ref LL_DMAMUX_CHANNEL_12
1989 * @arg @ref LL_DMAMUX_CHANNEL_13
1990 * @arg @ref LL_DMAMUX_CHANNEL_14
1991 * @arg @ref LL_DMAMUX_CHANNEL_15
1992 * @retval None
1993 */
LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)1994 __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1995 {
1996 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1997
1998 CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
1999 }
2000
2001 /**
2002 * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
2003 * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO
2004 * @param DMAMUXx DMAMUXx Instance
2005 * @param Channel This parameter can be one of the following values:
2006 * @arg @ref LL_DMAMUX_CHANNEL_0
2007 * @arg @ref LL_DMAMUX_CHANNEL_1
2008 * @arg @ref LL_DMAMUX_CHANNEL_2
2009 * @arg @ref LL_DMAMUX_CHANNEL_3
2010 * @arg @ref LL_DMAMUX_CHANNEL_4
2011 * @arg @ref LL_DMAMUX_CHANNEL_5
2012 * @arg @ref LL_DMAMUX_CHANNEL_6
2013 * @arg @ref LL_DMAMUX_CHANNEL_7
2014 * @arg @ref LL_DMAMUX_CHANNEL_8
2015 * @arg @ref LL_DMAMUX_CHANNEL_9
2016 * @arg @ref LL_DMAMUX_CHANNEL_10
2017 * @arg @ref LL_DMAMUX_CHANNEL_11
2018 * @arg @ref LL_DMAMUX_CHANNEL_12
2019 * @arg @ref LL_DMAMUX_CHANNEL_13
2020 * @arg @ref LL_DMAMUX_CHANNEL_14
2021 * @arg @ref LL_DMAMUX_CHANNEL_15
2022 * @retval State of bit (1 or 0).
2023 */
LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)2024 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
2025 {
2026 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2027
2028 return (READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SOIE));
2029 }
2030
2031 /**
2032 * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
2033 * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO
2034 * @param DMAMUXx DMAMUXx Instance
2035 * @param RequestGenChannel This parameter can be one of the following values:
2036 * @arg @ref LL_DMAMUX_REQ_GEN_0
2037 * @arg @ref LL_DMAMUX_REQ_GEN_1
2038 * @arg @ref LL_DMAMUX_REQ_GEN_2
2039 * @arg @ref LL_DMAMUX_REQ_GEN_3
2040 * @arg @ref LL_DMAMUX_REQ_GEN_4
2041 * @arg @ref LL_DMAMUX_REQ_GEN_5
2042 * @arg @ref LL_DMAMUX_REQ_GEN_6
2043 * @arg @ref LL_DMAMUX_REQ_GEN_7
2044 * @retval None
2045 */
LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)2046 __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
2047 {
2048 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2049
2050 SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
2051 }
2052
2053 /**
2054 * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
2055 * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO
2056 * @param DMAMUXx DMAMUXx Instance
2057 * @param RequestGenChannel This parameter can be one of the following values:
2058 * @arg @ref LL_DMAMUX_REQ_GEN_0
2059 * @arg @ref LL_DMAMUX_REQ_GEN_1
2060 * @arg @ref LL_DMAMUX_REQ_GEN_2
2061 * @arg @ref LL_DMAMUX_REQ_GEN_3
2062 * @arg @ref LL_DMAMUX_REQ_GEN_4
2063 * @arg @ref LL_DMAMUX_REQ_GEN_5
2064 * @arg @ref LL_DMAMUX_REQ_GEN_6
2065 * @arg @ref LL_DMAMUX_REQ_GEN_7
2066 * @retval None
2067 */
LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)2068 __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
2069 {
2070 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2071
2072 CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
2073 }
2074
2075 /**
2076 * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
2077 * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO
2078 * @param DMAMUXx DMAMUXx Instance
2079 * @param RequestGenChannel This parameter can be one of the following values:
2080 * @arg @ref LL_DMAMUX_REQ_GEN_0
2081 * @arg @ref LL_DMAMUX_REQ_GEN_1
2082 * @arg @ref LL_DMAMUX_REQ_GEN_2
2083 * @arg @ref LL_DMAMUX_REQ_GEN_3
2084 * @arg @ref LL_DMAMUX_REQ_GEN_4
2085 * @arg @ref LL_DMAMUX_REQ_GEN_5
2086 * @arg @ref LL_DMAMUX_REQ_GEN_6
2087 * @arg @ref LL_DMAMUX_REQ_GEN_7
2088 * @retval State of bit (1 or 0).
2089 */
LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)2090 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
2091 {
2092 uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2093
2094 return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
2095 }
2096
2097 /**
2098 * @}
2099 */
2100
2101 /**
2102 * @}
2103 */
2104
2105 /**
2106 * @}
2107 */
2108
2109 #endif /* DMAMUX1 || DMAMUX2 */
2110
2111 /**
2112 * @}
2113 */
2114
2115 #ifdef __cplusplus
2116 }
2117 #endif
2118
2119 #endif /* __STM32MP1xx_LL_DMAMUX_H */
2120
