1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32MP1xx_LL_DMA_H
21 #define STM32MP1xx_LL_DMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32mp1xx.h"
29 #include "stm32mp1xx_ll_dmamux.h"
30 /** @addtogroup STM32MP1xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DMA1) || defined (DMA2)
35
36 /** @defgroup DMA_LL DMA
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
43 * @{
44 */
45 /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
46 static const uint8_t LL_DMA_STR_OFFSET_TAB[] =
47 {
48 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
49 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
55 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
56 };
57
58
59 /**
60 * @}
61 */
62
63 /* Private macros ------------------------------------------------------------*/
64
65 /**
66 * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel
67 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
68 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
69 * @param __DMA_INSTANCE__ DMAx
70 * @retval Channel_Offset (LL_DMAMUX_CHANNEL_8 or 0).
71 */
72 #define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \
73 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL)
74
75 /* Exported types ------------------------------------------------------------*/
76 #if defined(USE_FULL_LL_DRIVER)
77 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
78 * @{
79 */
80 typedef struct
81 {
82 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
83 or as Source base address in case of memory to memory transfer direction.
84
85 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
86
87 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
88 or as Destination base address in case of memory to memory transfer direction.
89
90 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
91
92 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
93 from memory to memory or from peripheral to memory.
94 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
95
96 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
97
98 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
99 This parameter can be a value of @ref DMA_LL_EC_MODE
100 @note The circular buffer mode cannot be used if the memory to memory
101 data transfer direction is configured on the selected Stream
102
103 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
104
105 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
106 is incremented or not.
107 This parameter can be a value of @ref DMA_LL_EC_PERIPH
108
109 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
110
111 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
112 is incremented or not.
113 This parameter can be a value of @ref DMA_LL_EC_MEMORY
114
115 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
116
117 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
118 in case of memory to memory transfer direction.
119 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
120
121 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
122
123 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
124 in case of memory to memory transfer direction.
125 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
126
127 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
128
129 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
130 The data unit is equal to the source buffer configuration set in PeripheralSize
131 or MemorySize parameters depending in the transfer direction.
132 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
133
134 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
135
136 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
137 This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
138
139 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
140
141 uint32_t Priority; /*!< Specifies the channel priority level.
142 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
143
144 This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
145
146 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
147 This parameter can be a value of @ref DMA_LL_FIFOMODE
148 @note The Direct mode (FIFO mode disabled) cannot be used if the
149 memory-to-memory data transfer is configured on the selected stream
150
151 This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
152
153 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
154 This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
155
156 This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
157
158 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
159 It specifies the amount of data to be transferred in a single non interruptible
160 transaction.
161 This parameter can be a value of @ref DMA_LL_EC_MBURST
162 @note The burst mode is possible only if the address Increment mode is enabled.
163
164 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
165
166 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
167 It specifies the amount of data to be transferred in a single non interruptible
168 transaction.
169 This parameter can be a value of @ref DMA_LL_EC_PBURST
170 @note The burst mode is possible only if the address Increment mode is enabled.
171
172 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
173
174 } LL_DMA_InitTypeDef;
175 /**
176 * @}
177 */
178 #endif /*USE_FULL_LL_DRIVER*/
179 /* Exported constants --------------------------------------------------------*/
180 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
181 * @{
182 */
183
184 /** @defgroup DMA_LL_EC_STREAM STREAM
185 * @{
186 */
187 #define LL_DMA_STREAM_0 0x00000000U
188 #define LL_DMA_STREAM_1 0x00000001U
189 #define LL_DMA_STREAM_2 0x00000002U
190 #define LL_DMA_STREAM_3 0x00000003U
191 #define LL_DMA_STREAM_4 0x00000004U
192 #define LL_DMA_STREAM_5 0x00000005U
193 #define LL_DMA_STREAM_6 0x00000006U
194 #define LL_DMA_STREAM_7 0x00000007U
195 #define LL_DMA_STREAM_ALL 0xFFFF0000U
196 /**
197 * @}
198 */
199
200
201 /** @defgroup DMA_LL_EC_DIRECTION DIRECTION
202 * @{
203 */
204 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
205 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */
206 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */
207 /**
208 * @}
209 */
210
211 /** @defgroup DMA_LL_EC_MODE MODE
212 * @{
213 */
214 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
215 #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */
216 #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */
217 /**
218 * @}
219 */
220
221 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
222 * @{
223 */
224 #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
225 #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */
226 /**
227 * @}
228 */
229
230 /** @defgroup DMA_LL_EC_PERIPH PERIPH
231 * @{
232 */
233 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
234 #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */
235 /**
236 * @}
237 */
238
239 /** @defgroup DMA_LL_EC_MEMORY MEMORY
240 * @{
241 */
242 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
243 #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */
244 /**
245 * @}
246 */
247
248 /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
249 * @{
250 */
251 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
252 #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
253 #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */
254 /**
255 * @}
256 */
257
258 /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
259 * @{
260 */
261 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
262 #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
263 #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */
264 /**
265 * @}
266 */
267
268 /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
269 * @{
270 */
271 #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */
272 #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
273 /**
274 * @}
275 */
276
277 /** @defgroup DMA_LL_EC_PRIORITY PRIORITY
278 * @{
279 */
280 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
281 #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */
282 #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */
283 #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */
284 /**
285 * @}
286 */
287
288
289 /** @defgroup DMA_LL_EC_MBURST MBURST
290 * @{
291 */
292 #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */
293 #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */
294 #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */
295 #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
296 /**
297 * @}
298 */
299
300 /** @defgroup DMA_LL_EC_PBURST PBURST
301 * @{
302 */
303 #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */
304 #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */
305 #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */
306 #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
307 /**
308 * @}
309 */
310
311 /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
312 * @{
313 */
314 #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */
315 #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */
316 /**
317 * @}
318 */
319
320 /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
321 * @{
322 */
323 #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */
324 #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */
325 #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */
326 #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */
327 #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */
328 #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */
329 /**
330 * @}
331 */
332
333 /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
334 * @{
335 */
336 #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */
337 #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */
338 #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */
339 #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */
340 /**
341 * @}
342 */
343
344 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
345 * @{
346 */
347 #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
348 #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
349 /**
350 * @}
351 */
352
353 /**
354 * @}
355 */
356
357 /* Exported macro ------------------------------------------------------------*/
358 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
359 * @{
360 */
361
362 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
363 * @{
364 */
365 /**
366 * @brief Write a value in DMA register
367 * @param __INSTANCE__ DMA Instance
368 * @param __REG__ Register to be written
369 * @param __VALUE__ Value to be written in the register
370 * @retval None
371 */
372 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
373
374 /**
375 * @brief Read a value in DMA register
376 * @param __INSTANCE__ DMA Instance
377 * @param __REG__ Register to be read
378 * @retval Register value
379 */
380 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
381 /**
382 * @}
383 */
384
385 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
386 * @{
387 */
388 /**
389 * @brief Convert DMAx_Streamy into DMAx
390 * @param __STREAM_INSTANCE__ DMAx_Streamy
391 * @retval DMAx
392 */
393 #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
394 (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
395
396 /**
397 * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
398 * @param __STREAM_INSTANCE__ DMAx_Streamy
399 * @retval LL_DMA_STREAM_y
400 */
401 #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
402 (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
403 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
404 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
405 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
406 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
407 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
408 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
409 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
410 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
411 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
412 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
413 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
414 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
415 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
416 LL_DMA_STREAM_7)
417
418 /**
419 * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
420 * @param __DMA_INSTANCE__ DMAx
421 * @param __STREAM__ LL_DMA_STREAM_y
422 * @retval DMAx_Streamy
423 */
424 #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
425 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
426 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
427 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
428 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
429 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
430 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
431 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
432 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
433 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
434 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
435 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
436 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
437 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
439 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
440 DMA2_Stream7)
441
442 /**
443 * @}
444 */
445
446 /**
447 * @}
448 */
449
450
451 /* Exported functions --------------------------------------------------------*/
452 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
453 * @{
454 */
455
456 /** @defgroup DMA_LL_EF_Configuration Configuration
457 * @{
458 */
459 /**
460 * @brief Enable DMA stream.
461 * @rmtoll CR EN LL_DMA_EnableStream
462 * @param DMAx DMAx Instance
463 * @param Stream This parameter can be one of the following values:
464 * @arg @ref LL_DMA_STREAM_0
465 * @arg @ref LL_DMA_STREAM_1
466 * @arg @ref LL_DMA_STREAM_2
467 * @arg @ref LL_DMA_STREAM_3
468 * @arg @ref LL_DMA_STREAM_4
469 * @arg @ref LL_DMA_STREAM_5
470 * @arg @ref LL_DMA_STREAM_6
471 * @arg @ref LL_DMA_STREAM_7
472 * @retval None
473 */
LL_DMA_EnableStream(DMA_TypeDef * DMAx,uint32_t Stream)474 __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
475 {
476 uint32_t dma_base_addr = (uint32_t)DMAx;
477
478 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
479 }
480
481 /**
482 * @brief Disable DMA stream.
483 * @rmtoll CR EN LL_DMA_DisableStream
484 * @param DMAx DMAx Instance
485 * @param Stream This parameter can be one of the following values:
486 * @arg @ref LL_DMA_STREAM_0
487 * @arg @ref LL_DMA_STREAM_1
488 * @arg @ref LL_DMA_STREAM_2
489 * @arg @ref LL_DMA_STREAM_3
490 * @arg @ref LL_DMA_STREAM_4
491 * @arg @ref LL_DMA_STREAM_5
492 * @arg @ref LL_DMA_STREAM_6
493 * @arg @ref LL_DMA_STREAM_7
494 * @retval None
495 */
LL_DMA_DisableStream(DMA_TypeDef * DMAx,uint32_t Stream)496 __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
497 {
498 uint32_t dma_base_addr = (uint32_t)DMAx;
499
500 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
501 }
502
503 /**
504 * @brief Check if DMA stream is enabled or disabled.
505 * @rmtoll CR EN LL_DMA_IsEnabledStream
506 * @param DMAx DMAx Instance
507 * @param Stream This parameter can be one of the following values:
508 * @arg @ref LL_DMA_STREAM_0
509 * @arg @ref LL_DMA_STREAM_1
510 * @arg @ref LL_DMA_STREAM_2
511 * @arg @ref LL_DMA_STREAM_3
512 * @arg @ref LL_DMA_STREAM_4
513 * @arg @ref LL_DMA_STREAM_5
514 * @arg @ref LL_DMA_STREAM_6
515 * @arg @ref LL_DMA_STREAM_7
516 * @retval State of bit (1 or 0).
517 */
LL_DMA_IsEnabledStream(DMA_TypeDef * DMAx,uint32_t Stream)518 __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
519 {
520 uint32_t dma_base_addr = (uint32_t)DMAx;
521
522 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL);
523 }
524
525 /**
526 * @brief Configure all parameters linked to DMA transfer.
527 * @rmtoll CR DIR LL_DMA_ConfigTransfer\n
528 * CR CIRC LL_DMA_ConfigTransfer\n
529 * CR PINC LL_DMA_ConfigTransfer\n
530 * CR MINC LL_DMA_ConfigTransfer\n
531 * CR PSIZE LL_DMA_ConfigTransfer\n
532 * CR MSIZE LL_DMA_ConfigTransfer\n
533 * CR PL LL_DMA_ConfigTransfer\n
534 * CR PFCTRL LL_DMA_ConfigTransfer
535 * @param DMAx DMAx Instance
536 * @param Stream This parameter can be one of the following values:
537 * @arg @ref LL_DMA_STREAM_0
538 * @arg @ref LL_DMA_STREAM_1
539 * @arg @ref LL_DMA_STREAM_2
540 * @arg @ref LL_DMA_STREAM_3
541 * @arg @ref LL_DMA_STREAM_4
542 * @arg @ref LL_DMA_STREAM_5
543 * @arg @ref LL_DMA_STREAM_6
544 * @arg @ref LL_DMA_STREAM_7
545 * @param Configuration This parameter must be a combination of all the following values:
546 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
547 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
548 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
549 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
550 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
551 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
552 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
553 *@retval None
554 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Configuration)555 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
556 {
557 uint32_t dma_base_addr = (uint32_t)DMAx;
558
559 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR,
560 DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
561 Configuration);
562 }
563
564 /**
565 * @brief Set Data transfer direction (read from peripheral or from memory).
566 * @rmtoll CR DIR LL_DMA_SetDataTransferDirection
567 * @param DMAx DMAx Instance
568 * @param Stream This parameter can be one of the following values:
569 * @arg @ref LL_DMA_STREAM_0
570 * @arg @ref LL_DMA_STREAM_1
571 * @arg @ref LL_DMA_STREAM_2
572 * @arg @ref LL_DMA_STREAM_3
573 * @arg @ref LL_DMA_STREAM_4
574 * @arg @ref LL_DMA_STREAM_5
575 * @arg @ref LL_DMA_STREAM_6
576 * @arg @ref LL_DMA_STREAM_7
577 * @param Direction This parameter can be one of the following values:
578 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
579 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
580 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
581 * @retval None
582 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Direction)583 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
584 {
585 uint32_t dma_base_addr = (uint32_t)DMAx;
586
587 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction);
588 }
589
590 /**
591 * @brief Get Data transfer direction (read from peripheral or from memory).
592 * @rmtoll CR DIR LL_DMA_GetDataTransferDirection
593 * @param DMAx DMAx Instance
594 * @param Stream This parameter can be one of the following values:
595 * @arg @ref LL_DMA_STREAM_0
596 * @arg @ref LL_DMA_STREAM_1
597 * @arg @ref LL_DMA_STREAM_2
598 * @arg @ref LL_DMA_STREAM_3
599 * @arg @ref LL_DMA_STREAM_4
600 * @arg @ref LL_DMA_STREAM_5
601 * @arg @ref LL_DMA_STREAM_6
602 * @arg @ref LL_DMA_STREAM_7
603 * @retval Returned value can be one of the following values:
604 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
605 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
606 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
607 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Stream)608 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
609 {
610 uint32_t dma_base_addr = (uint32_t)DMAx;
611
612 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR));
613 }
614
615 /**
616 * @brief Set DMA mode normal, circular or peripheral flow control.
617 * @rmtoll CR CIRC LL_DMA_SetMode\n
618 * CR PFCTRL LL_DMA_SetMode
619 * @param DMAx DMAx Instance
620 * @param Stream This parameter can be one of the following values:
621 * @arg @ref LL_DMA_STREAM_0
622 * @arg @ref LL_DMA_STREAM_1
623 * @arg @ref LL_DMA_STREAM_2
624 * @arg @ref LL_DMA_STREAM_3
625 * @arg @ref LL_DMA_STREAM_4
626 * @arg @ref LL_DMA_STREAM_5
627 * @arg @ref LL_DMA_STREAM_6
628 * @arg @ref LL_DMA_STREAM_7
629 * @param Mode This parameter can be one of the following values:
630 * @arg @ref LL_DMA_MODE_NORMAL
631 * @arg @ref LL_DMA_MODE_CIRCULAR
632 * @arg @ref LL_DMA_MODE_PFCTRL
633 * @retval None
634 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Mode)635 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
636 {
637 uint32_t dma_base_addr = (uint32_t)DMAx;
638
639 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
640 }
641
642 /**
643 * @brief Get DMA mode normal, circular or peripheral flow control.
644 * @rmtoll CR CIRC LL_DMA_GetMode\n
645 * CR PFCTRL LL_DMA_GetMode
646 * @param DMAx DMAx Instance
647 * @param Stream This parameter can be one of the following values:
648 * @arg @ref LL_DMA_STREAM_0
649 * @arg @ref LL_DMA_STREAM_1
650 * @arg @ref LL_DMA_STREAM_2
651 * @arg @ref LL_DMA_STREAM_3
652 * @arg @ref LL_DMA_STREAM_4
653 * @arg @ref LL_DMA_STREAM_5
654 * @arg @ref LL_DMA_STREAM_6
655 * @arg @ref LL_DMA_STREAM_7
656 * @retval Returned value can be one of the following values:
657 * @arg @ref LL_DMA_MODE_NORMAL
658 * @arg @ref LL_DMA_MODE_CIRCULAR
659 * @arg @ref LL_DMA_MODE_PFCTRL
660 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Stream)661 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
662 {
663 uint32_t dma_base_addr = (uint32_t)DMAx;
664
665 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
666 }
667
668 /**
669 * @brief Set Peripheral increment mode.
670 * @rmtoll CR PINC LL_DMA_SetPeriphIncMode
671 * @param DMAx DMAx Instance
672 * @param Stream This parameter can be one of the following values:
673 * @arg @ref LL_DMA_STREAM_0
674 * @arg @ref LL_DMA_STREAM_1
675 * @arg @ref LL_DMA_STREAM_2
676 * @arg @ref LL_DMA_STREAM_3
677 * @arg @ref LL_DMA_STREAM_4
678 * @arg @ref LL_DMA_STREAM_5
679 * @arg @ref LL_DMA_STREAM_6
680 * @arg @ref LL_DMA_STREAM_7
681 * @param IncrementMode This parameter can be one of the following values:
682 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
683 * @arg @ref LL_DMA_PERIPH_INCREMENT
684 * @retval None
685 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t IncrementMode)686 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
687 {
688 uint32_t dma_base_addr = (uint32_t)DMAx;
689
690 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode);
691 }
692
693 /**
694 * @brief Get Peripheral increment mode.
695 * @rmtoll CR PINC LL_DMA_GetPeriphIncMode
696 * @param DMAx DMAx Instance
697 * @param Stream This parameter can be one of the following values:
698 * @arg @ref LL_DMA_STREAM_0
699 * @arg @ref LL_DMA_STREAM_1
700 * @arg @ref LL_DMA_STREAM_2
701 * @arg @ref LL_DMA_STREAM_3
702 * @arg @ref LL_DMA_STREAM_4
703 * @arg @ref LL_DMA_STREAM_5
704 * @arg @ref LL_DMA_STREAM_6
705 * @arg @ref LL_DMA_STREAM_7
706 * @retval Returned value can be one of the following values:
707 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
708 * @arg @ref LL_DMA_PERIPH_INCREMENT
709 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Stream)710 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
711 {
712 uint32_t dma_base_addr = (uint32_t)DMAx;
713
714 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC));
715 }
716
717 /**
718 * @brief Set Memory increment mode.
719 * @rmtoll CR MINC LL_DMA_SetMemoryIncMode
720 * @param DMAx DMAx Instance
721 * @param Stream This parameter can be one of the following values:
722 * @arg @ref LL_DMA_STREAM_0
723 * @arg @ref LL_DMA_STREAM_1
724 * @arg @ref LL_DMA_STREAM_2
725 * @arg @ref LL_DMA_STREAM_3
726 * @arg @ref LL_DMA_STREAM_4
727 * @arg @ref LL_DMA_STREAM_5
728 * @arg @ref LL_DMA_STREAM_6
729 * @arg @ref LL_DMA_STREAM_7
730 * @param IncrementMode This parameter can be one of the following values:
731 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
732 * @arg @ref LL_DMA_MEMORY_INCREMENT
733 * @retval None
734 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t IncrementMode)735 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
736 {
737 uint32_t dma_base_addr = (uint32_t)DMAx;
738
739 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode);
740 }
741
742 /**
743 * @brief Get Memory increment mode.
744 * @rmtoll CR MINC LL_DMA_GetMemoryIncMode
745 * @param DMAx DMAx Instance
746 * @param Stream This parameter can be one of the following values:
747 * @arg @ref LL_DMA_STREAM_0
748 * @arg @ref LL_DMA_STREAM_1
749 * @arg @ref LL_DMA_STREAM_2
750 * @arg @ref LL_DMA_STREAM_3
751 * @arg @ref LL_DMA_STREAM_4
752 * @arg @ref LL_DMA_STREAM_5
753 * @arg @ref LL_DMA_STREAM_6
754 * @arg @ref LL_DMA_STREAM_7
755 * @retval Returned value can be one of the following values:
756 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
757 * @arg @ref LL_DMA_MEMORY_INCREMENT
758 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Stream)759 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
760 {
761 uint32_t dma_base_addr = (uint32_t)DMAx;
762
763 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC));
764 }
765
766 /**
767 * @brief Set Peripheral size.
768 * @rmtoll CR PSIZE LL_DMA_SetPeriphSize
769 * @param DMAx DMAx Instance
770 * @param Stream This parameter can be one of the following values:
771 * @arg @ref LL_DMA_STREAM_0
772 * @arg @ref LL_DMA_STREAM_1
773 * @arg @ref LL_DMA_STREAM_2
774 * @arg @ref LL_DMA_STREAM_3
775 * @arg @ref LL_DMA_STREAM_4
776 * @arg @ref LL_DMA_STREAM_5
777 * @arg @ref LL_DMA_STREAM_6
778 * @arg @ref LL_DMA_STREAM_7
779 * @param Size This parameter can be one of the following values:
780 * @arg @ref LL_DMA_PDATAALIGN_BYTE
781 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
782 * @arg @ref LL_DMA_PDATAALIGN_WORD
783 * @retval None
784 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Size)785 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
786 {
787 uint32_t dma_base_addr = (uint32_t)DMAx;
788
789 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size);
790 }
791
792 /**
793 * @brief Get Peripheral size.
794 * @rmtoll CR PSIZE LL_DMA_GetPeriphSize
795 * @param DMAx DMAx Instance
796 * @param Stream This parameter can be one of the following values:
797 * @arg @ref LL_DMA_STREAM_0
798 * @arg @ref LL_DMA_STREAM_1
799 * @arg @ref LL_DMA_STREAM_2
800 * @arg @ref LL_DMA_STREAM_3
801 * @arg @ref LL_DMA_STREAM_4
802 * @arg @ref LL_DMA_STREAM_5
803 * @arg @ref LL_DMA_STREAM_6
804 * @arg @ref LL_DMA_STREAM_7
805 * @retval Returned value can be one of the following values:
806 * @arg @ref LL_DMA_PDATAALIGN_BYTE
807 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
808 * @arg @ref LL_DMA_PDATAALIGN_WORD
809 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Stream)810 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
811 {
812 uint32_t dma_base_addr = (uint32_t)DMAx;
813
814 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE));
815 }
816
817 /**
818 * @brief Set Memory size.
819 * @rmtoll CR MSIZE LL_DMA_SetMemorySize
820 * @param DMAx DMAx Instance
821 * @param Stream This parameter can be one of the following values:
822 * @arg @ref LL_DMA_STREAM_0
823 * @arg @ref LL_DMA_STREAM_1
824 * @arg @ref LL_DMA_STREAM_2
825 * @arg @ref LL_DMA_STREAM_3
826 * @arg @ref LL_DMA_STREAM_4
827 * @arg @ref LL_DMA_STREAM_5
828 * @arg @ref LL_DMA_STREAM_6
829 * @arg @ref LL_DMA_STREAM_7
830 * @param Size This parameter can be one of the following values:
831 * @arg @ref LL_DMA_MDATAALIGN_BYTE
832 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
833 * @arg @ref LL_DMA_MDATAALIGN_WORD
834 * @retval None
835 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Size)836 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
837 {
838 uint32_t dma_base_addr = (uint32_t)DMAx;
839
840 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size);
841 }
842
843 /**
844 * @brief Get Memory size.
845 * @rmtoll CR MSIZE LL_DMA_GetMemorySize
846 * @param DMAx DMAx Instance
847 * @param Stream This parameter can be one of the following values:
848 * @arg @ref LL_DMA_STREAM_0
849 * @arg @ref LL_DMA_STREAM_1
850 * @arg @ref LL_DMA_STREAM_2
851 * @arg @ref LL_DMA_STREAM_3
852 * @arg @ref LL_DMA_STREAM_4
853 * @arg @ref LL_DMA_STREAM_5
854 * @arg @ref LL_DMA_STREAM_6
855 * @arg @ref LL_DMA_STREAM_7
856 * @retval Returned value can be one of the following values:
857 * @arg @ref LL_DMA_MDATAALIGN_BYTE
858 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
859 * @arg @ref LL_DMA_MDATAALIGN_WORD
860 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Stream)861 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
862 {
863 uint32_t dma_base_addr = (uint32_t)DMAx;
864
865 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE));
866 }
867
868 /**
869 * @brief Set Peripheral increment offset size.
870 * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
871 * @param DMAx DMAx Instance
872 * @param Stream This parameter can be one of the following values:
873 * @arg @ref LL_DMA_STREAM_0
874 * @arg @ref LL_DMA_STREAM_1
875 * @arg @ref LL_DMA_STREAM_2
876 * @arg @ref LL_DMA_STREAM_3
877 * @arg @ref LL_DMA_STREAM_4
878 * @arg @ref LL_DMA_STREAM_5
879 * @arg @ref LL_DMA_STREAM_6
880 * @arg @ref LL_DMA_STREAM_7
881 * @param OffsetSize This parameter can be one of the following values:
882 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
883 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
884 * @retval None
885 */
LL_DMA_SetIncOffsetSize(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t OffsetSize)886 __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
887 {
888 uint32_t dma_base_addr = (uint32_t)DMAx;
889
890 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize);
891 }
892
893 /**
894 * @brief Get Peripheral increment offset size.
895 * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
896 * @param DMAx DMAx Instance
897 * @param Stream This parameter can be one of the following values:
898 * @arg @ref LL_DMA_STREAM_0
899 * @arg @ref LL_DMA_STREAM_1
900 * @arg @ref LL_DMA_STREAM_2
901 * @arg @ref LL_DMA_STREAM_3
902 * @arg @ref LL_DMA_STREAM_4
903 * @arg @ref LL_DMA_STREAM_5
904 * @arg @ref LL_DMA_STREAM_6
905 * @arg @ref LL_DMA_STREAM_7
906 * @retval Returned value can be one of the following values:
907 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
908 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
909 */
LL_DMA_GetIncOffsetSize(DMA_TypeDef * DMAx,uint32_t Stream)910 __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
911 {
912 uint32_t dma_base_addr = (uint32_t)DMAx;
913
914 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS));
915 }
916
917 /**
918 * @brief Set Stream priority level.
919 * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
920 * @param DMAx DMAx Instance
921 * @param Stream This parameter can be one of the following values:
922 * @arg @ref LL_DMA_STREAM_0
923 * @arg @ref LL_DMA_STREAM_1
924 * @arg @ref LL_DMA_STREAM_2
925 * @arg @ref LL_DMA_STREAM_3
926 * @arg @ref LL_DMA_STREAM_4
927 * @arg @ref LL_DMA_STREAM_5
928 * @arg @ref LL_DMA_STREAM_6
929 * @arg @ref LL_DMA_STREAM_7
930 * @param Priority This parameter can be one of the following values:
931 * @arg @ref LL_DMA_PRIORITY_LOW
932 * @arg @ref LL_DMA_PRIORITY_MEDIUM
933 * @arg @ref LL_DMA_PRIORITY_HIGH
934 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
935 * @retval None
936 */
LL_DMA_SetStreamPriorityLevel(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Priority)937 __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
938 {
939 uint32_t dma_base_addr = (uint32_t)DMAx;
940
941 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority);
942 }
943
944 /**
945 * @brief Get Stream priority level.
946 * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
947 * @param DMAx DMAx Instance
948 * @param Stream This parameter can be one of the following values:
949 * @arg @ref LL_DMA_STREAM_0
950 * @arg @ref LL_DMA_STREAM_1
951 * @arg @ref LL_DMA_STREAM_2
952 * @arg @ref LL_DMA_STREAM_3
953 * @arg @ref LL_DMA_STREAM_4
954 * @arg @ref LL_DMA_STREAM_5
955 * @arg @ref LL_DMA_STREAM_6
956 * @arg @ref LL_DMA_STREAM_7
957 * @retval Returned value can be one of the following values:
958 * @arg @ref LL_DMA_PRIORITY_LOW
959 * @arg @ref LL_DMA_PRIORITY_MEDIUM
960 * @arg @ref LL_DMA_PRIORITY_HIGH
961 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
962 */
LL_DMA_GetStreamPriorityLevel(DMA_TypeDef * DMAx,uint32_t Stream)963 __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
964 {
965 uint32_t dma_base_addr = (uint32_t)DMAx;
966
967 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL));
968 }
969
970 /**
971 * @brief Set Number of data to transfer.
972 * @rmtoll NDTR NDT LL_DMA_SetDataLength
973 * @note This action has no effect if
974 * stream is enabled.
975 * @param DMAx DMAx Instance
976 * @param Stream This parameter can be one of the following values:
977 * @arg @ref LL_DMA_STREAM_0
978 * @arg @ref LL_DMA_STREAM_1
979 * @arg @ref LL_DMA_STREAM_2
980 * @arg @ref LL_DMA_STREAM_3
981 * @arg @ref LL_DMA_STREAM_4
982 * @arg @ref LL_DMA_STREAM_5
983 * @arg @ref LL_DMA_STREAM_6
984 * @arg @ref LL_DMA_STREAM_7
985 * @param NbData Between 0 to 0xFFFFFFFF
986 * @retval None
987 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t NbData)988 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData)
989 {
990 uint32_t dma_base_addr = (uint32_t)DMAx;
991
992 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData);
993 }
994
995 /**
996 * @brief Get Number of data to transfer.
997 * @rmtoll NDTR NDT LL_DMA_GetDataLength
998 * @note Once the stream is enabled, the return value indicate the
999 * remaining bytes to be transmitted.
1000 * @param DMAx DMAx Instance
1001 * @param Stream This parameter can be one of the following values:
1002 * @arg @ref LL_DMA_STREAM_0
1003 * @arg @ref LL_DMA_STREAM_1
1004 * @arg @ref LL_DMA_STREAM_2
1005 * @arg @ref LL_DMA_STREAM_3
1006 * @arg @ref LL_DMA_STREAM_4
1007 * @arg @ref LL_DMA_STREAM_5
1008 * @arg @ref LL_DMA_STREAM_6
1009 * @arg @ref LL_DMA_STREAM_7
1010 * @retval Between 0 to 0xFFFFFFFF
1011 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Stream)1012 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream)
1013 {
1014 uint32_t dma_base_addr = (uint32_t)DMAx;
1015
1016 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT));
1017 }
1018
1019 /**
1020 * @brief Set DMA request for DMA Streams on DMAMUX Channel x.
1021 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
1022 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
1023 * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
1024 * @param DMAx DMAx Instance
1025 * @param Stream This parameter can be one of the following values:
1026 * @arg @ref LL_DMA_STREAM_0
1027 * @arg @ref LL_DMA_STREAM_1
1028 * @arg @ref LL_DMA_STREAM_2
1029 * @arg @ref LL_DMA_STREAM_3
1030 * @arg @ref LL_DMA_STREAM_4
1031 * @arg @ref LL_DMA_STREAM_5
1032 * @arg @ref LL_DMA_STREAM_6
1033 * @arg @ref LL_DMA_STREAM_7
1034 * @param Request This parameter can be one of the following values:
1035 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
1036 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
1037 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
1038 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
1039 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
1040 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
1041 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
1042 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
1043 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
1044 * @arg @ref LL_DMAMUX1_REQ_ADC1
1045 * @arg @ref LL_DMAMUX1_REQ_ADC2
1046 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
1047 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
1048 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
1049 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
1050 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
1051 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
1052 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
1053 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
1054 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
1055 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
1056 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
1057 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
1058 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
1059 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
1060 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
1061 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
1062 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
1063 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
1064 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
1065 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
1066 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
1067 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
1068 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
1069 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
1070 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
1071 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
1072 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
1073 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
1074 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
1075 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
1076 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
1077 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
1078 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
1079 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
1080 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
1081 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
1082 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
1083 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
1084 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
1085 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
1086 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
1087 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
1088 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
1089 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
1090 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
1091 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
1092 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
1093 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
1094 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
1095 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
1096 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
1097 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
1098 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
1099 * @arg @ref LL_DMAMUX1_REQ_DAC1
1100 * @arg @ref LL_DMAMUX1_REQ_DAC2
1101 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
1102 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
1103 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
1104 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
1105 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
1106 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
1107 * @arg @ref LL_DMAMUX1_REQ_DCMI
1108 * @arg @ref LL_DMAMUX1_REQ_CRYP2_IN
1109 * @arg @ref LL_DMAMUX1_REQ_CRYP2_OUT
1110 * @arg @ref LL_DMAMUX1_REQ_HASH2_IN
1111 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
1112 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
1113 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
1114 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
1115 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
1116 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
1117 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
1118 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
1119 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
1120 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
1121 * @arg @ref LL_DMAMUX1_REQ_SAI2_A
1122 * @arg @ref LL_DMAMUX1_REQ_SAI2_B
1123 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT4
1124 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT5
1125 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
1126 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
1127 * @arg @ref LL_DMAMUX1_REQ_SAI4_B
1128 * @arg @ref LL_DMAMUX1_REQ_SAI4_B
1129 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
1130 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
1131 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
1132 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
1133 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
1134 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
1135 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
1136 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
1137 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
1138 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
1139 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
1140 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
1141 * @arg @ref LL_DMAMUX1_REQ_SAI3_A
1142 * @arg @ref LL_DMAMUX1_REQ_SAI3_B
1143 * @arg @ref LL_DMAMUX1_REQ_I2C5_RX
1144 * @arg @ref LL_DMAMUX1_REQ_I2C5_TX
1145 * @retval None
1146 */
LL_DMA_SetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Request)1147 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Request)
1148 {
1149 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
1150 }
1151
1152 /**
1153 * @brief Get DMA request for DMA Channels on DMAMUX Channel x.
1154 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
1155 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
1156 * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
1157 * @param DMAx DMAx Instance
1158 * @param Stream This parameter can be one of the following values:
1159 * @arg @ref LL_DMA_STREAM_0
1160 * @arg @ref LL_DMA_STREAM_1
1161 * @arg @ref LL_DMA_STREAM_2
1162 * @arg @ref LL_DMA_STREAM_3
1163 * @arg @ref LL_DMA_STREAM_4
1164 * @arg @ref LL_DMA_STREAM_5
1165 * @arg @ref LL_DMA_STREAM_6
1166 * @arg @ref LL_DMA_STREAM_7
1167 * @retval Returned value can be one of the following values:
1168 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
1169 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
1170 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
1171 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
1172 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
1173 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
1174 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
1175 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
1176 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
1177 * @arg @ref LL_DMAMUX1_REQ_ADC1
1178 * @arg @ref LL_DMAMUX1_REQ_ADC2
1179 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
1180 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
1181 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
1182 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
1183 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
1184 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
1185 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
1186 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
1187 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
1188 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
1189 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
1190 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
1191 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
1192 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
1193 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
1194 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
1195 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
1196 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
1197 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
1198 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
1199 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
1200 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
1201 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
1202 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
1203 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
1204 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
1205 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
1206 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
1207 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
1208 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
1209 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
1210 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
1211 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
1212 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
1213 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
1214 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
1215 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
1216 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
1217 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
1218 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
1219 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
1220 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
1221 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
1222 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
1223 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
1224 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
1225 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
1226 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
1227 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
1228 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
1229 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
1230 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
1231 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
1232 * @arg @ref LL_DMAMUX1_REQ_DAC1
1233 * @arg @ref LL_DMAMUX1_REQ_DAC2
1234 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
1235 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
1236 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
1237 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
1238 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
1239 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
1240 * @arg @ref LL_DMAMUX1_REQ_DCMI
1241 * @arg @ref LL_DMAMUX1_REQ_CRYP2_IN
1242 * @arg @ref LL_DMAMUX1_REQ_CRYP2_OUT
1243 * @arg @ref LL_DMAMUX1_REQ_HASH2_IN
1244 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
1245 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
1246 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
1247 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
1248 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
1249 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
1250 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
1251 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
1252 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
1253 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
1254 * @arg @ref LL_DMAMUX1_REQ_SAI2_A
1255 * @arg @ref LL_DMAMUX1_REQ_SAI2_B
1256 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT4
1257 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT5
1258 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
1259 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
1260 * @arg @ref LL_DMAMUX1_REQ_SAI4_B
1261 * @arg @ref LL_DMAMUX1_REQ_SAI4_B
1262 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
1263 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
1264 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
1265 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
1266 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
1267 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
1268 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
1269 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
1270 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
1271 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
1272 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
1273 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
1274 * @arg @ref LL_DMAMUX1_REQ_SAI3_A
1275 * @arg @ref LL_DMAMUX1_REQ_SAI3_B
1276 * @arg @ref LL_DMAMUX1_REQ_I2C5_RX
1277 * @arg @ref LL_DMAMUX1_REQ_I2C5_TX
1278 */
LL_DMA_GetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Stream)1279 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream)
1280 {
1281 return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
1282 }
1283 /**
1284 * @brief Set Memory burst transfer configuration.
1285 * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
1286 * @param DMAx DMAx Instance
1287 * @param Stream This parameter can be one of the following values:
1288 * @arg @ref LL_DMA_STREAM_0
1289 * @arg @ref LL_DMA_STREAM_1
1290 * @arg @ref LL_DMA_STREAM_2
1291 * @arg @ref LL_DMA_STREAM_3
1292 * @arg @ref LL_DMA_STREAM_4
1293 * @arg @ref LL_DMA_STREAM_5
1294 * @arg @ref LL_DMA_STREAM_6
1295 * @arg @ref LL_DMA_STREAM_7
1296 * @param Mburst This parameter can be one of the following values:
1297 * @arg @ref LL_DMA_MBURST_SINGLE
1298 * @arg @ref LL_DMA_MBURST_INC4
1299 * @arg @ref LL_DMA_MBURST_INC8
1300 * @arg @ref LL_DMA_MBURST_INC16
1301 * @retval None
1302 */
LL_DMA_SetMemoryBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Mburst)1303 __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
1304 {
1305 uint32_t dma_base_addr = (uint32_t)DMAx;
1306
1307 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst);
1308 }
1309
1310 /**
1311 * @brief Get Memory burst transfer configuration.
1312 * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
1313 * @param DMAx DMAx Instance
1314 * @param Stream This parameter can be one of the following values:
1315 * @arg @ref LL_DMA_STREAM_0
1316 * @arg @ref LL_DMA_STREAM_1
1317 * @arg @ref LL_DMA_STREAM_2
1318 * @arg @ref LL_DMA_STREAM_3
1319 * @arg @ref LL_DMA_STREAM_4
1320 * @arg @ref LL_DMA_STREAM_5
1321 * @arg @ref LL_DMA_STREAM_6
1322 * @arg @ref LL_DMA_STREAM_7
1323 * @retval Returned value can be one of the following values:
1324 * @arg @ref LL_DMA_MBURST_SINGLE
1325 * @arg @ref LL_DMA_MBURST_INC4
1326 * @arg @ref LL_DMA_MBURST_INC8
1327 * @arg @ref LL_DMA_MBURST_INC16
1328 */
LL_DMA_GetMemoryBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream)1329 __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1330 {
1331 uint32_t dma_base_addr = (uint32_t)DMAx;
1332
1333 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST));
1334 }
1335
1336 /**
1337 * @brief Set Peripheral burst transfer configuration.
1338 * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
1339 * @param DMAx DMAx Instance
1340 * @param Stream This parameter can be one of the following values:
1341 * @arg @ref LL_DMA_STREAM_0
1342 * @arg @ref LL_DMA_STREAM_1
1343 * @arg @ref LL_DMA_STREAM_2
1344 * @arg @ref LL_DMA_STREAM_3
1345 * @arg @ref LL_DMA_STREAM_4
1346 * @arg @ref LL_DMA_STREAM_5
1347 * @arg @ref LL_DMA_STREAM_6
1348 * @arg @ref LL_DMA_STREAM_7
1349 * @param Pburst This parameter can be one of the following values:
1350 * @arg @ref LL_DMA_PBURST_SINGLE
1351 * @arg @ref LL_DMA_PBURST_INC4
1352 * @arg @ref LL_DMA_PBURST_INC8
1353 * @arg @ref LL_DMA_PBURST_INC16
1354 * @retval None
1355 */
LL_DMA_SetPeriphBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Pburst)1356 __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
1357 {
1358 uint32_t dma_base_addr = (uint32_t)DMAx;
1359
1360 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst);
1361 }
1362
1363 /**
1364 * @brief Get Peripheral burst transfer configuration.
1365 * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
1366 * @param DMAx DMAx Instance
1367 * @param Stream This parameter can be one of the following values:
1368 * @arg @ref LL_DMA_STREAM_0
1369 * @arg @ref LL_DMA_STREAM_1
1370 * @arg @ref LL_DMA_STREAM_2
1371 * @arg @ref LL_DMA_STREAM_3
1372 * @arg @ref LL_DMA_STREAM_4
1373 * @arg @ref LL_DMA_STREAM_5
1374 * @arg @ref LL_DMA_STREAM_6
1375 * @arg @ref LL_DMA_STREAM_7
1376 * @retval Returned value can be one of the following values:
1377 * @arg @ref LL_DMA_PBURST_SINGLE
1378 * @arg @ref LL_DMA_PBURST_INC4
1379 * @arg @ref LL_DMA_PBURST_INC8
1380 * @arg @ref LL_DMA_PBURST_INC16
1381 */
LL_DMA_GetPeriphBurstxfer(DMA_TypeDef * DMAx,uint32_t Stream)1382 __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1383 {
1384 uint32_t dma_base_addr = (uint32_t)DMAx;
1385
1386 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST));
1387 }
1388
1389 /**
1390 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1391 * @rmtoll CR CT LL_DMA_SetCurrentTargetMem
1392 * @param DMAx DMAx Instance
1393 * @param Stream This parameter can be one of the following values:
1394 * @arg @ref LL_DMA_STREAM_0
1395 * @arg @ref LL_DMA_STREAM_1
1396 * @arg @ref LL_DMA_STREAM_2
1397 * @arg @ref LL_DMA_STREAM_3
1398 * @arg @ref LL_DMA_STREAM_4
1399 * @arg @ref LL_DMA_STREAM_5
1400 * @arg @ref LL_DMA_STREAM_6
1401 * @arg @ref LL_DMA_STREAM_7
1402 * @param CurrentMemory This parameter can be one of the following values:
1403 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1404 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1405 * @retval None
1406 */
LL_DMA_SetCurrentTargetMem(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t CurrentMemory)1407 __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
1408 {
1409 uint32_t dma_base_addr = (uint32_t)DMAx;
1410
1411 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory);
1412 }
1413
1414 /**
1415 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1416 * @rmtoll CR CT LL_DMA_GetCurrentTargetMem
1417 * @param DMAx DMAx Instance
1418 * @param Stream This parameter can be one of the following values:
1419 * @arg @ref LL_DMA_STREAM_0
1420 * @arg @ref LL_DMA_STREAM_1
1421 * @arg @ref LL_DMA_STREAM_2
1422 * @arg @ref LL_DMA_STREAM_3
1423 * @arg @ref LL_DMA_STREAM_4
1424 * @arg @ref LL_DMA_STREAM_5
1425 * @arg @ref LL_DMA_STREAM_6
1426 * @arg @ref LL_DMA_STREAM_7
1427 * @retval Returned value can be one of the following values:
1428 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1429 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1430 */
LL_DMA_GetCurrentTargetMem(DMA_TypeDef * DMAx,uint32_t Stream)1431 __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
1432 {
1433 uint32_t dma_base_addr = (uint32_t)DMAx;
1434
1435 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT));
1436 }
1437
1438 /**
1439 * @brief Enable the double buffer mode.
1440 * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
1441 * @param DMAx DMAx Instance
1442 * @param Stream This parameter can be one of the following values:
1443 * @arg @ref LL_DMA_STREAM_0
1444 * @arg @ref LL_DMA_STREAM_1
1445 * @arg @ref LL_DMA_STREAM_2
1446 * @arg @ref LL_DMA_STREAM_3
1447 * @arg @ref LL_DMA_STREAM_4
1448 * @arg @ref LL_DMA_STREAM_5
1449 * @arg @ref LL_DMA_STREAM_6
1450 * @arg @ref LL_DMA_STREAM_7
1451 * @retval None
1452 */
LL_DMA_EnableDoubleBufferMode(DMA_TypeDef * DMAx,uint32_t Stream)1453 __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1454 {
1455 uint32_t dma_base_addr = (uint32_t)DMAx;
1456
1457 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
1458 }
1459
1460 /**
1461 * @brief Disable the double buffer mode.
1462 * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
1463 * @param DMAx DMAx Instance
1464 * @param Stream This parameter can be one of the following values:
1465 * @arg @ref LL_DMA_STREAM_0
1466 * @arg @ref LL_DMA_STREAM_1
1467 * @arg @ref LL_DMA_STREAM_2
1468 * @arg @ref LL_DMA_STREAM_3
1469 * @arg @ref LL_DMA_STREAM_4
1470 * @arg @ref LL_DMA_STREAM_5
1471 * @arg @ref LL_DMA_STREAM_6
1472 * @arg @ref LL_DMA_STREAM_7
1473 * @retval None
1474 */
LL_DMA_DisableDoubleBufferMode(DMA_TypeDef * DMAx,uint32_t Stream)1475 __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1476 {
1477 uint32_t dma_base_addr = (uint32_t)DMAx;
1478
1479 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
1480 }
1481
1482 /**
1483 * @brief Get FIFO status.
1484 * @rmtoll FCR FS LL_DMA_GetFIFOStatus
1485 * @param DMAx DMAx Instance
1486 * @param Stream This parameter can be one of the following values:
1487 * @arg @ref LL_DMA_STREAM_0
1488 * @arg @ref LL_DMA_STREAM_1
1489 * @arg @ref LL_DMA_STREAM_2
1490 * @arg @ref LL_DMA_STREAM_3
1491 * @arg @ref LL_DMA_STREAM_4
1492 * @arg @ref LL_DMA_STREAM_5
1493 * @arg @ref LL_DMA_STREAM_6
1494 * @arg @ref LL_DMA_STREAM_7
1495 * @retval Returned value can be one of the following values:
1496 * @arg @ref LL_DMA_FIFOSTATUS_0_25
1497 * @arg @ref LL_DMA_FIFOSTATUS_25_50
1498 * @arg @ref LL_DMA_FIFOSTATUS_50_75
1499 * @arg @ref LL_DMA_FIFOSTATUS_75_100
1500 * @arg @ref LL_DMA_FIFOSTATUS_EMPTY
1501 * @arg @ref LL_DMA_FIFOSTATUS_FULL
1502 */
LL_DMA_GetFIFOStatus(DMA_TypeDef * DMAx,uint32_t Stream)1503 __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
1504 {
1505 uint32_t dma_base_addr = (uint32_t)DMAx;
1506
1507 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS));
1508 }
1509
1510 /**
1511 * @brief Disable Fifo mode.
1512 * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
1513 * @param DMAx DMAx Instance
1514 * @param Stream This parameter can be one of the following values:
1515 * @arg @ref LL_DMA_STREAM_0
1516 * @arg @ref LL_DMA_STREAM_1
1517 * @arg @ref LL_DMA_STREAM_2
1518 * @arg @ref LL_DMA_STREAM_3
1519 * @arg @ref LL_DMA_STREAM_4
1520 * @arg @ref LL_DMA_STREAM_5
1521 * @arg @ref LL_DMA_STREAM_6
1522 * @arg @ref LL_DMA_STREAM_7
1523 * @retval None
1524 */
LL_DMA_DisableFifoMode(DMA_TypeDef * DMAx,uint32_t Stream)1525 __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1526 {
1527 uint32_t dma_base_addr = (uint32_t)DMAx;
1528
1529 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
1530 }
1531
1532 /**
1533 * @brief Enable Fifo mode.
1534 * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
1535 * @param DMAx DMAx Instance
1536 * @param Stream This parameter can be one of the following values:
1537 * @arg @ref LL_DMA_STREAM_0
1538 * @arg @ref LL_DMA_STREAM_1
1539 * @arg @ref LL_DMA_STREAM_2
1540 * @arg @ref LL_DMA_STREAM_3
1541 * @arg @ref LL_DMA_STREAM_4
1542 * @arg @ref LL_DMA_STREAM_5
1543 * @arg @ref LL_DMA_STREAM_6
1544 * @arg @ref LL_DMA_STREAM_7
1545 * @retval None
1546 */
LL_DMA_EnableFifoMode(DMA_TypeDef * DMAx,uint32_t Stream)1547 __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1548 {
1549 uint32_t dma_base_addr = (uint32_t)DMAx;
1550
1551 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
1552 }
1553
1554 /**
1555 * @brief Select FIFO threshold.
1556 * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
1557 * @param DMAx DMAx Instance
1558 * @param Stream This parameter can be one of the following values:
1559 * @arg @ref LL_DMA_STREAM_0
1560 * @arg @ref LL_DMA_STREAM_1
1561 * @arg @ref LL_DMA_STREAM_2
1562 * @arg @ref LL_DMA_STREAM_3
1563 * @arg @ref LL_DMA_STREAM_4
1564 * @arg @ref LL_DMA_STREAM_5
1565 * @arg @ref LL_DMA_STREAM_6
1566 * @arg @ref LL_DMA_STREAM_7
1567 * @param Threshold This parameter can be one of the following values:
1568 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1569 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1570 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1571 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1572 * @retval None
1573 */
LL_DMA_SetFIFOThreshold(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Threshold)1574 __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
1575 {
1576 uint32_t dma_base_addr = (uint32_t)DMAx;
1577
1578 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold);
1579 }
1580
1581 /**
1582 * @brief Get FIFO threshold.
1583 * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
1584 * @param DMAx DMAx Instance
1585 * @param Stream This parameter can be one of the following values:
1586 * @arg @ref LL_DMA_STREAM_0
1587 * @arg @ref LL_DMA_STREAM_1
1588 * @arg @ref LL_DMA_STREAM_2
1589 * @arg @ref LL_DMA_STREAM_3
1590 * @arg @ref LL_DMA_STREAM_4
1591 * @arg @ref LL_DMA_STREAM_5
1592 * @arg @ref LL_DMA_STREAM_6
1593 * @arg @ref LL_DMA_STREAM_7
1594 * @retval Returned value can be one of the following values:
1595 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1596 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1597 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1598 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1599 */
LL_DMA_GetFIFOThreshold(DMA_TypeDef * DMAx,uint32_t Stream)1600 __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
1601 {
1602 uint32_t dma_base_addr = (uint32_t)DMAx;
1603
1604 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH));
1605 }
1606
1607 /**
1608 * @brief Configure the FIFO .
1609 * @rmtoll FCR FTH LL_DMA_ConfigFifo\n
1610 * FCR DMDIS LL_DMA_ConfigFifo
1611 * @param DMAx DMAx Instance
1612 * @param Stream This parameter can be one of the following values:
1613 * @arg @ref LL_DMA_STREAM_0
1614 * @arg @ref LL_DMA_STREAM_1
1615 * @arg @ref LL_DMA_STREAM_2
1616 * @arg @ref LL_DMA_STREAM_3
1617 * @arg @ref LL_DMA_STREAM_4
1618 * @arg @ref LL_DMA_STREAM_5
1619 * @arg @ref LL_DMA_STREAM_6
1620 * @arg @ref LL_DMA_STREAM_7
1621 * @param FifoMode This parameter can be one of the following values:
1622 * @arg @ref LL_DMA_FIFOMODE_ENABLE
1623 * @arg @ref LL_DMA_FIFOMODE_DISABLE
1624 * @param FifoThreshold This parameter can be one of the following values:
1625 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1626 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1627 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1628 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1629 * @retval None
1630 */
LL_DMA_ConfigFifo(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t FifoMode,uint32_t FifoThreshold)1631 __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
1632 {
1633 uint32_t dma_base_addr = (uint32_t)DMAx;
1634
1635 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold);
1636 }
1637
1638 /**
1639 * @brief Configure the Source and Destination addresses.
1640 * @note This API must not be called when the DMA stream is enabled.
1641 * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
1642 * PAR PA LL_DMA_ConfigAddresses
1643 * @param DMAx DMAx Instance
1644 * @param Stream This parameter can be one of the following values:
1645 * @arg @ref LL_DMA_STREAM_0
1646 * @arg @ref LL_DMA_STREAM_1
1647 * @arg @ref LL_DMA_STREAM_2
1648 * @arg @ref LL_DMA_STREAM_3
1649 * @arg @ref LL_DMA_STREAM_4
1650 * @arg @ref LL_DMA_STREAM_5
1651 * @arg @ref LL_DMA_STREAM_6
1652 * @arg @ref LL_DMA_STREAM_7
1653 * @param SrcAddress Between 0 to 0xFFFFFFFF
1654 * @param DstAddress Between 0 to 0xFFFFFFFF
1655 * @param Direction This parameter can be one of the following values:
1656 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1657 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1658 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1659 * @retval None
1660 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)1661 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
1662 {
1663 uint32_t dma_base_addr = (uint32_t)DMAx;
1664
1665 /* Direction Memory to Periph */
1666 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1667 {
1668 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, SrcAddress);
1669 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, DstAddress);
1670 }
1671 /* Direction Periph to Memory and Memory to Memory */
1672 else
1673 {
1674 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, SrcAddress);
1675 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, DstAddress);
1676 }
1677 }
1678
1679 /**
1680 * @brief Set the Memory address.
1681 * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
1682 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1683 * @note This API must not be called when the DMA stream is enabled.
1684 * @param DMAx DMAx Instance
1685 * @param Stream This parameter can be one of the following values:
1686 * @arg @ref LL_DMA_STREAM_0
1687 * @arg @ref LL_DMA_STREAM_1
1688 * @arg @ref LL_DMA_STREAM_2
1689 * @arg @ref LL_DMA_STREAM_3
1690 * @arg @ref LL_DMA_STREAM_4
1691 * @arg @ref LL_DMA_STREAM_5
1692 * @arg @ref LL_DMA_STREAM_6
1693 * @arg @ref LL_DMA_STREAM_7
1694 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1695 * @retval None
1696 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t MemoryAddress)1697 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
1698 {
1699 uint32_t dma_base_addr = (uint32_t)DMAx;
1700
1701 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
1702 }
1703
1704 /**
1705 * @brief Set the Peripheral address.
1706 * @rmtoll PAR PA LL_DMA_SetPeriphAddress
1707 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1708 * @note This API must not be called when the DMA stream is enabled.
1709 * @param DMAx DMAx Instance
1710 * @param Stream This parameter can be one of the following values:
1711 * @arg @ref LL_DMA_STREAM_0
1712 * @arg @ref LL_DMA_STREAM_1
1713 * @arg @ref LL_DMA_STREAM_2
1714 * @arg @ref LL_DMA_STREAM_3
1715 * @arg @ref LL_DMA_STREAM_4
1716 * @arg @ref LL_DMA_STREAM_5
1717 * @arg @ref LL_DMA_STREAM_6
1718 * @arg @ref LL_DMA_STREAM_7
1719 * @param PeriphAddress Between 0 to 0xFFFFFFFF
1720 * @retval None
1721 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t PeriphAddress)1722 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress)
1723 {
1724 uint32_t dma_base_addr = (uint32_t)DMAx;
1725
1726 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress);
1727 }
1728
1729 /**
1730 * @brief Get the Memory address.
1731 * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
1732 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1733 * @param DMAx DMAx Instance
1734 * @param Stream This parameter can be one of the following values:
1735 * @arg @ref LL_DMA_STREAM_0
1736 * @arg @ref LL_DMA_STREAM_1
1737 * @arg @ref LL_DMA_STREAM_2
1738 * @arg @ref LL_DMA_STREAM_3
1739 * @arg @ref LL_DMA_STREAM_4
1740 * @arg @ref LL_DMA_STREAM_5
1741 * @arg @ref LL_DMA_STREAM_6
1742 * @arg @ref LL_DMA_STREAM_7
1743 * @retval Between 0 to 0xFFFFFFFF
1744 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Stream)1745 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream)
1746 {
1747 uint32_t dma_base_addr = (uint32_t)DMAx;
1748
1749 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
1750 }
1751
1752 /**
1753 * @brief Get the Peripheral address.
1754 * @rmtoll PAR PA LL_DMA_GetPeriphAddress
1755 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1756 * @param DMAx DMAx Instance
1757 * @param Stream This parameter can be one of the following values:
1758 * @arg @ref LL_DMA_STREAM_0
1759 * @arg @ref LL_DMA_STREAM_1
1760 * @arg @ref LL_DMA_STREAM_2
1761 * @arg @ref LL_DMA_STREAM_3
1762 * @arg @ref LL_DMA_STREAM_4
1763 * @arg @ref LL_DMA_STREAM_5
1764 * @arg @ref LL_DMA_STREAM_6
1765 * @arg @ref LL_DMA_STREAM_7
1766 * @retval Between 0 to 0xFFFFFFFF
1767 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Stream)1768 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream)
1769 {
1770 uint32_t dma_base_addr = (uint32_t)DMAx;
1771
1772 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
1773 }
1774
1775 /**
1776 * @brief Set the Memory to Memory Source address.
1777 * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
1778 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1779 * @note This API must not be called when the DMA stream is enabled.
1780 * @param DMAx DMAx Instance
1781 * @param Stream This parameter can be one of the following values:
1782 * @arg @ref LL_DMA_STREAM_0
1783 * @arg @ref LL_DMA_STREAM_1
1784 * @arg @ref LL_DMA_STREAM_2
1785 * @arg @ref LL_DMA_STREAM_3
1786 * @arg @ref LL_DMA_STREAM_4
1787 * @arg @ref LL_DMA_STREAM_5
1788 * @arg @ref LL_DMA_STREAM_6
1789 * @arg @ref LL_DMA_STREAM_7
1790 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1791 * @retval None
1792 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t MemoryAddress)1793 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
1794 {
1795 uint32_t dma_base_addr = (uint32_t)DMAx;
1796
1797 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress);
1798 }
1799
1800 /**
1801 * @brief Set the Memory to Memory Destination address.
1802 * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
1803 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1804 * @note This API must not be called when the DMA stream is enabled.
1805 * @param DMAx DMAx Instance
1806 * @param Stream This parameter can be one of the following values:
1807 * @arg @ref LL_DMA_STREAM_0
1808 * @arg @ref LL_DMA_STREAM_1
1809 * @arg @ref LL_DMA_STREAM_2
1810 * @arg @ref LL_DMA_STREAM_3
1811 * @arg @ref LL_DMA_STREAM_4
1812 * @arg @ref LL_DMA_STREAM_5
1813 * @arg @ref LL_DMA_STREAM_6
1814 * @arg @ref LL_DMA_STREAM_7
1815 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1816 * @retval None
1817 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t MemoryAddress)1818 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
1819 {
1820 uint32_t dma_base_addr = (uint32_t)DMAx;
1821
1822 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
1823 }
1824
1825 /**
1826 * @brief Get the Memory to Memory Source address.
1827 * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
1828 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1829 * @param DMAx DMAx Instance
1830 * @param Stream This parameter can be one of the following values:
1831 * @arg @ref LL_DMA_STREAM_0
1832 * @arg @ref LL_DMA_STREAM_1
1833 * @arg @ref LL_DMA_STREAM_2
1834 * @arg @ref LL_DMA_STREAM_3
1835 * @arg @ref LL_DMA_STREAM_4
1836 * @arg @ref LL_DMA_STREAM_5
1837 * @arg @ref LL_DMA_STREAM_6
1838 * @arg @ref LL_DMA_STREAM_7
1839 * @retval Between 0 to 0xFFFFFFFF
1840 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Stream)1841 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream)
1842 {
1843 uint32_t dma_base_addr = (uint32_t)DMAx;
1844
1845 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
1846 }
1847
1848 /**
1849 * @brief Get the Memory to Memory Destination address.
1850 * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
1851 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1852 * @param DMAx DMAx Instance
1853 * @param Stream This parameter can be one of the following values:
1854 * @arg @ref LL_DMA_STREAM_0
1855 * @arg @ref LL_DMA_STREAM_1
1856 * @arg @ref LL_DMA_STREAM_2
1857 * @arg @ref LL_DMA_STREAM_3
1858 * @arg @ref LL_DMA_STREAM_4
1859 * @arg @ref LL_DMA_STREAM_5
1860 * @arg @ref LL_DMA_STREAM_6
1861 * @arg @ref LL_DMA_STREAM_7
1862 * @retval Between 0 to 0xFFFFFFFF
1863 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Stream)1864 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream)
1865 {
1866 uint32_t dma_base_addr = (uint32_t)DMAx;
1867
1868 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
1869 }
1870
1871 /**
1872 * @brief Set Memory 1 address (used in case of Double buffer mode).
1873 * @rmtoll M1AR M1A LL_DMA_SetMemory1Address
1874 * @param DMAx DMAx Instance
1875 * @param Stream This parameter can be one of the following values:
1876 * @arg @ref LL_DMA_STREAM_0
1877 * @arg @ref LL_DMA_STREAM_1
1878 * @arg @ref LL_DMA_STREAM_2
1879 * @arg @ref LL_DMA_STREAM_3
1880 * @arg @ref LL_DMA_STREAM_4
1881 * @arg @ref LL_DMA_STREAM_5
1882 * @arg @ref LL_DMA_STREAM_6
1883 * @arg @ref LL_DMA_STREAM_7
1884 * @param Address Between 0 to 0xFFFFFFFF
1885 * @retval None
1886 */
LL_DMA_SetMemory1Address(DMA_TypeDef * DMAx,uint32_t Stream,uint32_t Address)1887 __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
1888 {
1889 uint32_t dma_base_addr = (uint32_t)DMAx;
1890
1891 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address);
1892 }
1893
1894 /**
1895 * @brief Get Memory 1 address (used in case of Double buffer mode).
1896 * @rmtoll M1AR M1A LL_DMA_GetMemory1Address
1897 * @param DMAx DMAx Instance
1898 * @param Stream This parameter can be one of the following values:
1899 * @arg @ref LL_DMA_STREAM_0
1900 * @arg @ref LL_DMA_STREAM_1
1901 * @arg @ref LL_DMA_STREAM_2
1902 * @arg @ref LL_DMA_STREAM_3
1903 * @arg @ref LL_DMA_STREAM_4
1904 * @arg @ref LL_DMA_STREAM_5
1905 * @arg @ref LL_DMA_STREAM_6
1906 * @arg @ref LL_DMA_STREAM_7
1907 * @retval Between 0 to 0xFFFFFFFF
1908 */
LL_DMA_GetMemory1Address(DMA_TypeDef * DMAx,uint32_t Stream)1909 __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
1910 {
1911 uint32_t dma_base_addr = (uint32_t)DMAx;
1912
1913 return (((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR);
1914 }
1915
1916 /**
1917 * @}
1918 */
1919
1920 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1921 * @{
1922 */
1923
1924 /**
1925 * @brief Get Stream 0 half transfer flag.
1926 * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
1927 * @param DMAx DMAx Instance
1928 * @retval State of bit (1 or 0).
1929 */
LL_DMA_IsActiveFlag_HT0(DMA_TypeDef * DMAx)1930 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
1931 {
1932 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL);
1933 }
1934
1935 /**
1936 * @brief Get Stream 1 half transfer flag.
1937 * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
1938 * @param DMAx DMAx Instance
1939 * @retval State of bit (1 or 0).
1940 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1941 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1942 {
1943 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL);
1944 }
1945
1946 /**
1947 * @brief Get Stream 2 half transfer flag.
1948 * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
1949 * @param DMAx DMAx Instance
1950 * @retval State of bit (1 or 0).
1951 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1952 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1953 {
1954 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL);
1955 }
1956
1957 /**
1958 * @brief Get Stream 3 half transfer flag.
1959 * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
1960 * @param DMAx DMAx Instance
1961 * @retval State of bit (1 or 0).
1962 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1963 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1964 {
1965 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL);
1966 }
1967
1968 /**
1969 * @brief Get Stream 4 half transfer flag.
1970 * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
1971 * @param DMAx DMAx Instance
1972 * @retval State of bit (1 or 0).
1973 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1974 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1975 {
1976 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL);
1977 }
1978
1979 /**
1980 * @brief Get Stream 5 half transfer flag.
1981 * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
1982 * @param DMAx DMAx Instance
1983 * @retval State of bit (1 or 0).
1984 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1985 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1986 {
1987 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL);
1988 }
1989
1990 /**
1991 * @brief Get Stream 6 half transfer flag.
1992 * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
1993 * @param DMAx DMAx Instance
1994 * @retval State of bit (1 or 0).
1995 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)1996 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1997 {
1998 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL);
1999 }
2000
2001 /**
2002 * @brief Get Stream 7 half transfer flag.
2003 * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
2004 * @param DMAx DMAx Instance
2005 * @retval State of bit (1 or 0).
2006 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)2007 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
2008 {
2009 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL);
2010 }
2011
2012 /**
2013 * @brief Get Stream 0 transfer complete flag.
2014 * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
2015 * @param DMAx DMAx Instance
2016 * @retval State of bit (1 or 0).
2017 */
LL_DMA_IsActiveFlag_TC0(DMA_TypeDef * DMAx)2018 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
2019 {
2020 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL);
2021 }
2022
2023 /**
2024 * @brief Get Stream 1 transfer complete flag.
2025 * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
2026 * @param DMAx DMAx Instance
2027 * @retval State of bit (1 or 0).
2028 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)2029 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
2030 {
2031 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL);
2032 }
2033
2034 /**
2035 * @brief Get Stream 2 transfer complete flag.
2036 * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
2037 * @param DMAx DMAx Instance
2038 * @retval State of bit (1 or 0).
2039 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)2040 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
2041 {
2042 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL);
2043 }
2044
2045 /**
2046 * @brief Get Stream 3 transfer complete flag.
2047 * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
2048 * @param DMAx DMAx Instance
2049 * @retval State of bit (1 or 0).
2050 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)2051 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
2052 {
2053 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL);
2054 }
2055
2056 /**
2057 * @brief Get Stream 4 transfer complete flag.
2058 * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
2059 * @param DMAx DMAx Instance
2060 * @retval State of bit (1 or 0).
2061 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)2062 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
2063 {
2064 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL);
2065 }
2066
2067 /**
2068 * @brief Get Stream 5 transfer complete flag.
2069 * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
2070 * @param DMAx DMAx Instance
2071 * @retval State of bit (1 or 0).
2072 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)2073 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
2074 {
2075 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL);
2076 }
2077
2078 /**
2079 * @brief Get Stream 6 transfer complete flag.
2080 * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
2081 * @param DMAx DMAx Instance
2082 * @retval State of bit (1 or 0).
2083 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)2084 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
2085 {
2086 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL);
2087 }
2088
2089 /**
2090 * @brief Get Stream 7 transfer complete flag.
2091 * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
2092 * @param DMAx DMAx Instance
2093 * @retval State of bit (1 or 0).
2094 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)2095 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
2096 {
2097 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL);
2098 }
2099
2100 /**
2101 * @brief Get Stream 0 transfer error flag.
2102 * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
2103 * @param DMAx DMAx Instance
2104 * @retval State of bit (1 or 0).
2105 */
LL_DMA_IsActiveFlag_TE0(DMA_TypeDef * DMAx)2106 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
2107 {
2108 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL);
2109 }
2110
2111 /**
2112 * @brief Get Stream 1 transfer error flag.
2113 * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
2114 * @param DMAx DMAx Instance
2115 * @retval State of bit (1 or 0).
2116 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)2117 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
2118 {
2119 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL);
2120 }
2121
2122 /**
2123 * @brief Get Stream 2 transfer error flag.
2124 * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
2125 * @param DMAx DMAx Instance
2126 * @retval State of bit (1 or 0).
2127 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)2128 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
2129 {
2130 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL);
2131 }
2132
2133 /**
2134 * @brief Get Stream 3 transfer error flag.
2135 * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
2136 * @param DMAx DMAx Instance
2137 * @retval State of bit (1 or 0).
2138 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)2139 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
2140 {
2141 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL);
2142 }
2143
2144 /**
2145 * @brief Get Stream 4 transfer error flag.
2146 * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
2147 * @param DMAx DMAx Instance
2148 * @retval State of bit (1 or 0).
2149 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)2150 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
2151 {
2152 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL);
2153 }
2154
2155 /**
2156 * @brief Get Stream 5 transfer error flag.
2157 * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
2158 * @param DMAx DMAx Instance
2159 * @retval State of bit (1 or 0).
2160 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)2161 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
2162 {
2163 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL);
2164 }
2165
2166 /**
2167 * @brief Get Stream 6 transfer error flag.
2168 * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
2169 * @param DMAx DMAx Instance
2170 * @retval State of bit (1 or 0).
2171 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)2172 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
2173 {
2174 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL);
2175 }
2176
2177 /**
2178 * @brief Get Stream 7 transfer error flag.
2179 * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
2180 * @param DMAx DMAx Instance
2181 * @retval State of bit (1 or 0).
2182 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)2183 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
2184 {
2185 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL);
2186 }
2187
2188 /**
2189 * @brief Get Stream 0 direct mode error flag.
2190 * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
2191 * @param DMAx DMAx Instance
2192 * @retval State of bit (1 or 0).
2193 */
LL_DMA_IsActiveFlag_DME0(DMA_TypeDef * DMAx)2194 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
2195 {
2196 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL);
2197 }
2198
2199 /**
2200 * @brief Get Stream 1 direct mode error flag.
2201 * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
2202 * @param DMAx DMAx Instance
2203 * @retval State of bit (1 or 0).
2204 */
LL_DMA_IsActiveFlag_DME1(DMA_TypeDef * DMAx)2205 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
2206 {
2207 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL);
2208 }
2209
2210 /**
2211 * @brief Get Stream 2 direct mode error flag.
2212 * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
2213 * @param DMAx DMAx Instance
2214 * @retval State of bit (1 or 0).
2215 */
LL_DMA_IsActiveFlag_DME2(DMA_TypeDef * DMAx)2216 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
2217 {
2218 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL);
2219 }
2220
2221 /**
2222 * @brief Get Stream 3 direct mode error flag.
2223 * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
2224 * @param DMAx DMAx Instance
2225 * @retval State of bit (1 or 0).
2226 */
LL_DMA_IsActiveFlag_DME3(DMA_TypeDef * DMAx)2227 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
2228 {
2229 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL);
2230 }
2231
2232 /**
2233 * @brief Get Stream 4 direct mode error flag.
2234 * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
2235 * @param DMAx DMAx Instance
2236 * @retval State of bit (1 or 0).
2237 */
LL_DMA_IsActiveFlag_DME4(DMA_TypeDef * DMAx)2238 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
2239 {
2240 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL);
2241 }
2242
2243 /**
2244 * @brief Get Stream 5 direct mode error flag.
2245 * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
2246 * @param DMAx DMAx Instance
2247 * @retval State of bit (1 or 0).
2248 */
LL_DMA_IsActiveFlag_DME5(DMA_TypeDef * DMAx)2249 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
2250 {
2251 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL);
2252 }
2253
2254 /**
2255 * @brief Get Stream 6 direct mode error flag.
2256 * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
2257 * @param DMAx DMAx Instance
2258 * @retval State of bit (1 or 0).
2259 */
LL_DMA_IsActiveFlag_DME6(DMA_TypeDef * DMAx)2260 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
2261 {
2262 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL);
2263 }
2264
2265 /**
2266 * @brief Get Stream 7 direct mode error flag.
2267 * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
2268 * @param DMAx DMAx Instance
2269 * @retval State of bit (1 or 0).
2270 */
LL_DMA_IsActiveFlag_DME7(DMA_TypeDef * DMAx)2271 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
2272 {
2273 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL);
2274 }
2275
2276 /**
2277 * @brief Get Stream 0 FIFO error flag.
2278 * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
2279 * @param DMAx DMAx Instance
2280 * @retval State of bit (1 or 0).
2281 */
LL_DMA_IsActiveFlag_FE0(DMA_TypeDef * DMAx)2282 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
2283 {
2284 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL);
2285 }
2286
2287 /**
2288 * @brief Get Stream 1 FIFO error flag.
2289 * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
2290 * @param DMAx DMAx Instance
2291 * @retval State of bit (1 or 0).
2292 */
LL_DMA_IsActiveFlag_FE1(DMA_TypeDef * DMAx)2293 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
2294 {
2295 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL);
2296 }
2297
2298 /**
2299 * @brief Get Stream 2 FIFO error flag.
2300 * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
2301 * @param DMAx DMAx Instance
2302 * @retval State of bit (1 or 0).
2303 */
LL_DMA_IsActiveFlag_FE2(DMA_TypeDef * DMAx)2304 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
2305 {
2306 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL);
2307 }
2308
2309 /**
2310 * @brief Get Stream 3 FIFO error flag.
2311 * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
2312 * @param DMAx DMAx Instance
2313 * @retval State of bit (1 or 0).
2314 */
LL_DMA_IsActiveFlag_FE3(DMA_TypeDef * DMAx)2315 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
2316 {
2317 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL);
2318 }
2319
2320 /**
2321 * @brief Get Stream 4 FIFO error flag.
2322 * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
2323 * @param DMAx DMAx Instance
2324 * @retval State of bit (1 or 0).
2325 */
LL_DMA_IsActiveFlag_FE4(DMA_TypeDef * DMAx)2326 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
2327 {
2328 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL);
2329 }
2330
2331 /**
2332 * @brief Get Stream 5 FIFO error flag.
2333 * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
2334 * @param DMAx DMAx Instance
2335 * @retval State of bit (1 or 0).
2336 */
LL_DMA_IsActiveFlag_FE5(DMA_TypeDef * DMAx)2337 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
2338 {
2339 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL);
2340 }
2341
2342 /**
2343 * @brief Get Stream 6 FIFO error flag.
2344 * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
2345 * @param DMAx DMAx Instance
2346 * @retval State of bit (1 or 0).
2347 */
LL_DMA_IsActiveFlag_FE6(DMA_TypeDef * DMAx)2348 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
2349 {
2350 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL);
2351 }
2352
2353 /**
2354 * @brief Get Stream 7 FIFO error flag.
2355 * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
2356 * @param DMAx DMAx Instance
2357 * @retval State of bit (1 or 0).
2358 */
LL_DMA_IsActiveFlag_FE7(DMA_TypeDef * DMAx)2359 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
2360 {
2361 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL);
2362 }
2363
2364 /**
2365 * @brief Clear Stream 0 half transfer flag.
2366 * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
2367 * @param DMAx DMAx Instance
2368 * @retval None
2369 */
LL_DMA_ClearFlag_HT0(DMA_TypeDef * DMAx)2370 __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
2371 {
2372 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF0);
2373 }
2374
2375 /**
2376 * @brief Clear Stream 1 half transfer flag.
2377 * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
2378 * @param DMAx DMAx Instance
2379 * @retval None
2380 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)2381 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
2382 {
2383 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF1);
2384 }
2385
2386 /**
2387 * @brief Clear Stream 2 half transfer flag.
2388 * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
2389 * @param DMAx DMAx Instance
2390 * @retval None
2391 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)2392 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
2393 {
2394 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF2);
2395 }
2396
2397 /**
2398 * @brief Clear Stream 3 half transfer flag.
2399 * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
2400 * @param DMAx DMAx Instance
2401 * @retval None
2402 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)2403 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
2404 {
2405 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF3);
2406 }
2407
2408 /**
2409 * @brief Clear Stream 4 half transfer flag.
2410 * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
2411 * @param DMAx DMAx Instance
2412 * @retval None
2413 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)2414 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
2415 {
2416 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF4);
2417 }
2418
2419 /**
2420 * @brief Clear Stream 5 half transfer flag.
2421 * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
2422 * @param DMAx DMAx Instance
2423 * @retval None
2424 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)2425 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
2426 {
2427 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF5);
2428 }
2429
2430 /**
2431 * @brief Clear Stream 6 half transfer flag.
2432 * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
2433 * @param DMAx DMAx Instance
2434 * @retval None
2435 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)2436 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
2437 {
2438 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF6);
2439 }
2440
2441 /**
2442 * @brief Clear Stream 7 half transfer flag.
2443 * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
2444 * @param DMAx DMAx Instance
2445 * @retval None
2446 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)2447 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
2448 {
2449 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF7);
2450 }
2451
2452 /**
2453 * @brief Clear Stream 0 transfer complete flag.
2454 * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
2455 * @param DMAx DMAx Instance
2456 * @retval None
2457 */
LL_DMA_ClearFlag_TC0(DMA_TypeDef * DMAx)2458 __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
2459 {
2460 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF0);
2461 }
2462
2463 /**
2464 * @brief Clear Stream 1 transfer complete flag.
2465 * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
2466 * @param DMAx DMAx Instance
2467 * @retval None
2468 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)2469 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
2470 {
2471 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF1);
2472 }
2473
2474 /**
2475 * @brief Clear Stream 2 transfer complete flag.
2476 * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
2477 * @param DMAx DMAx Instance
2478 * @retval None
2479 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)2480 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
2481 {
2482 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF2);
2483 }
2484
2485 /**
2486 * @brief Clear Stream 3 transfer complete flag.
2487 * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
2488 * @param DMAx DMAx Instance
2489 * @retval None
2490 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)2491 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
2492 {
2493 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF3);
2494 }
2495
2496 /**
2497 * @brief Clear Stream 4 transfer complete flag.
2498 * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
2499 * @param DMAx DMAx Instance
2500 * @retval None
2501 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)2502 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
2503 {
2504 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF4);
2505 }
2506
2507 /**
2508 * @brief Clear Stream 5 transfer complete flag.
2509 * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
2510 * @param DMAx DMAx Instance
2511 * @retval None
2512 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)2513 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
2514 {
2515 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF5);
2516 }
2517
2518 /**
2519 * @brief Clear Stream 6 transfer complete flag.
2520 * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
2521 * @param DMAx DMAx Instance
2522 * @retval None
2523 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)2524 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
2525 {
2526 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF6);
2527 }
2528
2529 /**
2530 * @brief Clear Stream 7 transfer complete flag.
2531 * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
2532 * @param DMAx DMAx Instance
2533 * @retval None
2534 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)2535 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
2536 {
2537 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF7);
2538 }
2539
2540 /**
2541 * @brief Clear Stream 0 transfer error flag.
2542 * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
2543 * @param DMAx DMAx Instance
2544 * @retval None
2545 */
LL_DMA_ClearFlag_TE0(DMA_TypeDef * DMAx)2546 __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
2547 {
2548 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF0);
2549 }
2550
2551 /**
2552 * @brief Clear Stream 1 transfer error flag.
2553 * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
2554 * @param DMAx DMAx Instance
2555 * @retval None
2556 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)2557 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
2558 {
2559 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF1);
2560 }
2561
2562 /**
2563 * @brief Clear Stream 2 transfer error flag.
2564 * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
2565 * @param DMAx DMAx Instance
2566 * @retval None
2567 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)2568 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
2569 {
2570 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF2);
2571 }
2572
2573 /**
2574 * @brief Clear Stream 3 transfer error flag.
2575 * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
2576 * @param DMAx DMAx Instance
2577 * @retval None
2578 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)2579 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
2580 {
2581 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF3);
2582 }
2583
2584 /**
2585 * @brief Clear Stream 4 transfer error flag.
2586 * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
2587 * @param DMAx DMAx Instance
2588 * @retval None
2589 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)2590 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
2591 {
2592 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF4);
2593 }
2594
2595 /**
2596 * @brief Clear Stream 5 transfer error flag.
2597 * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
2598 * @param DMAx DMAx Instance
2599 * @retval None
2600 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)2601 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
2602 {
2603 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF5);
2604 }
2605
2606 /**
2607 * @brief Clear Stream 6 transfer error flag.
2608 * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
2609 * @param DMAx DMAx Instance
2610 * @retval None
2611 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)2612 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
2613 {
2614 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF6);
2615 }
2616
2617 /**
2618 * @brief Clear Stream 7 transfer error flag.
2619 * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
2620 * @param DMAx DMAx Instance
2621 * @retval None
2622 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)2623 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2624 {
2625 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF7);
2626 }
2627
2628 /**
2629 * @brief Clear Stream 0 direct mode error flag.
2630 * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
2631 * @param DMAx DMAx Instance
2632 * @retval None
2633 */
LL_DMA_ClearFlag_DME0(DMA_TypeDef * DMAx)2634 __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
2635 {
2636 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF0);
2637 }
2638
2639 /**
2640 * @brief Clear Stream 1 direct mode error flag.
2641 * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
2642 * @param DMAx DMAx Instance
2643 * @retval None
2644 */
LL_DMA_ClearFlag_DME1(DMA_TypeDef * DMAx)2645 __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
2646 {
2647 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF1);
2648 }
2649
2650 /**
2651 * @brief Clear Stream 2 direct mode error flag.
2652 * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
2653 * @param DMAx DMAx Instance
2654 * @retval None
2655 */
LL_DMA_ClearFlag_DME2(DMA_TypeDef * DMAx)2656 __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
2657 {
2658 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF2);
2659 }
2660
2661 /**
2662 * @brief Clear Stream 3 direct mode error flag.
2663 * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
2664 * @param DMAx DMAx Instance
2665 * @retval None
2666 */
LL_DMA_ClearFlag_DME3(DMA_TypeDef * DMAx)2667 __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
2668 {
2669 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF3);
2670 }
2671
2672 /**
2673 * @brief Clear Stream 4 direct mode error flag.
2674 * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
2675 * @param DMAx DMAx Instance
2676 * @retval None
2677 */
LL_DMA_ClearFlag_DME4(DMA_TypeDef * DMAx)2678 __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
2679 {
2680 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF4);
2681 }
2682
2683 /**
2684 * @brief Clear Stream 5 direct mode error flag.
2685 * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
2686 * @param DMAx DMAx Instance
2687 * @retval None
2688 */
LL_DMA_ClearFlag_DME5(DMA_TypeDef * DMAx)2689 __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
2690 {
2691 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF5);
2692 }
2693
2694 /**
2695 * @brief Clear Stream 6 direct mode error flag.
2696 * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
2697 * @param DMAx DMAx Instance
2698 * @retval None
2699 */
LL_DMA_ClearFlag_DME6(DMA_TypeDef * DMAx)2700 __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
2701 {
2702 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF6);
2703 }
2704
2705 /**
2706 * @brief Clear Stream 7 direct mode error flag.
2707 * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
2708 * @param DMAx DMAx Instance
2709 * @retval None
2710 */
LL_DMA_ClearFlag_DME7(DMA_TypeDef * DMAx)2711 __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
2712 {
2713 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF7);
2714 }
2715
2716 /**
2717 * @brief Clear Stream 0 FIFO error flag.
2718 * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
2719 * @param DMAx DMAx Instance
2720 * @retval None
2721 */
LL_DMA_ClearFlag_FE0(DMA_TypeDef * DMAx)2722 __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
2723 {
2724 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF0);
2725 }
2726
2727 /**
2728 * @brief Clear Stream 1 FIFO error flag.
2729 * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
2730 * @param DMAx DMAx Instance
2731 * @retval None
2732 */
LL_DMA_ClearFlag_FE1(DMA_TypeDef * DMAx)2733 __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
2734 {
2735 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF1);
2736 }
2737
2738 /**
2739 * @brief Clear Stream 2 FIFO error flag.
2740 * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
2741 * @param DMAx DMAx Instance
2742 * @retval None
2743 */
LL_DMA_ClearFlag_FE2(DMA_TypeDef * DMAx)2744 __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
2745 {
2746 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF2);
2747 }
2748
2749 /**
2750 * @brief Clear Stream 3 FIFO error flag.
2751 * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
2752 * @param DMAx DMAx Instance
2753 * @retval None
2754 */
LL_DMA_ClearFlag_FE3(DMA_TypeDef * DMAx)2755 __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
2756 {
2757 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF3);
2758 }
2759
2760 /**
2761 * @brief Clear Stream 4 FIFO error flag.
2762 * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
2763 * @param DMAx DMAx Instance
2764 * @retval None
2765 */
LL_DMA_ClearFlag_FE4(DMA_TypeDef * DMAx)2766 __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
2767 {
2768 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF4);
2769 }
2770
2771 /**
2772 * @brief Clear Stream 5 FIFO error flag.
2773 * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
2774 * @param DMAx DMAx Instance
2775 * @retval None
2776 */
LL_DMA_ClearFlag_FE5(DMA_TypeDef * DMAx)2777 __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
2778 {
2779 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF5);
2780 }
2781
2782 /**
2783 * @brief Clear Stream 6 FIFO error flag.
2784 * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
2785 * @param DMAx DMAx Instance
2786 * @retval None
2787 */
LL_DMA_ClearFlag_FE6(DMA_TypeDef * DMAx)2788 __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
2789 {
2790 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF6);
2791 }
2792
2793 /**
2794 * @brief Clear Stream 7 FIFO error flag.
2795 * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
2796 * @param DMAx DMAx Instance
2797 * @retval None
2798 */
LL_DMA_ClearFlag_FE7(DMA_TypeDef * DMAx)2799 __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
2800 {
2801 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF7);
2802 }
2803
2804 /**
2805 * @}
2806 */
2807
2808 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2809 * @{
2810 */
2811
2812 /**
2813 * @brief Enable Half transfer interrupt.
2814 * @rmtoll CR HTIE LL_DMA_EnableIT_HT
2815 * @param DMAx DMAx Instance
2816 * @param Stream This parameter can be one of the following values:
2817 * @arg @ref LL_DMA_STREAM_0
2818 * @arg @ref LL_DMA_STREAM_1
2819 * @arg @ref LL_DMA_STREAM_2
2820 * @arg @ref LL_DMA_STREAM_3
2821 * @arg @ref LL_DMA_STREAM_4
2822 * @arg @ref LL_DMA_STREAM_5
2823 * @arg @ref LL_DMA_STREAM_6
2824 * @arg @ref LL_DMA_STREAM_7
2825 * @retval None
2826 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Stream)2827 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2828 {
2829 uint32_t dma_base_addr = (uint32_t)DMAx;
2830
2831 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
2832 }
2833
2834 /**
2835 * @brief Enable Transfer error interrupt.
2836 * @rmtoll CR TEIE LL_DMA_EnableIT_TE
2837 * @param DMAx DMAx Instance
2838 * @param Stream This parameter can be one of the following values:
2839 * @arg @ref LL_DMA_STREAM_0
2840 * @arg @ref LL_DMA_STREAM_1
2841 * @arg @ref LL_DMA_STREAM_2
2842 * @arg @ref LL_DMA_STREAM_3
2843 * @arg @ref LL_DMA_STREAM_4
2844 * @arg @ref LL_DMA_STREAM_5
2845 * @arg @ref LL_DMA_STREAM_6
2846 * @arg @ref LL_DMA_STREAM_7
2847 * @retval None
2848 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Stream)2849 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2850 {
2851 uint32_t dma_base_addr = (uint32_t)DMAx;
2852
2853 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
2854 }
2855
2856 /**
2857 * @brief Enable Transfer complete interrupt.
2858 * @rmtoll CR TCIE LL_DMA_EnableIT_TC
2859 * @param DMAx DMAx Instance
2860 * @param Stream This parameter can be one of the following values:
2861 * @arg @ref LL_DMA_STREAM_0
2862 * @arg @ref LL_DMA_STREAM_1
2863 * @arg @ref LL_DMA_STREAM_2
2864 * @arg @ref LL_DMA_STREAM_3
2865 * @arg @ref LL_DMA_STREAM_4
2866 * @arg @ref LL_DMA_STREAM_5
2867 * @arg @ref LL_DMA_STREAM_6
2868 * @arg @ref LL_DMA_STREAM_7
2869 * @retval None
2870 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Stream)2871 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2872 {
2873 uint32_t dma_base_addr = (uint32_t)DMAx;
2874
2875 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
2876 }
2877
2878 /**
2879 * @brief Enable Direct mode error interrupt.
2880 * @rmtoll CR DMEIE LL_DMA_EnableIT_DME
2881 * @param DMAx DMAx Instance
2882 * @param Stream This parameter can be one of the following values:
2883 * @arg @ref LL_DMA_STREAM_0
2884 * @arg @ref LL_DMA_STREAM_1
2885 * @arg @ref LL_DMA_STREAM_2
2886 * @arg @ref LL_DMA_STREAM_3
2887 * @arg @ref LL_DMA_STREAM_4
2888 * @arg @ref LL_DMA_STREAM_5
2889 * @arg @ref LL_DMA_STREAM_6
2890 * @arg @ref LL_DMA_STREAM_7
2891 * @retval None
2892 */
LL_DMA_EnableIT_DME(DMA_TypeDef * DMAx,uint32_t Stream)2893 __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2894 {
2895 uint32_t dma_base_addr = (uint32_t)DMAx;
2896
2897 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
2898 }
2899
2900 /**
2901 * @brief Enable FIFO error interrupt.
2902 * @rmtoll FCR FEIE LL_DMA_EnableIT_FE
2903 * @param DMAx DMAx Instance
2904 * @param Stream This parameter can be one of the following values:
2905 * @arg @ref LL_DMA_STREAM_0
2906 * @arg @ref LL_DMA_STREAM_1
2907 * @arg @ref LL_DMA_STREAM_2
2908 * @arg @ref LL_DMA_STREAM_3
2909 * @arg @ref LL_DMA_STREAM_4
2910 * @arg @ref LL_DMA_STREAM_5
2911 * @arg @ref LL_DMA_STREAM_6
2912 * @arg @ref LL_DMA_STREAM_7
2913 * @retval None
2914 */
LL_DMA_EnableIT_FE(DMA_TypeDef * DMAx,uint32_t Stream)2915 __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2916 {
2917 uint32_t dma_base_addr = (uint32_t)DMAx;
2918
2919 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
2920 }
2921
2922 /**
2923 * @brief Disable Half transfer interrupt.
2924 * @rmtoll CR HTIE LL_DMA_DisableIT_HT
2925 * @param DMAx DMAx Instance
2926 * @param Stream This parameter can be one of the following values:
2927 * @arg @ref LL_DMA_STREAM_0
2928 * @arg @ref LL_DMA_STREAM_1
2929 * @arg @ref LL_DMA_STREAM_2
2930 * @arg @ref LL_DMA_STREAM_3
2931 * @arg @ref LL_DMA_STREAM_4
2932 * @arg @ref LL_DMA_STREAM_5
2933 * @arg @ref LL_DMA_STREAM_6
2934 * @arg @ref LL_DMA_STREAM_7
2935 * @retval None
2936 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Stream)2937 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2938 {
2939 uint32_t dma_base_addr = (uint32_t)DMAx;
2940
2941 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
2942 }
2943
2944 /**
2945 * @brief Disable Transfer error interrupt.
2946 * @rmtoll CR TEIE LL_DMA_DisableIT_TE
2947 * @param DMAx DMAx Instance
2948 * @param Stream This parameter can be one of the following values:
2949 * @arg @ref LL_DMA_STREAM_0
2950 * @arg @ref LL_DMA_STREAM_1
2951 * @arg @ref LL_DMA_STREAM_2
2952 * @arg @ref LL_DMA_STREAM_3
2953 * @arg @ref LL_DMA_STREAM_4
2954 * @arg @ref LL_DMA_STREAM_5
2955 * @arg @ref LL_DMA_STREAM_6
2956 * @arg @ref LL_DMA_STREAM_7
2957 * @retval None
2958 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Stream)2959 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2960 {
2961 uint32_t dma_base_addr = (uint32_t)DMAx;
2962
2963 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
2964 }
2965
2966 /**
2967 * @brief Disable Transfer complete interrupt.
2968 * @rmtoll CR TCIE LL_DMA_DisableIT_TC
2969 * @param DMAx DMAx Instance
2970 * @param Stream This parameter can be one of the following values:
2971 * @arg @ref LL_DMA_STREAM_0
2972 * @arg @ref LL_DMA_STREAM_1
2973 * @arg @ref LL_DMA_STREAM_2
2974 * @arg @ref LL_DMA_STREAM_3
2975 * @arg @ref LL_DMA_STREAM_4
2976 * @arg @ref LL_DMA_STREAM_5
2977 * @arg @ref LL_DMA_STREAM_6
2978 * @arg @ref LL_DMA_STREAM_7
2979 * @retval None
2980 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Stream)2981 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2982 {
2983 uint32_t dma_base_addr = (uint32_t)DMAx;
2984
2985 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
2986 }
2987
2988 /**
2989 * @brief Disable Direct mode error interrupt.
2990 * @rmtoll CR DMEIE LL_DMA_DisableIT_DME
2991 * @param DMAx DMAx Instance
2992 * @param Stream This parameter can be one of the following values:
2993 * @arg @ref LL_DMA_STREAM_0
2994 * @arg @ref LL_DMA_STREAM_1
2995 * @arg @ref LL_DMA_STREAM_2
2996 * @arg @ref LL_DMA_STREAM_3
2997 * @arg @ref LL_DMA_STREAM_4
2998 * @arg @ref LL_DMA_STREAM_5
2999 * @arg @ref LL_DMA_STREAM_6
3000 * @arg @ref LL_DMA_STREAM_7
3001 * @retval None
3002 */
LL_DMA_DisableIT_DME(DMA_TypeDef * DMAx,uint32_t Stream)3003 __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
3004 {
3005 uint32_t dma_base_addr = (uint32_t)DMAx;
3006
3007 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
3008 }
3009
3010 /**
3011 * @brief Disable FIFO error interrupt.
3012 * @rmtoll FCR FEIE LL_DMA_DisableIT_FE
3013 * @param DMAx DMAx Instance
3014 * @param Stream This parameter can be one of the following values:
3015 * @arg @ref LL_DMA_STREAM_0
3016 * @arg @ref LL_DMA_STREAM_1
3017 * @arg @ref LL_DMA_STREAM_2
3018 * @arg @ref LL_DMA_STREAM_3
3019 * @arg @ref LL_DMA_STREAM_4
3020 * @arg @ref LL_DMA_STREAM_5
3021 * @arg @ref LL_DMA_STREAM_6
3022 * @arg @ref LL_DMA_STREAM_7
3023 * @retval None
3024 */
LL_DMA_DisableIT_FE(DMA_TypeDef * DMAx,uint32_t Stream)3025 __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
3026 {
3027 uint32_t dma_base_addr = (uint32_t)DMAx;
3028
3029 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
3030 }
3031
3032 /**
3033 * @brief Check if Half transfer interrup is enabled.
3034 * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
3035 * @param DMAx DMAx Instance
3036 * @param Stream This parameter can be one of the following values:
3037 * @arg @ref LL_DMA_STREAM_0
3038 * @arg @ref LL_DMA_STREAM_1
3039 * @arg @ref LL_DMA_STREAM_2
3040 * @arg @ref LL_DMA_STREAM_3
3041 * @arg @ref LL_DMA_STREAM_4
3042 * @arg @ref LL_DMA_STREAM_5
3043 * @arg @ref LL_DMA_STREAM_6
3044 * @arg @ref LL_DMA_STREAM_7
3045 * @retval State of bit (1 or 0).
3046 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Stream)3047 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
3048 {
3049 uint32_t dma_base_addr = (uint32_t)DMAx;
3050
3051 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL);
3052 }
3053
3054 /**
3055 * @brief Check if Transfer error nterrup is enabled.
3056 * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
3057 * @param DMAx DMAx Instance
3058 * @param Stream This parameter can be one of the following values:
3059 * @arg @ref LL_DMA_STREAM_0
3060 * @arg @ref LL_DMA_STREAM_1
3061 * @arg @ref LL_DMA_STREAM_2
3062 * @arg @ref LL_DMA_STREAM_3
3063 * @arg @ref LL_DMA_STREAM_4
3064 * @arg @ref LL_DMA_STREAM_5
3065 * @arg @ref LL_DMA_STREAM_6
3066 * @arg @ref LL_DMA_STREAM_7
3067 * @retval State of bit (1 or 0).
3068 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Stream)3069 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
3070 {
3071 uint32_t dma_base_addr = (uint32_t)DMAx;
3072
3073 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL);
3074 }
3075
3076 /**
3077 * @brief Check if Transfer complete interrup is enabled.
3078 * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
3079 * @param DMAx DMAx Instance
3080 * @param Stream This parameter can be one of the following values:
3081 * @arg @ref LL_DMA_STREAM_0
3082 * @arg @ref LL_DMA_STREAM_1
3083 * @arg @ref LL_DMA_STREAM_2
3084 * @arg @ref LL_DMA_STREAM_3
3085 * @arg @ref LL_DMA_STREAM_4
3086 * @arg @ref LL_DMA_STREAM_5
3087 * @arg @ref LL_DMA_STREAM_6
3088 * @arg @ref LL_DMA_STREAM_7
3089 * @retval State of bit (1 or 0).
3090 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Stream)3091 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
3092 {
3093 uint32_t dma_base_addr = (uint32_t)DMAx;
3094
3095 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL);
3096 }
3097
3098 /**
3099 * @brief Check if Direct mode error interrupt is enabled.
3100 * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
3101 * @param DMAx DMAx Instance
3102 * @param Stream This parameter can be one of the following values:
3103 * @arg @ref LL_DMA_STREAM_0
3104 * @arg @ref LL_DMA_STREAM_1
3105 * @arg @ref LL_DMA_STREAM_2
3106 * @arg @ref LL_DMA_STREAM_3
3107 * @arg @ref LL_DMA_STREAM_4
3108 * @arg @ref LL_DMA_STREAM_5
3109 * @arg @ref LL_DMA_STREAM_6
3110 * @arg @ref LL_DMA_STREAM_7
3111 * @retval State of bit (1 or 0).
3112 */
LL_DMA_IsEnabledIT_DME(DMA_TypeDef * DMAx,uint32_t Stream)3113 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
3114 {
3115 uint32_t dma_base_addr = (uint32_t)DMAx;
3116
3117 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL);
3118 }
3119
3120 /**
3121 * @brief Check if FIFO error interrup is enabled.
3122 * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
3123 * @param DMAx DMAx Instance
3124 * @param Stream This parameter can be one of the following values:
3125 * @arg @ref LL_DMA_STREAM_0
3126 * @arg @ref LL_DMA_STREAM_1
3127 * @arg @ref LL_DMA_STREAM_2
3128 * @arg @ref LL_DMA_STREAM_3
3129 * @arg @ref LL_DMA_STREAM_4
3130 * @arg @ref LL_DMA_STREAM_5
3131 * @arg @ref LL_DMA_STREAM_6
3132 * @arg @ref LL_DMA_STREAM_7
3133 * @retval State of bit (1 or 0).
3134 */
LL_DMA_IsEnabledIT_FE(DMA_TypeDef * DMAx,uint32_t Stream)3135 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
3136 {
3137 uint32_t dma_base_addr = (uint32_t)DMAx;
3138
3139 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL);
3140 }
3141
3142 /**
3143 * @}
3144 */
3145
3146 #if defined(USE_FULL_LL_DRIVER)
3147 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
3148 * @{
3149 */
3150
3151 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
3152 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
3153 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
3154
3155 /**
3156 * @}
3157 */
3158 #endif /* USE_FULL_LL_DRIVER */
3159
3160 /**
3161 * @}
3162 */
3163
3164 /**
3165 * @}
3166 */
3167
3168 #endif /* DMA1 || DMA2 */
3169 /**
3170 * @}
3171 */
3172
3173 #ifdef __cplusplus
3174 }
3175 #endif
3176
3177 #endif /* __STM32MP1xx_LL_DMA_H */
3178
