1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32MP1xx_LL_ADC_H
21 #define STM32MP1xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32mp1xx.h"
29
30 /** @addtogroup STM32MP1xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC calibration: */
49 /* Internal register offset for ADC calibration factors configuration */
50
51 /* To select into literals LL_ADC_CALIB_OFFSET, LL_ADC_CALIB_LINEARITY, ... */
52 /* the relevant bits for: */
53 /* (concatenation of multiple bits used in different registers) */
54 /* - ADC calibration configuration: configuration before calibration start */
55 /* - ADC calibration factors: register offset */
56 #define ADC_CALIB_FACTOR_OFFSET_REGOFFSET (0x00000000UL) /* Register CALFACT defined as reference register */
57 #define ADC_CALIB_FACTOR_LINEARITY_REGOFFSET (0x00000001UL) /* Register CALFACT2 offset vs register CALFACT */
58 #define ADC_CALIB_FACTOR_REGOFFSET_MASK (ADC_CALIB_FACTOR_OFFSET_REGOFFSET | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)
59 #define ADC_CALIB_MODE_MASK (ADC_CR_ADCALLIN)
60 #define ADC_CALIB_MODE_BINARY_MASK (ADC_CALIB_FACTOR_REGOFFSET_MASK) /* Mask to get binary value of calibration mode: 0 for offset, 1 for linearity */
61
62
63 /* Internal mask for ADC group regular sequencer: */
64 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
65 /* - sequencer register offset */
66 /* - sequencer rank bits position into the selected register */
67
68 /* Internal register offset for ADC group regular sequencer configuration */
69 /* (offset placed into a spare area of literal definition) */
70 #define ADC_SQR1_REGOFFSET (0x00000000UL)
71 #define ADC_SQR2_REGOFFSET (0x00000100UL)
72 #define ADC_SQR3_REGOFFSET (0x00000200UL)
73 #define ADC_SQR4_REGOFFSET (0x00000300UL)
74
75 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
76 | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
77 #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
78 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
79
80 /* Definition of ADC group regular sequencer bits information to be inserted */
81 /* into ADC group regular sequencer ranks literals definition. */
82 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR1_SQ1" position in register */
83 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR1_SQ2" position in register */
84 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR1_SQ3" position in register */
85 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR1_SQ4" position in register */
86 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR2_SQ5" position in register */
87 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR2_SQ6" position in register */
88 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR2_SQ7" position in register */
89 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR2_SQ8" position in register */
90 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR2_SQ9" position in register */
91 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR3_SQ10" position in register */
92 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR3_SQ11" position in register */
93 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR3_SQ12" position in register */
94 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR3_SQ13" position in register */
95 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR3_SQ14" position in register */
96 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR4_SQ15" position in register */
97 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR4_SQ16" position in register */
98
99
100
101 /* Internal mask for ADC group injected sequencer: */
102 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
103 /* - data register offset */
104 /* - sequencer rank bits position into the selected register */
105
106 /* Internal register offset for ADC group injected data register */
107 /* (offset placed into a spare area of literal definition) */
108 #define ADC_JDR1_REGOFFSET (0x00000000UL)
109 #define ADC_JDR2_REGOFFSET (0x00000100UL)
110 #define ADC_JDR3_REGOFFSET (0x00000200UL)
111 #define ADC_JDR4_REGOFFSET (0x00000300UL)
112
113 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
114 | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
115 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
116 #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
117
118 /* Definition of ADC group injected sequencer bits information to be inserted */
119 /* into ADC group injected sequencer ranks literals definition. */
120 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
121 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
122 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
123 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
124
125
126
127 /* Internal mask for ADC group regular trigger: */
128 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
129 /* - regular trigger source */
130 /* - regular trigger edge */
131 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
132
133 /* Mask containing trigger source masks for each of possible */
134 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
135 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
136 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
137 ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \
138 ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
139 ((ADC_CFGR_EXTSEL) << (4U * 3UL)) )
140
141 /* Mask containing trigger edge masks for each of possible */
142 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
143 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
144 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
145 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
146 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
147 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
148
149 /* Definition of ADC group regular trigger bits information. */
150 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */
151 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR_EXTEN" position in register */
152
153
154
155 /* Internal mask for ADC group injected trigger: */
156 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
157 /* - injected trigger source */
158 /* - injected trigger edge */
159 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
160
161 /* Mask containing trigger source masks for each of possible */
162 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
163 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
164 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
165 ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
166 ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
167 ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
168
169 /* Mask containing trigger edge masks for each of possible */
170 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
171 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
172 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
173 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
174 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
175 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
176
177 /* Definition of ADC group injected trigger bits information. */
178 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */
179 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */
180
181
182
183
184
185
186 /* Internal mask for ADC channel: */
187 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
188 /* - channel identifier defined by number */
189 /* - channel identifier defined by bitfield */
190 /* - channel differentiation between external channels (connected to */
191 /* GPIO pins) and internal channels (connected to internal paths) */
192 /* - channel sampling time defined by SMPRx register offset */
193 /* and SMPx bits positions into SMPRx register */
194 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
195 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
196 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
197 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
198 | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
199 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
200 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
201
202 /* Channel differentiation between external and internal channels */
203 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
204 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
205
206 /* Internal register offset for ADC channel sampling time configuration */
207 /* (offset placed into a spare area of literal definition) */
208 #define ADC_SMPR1_REGOFFSET (0x00000000UL)
209 #define ADC_SMPR2_REGOFFSET (0x02000000UL)
210 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
211 #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
212
213 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
214 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
215
216 /* Definition of channels ID number information to be inserted into */
217 /* channels literals definition. */
218 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
219 #define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0)
220 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1)
221 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
222 #define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2)
223 #define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
224 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
225 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
226 #define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3)
227 #define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
228 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
229 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
230 #define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
231 #define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
232 #define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
233 #define ADC_CHANNEL_15_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \
234 ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
235 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4)
236 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
237 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
238 #define ADC_CHANNEL_19_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
239
240 /* Definition of channels ID bitfield information to be inserted into */
241 /* channels literals definition. */
242 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
243 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
244 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
245 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
246 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
247 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
248 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
249 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
250 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
251 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
252 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
253 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
254 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
255 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
256 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
257 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
258 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
259 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
260 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
261 #define ADC_CHANNEL_19_BITFIELD (ADC_AWD2CR_AWD2CH_19)
262
263 /* Definition of channels sampling time information to be inserted into */
264 /* channels literals definition. */
265 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
266 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
267 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
268 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
269 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
270 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
271 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
272 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
273 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
274 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
275 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
276 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
277 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
278 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
279 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
280 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
281 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
282 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
283 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
284 #define ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP19" position in register */
285
286
287 /* Internal mask for ADC mode single or differential ended: */
288 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
289 /* the relevant bits for: */
290 /* (concatenation of multiple bits used in different registers) */
291 /* - ADC calibration: calibration start, calibration factor get or set */
292 /* - ADC channels: set each ADC channel ending mode */
293 #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
294 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
295 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
296 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
297 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */
298 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */
299 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
300
301 /* Internal mask for ADC analog watchdog: */
302 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
303 /* (concatenation of multiple bits used in different analog watchdogs, */
304 /* (feature of several watchdogs not available on all STM32 families)). */
305 /* - analog watchdog 1: monitored channel defined by number, */
306 /* selection of ADC group (ADC groups regular and-or injected). */
307 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
308 /* selection on groups. */
309
310 /* Internal register offset for ADC analog watchdog channel configuration */
311 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
312 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
313 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
314
315 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
316 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
317 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
318 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
319
320 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
321
322 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
323 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
324 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
325
326 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
327
328 /* Internal register offset for ADC analog watchdog threshold configuration */
329 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
330 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
331 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
332 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
333 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_TRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
334
335 /* Register offset gap between AWD1 and AWD2-AWD3 thresholds registers */
336 /* (Set separately as ADC_AWD_TRX_REGOFFSET to spare 32 bits space */
337 #define ADC_AWD_TR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
338 #define ADC_AWD_TR12_REGOFFSETGAP_VAL (0x00000022UL)
339
340 /* Internal mask for ADC offset: */
341 /* Internal register offset for ADC offset number configuration */
342 #define ADC_OFR1_REGOFFSET (0x00000000UL)
343 #define ADC_OFR2_REGOFFSET (0x00000001UL)
344 #define ADC_OFR3_REGOFFSET (0x00000002UL)
345 #define ADC_OFR4_REGOFFSET (0x00000003UL)
346 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
347 | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
348
349
350 /* ADC registers bits positions */
351 #define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)
352 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
353 #define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
354 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
355
356
357 /* ADC registers bits groups */
358 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
359
360
361 /* ADC internal channels related definitions */
362 /* Internal voltage reference VrefInt */
363 #define VREFINT_CAL_ADDR ((uint16_t*) (0x5C005252UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
364 #define VREFINT_CAL_VREF ( 3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
365 /* Temperature sensor */
366 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x5C00525CUL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32MP1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
367 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x5C00525EUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32MP1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
368 #define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
369 #define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
370 #define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
371
372
373 #define ADC_LINEAR_CALIB_REG_COUNT (6UL)
374 /**
375 * @}
376 */
377
378
379 /* Private macros ------------------------------------------------------------*/
380 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
381 * @{
382 */
383
384 /**
385 * @brief Driver macro reserved for internal use: set a pointer to
386 * a register from a register basis from which an offset
387 * is applied.
388 * @param __REG__ Register basis from which the offset is applied.
389 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
390 * @retval Pointer to register address
391 */
392 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
393 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
394
395 /**
396 * @}
397 */
398
399
400 /* Exported types ------------------------------------------------------------*/
401 #if defined(USE_FULL_LL_DRIVER)
402 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
403 * @{
404 */
405
406 /**
407 * @brief Structure definition of some features of ADC common parameters
408 * and multimode
409 * (all ADC instances belonging to the same ADC common instance).
410 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
411 * is conditioned to ADC instances state (all ADC instances
412 * sharing the same ADC common instance):
413 * All ADC instances sharing the same ADC common instance must be
414 * disabled.
415 */
416 typedef struct
417 {
418 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
419 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
420 @note On this STM32 series, if ADC group injected is used, some
421 clock ratio constraints between ADC clock and AHB clock
422 must be respected. Refer to reference manual.
423
424 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
425
426 #if defined(ADC_MULTIMODE_SUPPORT)
427 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
428 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
429
430 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
431
432 uint32_t MultiDMATransfer; /*!< Set ADC dual ADC mode DMA transfer data format: Each DMA, 32 down to 10-bits or 8-bits resolution.
433 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
434
435 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
436
437 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
438 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
439
440 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
441 #endif /* ADC_MULTIMODE_SUPPORT */
442
443 } LL_ADC_CommonInitTypeDef;
444
445 /**
446 * @brief Structure definition of some features of ADC instance.
447 * @note These parameters have an impact on ADC scope: ADC instance.
448 * Affects both group regular and group injected (availability
449 * of ADC group injected depends on STM32 families).
450 * Refer to corresponding unitary functions into
451 * @ref ADC_LL_EF_Configuration_ADC_Instance .
452 * @note The setting of these parameters by function @ref LL_ADC_Init()
453 * is conditioned to ADC state:
454 * ADC instance must be disabled.
455 * This condition is applied to all ADC features, for efficiency
456 * and compatibility over all STM32 families. However, the different
457 * features can be set under different ADC state conditions
458 * (setting possible with ADC enabled without conversion on going,
459 * ADC enabled with conversion on going, ...)
460 * Each feature can be updated afterwards with a unitary function
461 * and potentially with ADC in a different state than disabled,
462 * refer to description of each function for setting
463 * conditioned to ADC state.
464 */
465 typedef struct
466 {
467 uint32_t Resolution; /*!< Set ADC resolution.
468 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
469
470 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
471
472 uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.
473 This parameter can be a value of @ref ADC_LL_EC_LEFT_BIT_SHIFT. */
474
475 uint32_t LowPowerMode; /*!< Set ADC low power mode.
476 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
477
478 This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
479
480 } LL_ADC_InitTypeDef;
481
482 /**
483 * @brief Structure definition of some features of ADC group regular.
484 * @note These parameters have an impact on ADC scope: ADC group regular.
485 * Refer to corresponding unitary functions into
486 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
487 * (functions with prefix "REG").
488 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
489 * is conditioned to ADC state:
490 * ADC instance must be disabled.
491 * This condition is applied to all ADC features, for efficiency
492 * and compatibility over all STM32 families. However, the different
493 * features can be set under different ADC state conditions
494 * (setting possible with ADC enabled without conversion on going,
495 * ADC enabled with conversion on going, ...)
496 * Each feature can be updated afterwards with a unitary function
497 * and potentially with ADC in a different state than disabled,
498 * refer to description of each function for setting
499 * conditioned to ADC state.
500 */
501 typedef struct
502 {
503 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
504 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
505 @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
506 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
507 In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
508
509 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
510
511 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
512 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
513
514 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
515
516 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
517 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
518 @note This parameter has an effect only if group regular sequencer is enabled
519 (scan length of 2 ranks or more).
520
521 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
522
523 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
524 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
525 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
526
527 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
528
529 uint32_t DataTransferMode; /*!< Set ADC group regular conversion data transfer mode: no transfer, transfer by DMA (Limited/Unlimited) or DFSDM.
530 This parameter can be a value of @ref ADC_LL_EC_REG_DATA_TRANSFER_MODE
531
532 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDataTransferMode(). */
533
534 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
535 data preserved or overwritten.
536 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
537
538 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
539
540 } LL_ADC_REG_InitTypeDef;
541
542 /**
543 * @brief Structure definition of some features of ADC group injected.
544 * @note These parameters have an impact on ADC scope: ADC group injected.
545 * Refer to corresponding unitary functions into
546 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
547 * (functions with prefix "INJ").
548 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
549 * is conditioned to ADC state:
550 * ADC instance must be disabled.
551 * This condition is applied to all ADC features, for efficiency
552 * and compatibility over all STM32 families. However, the different
553 * features can be set under different ADC state conditions
554 * (setting possible with ADC enabled without conversion on going,
555 * ADC enabled with conversion on going, ...)
556 * Each feature can be updated afterwards with a unitary function
557 * and potentially with ADC in a different state than disabled,
558 * refer to description of each function for setting
559 * conditioned to ADC state.
560 */
561 typedef struct
562 {
563 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
564 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
565 @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
566 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
567 In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
568
569 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
570
571 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
572 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
573
574 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
575
576 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
577 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
578 @note This parameter has an effect only if group injected sequencer is enabled
579 (scan length of 2 ranks or more).
580
581 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
582
583 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
584 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
585 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
586
587 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
588
589 } LL_ADC_INJ_InitTypeDef;
590
591 /**
592 * @}
593 */
594 #endif /* USE_FULL_LL_DRIVER */
595
596 /* Exported constants --------------------------------------------------------*/
597 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
598 * @{
599 */
600
601 /** @defgroup ADC_LL_EC_FLAG ADC flags
602 * @brief Flags defines which can be used with LL_ADC_ReadReg function
603 * @{
604 */
605 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
606 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
607 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
608 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
609 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
610 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
611 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
612 #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */
613 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
614 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
615 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
616 #if defined(ADC_MULTIMODE_SUPPORT)
617 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
618 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
619 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */
620 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
621 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */
622 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
623 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
624 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
625 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */
626 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */
627 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */
628 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
629 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */
630 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
631 #define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */
632 #define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
633 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
634 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
635 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
636 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
637 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
638 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
639 #endif /* ADC_MULTIMODE_SUPPORT */
640 /**
641 * @}
642 */
643
644 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
645 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
646 * @{
647 */
648 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
649 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
650 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
651 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
652 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
653 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */
654 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */
655 #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */
656 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
657 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
658 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
659 /**
660 * @}
661 */
662
663 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
664 * @{
665 */
666 /* List of ADC registers intended to be used (most commonly) with */
667 /* DMA transfer. */
668 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
669 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
670 #if defined(ADC_MULTIMODE_SUPPORT)
671 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
672 #endif /* ADC_MULTIMODE_SUPPORT */
673 /**
674 * @}
675 */
676
677 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
678 * @{
679 */
680 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
681 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
682 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
683 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */
684 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */
685 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */
686 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */
687 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8 */
688 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10 */
689 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12 */
690 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16 */
691 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 */
692 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64 */
693 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128 */
694 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */
695 /**
696 * @}
697 */
698
699 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
700 * @{
701 */
702 /* Note: Other measurement paths to internal channels may be available */
703 /* (connections to other peripherals). */
704 /* If they are not listed below, they do not require any specific */
705 /* path enable. In this case, Access to measurement path is done */
706 /* only by selecting the corresponding ADC internal channel. */
707 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
708 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
709 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSEEN) /*!< ADC measurement path to internal channel temperature sensor */
710 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
711 #define LL_ADC_PATH_INTERNAL_VDDCORE (ADC2_OR_VDDCOREEN) /*!< ADC measurement path to internal channel Vddcore */
712 /**
713 * @}
714 */
715
716 /** @defgroup ADC_LL_EC_BOOST_MODE ADC instance - Boost mode
717 * @{
718 */
719 #define LL_ADC_BOOST_MODE_DISABLE (0x00000000UL) /*!< ADC boost mode disable: can be used when ADC clock < 20 MHz to save power at lower clock frequency */
720 #define LL_ADC_BOOST_MODE_ENABLE (ADC_CR_BOOST) /*!< ADC boost mode enable: must be used when ADC clock > 20 MHz. Note: In multimode, boost setting of ADC slave is discarded are applies setting of ADC master. */
721 /**
722 * @}
723 */
724
725 /** @defgroup ADC_LL_EC_CALIBRATION_OFFSET_LINEARITY ADC instance - Calibration mode for offset and linearity
726 * @{
727 */
728 #define LL_ADC_CALIB_OFFSET (ADC_CALIB_FACTOR_OFFSET_REGOFFSET) /*!< Calibration of ADC offset. Duration of calibration of offset duration: 1280 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes. */
729 #define LL_ADC_CALIB_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET) /*!< Calibration of ADC linearity. Duration of calibration of linearity: 15104 ADC clock cycles. For devices with differential mode available: Calibration of linearity is common to both single-ended and differential modes. */
730 #define LL_ADC_CALIB_OFFSET_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET | ADC_CR_ADCALLIN) /*!< Calibration of ADC offset and linearity. Duration of calibration of offset and linearity: 16384 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes, calibration of linearity is common to both single-ended and differential modes. */
731 /**
732 * @}
733 */
734
735 /** @defgroup ADC_LL_EC_CALIBRATION_LINEARITY_WORD ADC instance - Calibration linearity words
736 * @{
737 */
738 #define LL_ADC_CALIB_LINEARITY_WORD1 (ADC_CR_LINCALRDYW1) /*!< ADC calibration linearity word 1 */
739 #define LL_ADC_CALIB_LINEARITY_WORD2 (ADC_CR_LINCALRDYW2) /*!< ADC calibration linearity word 2 */
740 #define LL_ADC_CALIB_LINEARITY_WORD3 (ADC_CR_LINCALRDYW3) /*!< ADC calibration linearity word 3 */
741 #define LL_ADC_CALIB_LINEARITY_WORD4 (ADC_CR_LINCALRDYW4) /*!< ADC calibration linearity word 4 */
742 #define LL_ADC_CALIB_LINEARITY_WORD5 (ADC_CR_LINCALRDYW5) /*!< ADC calibration linearity word 5 */
743 #define LL_ADC_CALIB_LINEARITY_WORD6 (ADC_CR_LINCALRDYW6) /*!< ADC calibration linearity word 6 */
744 /**
745 * @}
746 */
747
748 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
749 * @{
750 */
751 #define LL_ADC_RESOLUTION_16B (0x00000000UL) /*!< ADC resolution 16 bits */
752 #define LL_ADC_RESOLUTION_14B ( ADC_CFGR_RES_0) /*!< ADC resolution 12 bits */
753 #define LL_ADC_RESOLUTION_12B ( ADC_CFGR_RES_1 ) /*!< ADC resolution 12 bits */
754 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
755 #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2 ) /*!< ADC resolution 8 bits */
756 /**
757 * @}
758 */
759
760 /** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT ADC left Shift
761 * @{
762 */
763 #define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL) /*!< ADC no bit shift left applied on the final ADC convesion data */
764 #define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0) /*!< ADC 1 bit shift left applied on the final ADC convesion data */
765 #define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1) /*!< ADC 2 bits shift left applied on the final ADC convesion data */
766 #define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 3 bits shift left applied on the final ADC convesion data */
767 #define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2) /*!< ADC 4 bits shift left applied on the final ADC convesion data */
768 #define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 5 bits shift left applied on the final ADC convesion data */
769 #define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 6 bits shift left applied on the final ADC convesion data */
770 #define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 7 bits shift left applied on the final ADC convesion data */
771 #define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3) /*!< ADC 8 bits shift left applied on the final ADC convesion data */
772 #define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0) /*!< ADC 9 bits shift left applied on the final ADC convesion data */
773 #define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1) /*!< ADC 10 bits shift left applied on the final ADC convesion data */
774 #define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 11 bits shift left applied on the final ADC convesion data */
775 #define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2) /*!< ADC 12 bits shift left applied on the final ADC convesion data */
776 #define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 13 bits shift left applied on the final ADC convesion data */
777 #define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 14 bits shift left applied on the final ADC convesion data */
778 #define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 15 bits shift left applied on the final ADC convesion data */
779 /**
780 * @}
781 */
782
783 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
784 * @{
785 */
786 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
787 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
788 /**
789 * @}
790 */
791
792 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
793 * @{
794 */
795 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
796 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
797 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
798 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
799 /**
800 * @}
801 */
802
803 /** @defgroup ADC_LL_EC_OFFSET_SIGNED_SATURATION ADC instance - Offset signed saturation mode
804 * @{
805 */
806 #define LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset signed saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */
807 #define LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE (ADC_OFR1_SSATE) /*!< ADC offset signed saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */
808 /**
809 * @}
810 */
811
812 /** @defgroup ADC_LL_EC_OFFSET_RSHIFT ADC instance - Offset right shift
813 * @{
814 */
815 #define LL_ADC_OFFSET_RSHIFT_DISABLE (0x00000000UL) /*!< ADC offset right shift is disabled (among ADC selected offset number 1, 2, 3 or 4) */
816 #define LL_ADC_OFFSET_RSHIFT_ENABLE (ADC_CFGR2_RSHIFT1) /*!< ADC offset right shif is enabled (among ADC selected offset number 1, 2, 3 or 4) */
817 /**
818 * @}
819 */
820 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
821 * @{
822 */
823 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
824 #define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
825 #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
826 /**
827 * @}
828 */
829
830 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
831 * @{
832 */
833 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
834 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
835 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
836 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
837 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
838 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
839 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
840 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
841 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
842 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
843 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
844 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
845 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
846 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
847 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
848 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
849 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
850 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
851 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
852 #define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */
853 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32MP1, ADC channel available only on ADC instance: ADC2. */
854 #define LL_ADC_CHANNEL_VCORE (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VddCore. On STM32MP1, ADC channel available only on ADC instance: ADC2. */
855 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32MP1, ADC channel available only on ADC instance: ADC2. */
856 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32MP1, ADC channel available only on ADC instance: ADC2. */
857 #define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
858 #define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
859 /**
860 * @}
861 */
862
863 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
864 * @{
865 */
866 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */
867 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
868 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
869 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
870 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
871 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
872 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
873 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */
874 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
875 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
876 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
877 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
878 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
879 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
880 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
881 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
882 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
883 #define LL_ADC_REG_TRIG_EXT_LPTIM1_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
884 #define LL_ADC_REG_TRIG_EXT_LPTIM2_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1| ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
885 #define LL_ADC_REG_TRIG_EXT_LPTIM3_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */
886 /**
887 * @}
888 */
889
890 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
891 * @{
892 */
893 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
894 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
895 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
896 /**
897 * @}
898 */
899
900 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
901 * @{
902 */
903 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */
904 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
905 /**
906 * @}
907 */
908
909 /** @defgroup ADC_LL_EC_REG_DATA_TRANSFER_MODE ADC group regular - Data transfer mode of ADC conversion data
910 * @{
911 */
912 #define LL_ADC_REG_DR_TRANSFER (0x00000000UL) /*!< ADC conversions are transferred to DR rigister */
913 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
914 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMNGT_1 | ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
915 #define LL_ADC_REG_DFSDM_TRANSFER (ADC_CFGR_DMNGT_1 ) /*!< ADC conversion data are transferred to DFSDM */
916 /**
917 * @}
918 */
919
920 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
921 * @{
922 */
923 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */
924 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
925 /**
926 * @}
927 */
928
929 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
930 * @{
931 */
932 #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
933 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
934 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
935 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
936 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
937 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
938 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
939 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
940 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
941 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
942 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
943 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
944 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
945 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
946 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
947 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
948 /**
949 * @}
950 */
951
952 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
953 * @{
954 */
955 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
956 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
957 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
958 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
959 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
960 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
961 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
962 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
963 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
964 /**
965 * @}
966 */
967
968 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
969 * @{
970 */
971 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
972 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
973 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
974 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
975 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
976 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
977 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
978 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
979 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
980 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
981 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
982 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
983 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
984 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
985 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
986 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
987 /**
988 * @}
989 */
990
991 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
992 * @{
993 */
994 #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start. */
995 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
996 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
997 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
998 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
999 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1000 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
1001 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
1002 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1003 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
1004 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
1005 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
1006 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1007 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
1008 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1009 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
1010 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
1011 #define LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
1012 #define LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
1013 #define LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1014 /**
1015 * @}
1016 */
1017
1018 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
1019 * @{
1020 */
1021 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
1022 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
1023 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
1024 /**
1025 * @}
1026 */
1027
1028 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
1029 * @{
1030 */
1031 #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
1032 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
1033 /**
1034 * @}
1035 */
1036
1037 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
1038 * @{
1039 */
1040 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
1041 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
1042 #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
1043 /**
1044 * @}
1045 */
1046
1047 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
1048 * @{
1049 */
1050 #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1051 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
1052 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
1053 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
1054 /**
1055 * @}
1056 */
1057
1058 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
1059 * @{
1060 */
1061 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */
1062 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
1063 /**
1064 * @}
1065 */
1066
1067 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
1068 * @{
1069 */
1070 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
1071 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
1072 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
1073 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
1074 /**
1075 * @}
1076 */
1077
1078 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1079 * @{
1080 */
1081 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycles */
1082 #define LL_ADC_SAMPLINGTIME_2CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */
1083 #define LL_ADC_SAMPLINGTIME_8CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 8.5 ADC clock cycles */
1084 #define LL_ADC_SAMPLINGTIME_16CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 16.5 ADC clock cycles */
1085 #define LL_ADC_SAMPLINGTIME_32CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 32.5 ADC clock cycles */
1086 #define LL_ADC_SAMPLINGTIME_64CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 64.5 ADC clock cycles */
1087 #define LL_ADC_SAMPLINGTIME_387CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 387.5 ADC clock cycles */
1088 #define LL_ADC_SAMPLINGTIME_810CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 810.5 ADC clock cycles */
1089 /**
1090 * @}
1091 */
1092
1093 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
1094 * @{
1095 */
1096 #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
1097 #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
1098 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
1099 /**
1100 * @}
1101 */
1102
1103 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1104 * @{
1105 */
1106 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1107 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
1108 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
1109 /**
1110 * @}
1111 */
1112
1113 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1114 * @{
1115 */
1116 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
1117 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
1118 #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
1119 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
1120 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
1121 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
1122 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
1123 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
1124 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
1125 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
1126 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
1127 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
1128 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
1129 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
1130 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
1131 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
1132 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
1133 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
1134 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
1135 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
1136 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
1137 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
1138 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
1139 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
1140 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
1141 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
1142 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
1143 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
1144 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
1145 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
1146 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
1147 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
1148 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
1149 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
1150 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
1151 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
1152 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
1153 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
1154 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
1155 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
1156 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
1157 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
1158 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
1159 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
1160 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
1161 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
1162 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
1163 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
1164 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
1165 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
1166 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
1167 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
1168 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
1169 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
1170 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
1171 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
1172 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
1173 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
1174 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
1175 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
1176 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
1177 #define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
1178 #define LL_ADC_AWD_CHANNEL_19_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
1179 #define LL_ADC_AWD_CHANNEL_19_REG_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
1180 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
1181 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
1182 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
1183 #define LL_ADC_AWD_CH_VCORE_REG ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VddCore, converted by group regular only */
1184 #define LL_ADC_AWD_CH_VCORE_INJ ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VddCore, converted by group injected only */
1185 #define LL_ADC_AWD_CH_VCORE_REG_INJ ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VddCore, converted by either group regular or injected */
1186 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
1187 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
1188 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
1189 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group regular only */
1190 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group injected only */
1191 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda */
1192 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
1193 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
1194 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
1195 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
1196 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
1197 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
1198 /**
1199 * @}
1200 */
1201
1202 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1203 * @{
1204 */
1205 #define LL_ADC_AWD_THRESHOLD_HIGH (0x1UL) /*!< ADC analog watchdog threshold high */
1206 #define LL_ADC_AWD_THRESHOLD_LOW (0x0UL) /*!< ADC analog watchdog threshold low */
1207 /**
1208 * @}
1209 */
1210
1211 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1212 * @{
1213 */
1214 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1215 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
1216 #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1217 #define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */
1218 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1219 /**
1220 * @}
1221 */
1222
1223 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1224 * @{
1225 */
1226 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
1227 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
1228 /**
1229 * @}
1230 */
1231
1232 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
1233 * @{
1234 */
1235 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
1236 #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
1237 #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
1238 #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
1239 #define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
1240 #define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
1241 #define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
1242 #define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
1243 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
1244 #define LL_ADC_OVS_SHIFT_RIGHT_9 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */
1245 #define LL_ADC_OVS_SHIFT_RIGHT_10 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */
1246 #define LL_ADC_OVS_SHIFT_RIGHT_11 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */
1247 /**
1248 * @}
1249 */
1250
1251 #if defined(ADC_MULTIMODE_SUPPORT)
1252 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
1253 * @{
1254 */
1255 #define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */
1256 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
1257 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
1258 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
1259 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
1260 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
1261 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
1262 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
1263 /**
1264 * @}
1265 */
1266
1267 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
1268 * @{
1269 */
1270 #define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
1271 #define LL_ADC_MULTI_REG_DMA_RES_32_10B (ADC_CCR_DAMDF_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 32 (16x2) down to 10 bits */
1272 #define LL_ADC_MULTI_REG_DMA_RES_8B (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 8 bits */
1273 /**
1274 * @}
1275 */
1276
1277 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1278 * @{
1279 */
1280 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5 (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1.5 ADC clock cycle for all resolution */
1281 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5 ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2.5 ADC clock cycles for all resolution */
1282 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5 ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3.5 ADC clock cycles for all resolution */
1283 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 16, 14, 12 or 10 bits resolution */
1284 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 8 bits resolution */
1285 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 16, 14, 12 bits resolution */
1286 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 10 bits resolution */
1287 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 16 or 14 bits resolution */
1288 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 12 bits resolution */
1289 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7.5 ADC clock cycles for 16 bits resolution */
1290 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5_14_BITS ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 7.5 ADC clock cycles for 14 bits resolution */
1291 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES_5 (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 8.5 ADC clock cycles for 16 bits resolution */
1292 /**
1293 * @}
1294 */
1295
1296 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1297 * @{
1298 */
1299 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1300 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1301 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1302 /**
1303 * @}
1304 */
1305
1306 #endif /* ADC_MULTIMODE_SUPPORT */
1307
1308
1309 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1310 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
1311 * not timeout values.
1312 * For details on delays values, refer to descriptions in source code
1313 * above each literal definition.
1314 * @{
1315 */
1316
1317 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
1318 /* not timeout values. */
1319 /* Timeout values for ADC operations are dependent to device clock */
1320 /* configuration (system clock versus ADC clock), */
1321 /* and therefore must be defined in user application. */
1322 /* Indications for estimation of ADC timeout delays, for this */
1323 /* STM32 series: */
1324 /* - ADC calibration time: maximum delay is 16384/fADC. */
1325 /* (refer to device datasheet, parameter "tCAL") */
1326 /* - ADC enable time: maximum delay is 1 conversion cycle. */
1327 /* (refer to device datasheet, parameter "tSTAB") */
1328 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
1329 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
1330 /* cycles */
1331 /* - ADC conversion time: duration depending on ADC clock and ADC */
1332 /* configuration. */
1333 /* (refer to device reference manual, section "Timing") */
1334
1335 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1336 /* Delay set to maximum value (refer to device datasheet, */
1337 /* parameter "tADCVREG_STUP"). */
1338 /* Unit: us */
1339 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1340
1341 /* Delay for internal voltage reference stabilization time. */
1342 /* Delay set to maximum value (refer to device datasheet, */
1343 /* parameter "ts_vrefint"). */
1344 /* Unit: us */
1345 #define LL_ADC_DELAY_VREFINT_STAB_US (5UL) /*!< Delay for internal voltage reference stabilization time */
1346
1347 /* Delay for temperature sensor stabilization time. */
1348 /* Literal set to maximum value (refer to device datasheet, */
1349 /* parameter "tSTART_RUN"). */
1350 /* Unit: us */
1351 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL) /*!< Delay for temperature sensor stabilization time */
1352
1353 /* Delay required between ADC end of calibration and ADC enable. */
1354 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
1355 /* are required between ADC end of calibration and ADC enable. */
1356 /* Wait time can be computed in user application by waiting for the */
1357 /* equivalent number of CPU cycles, by taking into account */
1358 /* ratio of CPU clock versus ADC clock prescalers. */
1359 /* Unit: ADC clock cycles. */
1360 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
1361
1362 /* Fixed timeout value for ADC linearity word bit set/clear delay. */
1363 /* Values defined to be higher than worst cases: low clock frequency, */
1364 /* maximum prescalers. */
1365 /* Example of profile low frequency (minimum value */
1366 /* according to Data sheet): ADC frequency at 15.625kHz (ADC clock */
1367 /* source PLL4_Q 4MHz, ADC clock prescaler 256), */
1368 /* linearity set/clear bit delay MAX = 6 / f_ADC + 3 cycles AHB */
1369 /* 6 / 15625 = 0,384ms */
1370 /* At CPU speed example of 650 MHz, this means */
1371 /* 3.58 * 650 MHz = 524400 CPU cycles */
1372 #define ADC_LINEARITY_BIT_TOGGLE_TIMEOUT (524400UL) /*!< ADC linearity set/clear bit delay */
1373
1374 /**
1375 * @}
1376 */
1377
1378 /**
1379 * @}
1380 */
1381
1382
1383 /* Exported macro ------------------------------------------------------------*/
1384 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1385 * @{
1386 */
1387
1388 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1389 * @{
1390 */
1391
1392 /**
1393 * @brief Write a value in ADC register
1394 * @param __INSTANCE__ ADC Instance
1395 * @param __REG__ Register to be written
1396 * @param __VALUE__ Value to be written in the register
1397 * @retval None
1398 */
1399 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1400
1401 /**
1402 * @brief Read a value in ADC register
1403 * @param __INSTANCE__ ADC Instance
1404 * @param __REG__ Register to be read
1405 * @retval Register value
1406 */
1407 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1408 /**
1409 * @}
1410 */
1411
1412 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1413 * @{
1414 */
1415
1416 /**
1417 * @brief Helper macro to get ADC channel number in decimal format
1418 * from literals LL_ADC_CHANNEL_x.
1419 * @note Example:
1420 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1421 * will return decimal number "4".
1422 * @note The input can be a value from functions where a channel
1423 * number is returned, either defined with number
1424 * or with bitfield (only one bit must be set).
1425 * @param __CHANNEL__ This parameter can be one of the following values:
1426 * @arg @ref LL_ADC_CHANNEL_0 (3)
1427 * @arg @ref LL_ADC_CHANNEL_1 (3)
1428 * @arg @ref LL_ADC_CHANNEL_2 (3)
1429 * @arg @ref LL_ADC_CHANNEL_3 (3)
1430 * @arg @ref LL_ADC_CHANNEL_4 (3)
1431 * @arg @ref LL_ADC_CHANNEL_5 (3)
1432 * @arg @ref LL_ADC_CHANNEL_6
1433 * @arg @ref LL_ADC_CHANNEL_7
1434 * @arg @ref LL_ADC_CHANNEL_8
1435 * @arg @ref LL_ADC_CHANNEL_9
1436 * @arg @ref LL_ADC_CHANNEL_10
1437 * @arg @ref LL_ADC_CHANNEL_11
1438 * @arg @ref LL_ADC_CHANNEL_12
1439 * @arg @ref LL_ADC_CHANNEL_13
1440 * @arg @ref LL_ADC_CHANNEL_14
1441 * @arg @ref LL_ADC_CHANNEL_15
1442 * @arg @ref LL_ADC_CHANNEL_16
1443 * @arg @ref LL_ADC_CHANNEL_17
1444 * @arg @ref LL_ADC_CHANNEL_18
1445 * @arg @ref LL_ADC_CHANNEL_19
1446 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1447 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
1448 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1449 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1450 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
1451 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
1452 *
1453 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
1454 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
1455 * Other channels are slow channels (conversion rate: refer to reference manual).
1456 * @retval Value between Min_Data=0 and Max_Data=18
1457 */
1458 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1459 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
1460 ( \
1461 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1462 ) \
1463 : \
1464 ( \
1465 (uint32_t)POSITION_VAL((__CHANNEL__)) \
1466 ) \
1467 )
1468
1469 /**
1470 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1471 * from number in decimal format.
1472 * @note Example:
1473 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1474 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1475 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1476 * @retval Returned value can be one of the following values:
1477 * @arg @ref LL_ADC_CHANNEL_0 (3)
1478 * @arg @ref LL_ADC_CHANNEL_1 (3)
1479 * @arg @ref LL_ADC_CHANNEL_2 (3)
1480 * @arg @ref LL_ADC_CHANNEL_3 (3)
1481 * @arg @ref LL_ADC_CHANNEL_4 (3)
1482 * @arg @ref LL_ADC_CHANNEL_5 (3)
1483 * @arg @ref LL_ADC_CHANNEL_6
1484 * @arg @ref LL_ADC_CHANNEL_7
1485 * @arg @ref LL_ADC_CHANNEL_8
1486 * @arg @ref LL_ADC_CHANNEL_9
1487 * @arg @ref LL_ADC_CHANNEL_10
1488 * @arg @ref LL_ADC_CHANNEL_11
1489 * @arg @ref LL_ADC_CHANNEL_12
1490 * @arg @ref LL_ADC_CHANNEL_13
1491 * @arg @ref LL_ADC_CHANNEL_14
1492 * @arg @ref LL_ADC_CHANNEL_15
1493 * @arg @ref LL_ADC_CHANNEL_16
1494 * @arg @ref LL_ADC_CHANNEL_17
1495 * @arg @ref LL_ADC_CHANNEL_18
1496 * @arg @ref LL_ADC_CHANNEL_19
1497 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1498 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
1499 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1500 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1501 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
1502 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
1503 *
1504 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
1505 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
1506 * Other channels are slow channels (conversion rate: refer to reference manual).\n
1507 * (1) For ADC channel read back from ADC register,
1508 * comparison with internal channel parameter to be done
1509 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1510 */
1511 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1512 (((__DECIMAL_NB__) <= 9UL) ? \
1513 ( \
1514 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1515 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1516 (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1517 ) \
1518 : \
1519 ( \
1520 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1521 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1522 (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1523 ) \
1524 )
1525
1526 /**
1527 * @brief Helper macro to determine whether the selected channel
1528 * corresponds to literal definitions of driver.
1529 * @note The different literal definitions of ADC channels are:
1530 * - ADC internal channel:
1531 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1532 * - ADC external channel (channel connected to a GPIO pin):
1533 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1534 * @note The channel parameter must be a value defined from literal
1535 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1536 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1537 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1538 * must not be a value from functions where a channel number is
1539 * returned from ADC registers,
1540 * because internal and external channels share the same channel
1541 * number in ADC registers. The differentiation is made only with
1542 * parameters definitions of driver.
1543 * @param __CHANNEL__ This parameter can be one of the following values:
1544 * @arg @ref LL_ADC_CHANNEL_0 (3)
1545 * @arg @ref LL_ADC_CHANNEL_1 (3)
1546 * @arg @ref LL_ADC_CHANNEL_2 (3)
1547 * @arg @ref LL_ADC_CHANNEL_3 (3)
1548 * @arg @ref LL_ADC_CHANNEL_4 (3)
1549 * @arg @ref LL_ADC_CHANNEL_5 (3)
1550 * @arg @ref LL_ADC_CHANNEL_6
1551 * @arg @ref LL_ADC_CHANNEL_7
1552 * @arg @ref LL_ADC_CHANNEL_8
1553 * @arg @ref LL_ADC_CHANNEL_9
1554 * @arg @ref LL_ADC_CHANNEL_10
1555 * @arg @ref LL_ADC_CHANNEL_11
1556 * @arg @ref LL_ADC_CHANNEL_12
1557 * @arg @ref LL_ADC_CHANNEL_13
1558 * @arg @ref LL_ADC_CHANNEL_14
1559 * @arg @ref LL_ADC_CHANNEL_15
1560 * @arg @ref LL_ADC_CHANNEL_16
1561 * @arg @ref LL_ADC_CHANNEL_17
1562 * @arg @ref LL_ADC_CHANNEL_18
1563 * @arg @ref LL_ADC_CHANNEL_19
1564 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1565 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
1566 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1567 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1568 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
1569 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
1570 *
1571 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
1572 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
1573 * Other channels are slow channels (conversion rate: refer to reference manual).
1574 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1575 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1576 */
1577 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1578 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1579
1580 /**
1581 * @brief Helper macro to convert a channel defined from parameter
1582 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1583 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1584 * to its equivalent parameter definition of a ADC external channel
1585 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1586 * @note The channel parameter can be, additionally to a value
1587 * defined from parameter definition of a ADC internal channel
1588 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1589 * a value defined from parameter definition of
1590 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1591 * or a value from functions where a channel number is returned
1592 * from ADC registers.
1593 * @param __CHANNEL__ This parameter can be one of the following values:
1594 * @arg @ref LL_ADC_CHANNEL_0 (3)
1595 * @arg @ref LL_ADC_CHANNEL_1 (3)
1596 * @arg @ref LL_ADC_CHANNEL_2 (3)
1597 * @arg @ref LL_ADC_CHANNEL_3 (3)
1598 * @arg @ref LL_ADC_CHANNEL_4 (3)
1599 * @arg @ref LL_ADC_CHANNEL_5 (3)
1600 * @arg @ref LL_ADC_CHANNEL_6
1601 * @arg @ref LL_ADC_CHANNEL_7
1602 * @arg @ref LL_ADC_CHANNEL_8
1603 * @arg @ref LL_ADC_CHANNEL_9
1604 * @arg @ref LL_ADC_CHANNEL_10
1605 * @arg @ref LL_ADC_CHANNEL_11
1606 * @arg @ref LL_ADC_CHANNEL_12
1607 * @arg @ref LL_ADC_CHANNEL_13
1608 * @arg @ref LL_ADC_CHANNEL_14
1609 * @arg @ref LL_ADC_CHANNEL_15
1610 * @arg @ref LL_ADC_CHANNEL_16
1611 * @arg @ref LL_ADC_CHANNEL_17
1612 * @arg @ref LL_ADC_CHANNEL_18
1613 * @arg @ref LL_ADC_CHANNEL_19
1614 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1615 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
1616 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1617 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1618 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
1619 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
1620 *
1621 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
1622 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
1623 * Other channels are slow channels (conversion rate: refer to reference manual).
1624 * @retval Returned value can be one of the following values:
1625 * @arg @ref LL_ADC_CHANNEL_0
1626 * @arg @ref LL_ADC_CHANNEL_1
1627 * @arg @ref LL_ADC_CHANNEL_2
1628 * @arg @ref LL_ADC_CHANNEL_3
1629 * @arg @ref LL_ADC_CHANNEL_4
1630 * @arg @ref LL_ADC_CHANNEL_5
1631 * @arg @ref LL_ADC_CHANNEL_6
1632 * @arg @ref LL_ADC_CHANNEL_7
1633 * @arg @ref LL_ADC_CHANNEL_8
1634 * @arg @ref LL_ADC_CHANNEL_9
1635 * @arg @ref LL_ADC_CHANNEL_10
1636 * @arg @ref LL_ADC_CHANNEL_11
1637 * @arg @ref LL_ADC_CHANNEL_12
1638 * @arg @ref LL_ADC_CHANNEL_13
1639 * @arg @ref LL_ADC_CHANNEL_14
1640 * @arg @ref LL_ADC_CHANNEL_15
1641 * @arg @ref LL_ADC_CHANNEL_16
1642 * @arg @ref LL_ADC_CHANNEL_17
1643 * @arg @ref LL_ADC_CHANNEL_18
1644 * @arg @ref LL_ADC_CHANNEL_19
1645 */
1646 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1647 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1648
1649 /**
1650 * @brief Helper macro to determine whether the internal channel
1651 * selected is available on the ADC instance selected.
1652 * @note The channel parameter must be a value defined from parameter
1653 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1654 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1655 * must not be a value defined from parameter definition of
1656 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1657 * or a value from functions where a channel number is
1658 * returned from ADC registers,
1659 * because internal and external channels share the same channel
1660 * number in ADC registers. The differentiation is made only with
1661 * parameters definitions of driver.
1662 * @param __ADC_INSTANCE__ ADC instance
1663 * @param __CHANNEL__ This parameter can be one of the following values:
1664 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1665 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
1666 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1667 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1668 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
1669 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
1670 *
1671 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.
1672 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1673 * Value "1" if the internal channel selected is available on the ADC instance selected.
1674 */
1675 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1676 (((__ADC_INSTANCE__) == ADC2) \
1677 &&( \
1678 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1679 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1680 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1681 ((__CHANNEL__) == LL_ADC_CHANNEL_VCORE) || \
1682 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
1683 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
1684 ) \
1685 )
1686
1687 /**
1688 * @brief Helper macro to define ADC analog watchdog parameter:
1689 * define a single channel to monitor with analog watchdog
1690 * from sequencer channel and groups definition.
1691 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1692 * Example:
1693 * LL_ADC_SetAnalogWDMonitChannels(
1694 * ADC1, LL_ADC_AWD1,
1695 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1696 * @param __CHANNEL__ This parameter can be one of the following values:
1697 * @arg @ref LL_ADC_CHANNEL_0 (3)
1698 * @arg @ref LL_ADC_CHANNEL_1 (3)
1699 * @arg @ref LL_ADC_CHANNEL_2 (3)
1700 * @arg @ref LL_ADC_CHANNEL_3 (3)
1701 * @arg @ref LL_ADC_CHANNEL_4 (3)
1702 * @arg @ref LL_ADC_CHANNEL_5 (3)
1703 * @arg @ref LL_ADC_CHANNEL_6
1704 * @arg @ref LL_ADC_CHANNEL_7
1705 * @arg @ref LL_ADC_CHANNEL_8
1706 * @arg @ref LL_ADC_CHANNEL_9
1707 * @arg @ref LL_ADC_CHANNEL_10
1708 * @arg @ref LL_ADC_CHANNEL_11
1709 * @arg @ref LL_ADC_CHANNEL_12
1710 * @arg @ref LL_ADC_CHANNEL_13
1711 * @arg @ref LL_ADC_CHANNEL_14
1712 * @arg @ref LL_ADC_CHANNEL_15
1713 * @arg @ref LL_ADC_CHANNEL_16
1714 * @arg @ref LL_ADC_CHANNEL_17
1715 * @arg @ref LL_ADC_CHANNEL_18
1716 * @arg @ref LL_ADC_CHANNEL_19
1717 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1718 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
1719 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1720 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1721 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
1722 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
1723 *
1724 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
1725 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
1726 * Other channels are slow channels (conversion rate: refer to reference manual).\n
1727 * (1) For ADC channel read back from ADC register,
1728 * comparison with internal channel parameter to be done
1729 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1730 * @param __GROUP__ This parameter can be one of the following values:
1731 * @arg @ref LL_ADC_GROUP_REGULAR
1732 * @arg @ref LL_ADC_GROUP_INJECTED
1733 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
1734 * @retval Returned value can be one of the following values:
1735 * @arg @ref LL_ADC_AWD_DISABLE
1736 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
1737 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
1738 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
1739 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
1740 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
1741 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
1742 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
1743 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
1744 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
1745 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
1746 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
1747 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
1748 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
1749 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
1750 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
1751 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
1752 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
1753 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
1754 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
1755 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
1756 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
1757 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
1758 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
1759 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
1760 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
1761 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
1762 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
1763 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
1764 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
1765 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
1766 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
1767 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
1768 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
1769 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
1770 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
1771 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
1772 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
1773 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
1774 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
1775 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
1776 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
1777 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
1778 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
1779 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
1780 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
1781 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
1782 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
1783 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
1784 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
1785 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
1786 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
1787 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
1788 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
1789 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
1790 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
1791 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
1792 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
1793 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
1794 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
1795 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
1796 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
1797 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
1798 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
1799 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
1800 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
1801 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
1802 * @arg @ref LL_ADC_AWD_CH_VCORE_REG (0)(1)
1803 * @arg @ref LL_ADC_AWD_CH_VCORE_INJ (0)(1)
1804 * @arg @ref LL_ADC_AWD_CH_VCORE_REG_INJ (1)
1805 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
1806 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
1807 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
1808 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
1809 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
1810 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
1811 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(1)
1812 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(1)
1813 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (1)
1814 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(1)
1815 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(1)
1816 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (1)
1817 *
1818 * (0) On STM32MP1, parameter available only on analog watchdog number: AWD1.\n
1819 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.
1820 */
1821 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1822 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
1823 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
1824 : \
1825 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
1826 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
1827 : \
1828 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
1829 )
1830
1831 /**
1832 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1833 * or low in function of ADC resolution, when ADC resolution is
1834 * different of 16 bits.
1835 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
1836 * Example, with a ADC resolution of 8 bits, to set the value of
1837 * analog watchdog threshold high (on 18 bits):
1838 * LL_ADC_SetAnalogWDThresholds
1839 * (< ADCx param >,
1840 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_18_bits>)
1841 * );
1842 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1843 * @arg @ref LL_ADC_RESOLUTION_16B
1844 * @arg @ref LL_ADC_RESOLUTION_14B
1845 * @arg @ref LL_ADC_RESOLUTION_12B
1846 * @arg @ref LL_ADC_RESOLUTION_10B
1847 * @arg @ref LL_ADC_RESOLUTION_8B
1848 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
1849 * @retval Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
1850 */
1851 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1852 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
1853
1854 /**
1855 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1856 * or low in function of ADC resolution, when ADC resolution is
1857 * different of 16 bits.
1858 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1859 * Example, with a ADC resolution of 8 bits, to get the value of
1860 * analog watchdog threshold high (on 18 bits):
1861 * < threshold_value_18_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1862 * (LL_ADC_RESOLUTION_8B,
1863 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1864 * );
1865 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1866 * @arg @ref LL_ADC_RESOLUTION_16B
1867 * @arg @ref LL_ADC_RESOLUTION_14B
1868 * @arg @ref LL_ADC_RESOLUTION_12B
1869 * @arg @ref LL_ADC_RESOLUTION_10B
1870 * @arg @ref LL_ADC_RESOLUTION_8B
1871 * @param __AWD_THRESHOLD_16_BITS__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
1872 * @retval Value between Min_Data=0x000000 and Max_Data=0xFFFFFF
1873 */
1874 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_16_BITS__) \
1875 ((__AWD_THRESHOLD_16_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
1876
1877 /**
1878 * @brief Helper macro to set the ADC calibration value with both single ended
1879 * and differential modes calibration factors concatenated.
1880 * @note To be used with function @ref LL_ADC_SetCalibrationOffsetFactor().
1881 * Example, to set calibration factors single ended to 0x55
1882 * and differential ended to 0x2A:
1883 * LL_ADC_SetCalibrationOffsetFactor(
1884 * ADC1,
1885 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
1886 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
1887 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
1888 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1889 */
1890 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
1891 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
1892
1893 #if defined(ADC_MULTIMODE_SUPPORT)
1894 /**
1895 * @brief Helper macro to get the ADC multimode conversion data of ADC master
1896 * or ADC slave from raw value with both ADC conversion data concatenated.
1897 * @note This macro is intended to be used when multimode transfer by DMA
1898 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
1899 * In this case the transferred data need to processed with this macro
1900 * to separate the conversion data of ADC master and ADC slave.
1901 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
1902 * @arg @ref LL_ADC_MULTI_MASTER
1903 * @arg @ref LL_ADC_MULTI_SLAVE
1904 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
1905 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1906 */
1907 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
1908 (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
1909 #endif /* ADC_MULTIMODE_SUPPORT */
1910
1911 #if defined(ADC_MULTIMODE_SUPPORT)
1912 /**
1913 * @brief Helper macro to select, from a ADC instance, to which ADC instance
1914 * it has a dependence in multimode (ADC master of the corresponding
1915 * ADC common instance).
1916 * @note In case of device with multimode available and a mix of
1917 * ADC instances compliant and not compliant with multimode feature,
1918 * ADC instances not compliant with multimode feature are
1919 * considered as master instances (do not depend to
1920 * any other ADC instance).
1921 * @param __ADCx__ ADC instance
1922 * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
1923 */
1924 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
1925 ( ( ((__ADCx__) == ADC2) \
1926 )? \
1927 (ADC1) \
1928 : \
1929 (__ADCx__) \
1930 )
1931 #endif /* ADC_MULTIMODE_SUPPORT */
1932
1933 /**
1934 * @brief Helper macro to select the ADC common instance
1935 * to which is belonging the selected ADC instance.
1936 * @note ADC common register instance can be used for:
1937 * - Set parameters common to several ADC instances
1938 * - Multimode (for devices with several ADC instances)
1939 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1940 * @param __ADCx__ ADC instance
1941 * @retval ADC common register instance
1942 */
1943 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1944 (ADC12_COMMON)
1945
1946 /**
1947 * @brief Helper macro to check if all ADC instances sharing the same
1948 * ADC common instance are disabled.
1949 * @note This check is required by functions with setting conditioned to
1950 * ADC state:
1951 * All ADC instances of the ADC common group must be disabled.
1952 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1953 * @note On devices with only 1 ADC common instance, parameter of this macro
1954 * is useless and can be ignored (parameter kept for compatibility
1955 * with devices featuring several ADC common instances).
1956 * @param __ADCXY_COMMON__ ADC common instance
1957 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1958 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1959 * are disabled.
1960 * Value "1" if at least one ADC instance sharing the same ADC common instance
1961 * is enabled.
1962 */
1963 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1964 (LL_ADC_IsEnabled(ADC1) | \
1965 LL_ADC_IsEnabled(ADC2) )
1966
1967 /**
1968 * @brief Helper macro to define the ADC conversion data full-scale digital
1969 * value corresponding to the selected ADC resolution.
1970 * @note ADC conversion data full-scale corresponds to voltage range
1971 * determined by analog voltage references Vref+ and Vref-
1972 * (refer to reference manual).
1973 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1974 * @arg @ref LL_ADC_RESOLUTION_16B
1975 * @arg @ref LL_ADC_RESOLUTION_14B
1976 * @arg @ref LL_ADC_RESOLUTION_12B
1977 * @arg @ref LL_ADC_RESOLUTION_10B
1978 * @arg @ref LL_ADC_RESOLUTION_8B
1979 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
1980 */
1981 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1982 (0xFFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
1983
1984 /**
1985 * @brief Helper macro to convert the ADC conversion data from
1986 * a resolution to another resolution.
1987 * @param __DATA__ ADC conversion data to be converted
1988 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
1989 * This parameter can be one of the following values:
1990 * @arg @ref LL_ADC_RESOLUTION_16B
1991 * @arg @ref LL_ADC_RESOLUTION_14B
1992 * @arg @ref LL_ADC_RESOLUTION_12B
1993 * @arg @ref LL_ADC_RESOLUTION_10B
1994 * @arg @ref LL_ADC_RESOLUTION_8B
1995 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1996 * This parameter can be one of the following values:
1997 * @arg @ref LL_ADC_RESOLUTION_16B
1998 * @arg @ref LL_ADC_RESOLUTION_14B
1999 * @arg @ref LL_ADC_RESOLUTION_12B
2000 * @arg @ref LL_ADC_RESOLUTION_10B
2001 * @arg @ref LL_ADC_RESOLUTION_8B
2002 * @retval ADC conversion data to the requested resolution
2003 */
2004 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2005 __ADC_RESOLUTION_CURRENT__,\
2006 __ADC_RESOLUTION_TARGET__) \
2007 (((__DATA__) \
2008 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2009 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2010 )
2011
2012 /**
2013 * @brief Helper macro to calculate the voltage (unit: mVolt)
2014 * corresponding to a ADC conversion data (unit: digital value).
2015 * @note Analog reference voltage (Vref+) must be either known from
2016 * user board environment or can be calculated using ADC measurement
2017 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2018 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2019 * @param __ADC_DATA__ ADC conversion data (resolution 16 bits)
2020 * (unit: digital value).
2021 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2022 * @arg @ref LL_ADC_RESOLUTION_16B
2023 * @arg @ref LL_ADC_RESOLUTION_14B
2024 * @arg @ref LL_ADC_RESOLUTION_12B
2025 * @arg @ref LL_ADC_RESOLUTION_10B
2026 * @arg @ref LL_ADC_RESOLUTION_8B
2027 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2028 */
2029 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2030 __ADC_DATA__,\
2031 __ADC_RESOLUTION__) \
2032 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
2033 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2034 )
2035
2036 /**
2037 * @brief Helper macro to calculate analog reference voltage (Vref+)
2038 * (unit: mVolt) from ADC conversion data of internal voltage
2039 * reference VrefInt.
2040 * @note Computation is using VrefInt calibration value
2041 * stored in system memory for each device during production.
2042 * @note This voltage depends on user board environment: voltage level
2043 * connected to pin Vref+.
2044 * On devices with small package, the pin Vref+ is not present
2045 * and internally bonded to pin Vdda.
2046 * @note On this STM32 series, calibration data of internal voltage reference
2047 * VrefInt corresponds to a resolution of 16 bits,
2048 * this is the recommended ADC resolution to convert voltage of
2049 * internal voltage reference VrefInt.
2050 * Otherwise, this macro performs the processing to scale
2051 * ADC conversion data to 16 bits.
2052 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 16 bits)
2053 * of internal voltage reference VrefInt (unit: digital value).
2054 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2055 * @arg @ref LL_ADC_RESOLUTION_16B
2056 * @arg @ref LL_ADC_RESOLUTION_14B
2057 * @arg @ref LL_ADC_RESOLUTION_12B
2058 * @arg @ref LL_ADC_RESOLUTION_10B
2059 * @arg @ref LL_ADC_RESOLUTION_8B
2060 * @retval Analog reference voltage (unit: mV)
2061 */
2062 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
2063 __ADC_RESOLUTION__) \
2064 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2065 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
2066 (__ADC_RESOLUTION__), \
2067 LL_ADC_RESOLUTION_16B) \
2068 )
2069
2070 /**
2071 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2072 * from ADC conversion data of internal temperature sensor.
2073 * @note Computation is using temperature sensor calibration values
2074 * stored in system memory for each device during production.
2075 * @note Calculation formula:
2076 * Temperature = ((TS_ADC_DATA - TS_CAL1)
2077 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
2078 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
2079 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2080 * Avg_Slope = (TS_CAL2 - TS_CAL1)
2081 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
2082 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
2083 * TEMP_DEGC_CAL1 (calibrated in factory)
2084 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
2085 * TEMP_DEGC_CAL2 (calibrated in factory)
2086 * Caution: Calculation relevancy under reserve that calibration
2087 * parameters are correct (address and data).
2088 * To calculate temperature using temperature sensor
2089 * datasheet typical values (generic values less, therefore
2090 * less accurate than calibrated values),
2091 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
2092 * @note As calculation input, the analog reference voltage (Vref+) must be
2093 * defined as it impacts the ADC LSB equivalent voltage.
2094 * @note Analog reference voltage (Vref+) must be either known from
2095 * user board environment or can be calculated using ADC measurement
2096 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2097 * @note On this STM32 series, calibration data of temperature sensor
2098 * corresponds to a resolution of 16 bits,
2099 * this is the recommended ADC resolution to convert voltage of
2100 * temperature sensor.
2101 * Otherwise, this macro performs the processing to scale
2102 * ADC conversion data to 16 bits.
2103 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2104 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
2105 * temperature sensor (unit: digital value).
2106 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
2107 * sensor voltage has been measured.
2108 * This parameter can be one of the following values:
2109 * @arg @ref LL_ADC_RESOLUTION_16B
2110 * @arg @ref LL_ADC_RESOLUTION_14B
2111 * @arg @ref LL_ADC_RESOLUTION_12B
2112 * @arg @ref LL_ADC_RESOLUTION_10B
2113 * @arg @ref LL_ADC_RESOLUTION_8B
2114 * @retval Temperature (unit: degree Celsius)
2115 */
2116 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
2117 __TEMPSENSOR_ADC_DATA__,\
2118 __ADC_RESOLUTION__) \
2119 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
2120 (__ADC_RESOLUTION__), \
2121 LL_ADC_RESOLUTION_16B) \
2122 * (__VREFANALOG_VOLTAGE__)) \
2123 / TEMPSENSOR_CAL_VREFANALOG) \
2124 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2125 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2126 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2127 ) + TEMPSENSOR_CAL1_TEMP \
2128 )
2129
2130 /**
2131 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2132 * from ADC conversion data of internal temperature sensor.
2133 * @note Computation is using temperature sensor typical values
2134 * (refer to device datasheet).
2135 * @note Calculation formula:
2136 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
2137 * / Avg_Slope + CALx_TEMP
2138 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2139 * (unit: digital value)
2140 * Avg_Slope = temperature sensor slope
2141 * (unit: uV/Degree Celsius)
2142 * TS_TYP_CALx_VOLT = temperature sensor digital value at
2143 * temperature CALx_TEMP (unit: mV)
2144 * Caution: Calculation relevancy under reserve the temperature sensor
2145 * of the current device has characteristics in line with
2146 * datasheet typical values.
2147 * If temperature sensor calibration values are available on
2148 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
2149 * temperature calculation will be more accurate using
2150 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
2151 * @note As calculation input, the analog reference voltage (Vref+) must be
2152 * defined as it impacts the ADC LSB equivalent voltage.
2153 * @note Analog reference voltage (Vref+) must be either known from
2154 * user board environment or can be calculated using ADC measurement
2155 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2156 * @note ADC measurement data must correspond to a resolution of 16 bits
2157 * (full scale digital value 4095). If not the case, the data must be
2158 * preliminarily rescaled to an equivalent resolution of 16 bits.
2159 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
2160 * On STM32MP1, refer to device datasheet parameter "Avg_Slope".
2161 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
2162 * On STM32MP1, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
2163 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
2164 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
2165 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
2166 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
2167 * This parameter can be one of the following values:
2168 * @arg @ref LL_ADC_RESOLUTION_16B
2169 * @arg @ref LL_ADC_RESOLUTION_14B
2170 * @arg @ref LL_ADC_RESOLUTION_12B
2171 * @arg @ref LL_ADC_RESOLUTION_10B
2172 * @arg @ref LL_ADC_RESOLUTION_8B
2173 * @retval Temperature (unit: degree Celsius)
2174 */
2175 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
2176 __TEMPSENSOR_TYP_CALX_V__,\
2177 __TEMPSENSOR_CALX_TEMP__,\
2178 __VREFANALOG_VOLTAGE__,\
2179 __TEMPSENSOR_ADC_DATA__,\
2180 __ADC_RESOLUTION__) \
2181 (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2182 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
2183 * 1000UL) \
2184 - \
2185 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2186 * 1000UL) \
2187 ) \
2188 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
2189 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
2190 )
2191
2192 /**
2193 * @}
2194 */
2195
2196 /**
2197 * @}
2198 */
2199
2200
2201 /* Exported functions --------------------------------------------------------*/
2202 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
2203 * @{
2204 */
2205
2206 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
2207 * @{
2208 */
2209
2210 /**
2211 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2212 * ADC register address from ADC instance and a list of ADC registers
2213 * intended to be used (most commonly) with DMA transfer.
2214 * @note These ADC registers are data registers:
2215 * when ADC conversion data is available in ADC data registers,
2216 * ADC generates a DMA transfer request.
2217 * @note This macro is intended to be used with LL DMA driver, refer to
2218 * function "LL_DMA_ConfigAddresses()".
2219 * Example:
2220 * LL_DMA_ConfigAddresses(DMA1,
2221 * LL_DMA_CHANNEL_1,
2222 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2223 * (uint32_t)&< array or variable >,
2224 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
2225 * @note For devices with several ADC: in multimode, some devices
2226 * use a different data register outside of ADC instance scope
2227 * (common data register). This macro manages this register difference,
2228 * only ADC instance has to be set as parameter.
2229 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
2230 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
2231 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
2232 * @param ADCx ADC instance
2233 * @param Register This parameter can be one of the following values:
2234 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
2235 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
2236 *
2237 * (1) Available on devices with several ADC instances.
2238 * @retval ADC register address
2239 */
2240 #if defined(ADC_MULTIMODE_SUPPORT)
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)2241 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2242 {
2243 uint32_t data_reg_addr;
2244
2245 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
2246 {
2247 /* Retrieve address of register DR */
2248 data_reg_addr = (uint32_t) &(ADCx->DR);
2249 }
2250 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
2251 {
2252 /* Retrieve address of register CDR */
2253 data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
2254 }
2255
2256 return data_reg_addr;
2257 }
2258 #else
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)2259 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2260 {
2261 /* Prevent unused argument(s) compilation warning */
2262 (void)(Register);
2263
2264 /* Retrieve address of register DR */
2265 return (uint32_t) &(ADCx->DR);
2266 }
2267 #endif /* ADC_MULTIMODE_SUPPORT */
2268
2269 /**
2270 * @}
2271 */
2272
2273 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
2274 * @{
2275 */
2276
2277 /**
2278 * @brief Set parameter common to several ADC: Clock source and prescaler.
2279 * @note On this STM32 series, if ADC group injected is used, some
2280 * clock ratio constraints between ADC clock and AHB clock
2281 * must be respected.
2282 * Refer to reference manual.
2283 * @note On this STM32 series, setting of this feature is conditioned to
2284 * ADC state:
2285 * All ADC instances of the ADC common group must be disabled.
2286 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2287 * ADC instance or by using helper macro helper macro
2288 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2289 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
2290 * CCR PRESC LL_ADC_SetCommonClock
2291 * @param ADCxy_COMMON ADC common instance
2292 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2293 * @param CommonClock This parameter can be one of the following values:
2294 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2295 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2296 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2297 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2298 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2299 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2300 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2301 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2302 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2303 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2304 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2305 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2306 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2307 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2308 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2309 * @retval None
2310 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)2311 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
2312 {
2313 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
2314 }
2315
2316 /**
2317 * @brief Get parameter common to several ADC: Clock source and prescaler.
2318 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
2319 * CCR PRESC LL_ADC_GetCommonClock
2320 * @param ADCxy_COMMON ADC common instance
2321 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2322 * @retval Returned value can be one of the following values:
2323 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2324 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2325 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2326 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2327 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2328 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2329 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2330 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2331 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2332 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2333 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2334 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2335 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2336 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2337 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2338 */
LL_ADC_GetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON)2339 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
2340 {
2341 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
2342 }
2343
2344 /**
2345 * @brief Set parameter common to several ADC: measurement path to
2346 * internal channels (VrefInt, temperature sensor, ...).
2347 * Configure all paths (overwrite current configuration).
2348 * @note One or several values can be selected.
2349 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2350 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2351 * The values not selected are removed from configuration.
2352 * @note Stabilization time of measurement path to internal channel:
2353 * After enabling internal paths, before starting ADC conversion,
2354 * a delay is required for internal voltage reference and
2355 * temperature sensor stabilization time.
2356 * Refer to device datasheet.
2357 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2358 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
2359 * @note ADC internal channel sampling time constraint:
2360 * For ADC conversion of internal channels,
2361 * a sampling time minimum value is required.
2362 * Refer to device datasheet.
2363 * @note On this STM32 series, setting of this feature is conditioned to
2364 * ADC state:
2365 * All ADC instances of the ADC common group must be disabled.
2366 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2367 * ADC instance or by using helper macro helper macro
2368 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2369 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
2370 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
2371 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
2372 * @param ADCxy_COMMON ADC common instance
2373 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2374 * @param PathInternal This parameter can be a combination of the following values:
2375 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2376 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2377 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2378 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2379 * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE (1)
2380 *
2381 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.
2382 * @retval None
2383 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2384 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2385 {
2386 if(PathInternal == LL_ADC_PATH_INTERNAL_VDDCORE)
2387 {
2388 /* Feature limited to ADC instance ADC2 */
2389 SET_BIT(ADC2->OR, ADC2_OR_VDDCOREEN);
2390 }
2391 else
2392 {
2393 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN, PathInternal);
2394 }
2395 }
2396
2397 /**
2398 * @brief Set parameter common to several ADC: measurement path to
2399 * internal channels (VrefInt, temperature sensor, ...).
2400 * Add paths to the current configuration.
2401 * @note One or several values can be selected.
2402 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2403 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2404 * @note Stabilization time of measurement path to internal channel:
2405 * After enabling internal paths, before starting ADC conversion,
2406 * a delay is required for internal voltage reference and
2407 * temperature sensor stabilization time.
2408 * Refer to device datasheet.
2409 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2410 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
2411 * @note ADC internal channel sampling time constraint:
2412 * For ADC conversion of internal channels,
2413 * a sampling time minimum value is required.
2414 * Refer to device datasheet.
2415 * @note On this STM32 series, setting of this feature is conditioned to
2416 * ADC state:
2417 * All ADC instances of the ADC common group must be disabled.
2418 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2419 * ADC instance or by using helper macro helper macro
2420 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2421 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
2422 * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n
2423 * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
2424 * @param ADCxy_COMMON ADC common instance
2425 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2426 * @param PathInternal This parameter can be a combination of the following values:
2427 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2428 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2429 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2430 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2431 * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE (1)
2432 *
2433 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.
2434 * @retval None
2435 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2436 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2437 {
2438 if(PathInternal == LL_ADC_PATH_INTERNAL_VDDCORE)
2439 {
2440 /* Feature limited to ADC instance ADC2 */
2441 SET_BIT(ADC2->OR, ADC2_OR_VDDCOREEN);
2442 }
2443 else
2444 {
2445 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
2446 }
2447 }
2448
2449 /**
2450 * @brief Set parameter common to several ADC: measurement path to
2451 * internal channels (VrefInt, temperature sensor, ...).
2452 * Remove paths to the current configuration.
2453 * @note One or several values can be selected.
2454 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2455 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2456 * @note On this STM32 series, setting of this feature is conditioned to
2457 * ADC state:
2458 * All ADC instances of the ADC common group must be disabled.
2459 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2460 * ADC instance or by using helper macro helper macro
2461 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2462 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
2463 * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n
2464 * CCR VBATEN LL_ADC_SetCommonPathInternalChRem
2465 * @param ADCxy_COMMON ADC common instance
2466 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2467 * @param PathInternal This parameter can be a combination of the following values:
2468 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2469 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2470 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2471 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2472 * @arg @ref LL_ADC_PATH_INTERNAL_VDDCORE (1)
2473 *
2474 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.
2475 * @retval None
2476 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2477 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2478 {
2479 if(PathInternal == LL_ADC_PATH_INTERNAL_VDDCORE)
2480 {
2481 /* Feature limited to ADC instance ADC2 */
2482 CLEAR_BIT(ADC2->OR, ADC2_OR_VDDCOREEN);
2483 }
2484 else
2485 {
2486 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
2487 }
2488 }
2489
2490 /**
2491 * @brief Get parameter common to several ADC: measurement path to internal
2492 * channels (VrefInt, temperature sensor, ...).
2493 * @note One or several values can be selected.
2494 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2495 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2496 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
2497 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
2498 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
2499 * @param ADCxy_COMMON ADC common instance
2500 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2501 * @retval Returned value can be a combination of the following values:
2502 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2503 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2504 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2505 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2506 */
LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON)2507 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
2508 {
2509 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN));
2510 }
2511
2512 /**
2513 * @}
2514 */
2515
2516 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
2517 * @{
2518 */
2519
2520 /**
2521 * @brief Set ADC calibration factor in the mode single-ended
2522 * or differential (for devices with differential mode available).
2523 * @note This function is intended to set calibration parameters
2524 * without having to perform a new calibration using
2525 * @ref LL_ADC_StartCalibration().
2526 * @note For devices with differential mode available:
2527 * Calibration of offset is specific to each of
2528 * single-ended and differential modes
2529 * (calibration factor must be specified for each of these
2530 * differential modes, if used afterwards and if the application
2531 * requires their calibration).
2532 * Calibration of linearity is common to both
2533 * single-ended and differential modes
2534 * (calibration factor can be specified only once).
2535 * @note In case of setting calibration factors of both modes single ended
2536 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
2537 * both calibration factors must be concatenated.
2538 * To perform this processing, use helper macro
2539 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
2540 * @note On this STM32 series, setting of this feature is conditioned to
2541 * ADC state:
2542 * ADC must be enabled, without calibration on going, without conversion
2543 * on going on group regular.
2544 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationOffsetFactor\n
2545 * CALFACT CALFACT_D LL_ADC_SetCalibrationOffsetFactor
2546 * @param ADCx ADC instance
2547 * @param SingleDiff This parameter can be one of the following values:
2548 * @arg @ref LL_ADC_SINGLE_ENDED
2549 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2550 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
2551 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
2552 * @retval None
2553 */
LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff,uint32_t CalibrationFactor)2554 __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
2555 {
2556 MODIFY_REG(ADCx->CALFACT,
2557 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
2558 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
2559 }
2560
2561 /**
2562 * @brief Get ADC calibration factor in the mode single-ended
2563 * or differential (for devices with differential mode available).
2564 * @note Calibration factors are set by hardware after performing
2565 * a calibration run using function @ref LL_ADC_StartCalibration().
2566 * @note For devices with differential mode available:
2567 * Calibration of offset is specific to each of
2568 * single-ended and differential modes
2569 * Calibration of linearity is common to both
2570 * single-ended and differential modes
2571 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationOffsetFactor\n
2572 * CALFACT CALFACT_D LL_ADC_GetCalibrationOffsetFactor
2573 * @param ADCx ADC instance
2574 * @param SingleDiff This parameter can be one of the following values:
2575 * @arg @ref LL_ADC_SINGLE_ENDED
2576 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2577 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
2578 */
LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff)2579 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
2580 {
2581 /* Retrieve bits with position in register depending on parameter */
2582 /* "SingleDiff". */
2583 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
2584 /* containing other bits reserved for other purpose. */
2585 return (uint32_t)(READ_BIT(ADCx->CALFACT,
2586 (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
2587 ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
2588 }
2589
2590 /**
2591 * @brief Set ADC Linear calibration factor in the mode single-ended.
2592 * @note This function is intended to set linear calibration parameters
2593 * without having to perform a new calibration using
2594 * @ref LL_ADC_StartCalibration().
2595 * @note On this STM32 series, setting of this feature is conditioned to
2596 * ADC state:
2597 * ADC must be enabled, without calibration on going, without conversion
2598 * on going on group regular.
2599 * @rmtoll CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor\n
2600 * CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor
2601 * @param ADCx ADC instance
2602 * @param LinearityWord This parameter can be one of the following values:
2603 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD1
2604 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD2
2605 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD3
2606 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD4
2607 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD5
2608 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD6
2609 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF
2610 * @retval None
2611 */
LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef * ADCx,uint32_t LinearityWord,uint32_t CalibrationFactor)2612 __STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord, uint32_t CalibrationFactor)
2613 {
2614 uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
2615 MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT, CalibrationFactor);
2616 MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord);
2617 while ((READ_BIT(ADCx->CR, LinearityWord)==0UL) && (timeout_cpu_cycles > 0UL))
2618 {
2619 timeout_cpu_cycles--;
2620 }
2621 }
2622
2623 /**
2624 * @brief Get ADC Linear calibration factor in the mode single-ended.
2625 * @note Calibration factors are set by hardware after performing
2626 * a calibration run using function @ref LL_ADC_StartCalibration().
2627 * @rmtoll CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor\n
2628 * CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor
2629 * @param ADCx ADC instance
2630 * @param LinearityWord This parameter can be one of the following values:
2631 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD1
2632 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD2
2633 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD3
2634 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD4
2635 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD5
2636 * @arg @ref LL_ADC_CALIB_LINEARITY_WORD6
2637 * @retval Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF
2638 */
LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef * ADCx,uint32_t LinearityWord)2639 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord)
2640 {
2641 uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
2642 CLEAR_BIT(ADCx->CR, LinearityWord);
2643 while ((READ_BIT(ADCx->CR, LinearityWord)!=0UL) && (timeout_cpu_cycles > 0UL))
2644 {
2645 timeout_cpu_cycles--;
2646 }
2647 return (uint32_t)(READ_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT));
2648 }
2649 /**
2650 * @brief Set ADC resolution.
2651 * Refer to reference manual for alignments formats
2652 * dependencies to ADC resolutions.
2653 * @note On this STM32 series, setting of this feature is conditioned to
2654 * ADC state:
2655 * ADC must be disabled or enabled without conversion on going
2656 * on either groups regular or injected.
2657 * @rmtoll CFGR RES LL_ADC_SetResolution
2658 * @param ADCx ADC instance
2659 * @param Resolution This parameter can be one of the following values:
2660 * @arg @ref LL_ADC_RESOLUTION_16B
2661 * @arg @ref LL_ADC_RESOLUTION_14B
2662 * @arg @ref LL_ADC_RESOLUTION_12B
2663 * @arg @ref LL_ADC_RESOLUTION_10B
2664 * @arg @ref LL_ADC_RESOLUTION_8B
2665 * @retval None
2666 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)2667 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2668 {
2669 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
2670 }
2671
2672 /**
2673 * @brief Get ADC resolution.
2674 * Refer to reference manual for alignments formats
2675 * dependencies to ADC resolutions.
2676 * @rmtoll CFGR RES LL_ADC_GetResolution
2677 * @param ADCx ADC instance
2678 * @retval Returned value can be one of the following values:
2679 * @arg @ref LL_ADC_RESOLUTION_16B
2680 * @arg @ref LL_ADC_RESOLUTION_14B
2681 * @arg @ref LL_ADC_RESOLUTION_12B
2682 * @arg @ref LL_ADC_RESOLUTION_10B
2683 * @arg @ref LL_ADC_RESOLUTION_8B
2684 */
LL_ADC_GetResolution(ADC_TypeDef * ADCx)2685 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
2686 {
2687 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
2688 }
2689
2690 /**
2691 * @brief Set ADC low power mode.
2692 * @note Description of ADC low power modes:
2693 * - ADC low power mode "auto wait": Dynamic low power mode,
2694 * ADC conversions occurrences are limited to the minimum necessary
2695 * in order to reduce power consumption.
2696 * New ADC conversion starts only when the previous
2697 * unitary conversion data (for ADC group regular)
2698 * or previous sequence conversions data (for ADC group injected)
2699 * has been retrieved by user software.
2700 * In the meantime, ADC remains idle: does not performs any
2701 * other conversion.
2702 * This mode allows to automatically adapt the ADC conversions
2703 * triggers to the speed of the software that reads the data.
2704 * Moreover, this avoids risk of overrun for low frequency
2705 * applications.
2706 * How to use this low power mode:
2707 * - It is not recommended to use with interruption or DMA
2708 * since these modes have to clear immediately the EOC flag
2709 * (by CPU to free the IRQ pending event or by DMA).
2710 * Auto wait will work but fort a very short time, discarding
2711 * its intended benefit (except specific case of high load of CPU
2712 * or DMA transfers which can justify usage of auto wait).
2713 * - Do use with polling: 1. Start conversion,
2714 * 2. Later on, when conversion data is needed: poll for end of
2715 * conversion to ensure that conversion is completed and
2716 * retrieve ADC conversion data. This will trig another
2717 * ADC conversion start.
2718 * - ADC low power mode "auto power-off" (feature available on
2719 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2720 * the ADC automatically powers-off after a conversion and
2721 * automatically wakes up when a new conversion is triggered
2722 * (with startup time between trigger and start of sampling).
2723 * This feature can be combined with low power mode "auto wait".
2724 * @note With ADC low power mode "auto wait", the ADC conversion data read
2725 * is corresponding to previous ADC conversion start, independently
2726 * of delay during which ADC was idle.
2727 * Therefore, the ADC conversion data may be outdated: does not
2728 * correspond to the current voltage level on the selected
2729 * ADC channel.
2730 * @note On this STM32 series, setting of this feature is conditioned to
2731 * ADC state:
2732 * ADC must be disabled or enabled without conversion on going
2733 * on either groups regular or injected.
2734 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
2735 * @param ADCx ADC instance
2736 * @param LowPowerMode This parameter can be one of the following values:
2737 * @arg @ref LL_ADC_LP_MODE_NONE
2738 * @arg @ref LL_ADC_LP_AUTOWAIT
2739 * @retval None
2740 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)2741 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2742 {
2743 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
2744 }
2745
2746 /**
2747 * @brief Get ADC low power mode:
2748 * @note Description of ADC low power modes:
2749 * - ADC low power mode "auto wait": Dynamic low power mode,
2750 * ADC conversions occurrences are limited to the minimum necessary
2751 * in order to reduce power consumption.
2752 * New ADC conversion starts only when the previous
2753 * unitary conversion data (for ADC group regular)
2754 * or previous sequence conversions data (for ADC group injected)
2755 * has been retrieved by user software.
2756 * In the meantime, ADC remains idle: does not performs any
2757 * other conversion.
2758 * This mode allows to automatically adapt the ADC conversions
2759 * triggers to the speed of the software that reads the data.
2760 * Moreover, this avoids risk of overrun for low frequency
2761 * applications.
2762 * How to use this low power mode:
2763 * - It is not recommended to use with interruption or DMA
2764 * since these modes have to clear immediately the EOC flag
2765 * (by CPU to free the IRQ pending event or by DMA).
2766 * Auto wait will work but fort a very short time, discarding
2767 * its intended benefit (except specific case of high load of CPU
2768 * or DMA transfers which can justify usage of auto wait).
2769 * - Do use with polling: 1. Start conversion,
2770 * 2. Later on, when conversion data is needed: poll for end of
2771 * conversion to ensure that conversion is completed and
2772 * retrieve ADC conversion data. This will trig another
2773 * ADC conversion start.
2774 * - ADC low power mode "auto power-off" (feature available on
2775 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2776 * the ADC automatically powers-off after a conversion and
2777 * automatically wakes up when a new conversion is triggered
2778 * (with startup time between trigger and start of sampling).
2779 * This feature can be combined with low power mode "auto wait".
2780 * @note With ADC low power mode "auto wait", the ADC conversion data read
2781 * is corresponding to previous ADC conversion start, independently
2782 * of delay during which ADC was idle.
2783 * Therefore, the ADC conversion data may be outdated: does not
2784 * correspond to the current voltage level on the selected
2785 * ADC channel.
2786 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
2787 * @param ADCx ADC instance
2788 * @retval Returned value can be one of the following values:
2789 * @arg @ref LL_ADC_LP_MODE_NONE
2790 * @arg @ref LL_ADC_LP_AUTOWAIT
2791 */
LL_ADC_GetLowPowerMode(ADC_TypeDef * ADCx)2792 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
2793 {
2794 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
2795 }
2796
2797 /**
2798 * @brief Set ADC selected offset number 1, 2, 3 or 4.
2799 * @note This function set the 2 items of offset configuration:
2800 * - ADC channel to which the offset programmed will be applied
2801 * (independently of channel mapped on ADC group regular
2802 * or group injected)
2803 * - Offset level (offset to be subtracted from the raw
2804 * converted data).
2805 * @note Caution: Offset format is dependent to ADC resolution:
2806 * offset has to be left-aligned on bit 11, the LSB (right bits)
2807 * are set to 0.
2808 * @note This function enables the offset, by default. It can be forced
2809 * to disable state using function LL_ADC_SetOffsetState().
2810 * @note If a channel is mapped on several offsets numbers, only the offset
2811 * with the lowest value is considered for the subtraction.
2812 * @note On this STM32 series, setting of this feature is conditioned to
2813 * ADC state:
2814 * ADC must be disabled or enabled without conversion on going
2815 * on either groups regular or injected.
2816 * @note On STM32MP1, some fast channels are available: fast analog inputs
2817 * coming from GPIO pads (ADC_IN0..5).
2818 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
2819 * OFR1 OFFSET1 LL_ADC_SetOffset\n
2820 * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
2821 * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
2822 * OFR2 OFFSET2 LL_ADC_SetOffset\n
2823 * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
2824 * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
2825 * OFR3 OFFSET3 LL_ADC_SetOffset\n
2826 * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
2827 * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
2828 * OFR4 OFFSET4 LL_ADC_SetOffset\n
2829 * OFR4 OFFSET4_EN LL_ADC_SetOffset
2830 * @param ADCx ADC instance
2831 * @param Offsety This parameter can be one of the following values:
2832 * @arg @ref LL_ADC_OFFSET_1
2833 * @arg @ref LL_ADC_OFFSET_2
2834 * @arg @ref LL_ADC_OFFSET_3
2835 * @arg @ref LL_ADC_OFFSET_4
2836 * @param Channel This parameter can be one of the following values:
2837 * @arg @ref LL_ADC_CHANNEL_0 (3)
2838 * @arg @ref LL_ADC_CHANNEL_1 (3)
2839 * @arg @ref LL_ADC_CHANNEL_2 (3)
2840 * @arg @ref LL_ADC_CHANNEL_3 (3)
2841 * @arg @ref LL_ADC_CHANNEL_4 (3)
2842 * @arg @ref LL_ADC_CHANNEL_5 (3)
2843 * @arg @ref LL_ADC_CHANNEL_6
2844 * @arg @ref LL_ADC_CHANNEL_7
2845 * @arg @ref LL_ADC_CHANNEL_8
2846 * @arg @ref LL_ADC_CHANNEL_9
2847 * @arg @ref LL_ADC_CHANNEL_10
2848 * @arg @ref LL_ADC_CHANNEL_11
2849 * @arg @ref LL_ADC_CHANNEL_12
2850 * @arg @ref LL_ADC_CHANNEL_13
2851 * @arg @ref LL_ADC_CHANNEL_14
2852 * @arg @ref LL_ADC_CHANNEL_15
2853 * @arg @ref LL_ADC_CHANNEL_16
2854 * @arg @ref LL_ADC_CHANNEL_17
2855 * @arg @ref LL_ADC_CHANNEL_18
2856 * @arg @ref LL_ADC_CHANNEL_19
2857 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2858 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
2859 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2860 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2861 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
2862 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
2863 *
2864 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
2865 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
2866 * Other channels are slow channels (conversion rate: refer to reference manual).
2867 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
2868 * @retval None
2869 */
LL_ADC_SetOffset(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t Channel,uint32_t OffsetLevel)2870 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
2871 {
2872 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
2873
2874 MODIFY_REG(*preg,
2875 ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
2876 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
2877 }
2878
2879 /**
2880 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
2881 * Channel to which the offset programmed will be applied
2882 * (independently of channel mapped on ADC group regular
2883 * or group injected)
2884 * @note Usage of the returned channel number:
2885 * - To reinject this channel into another function LL_ADC_xxx:
2886 * the returned channel number is only partly formatted on definition
2887 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2888 * with parts of literals LL_ADC_CHANNEL_x or using
2889 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2890 * Then the selected literal LL_ADC_CHANNEL_x can be used
2891 * as parameter for another function.
2892 * - To get the channel number in decimal format:
2893 * process the returned value with the helper macro
2894 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2895 * @note On STM32MP1, some fast channels are available: fast analog inputs
2896 * coming from GPIO pads (ADC_IN0..5).
2897 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
2898 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
2899 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
2900 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
2901 * @param ADCx ADC instance
2902 * @param Offsety This parameter can be one of the following values:
2903 * @arg @ref LL_ADC_OFFSET_1
2904 * @arg @ref LL_ADC_OFFSET_2
2905 * @arg @ref LL_ADC_OFFSET_3
2906 * @arg @ref LL_ADC_OFFSET_4
2907 * @retval Returned value can be one of the following values:
2908 * @arg @ref LL_ADC_CHANNEL_0 (3)
2909 * @arg @ref LL_ADC_CHANNEL_1 (3)
2910 * @arg @ref LL_ADC_CHANNEL_2 (3)
2911 * @arg @ref LL_ADC_CHANNEL_3 (3)
2912 * @arg @ref LL_ADC_CHANNEL_4 (3)
2913 * @arg @ref LL_ADC_CHANNEL_5 (3)
2914 * @arg @ref LL_ADC_CHANNEL_6
2915 * @arg @ref LL_ADC_CHANNEL_7
2916 * @arg @ref LL_ADC_CHANNEL_8
2917 * @arg @ref LL_ADC_CHANNEL_9
2918 * @arg @ref LL_ADC_CHANNEL_10
2919 * @arg @ref LL_ADC_CHANNEL_11
2920 * @arg @ref LL_ADC_CHANNEL_12
2921 * @arg @ref LL_ADC_CHANNEL_13
2922 * @arg @ref LL_ADC_CHANNEL_14
2923 * @arg @ref LL_ADC_CHANNEL_15
2924 * @arg @ref LL_ADC_CHANNEL_16
2925 * @arg @ref LL_ADC_CHANNEL_17
2926 * @arg @ref LL_ADC_CHANNEL_18
2927 * @arg @ref LL_ADC_CHANNEL_19
2928 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2929 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
2930 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2931 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2932 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
2933 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
2934 *
2935 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
2936 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
2937 * Other channels are slow channels (conversion rate: refer to reference manual).\n
2938 * (1) For ADC channel read back from ADC register,
2939 * comparison with internal channel parameter to be done
2940 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2941 */
LL_ADC_GetOffsetChannel(ADC_TypeDef * ADCx,uint32_t Offsety)2942 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
2943 {
2944 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
2945
2946 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
2947 }
2948
2949 /**
2950 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
2951 * Offset level (offset to be subtracted from the raw
2952 * converted data).
2953 * @note Caution: Offset format is dependent to ADC resolution:
2954 * offset has to be left-aligned on bit 11, the LSB (right bits)
2955 * are set to 0.
2956 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
2957 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
2958 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
2959 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
2960 * @param ADCx ADC instance
2961 * @param Offsety This parameter can be one of the following values:
2962 * @arg @ref LL_ADC_OFFSET_1
2963 * @arg @ref LL_ADC_OFFSET_2
2964 * @arg @ref LL_ADC_OFFSET_3
2965 * @arg @ref LL_ADC_OFFSET_4
2966 * @retval Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
2967 */
LL_ADC_GetOffsetLevel(ADC_TypeDef * ADCx,uint32_t Offsety)2968 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
2969 {
2970 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
2971
2972 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
2973 }
2974
2975
2976 /**
2977 * @brief Set data right shift for the ADC selected offset number 1, 2, 3 or 4:
2978 * signed offset saturation if enabled or disabled.
2979 * @rmtoll CFGR2 RSHIFT LL_ADC_SetDataRightShift\n
2980 * @param ADCx ADC instance
2981 * @param Offsety This parameter can be one of the following values:
2982 * @arg @ref LL_ADC_OFFSET_1
2983 * @arg @ref LL_ADC_OFFSET_2
2984 * @arg @ref LL_ADC_OFFSET_3
2985 * @arg @ref LL_ADC_OFFSET_4
2986 * @param RigthShift This parameter can be one of the following values:
2987 * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE
2988 * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE
2989 * @retval Returned None
2990 */
LL_ADC_SetDataRightShift(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t RigthShift)2991 __STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift)
2992 {
2993 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL));
2994 }
2995
2996 /**
2997 * @brief Get data right shift for the ADC selected offset number 1, 2, 3 or 4:
2998 * signed offset saturation if enabled or disabled.
2999 * @rmtoll CFGR2 RSHIFT LL_ADC_GetDataRightShift\n
3000 * @param ADCx ADC instance
3001 * @param Offsety This parameter can be one of the following values:
3002 * @arg @ref LL_ADC_OFFSET_1
3003 * @arg @ref LL_ADC_OFFSET_2
3004 * @arg @ref LL_ADC_OFFSET_3
3005 * @arg @ref LL_ADC_OFFSET_4
3006 * @retval Returned value can be one of the following values:
3007 * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE
3008 * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE
3009 */
LL_ADC_GetDataRightShift(ADC_TypeDef * ADCx,uint32_t Offsety)3010 __STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety)
3011 {
3012 return (uint32_t) ((READ_BIT(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 << (Offsety & 0x1FUL)))) >> (Offsety & 0x1FUL));
3013 }
3014
3015 /**
3016 * @brief Set signed saturation for the ADC selected offset number 1, 2, 3 or 4:
3017 * signed offset saturation if enabled or disabled.
3018 * @rmtoll OFR1 SSATE LL_ADC_SetOffsetSignedSaturation\n
3019 * OFR2 SSATE LL_ADC_SetOffsetSignedSaturation\n
3020 * OFR3 SSATE LL_ADC_SetOffsetSignedSaturation\n
3021 * OFR4 SSATE LL_ADC_SetOffsetSignedSaturation
3022 * @param ADCx ADC instance
3023 * @param Offsety This parameter can be one of the following values:
3024 * @arg @ref LL_ADC_OFFSET_1
3025 * @arg @ref LL_ADC_OFFSET_2
3026 * @arg @ref LL_ADC_OFFSET_3
3027 * @arg @ref LL_ADC_OFFSET_4
3028 * @param OffsetSignedSaturation This parameter can be one of the following values:
3029 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
3030 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
3031 * @retval Returned None
3032 */
LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetSignedSaturation)3033 __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation)
3034 {
3035 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3036 MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);
3037 }
3038
3039 /**
3040 * @brief Get signed saturation for the ADC selected offset number 1, 2, 3 or 4:
3041 * signed offset saturation if enabled or disabled.
3042 * @rmtoll OFR1 SSATE LL_ADC_GetOffsetSignedSaturation\n
3043 * OFR2 SSATE LL_ADC_GetOffsetSignedSaturation\n
3044 * OFR3 SSATE LL_ADC_GetOffsetSignedSaturation\n
3045 * OFR4 SSATE LL_ADC_GetOffsetSignedSaturation
3046 * @param ADCx ADC instance
3047 * @param Offsety This parameter can be one of the following values:
3048 * @arg @ref LL_ADC_OFFSET_1
3049 * @arg @ref LL_ADC_OFFSET_2
3050 * @arg @ref LL_ADC_OFFSET_3
3051 * @arg @ref LL_ADC_OFFSET_4
3052 * @retval Returned value can be one of the following values:
3053 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
3054 * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
3055 */
LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef * ADCx,uint32_t Offsety)3056 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
3057 {
3058 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3059 return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE);
3060 }
3061
3062 /**
3063 * @}
3064 */
3065
3066 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
3067 * @{
3068 */
3069
3070 /**
3071 * @brief Set ADC group regular conversion trigger source:
3072 * internal (SW start) or from external peripheral (timer event,
3073 * external interrupt line).
3074 * @note On this STM32 series, setting trigger source to external trigger
3075 * also set trigger polarity to rising edge
3076 * (default setting for compatibility with some ADC on other
3077 * STM32 families having this setting set by HW default value).
3078 * In case of need to modify trigger edge, use
3079 * function @ref LL_ADC_REG_SetTriggerEdge().
3080 * @note Availability of parameters of trigger sources from timer
3081 * depends on timers availability on the selected device.
3082 * @note On this STM32 series, setting of this feature is conditioned to
3083 * ADC state:
3084 * ADC must be disabled or enabled without conversion on going
3085 * on group regular.
3086 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
3087 * CFGR EXTEN LL_ADC_REG_SetTriggerSource
3088 * @param ADCx ADC instance
3089 * @param TriggerSource This parameter can be one of the following values:
3090 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3091 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3092 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3093 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3094 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3095 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3096 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3097 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3098 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3099 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3100 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3101 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3102 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3103 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3104 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3105 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3106 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3107 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_OUT
3108 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT
3109 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT
3110 * @retval None
3111 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)3112 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3113 {
3114 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
3115 }
3116
3117 /**
3118 * @brief Get ADC group regular conversion trigger source:
3119 * internal (SW start) or from external peripheral (timer event,
3120 * external interrupt line).
3121 * @note To determine whether group regular trigger source is
3122 * internal (SW start) or external, without detail
3123 * of which peripheral is selected as external trigger,
3124 * (equivalent to
3125 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
3126 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
3127 * @note Availability of parameters of trigger sources from timer
3128 * depends on timers availability on the selected device.
3129 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
3130 * CFGR EXTEN LL_ADC_REG_GetTriggerSource
3131 * @param ADCx ADC instance
3132 * @retval Returned value can be one of the following values:
3133 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3134 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3135 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3136 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3137 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3138 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3139 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3140 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3141 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3142 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3143 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3144 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3145 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3146 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3147 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3148 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3149 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3150 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_OUT
3151 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT
3152 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT
3153 */
LL_ADC_REG_GetTriggerSource(ADC_TypeDef * ADCx)3154 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
3155 {
3156 __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
3157
3158 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3159 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
3160 uint32_t shift_exten = ((trigger_source & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3161
3162 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
3163 /* to match with triggers literals definition. */
3164 return ((trigger_source
3165 & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR_EXTSEL)
3166 | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR_EXTEN)
3167 );
3168 }
3169
3170 /**
3171 * @brief Get ADC group regular conversion trigger source internal (SW start)
3172 * or external.
3173 * @note In case of group regular trigger source set to external trigger,
3174 * to determine which peripheral is selected as external trigger,
3175 * use function @ref LL_ADC_REG_GetTriggerSource().
3176 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
3177 * @param ADCx ADC instance
3178 * @retval Value "0" if trigger source external trigger
3179 * Value "1" if trigger source SW start.
3180 */
LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)3181 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
3182 {
3183 return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
3184 }
3185
3186 /**
3187 * @brief Set ADC group regular conversion trigger polarity.
3188 * @note Applicable only for trigger source set to external trigger.
3189 * @note On this STM32 series, setting of this feature is conditioned to
3190 * ADC state:
3191 * ADC must be disabled or enabled without conversion on going
3192 * on group regular.
3193 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
3194 * @param ADCx ADC instance
3195 * @param ExternalTriggerEdge This parameter can be one of the following values:
3196 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3197 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3198 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3199 * @retval None
3200 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3201 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3202 {
3203 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
3204 }
3205
3206 /**
3207 * @brief Get ADC group regular conversion trigger polarity.
3208 * @note Applicable only for trigger source set to external trigger.
3209 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
3210 * @param ADCx ADC instance
3211 * @retval Returned value can be one of the following values:
3212 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3213 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3214 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3215 */
LL_ADC_REG_GetTriggerEdge(ADC_TypeDef * ADCx)3216 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
3217 {
3218 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
3219 }
3220
3221 /**
3222 * @brief Set ADC group regular sequencer length and scan direction.
3223 * @note Description of ADC group regular sequencer features:
3224 * - For devices with sequencer fully configurable
3225 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3226 * sequencer length and each rank affectation to a channel
3227 * are configurable.
3228 * This function performs configuration of:
3229 * - Sequence length: Number of ranks in the scan sequence.
3230 * - Sequence direction: Unless specified in parameters, sequencer
3231 * scan direction is forward (from rank 1 to rank n).
3232 * Sequencer ranks are selected using
3233 * function "LL_ADC_REG_SetSequencerRanks()".
3234 * - For devices with sequencer not fully configurable
3235 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3236 * sequencer length and each rank affectation to a channel
3237 * are defined by channel number.
3238 * This function performs configuration of:
3239 * - Sequence length: Number of ranks in the scan sequence is
3240 * defined by number of channels set in the sequence,
3241 * rank of each channel is fixed by channel HW number.
3242 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3243 * - Sequence direction: Unless specified in parameters, sequencer
3244 * scan direction is forward (from lowest channel number to
3245 * highest channel number).
3246 * Sequencer ranks are selected using
3247 * function "LL_ADC_REG_SetSequencerChannels()".
3248 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3249 * ADC conversion on only 1 channel.
3250 * @note On this STM32 series, setting of this feature is conditioned to
3251 * ADC state:
3252 * ADC must be disabled or enabled without conversion on going
3253 * on group regular.
3254 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
3255 * @param ADCx ADC instance
3256 * @param SequencerNbRanks This parameter can be one of the following values:
3257 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3258 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3259 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3260 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3261 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3262 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3263 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3264 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3265 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3266 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3267 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3268 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3269 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3270 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3271 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3272 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3273 * @retval None
3274 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)3275 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
3276 {
3277 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
3278 }
3279
3280 /**
3281 * @brief Get ADC group regular sequencer length and scan direction.
3282 * @note Description of ADC group regular sequencer features:
3283 * - For devices with sequencer fully configurable
3284 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3285 * sequencer length and each rank affectation to a channel
3286 * are configurable.
3287 * This function retrieves:
3288 * - Sequence length: Number of ranks in the scan sequence.
3289 * - Sequence direction: Unless specified in parameters, sequencer
3290 * scan direction is forward (from rank 1 to rank n).
3291 * Sequencer ranks are selected using
3292 * function "LL_ADC_REG_SetSequencerRanks()".
3293 * - For devices with sequencer not fully configurable
3294 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3295 * sequencer length and each rank affectation to a channel
3296 * are defined by channel number.
3297 * This function retrieves:
3298 * - Sequence length: Number of ranks in the scan sequence is
3299 * defined by number of channels set in the sequence,
3300 * rank of each channel is fixed by channel HW number.
3301 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3302 * - Sequence direction: Unless specified in parameters, sequencer
3303 * scan direction is forward (from lowest channel number to
3304 * highest channel number).
3305 * Sequencer ranks are selected using
3306 * function "LL_ADC_REG_SetSequencerChannels()".
3307 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3308 * ADC conversion on only 1 channel.
3309 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
3310 * @param ADCx ADC instance
3311 * @retval Returned value can be one of the following values:
3312 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3313 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3314 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3315 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3316 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3317 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3318 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3319 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3320 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3321 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3322 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3323 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3324 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3325 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3326 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3327 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3328 */
LL_ADC_REG_GetSequencerLength(ADC_TypeDef * ADCx)3329 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
3330 {
3331 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
3332 }
3333
3334 /**
3335 * @brief Set ADC group regular sequencer discontinuous mode:
3336 * sequence subdivided and scan conversions interrupted every selected
3337 * number of ranks.
3338 * @note It is not possible to enable both ADC group regular
3339 * continuous mode and sequencer discontinuous mode.
3340 * @note It is not possible to enable both ADC auto-injected mode
3341 * and ADC group regular sequencer discontinuous mode.
3342 * @note On this STM32 series, setting of this feature is conditioned to
3343 * ADC state:
3344 * ADC must be disabled or enabled without conversion on going
3345 * on group regular.
3346 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
3347 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
3348 * @param ADCx ADC instance
3349 * @param SeqDiscont This parameter can be one of the following values:
3350 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3351 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3352 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
3353 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
3354 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
3355 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
3356 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
3357 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
3358 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
3359 * @retval None
3360 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)3361 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
3362 {
3363 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
3364 }
3365
3366 /**
3367 * @brief Get ADC group regular sequencer discontinuous mode:
3368 * sequence subdivided and scan conversions interrupted every selected
3369 * number of ranks.
3370 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
3371 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
3372 * @param ADCx ADC instance
3373 * @retval Returned value can be one of the following values:
3374 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3375 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3376 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
3377 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
3378 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
3379 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
3380 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
3381 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
3382 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
3383 */
LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef * ADCx)3384 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
3385 {
3386 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
3387 }
3388
3389 /**
3390 * @brief Set ADC group regular sequence: channel on the selected
3391 * scan sequence rank.
3392 * @note This function performs configuration of:
3393 * - Channels ordering into each rank of scan sequence:
3394 * whatever channel can be placed into whatever rank.
3395 * @note On this STM32 series, ADC group regular sequencer is
3396 * fully configurable: sequencer length and each rank
3397 * affectation to a channel are configurable.
3398 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3399 * @note Depending on devices and packages, some channels may not be available.
3400 * Refer to device datasheet for channels availability.
3401 * @note On this STM32 series, to measure internal channels (VrefInt,
3402 * TempSensor, ...), measurement paths to internal channels must be
3403 * enabled separately.
3404 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3405 * @note On this STM32 series, setting of this feature is conditioned to
3406 * ADC state:
3407 * ADC must be disabled or enabled without conversion on going
3408 * on group regular.
3409 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
3410 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
3411 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
3412 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
3413 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
3414 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
3415 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
3416 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
3417 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
3418 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
3419 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
3420 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
3421 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
3422 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
3423 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
3424 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
3425 * @param ADCx ADC instance
3426 * @param Rank This parameter can be one of the following values:
3427 * @arg @ref LL_ADC_REG_RANK_1
3428 * @arg @ref LL_ADC_REG_RANK_2
3429 * @arg @ref LL_ADC_REG_RANK_3
3430 * @arg @ref LL_ADC_REG_RANK_4
3431 * @arg @ref LL_ADC_REG_RANK_5
3432 * @arg @ref LL_ADC_REG_RANK_6
3433 * @arg @ref LL_ADC_REG_RANK_7
3434 * @arg @ref LL_ADC_REG_RANK_8
3435 * @arg @ref LL_ADC_REG_RANK_9
3436 * @arg @ref LL_ADC_REG_RANK_10
3437 * @arg @ref LL_ADC_REG_RANK_11
3438 * @arg @ref LL_ADC_REG_RANK_12
3439 * @arg @ref LL_ADC_REG_RANK_13
3440 * @arg @ref LL_ADC_REG_RANK_14
3441 * @arg @ref LL_ADC_REG_RANK_15
3442 * @arg @ref LL_ADC_REG_RANK_16
3443 * @param Channel This parameter can be one of the following values:
3444 * @arg @ref LL_ADC_CHANNEL_0 (3)
3445 * @arg @ref LL_ADC_CHANNEL_1 (3)
3446 * @arg @ref LL_ADC_CHANNEL_2 (3)
3447 * @arg @ref LL_ADC_CHANNEL_3 (3)
3448 * @arg @ref LL_ADC_CHANNEL_4 (3)
3449 * @arg @ref LL_ADC_CHANNEL_5 (3)
3450 * @arg @ref LL_ADC_CHANNEL_6
3451 * @arg @ref LL_ADC_CHANNEL_7
3452 * @arg @ref LL_ADC_CHANNEL_8
3453 * @arg @ref LL_ADC_CHANNEL_9
3454 * @arg @ref LL_ADC_CHANNEL_10
3455 * @arg @ref LL_ADC_CHANNEL_11
3456 * @arg @ref LL_ADC_CHANNEL_12
3457 * @arg @ref LL_ADC_CHANNEL_13
3458 * @arg @ref LL_ADC_CHANNEL_14
3459 * @arg @ref LL_ADC_CHANNEL_15
3460 * @arg @ref LL_ADC_CHANNEL_16
3461 * @arg @ref LL_ADC_CHANNEL_17
3462 * @arg @ref LL_ADC_CHANNEL_18
3463 * @arg @ref LL_ADC_CHANNEL_19
3464 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3465 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
3466 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3467 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3468 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
3469 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
3470 *
3471 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
3472 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
3473 * Other channels are slow channels (conversion rate: refer to reference manual).
3474 * @retval None
3475 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)3476 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
3477 {
3478 /* Set bits with content of parameter "Channel" with bits position */
3479 /* in register and register position depending on parameter "Rank". */
3480 /* Parameters "Rank" and "Channel" are used with masks because containing */
3481 /* other bits reserved for other purpose. */
3482 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
3483
3484 MODIFY_REG(*preg,
3485 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
3486 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
3487 }
3488
3489 /**
3490 * @brief Get ADC group regular sequence: channel on the selected
3491 * scan sequence rank.
3492 * @note On this STM32 series, ADC group regular sequencer is
3493 * fully configurable: sequencer length and each rank
3494 * affectation to a channel are configurable.
3495 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3496 * @note Depending on devices and packages, some channels may not be available.
3497 * Refer to device datasheet for channels availability.
3498 * @note Usage of the returned channel number:
3499 * - To reinject this channel into another function LL_ADC_xxx:
3500 * the returned channel number is only partly formatted on definition
3501 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3502 * with parts of literals LL_ADC_CHANNEL_x or using
3503 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3504 * Then the selected literal LL_ADC_CHANNEL_x can be used
3505 * as parameter for another function.
3506 * - To get the channel number in decimal format:
3507 * process the returned value with the helper macro
3508 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3509 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
3510 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
3511 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
3512 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
3513 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
3514 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
3515 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
3516 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
3517 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
3518 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
3519 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
3520 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
3521 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
3522 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
3523 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
3524 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
3525 * @param ADCx ADC instance
3526 * @param Rank This parameter can be one of the following values:
3527 * @arg @ref LL_ADC_REG_RANK_1
3528 * @arg @ref LL_ADC_REG_RANK_2
3529 * @arg @ref LL_ADC_REG_RANK_3
3530 * @arg @ref LL_ADC_REG_RANK_4
3531 * @arg @ref LL_ADC_REG_RANK_5
3532 * @arg @ref LL_ADC_REG_RANK_6
3533 * @arg @ref LL_ADC_REG_RANK_7
3534 * @arg @ref LL_ADC_REG_RANK_8
3535 * @arg @ref LL_ADC_REG_RANK_9
3536 * @arg @ref LL_ADC_REG_RANK_10
3537 * @arg @ref LL_ADC_REG_RANK_11
3538 * @arg @ref LL_ADC_REG_RANK_12
3539 * @arg @ref LL_ADC_REG_RANK_13
3540 * @arg @ref LL_ADC_REG_RANK_14
3541 * @arg @ref LL_ADC_REG_RANK_15
3542 * @arg @ref LL_ADC_REG_RANK_16
3543 * @retval Returned value can be one of the following values:
3544 * @arg @ref LL_ADC_CHANNEL_0 (3)
3545 * @arg @ref LL_ADC_CHANNEL_1 (3)
3546 * @arg @ref LL_ADC_CHANNEL_2 (3)
3547 * @arg @ref LL_ADC_CHANNEL_3 (3)
3548 * @arg @ref LL_ADC_CHANNEL_4 (3)
3549 * @arg @ref LL_ADC_CHANNEL_5 (3)
3550 * @arg @ref LL_ADC_CHANNEL_6
3551 * @arg @ref LL_ADC_CHANNEL_7
3552 * @arg @ref LL_ADC_CHANNEL_8
3553 * @arg @ref LL_ADC_CHANNEL_9
3554 * @arg @ref LL_ADC_CHANNEL_10
3555 * @arg @ref LL_ADC_CHANNEL_11
3556 * @arg @ref LL_ADC_CHANNEL_12
3557 * @arg @ref LL_ADC_CHANNEL_13
3558 * @arg @ref LL_ADC_CHANNEL_14
3559 * @arg @ref LL_ADC_CHANNEL_15
3560 * @arg @ref LL_ADC_CHANNEL_16
3561 * @arg @ref LL_ADC_CHANNEL_17
3562 * @arg @ref LL_ADC_CHANNEL_18
3563 * @arg @ref LL_ADC_CHANNEL_19
3564 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3565 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
3566 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3567 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3568 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
3569 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
3570 *
3571 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
3572 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
3573 * Other channels are slow channels (conversion rate: refer to reference manual).\n
3574 * (1) For ADC channel read back from ADC register,
3575 * comparison with internal channel parameter to be done
3576 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3577 */
LL_ADC_REG_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)3578 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
3579 {
3580 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
3581
3582 return (uint32_t)((READ_BIT(*preg,
3583 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
3584 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
3585 );
3586 }
3587
3588 /**
3589 * @brief Set ADC continuous conversion mode on ADC group regular.
3590 * @note Description of ADC continuous conversion mode:
3591 * - single mode: one conversion per trigger
3592 * - continuous mode: after the first trigger, following
3593 * conversions launched successively automatically.
3594 * @note It is not possible to enable both ADC group regular
3595 * continuous mode and sequencer discontinuous mode.
3596 * @note On this STM32 series, setting of this feature is conditioned to
3597 * ADC state:
3598 * ADC must be disabled or enabled without conversion on going
3599 * on group regular.
3600 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
3601 * @param ADCx ADC instance
3602 * @param Continuous This parameter can be one of the following values:
3603 * @arg @ref LL_ADC_REG_CONV_SINGLE
3604 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3605 * @retval None
3606 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)3607 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
3608 {
3609 MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
3610 }
3611
3612 /**
3613 * @brief Get ADC continuous conversion mode on ADC group regular.
3614 * @note Description of ADC continuous conversion mode:
3615 * - single mode: one conversion per trigger
3616 * - continuous mode: after the first trigger, following
3617 * conversions launched successively automatically.
3618 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
3619 * @param ADCx ADC instance
3620 * @retval Returned value can be one of the following values:
3621 * @arg @ref LL_ADC_REG_CONV_SINGLE
3622 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3623 */
LL_ADC_REG_GetContinuousMode(ADC_TypeDef * ADCx)3624 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
3625 {
3626 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
3627 }
3628 /**
3629 * @brief Set ADC data transfer mode
3630 * @note Conversion data can be either:
3631 * - Available in Data Register
3632 * - Transferred by DMA in one shot mode
3633 * - Transferred by DMA in circular mode
3634 * - Transferred to DFSDM data register
3635 * @rmtoll CFGR DMNGT LL_ADC_REG_SetDataTransferMode
3636 * @param ADCx ADC instance
3637 * @param DataTransferMode This parameter can be one of the following values:
3638 * @arg @ref LL_ADC_REG_DR_TRANSFER
3639 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3640 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3641 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER
3642 * @retval None
3643 */
LL_ADC_REG_SetDataTransferMode(ADC_TypeDef * ADCx,uint32_t DataTransferMode)3644 __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)
3645 {
3646 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode);
3647 }
3648
3649
3650 /**
3651 * @brief Get ADC data transfer mode
3652 * @note Conversion data can be either:
3653 * - Available in Data Register
3654 * - Transferred by DMA in one shot mode
3655 * - Transferred by DMA in circular mode
3656 * - Transferred to DFSDM data register
3657 * @rmtoll CFGR DMNGT LL_ADC_REG_GetDataTransferMode
3658 * @param ADCx ADC instance
3659 * @retval Returned value can be one of the following values:
3660 * @arg @ref LL_ADC_REG_DR_TRANSFER
3661 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3662 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3663 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER
3664 */
LL_ADC_REG_GetDataTransferMode(ADC_TypeDef * ADCx)3665 __STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(ADC_TypeDef *ADCx)
3666 {
3667 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMNGT));
3668 }
3669
3670
3671 /**
3672 * @brief Set ADC group regular behavior in case of overrun:
3673 * data preserved or overwritten.
3674 * @note Compatibility with devices without feature overrun:
3675 * other devices without this feature have a behavior
3676 * equivalent to data overwritten.
3677 * The default setting of overrun is data preserved.
3678 * Therefore, for compatibility with all devices, parameter
3679 * overrun should be set to data overwritten.
3680 * @note On this STM32 series, setting of this feature is conditioned to
3681 * ADC state:
3682 * ADC must be disabled or enabled without conversion on going
3683 * on group regular.
3684 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
3685 * @param ADCx ADC instance
3686 * @param Overrun This parameter can be one of the following values:
3687 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3688 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3689 * @retval None
3690 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)3691 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
3692 {
3693 MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
3694 }
3695
3696 /**
3697 * @brief Get ADC group regular behavior in case of overrun:
3698 * data preserved or overwritten.
3699 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
3700 * @param ADCx ADC instance
3701 * @retval Returned value can be one of the following values:
3702 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3703 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3704 */
LL_ADC_REG_GetOverrun(ADC_TypeDef * ADCx)3705 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
3706 {
3707 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
3708 }
3709
3710 /**
3711 * @}
3712 */
3713
3714 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
3715 * @{
3716 */
3717
3718 /**
3719 * @brief Set ADC group injected conversion trigger source:
3720 * internal (SW start) or from external peripheral (timer event,
3721 * external interrupt line).
3722 * @note On this STM32 series, setting trigger source to external trigger
3723 * also set trigger polarity to rising edge
3724 * (default setting for compatibility with some ADC on other
3725 * STM32 families having this setting set by HW default value).
3726 * In case of need to modify trigger edge, use
3727 * function @ref LL_ADC_INJ_SetTriggerEdge().
3728 * @note Availability of parameters of trigger sources from timer
3729 * depends on timers availability on the selected device.
3730 * @note On this STM32 series, setting of this feature is conditioned to
3731 * ADC state:
3732 * ADC must not be disabled. Can be enabled with or without conversion
3733 * on going on either groups regular or injected.
3734 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
3735 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
3736 * @param ADCx ADC instance
3737 * @param TriggerSource This parameter can be one of the following values:
3738 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
3739 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
3740 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
3741 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
3742 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
3743 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
3744 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
3745 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
3746 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
3747 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
3748 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
3749 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
3750 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
3751 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
3752 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
3753 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
3754 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
3755 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT
3756 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT
3757 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT
3758 * @retval None
3759 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)3760 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3761 {
3762 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
3763 }
3764
3765 /**
3766 * @brief Get ADC group injected conversion trigger source:
3767 * internal (SW start) or from external peripheral (timer event,
3768 * external interrupt line).
3769 * @note To determine whether group injected trigger source is
3770 * internal (SW start) or external, without detail
3771 * of which peripheral is selected as external trigger,
3772 * (equivalent to
3773 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
3774 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
3775 * @note Availability of parameters of trigger sources from timer
3776 * depends on timers availability on the selected device.
3777 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
3778 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
3779 * @param ADCx ADC instance
3780 * @retval Returned value can be one of the following values:
3781 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
3782 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
3783 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
3784 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
3785 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
3786 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
3787 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
3788 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
3789 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
3790 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
3791 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
3792 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
3793 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
3794 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
3795 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
3796 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
3797 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
3798 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT
3799 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT
3800 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT
3801 */
LL_ADC_INJ_GetTriggerSource(ADC_TypeDef * ADCx)3802 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
3803 {
3804 __IO uint32_t trigger_source = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
3805
3806 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3807 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
3808 uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3809
3810 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
3811 /* to match with triggers literals definition. */
3812 return ((trigger_source
3813 & (ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) & ADC_JSQR_JEXTSEL)
3814 | ((ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN)
3815 );
3816 }
3817
3818 /**
3819 * @brief Get ADC group injected conversion trigger source internal (SW start)
3820 or external
3821 * @note In case of group injected trigger source set to external trigger,
3822 * to determine which peripheral is selected as external trigger,
3823 * use function @ref LL_ADC_INJ_GetTriggerSource.
3824 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
3825 * @param ADCx ADC instance
3826 * @retval Value "0" if trigger source external trigger
3827 * Value "1" if trigger source SW start.
3828 */
LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)3829 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
3830 {
3831 return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
3832 }
3833
3834 /**
3835 * @brief Set ADC group injected conversion trigger polarity.
3836 * Applicable only for trigger source set to external trigger.
3837 * @note On this STM32 series, setting of this feature is conditioned to
3838 * ADC state:
3839 * ADC must not be disabled. Can be enabled with or without conversion
3840 * on going on either groups regular or injected.
3841 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
3842 * @param ADCx ADC instance
3843 * @param ExternalTriggerEdge This parameter can be one of the following values:
3844 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
3845 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
3846 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
3847 * @retval None
3848 */
LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3849 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3850 {
3851 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
3852 }
3853
3854 /**
3855 * @brief Get ADC group injected conversion trigger polarity.
3856 * Applicable only for trigger source set to external trigger.
3857 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
3858 * @param ADCx ADC instance
3859 * @retval Returned value can be one of the following values:
3860 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
3861 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
3862 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
3863 */
LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef * ADCx)3864 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
3865 {
3866 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
3867 }
3868
3869 /**
3870 * @brief Set ADC group injected sequencer length and scan direction.
3871 * @note This function performs configuration of:
3872 * - Sequence length: Number of ranks in the scan sequence.
3873 * - Sequence direction: Unless specified in parameters, sequencer
3874 * scan direction is forward (from rank 1 to rank n).
3875 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3876 * ADC conversion on only 1 channel.
3877 * @note On this STM32 series, setting of this feature is conditioned to
3878 * ADC state:
3879 * ADC must not be disabled. Can be enabled with or without conversion
3880 * on going on either groups regular or injected.
3881 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
3882 * @param ADCx ADC instance
3883 * @param SequencerNbRanks This parameter can be one of the following values:
3884 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
3885 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
3886 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
3887 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
3888 * @retval None
3889 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)3890 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
3891 {
3892 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
3893 }
3894
3895 /**
3896 * @brief Get ADC group injected sequencer length and scan direction.
3897 * @note This function retrieves:
3898 * - Sequence length: Number of ranks in the scan sequence.
3899 * - Sequence direction: Unless specified in parameters, sequencer
3900 * scan direction is forward (from rank 1 to rank n).
3901 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3902 * ADC conversion on only 1 channel.
3903 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
3904 * @param ADCx ADC instance
3905 * @retval Returned value can be one of the following values:
3906 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
3907 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
3908 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
3909 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
3910 */
LL_ADC_INJ_GetSequencerLength(ADC_TypeDef * ADCx)3911 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
3912 {
3913 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
3914 }
3915
3916 /**
3917 * @brief Set ADC group injected sequencer discontinuous mode:
3918 * sequence subdivided and scan conversions interrupted every selected
3919 * number of ranks.
3920 * @note It is not possible to enable both ADC group injected
3921 * auto-injected mode and sequencer discontinuous mode.
3922 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
3923 * @param ADCx ADC instance
3924 * @param SeqDiscont This parameter can be one of the following values:
3925 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
3926 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
3927 * @retval None
3928 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)3929 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
3930 {
3931 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
3932 }
3933
3934 /**
3935 * @brief Get ADC group injected sequencer discontinuous mode:
3936 * sequence subdivided and scan conversions interrupted every selected
3937 * number of ranks.
3938 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
3939 * @param ADCx ADC instance
3940 * @retval Returned value can be one of the following values:
3941 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
3942 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
3943 */
LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef * ADCx)3944 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
3945 {
3946 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
3947 }
3948
3949 /**
3950 * @brief Set ADC group injected sequence: channel on the selected
3951 * sequence rank.
3952 * @note Depending on devices and packages, some channels may not be available.
3953 * Refer to device datasheet for channels availability.
3954 * @note On this STM32 series, to measure internal channels (VrefInt,
3955 * TempSensor, ...), measurement paths to internal channels must be
3956 * enabled separately.
3957 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3958 * @note On STM32MP1, some fast channels are available: fast analog inputs
3959 * coming from GPIO pads (ADC_IN0..5).
3960 * @note On this STM32 series, setting of this feature is conditioned to
3961 * ADC state:
3962 * ADC must not be disabled. Can be enabled with or without conversion
3963 * on going on either groups regular or injected.
3964 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
3965 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
3966 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
3967 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
3968 * @param ADCx ADC instance
3969 * @param Rank This parameter can be one of the following values:
3970 * @arg @ref LL_ADC_INJ_RANK_1
3971 * @arg @ref LL_ADC_INJ_RANK_2
3972 * @arg @ref LL_ADC_INJ_RANK_3
3973 * @arg @ref LL_ADC_INJ_RANK_4
3974 * @param Channel This parameter can be one of the following values:
3975 * @arg @ref LL_ADC_CHANNEL_0 (3)
3976 * @arg @ref LL_ADC_CHANNEL_1 (3)
3977 * @arg @ref LL_ADC_CHANNEL_2 (3)
3978 * @arg @ref LL_ADC_CHANNEL_3 (3)
3979 * @arg @ref LL_ADC_CHANNEL_4 (3)
3980 * @arg @ref LL_ADC_CHANNEL_5 (3)
3981 * @arg @ref LL_ADC_CHANNEL_6
3982 * @arg @ref LL_ADC_CHANNEL_7
3983 * @arg @ref LL_ADC_CHANNEL_8
3984 * @arg @ref LL_ADC_CHANNEL_9
3985 * @arg @ref LL_ADC_CHANNEL_10
3986 * @arg @ref LL_ADC_CHANNEL_11
3987 * @arg @ref LL_ADC_CHANNEL_12
3988 * @arg @ref LL_ADC_CHANNEL_13
3989 * @arg @ref LL_ADC_CHANNEL_14
3990 * @arg @ref LL_ADC_CHANNEL_15
3991 * @arg @ref LL_ADC_CHANNEL_16
3992 * @arg @ref LL_ADC_CHANNEL_17
3993 * @arg @ref LL_ADC_CHANNEL_18
3994 * @arg @ref LL_ADC_CHANNEL_19
3995 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3996 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
3997 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
3998 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3999 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
4000 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
4001 *
4002 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
4003 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4004 * Other channels are slow channels (conversion rate: refer to reference manual).
4005 * @retval None
4006 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4007 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4008 {
4009 /* Set bits with content of parameter "Channel" with bits position */
4010 /* in register depending on parameter "Rank". */
4011 /* Parameters "Rank" and "Channel" are used with masks because containing */
4012 /* other bits reserved for other purpose. */
4013 MODIFY_REG(ADCx->JSQR,
4014 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
4015 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
4016 }
4017
4018 /**
4019 * @brief Get ADC group injected sequence: channel on the selected
4020 * sequence rank.
4021 * @note Depending on devices and packages, some channels may not be available.
4022 * Refer to device datasheet for channels availability.
4023 * @note Usage of the returned channel number:
4024 * - To reinject this channel into another function LL_ADC_xxx:
4025 * the returned channel number is only partly formatted on definition
4026 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4027 * with parts of literals LL_ADC_CHANNEL_x or using
4028 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4029 * Then the selected literal LL_ADC_CHANNEL_x can be used
4030 * as parameter for another function.
4031 * - To get the channel number in decimal format:
4032 * process the returned value with the helper macro
4033 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4034 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
4035 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
4036 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
4037 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
4038 * @param ADCx ADC instance
4039 * @param Rank This parameter can be one of the following values:
4040 * @arg @ref LL_ADC_INJ_RANK_1
4041 * @arg @ref LL_ADC_INJ_RANK_2
4042 * @arg @ref LL_ADC_INJ_RANK_3
4043 * @arg @ref LL_ADC_INJ_RANK_4
4044 * @retval Returned value can be one of the following values:
4045 * @arg @ref LL_ADC_CHANNEL_0 (3)
4046 * @arg @ref LL_ADC_CHANNEL_1 (3)
4047 * @arg @ref LL_ADC_CHANNEL_2 (3)
4048 * @arg @ref LL_ADC_CHANNEL_3 (3)
4049 * @arg @ref LL_ADC_CHANNEL_4 (3)
4050 * @arg @ref LL_ADC_CHANNEL_5 (3)
4051 * @arg @ref LL_ADC_CHANNEL_6
4052 * @arg @ref LL_ADC_CHANNEL_7
4053 * @arg @ref LL_ADC_CHANNEL_8
4054 * @arg @ref LL_ADC_CHANNEL_9
4055 * @arg @ref LL_ADC_CHANNEL_10
4056 * @arg @ref LL_ADC_CHANNEL_11
4057 * @arg @ref LL_ADC_CHANNEL_12
4058 * @arg @ref LL_ADC_CHANNEL_13
4059 * @arg @ref LL_ADC_CHANNEL_14
4060 * @arg @ref LL_ADC_CHANNEL_15
4061 * @arg @ref LL_ADC_CHANNEL_16
4062 * @arg @ref LL_ADC_CHANNEL_17
4063 * @arg @ref LL_ADC_CHANNEL_18
4064 * @arg @ref LL_ADC_CHANNEL_19
4065 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4066 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
4067 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4068 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4069 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
4070 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
4071 *
4072 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
4073 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4074 * Other channels are slow channels (conversion rate: refer to reference manual).\n
4075 * (1) For ADC channel read back from ADC register,
4076 * comparison with internal channel parameter to be done
4077 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4078 */
LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)4079 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
4080 {
4081 return (uint32_t)((READ_BIT(ADCx->JSQR,
4082 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
4083 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4084 );
4085 }
4086
4087 /**
4088 * @brief Set ADC group injected conversion trigger:
4089 * independent or from ADC group regular.
4090 * @note This mode can be used to extend number of data registers
4091 * updated after one ADC conversion trigger and with data
4092 * permanently kept (not erased by successive conversions of scan of
4093 * ADC sequencer ranks), up to 5 data registers:
4094 * 1 data register on ADC group regular, 4 data registers
4095 * on ADC group injected.
4096 * @note If ADC group injected injected trigger source is set to an
4097 * external trigger, this feature must be must be set to
4098 * independent trigger.
4099 * ADC group injected automatic trigger is compliant only with
4100 * group injected trigger source set to SW start, without any
4101 * further action on ADC group injected conversion start or stop:
4102 * in this case, ADC group injected is controlled only
4103 * from ADC group regular.
4104 * @note It is not possible to enable both ADC group injected
4105 * auto-injected mode and sequencer discontinuous mode.
4106 * @note On this STM32 series, setting of this feature is conditioned to
4107 * ADC state:
4108 * ADC must be disabled or enabled without conversion on going
4109 * on either groups regular or injected.
4110 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
4111 * @param ADCx ADC instance
4112 * @param TrigAuto This parameter can be one of the following values:
4113 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4114 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4115 * @retval None
4116 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)4117 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
4118 {
4119 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
4120 }
4121
4122 /**
4123 * @brief Get ADC group injected conversion trigger:
4124 * independent or from ADC group regular.
4125 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
4126 * @param ADCx ADC instance
4127 * @retval Returned value can be one of the following values:
4128 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4129 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4130 */
LL_ADC_INJ_GetTrigAuto(ADC_TypeDef * ADCx)4131 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
4132 {
4133 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
4134 }
4135
4136 /**
4137 * @brief Set ADC group injected contexts queue mode.
4138 * @note A context is a setting of group injected sequencer:
4139 * - group injected trigger
4140 * - sequencer length
4141 * - sequencer ranks
4142 * If contexts queue is disabled:
4143 * - only 1 sequence can be configured
4144 * and is active perpetually.
4145 * If contexts queue is enabled:
4146 * - up to 2 contexts can be queued
4147 * and are checked in and out as a FIFO stack (first-in, first-out).
4148 * - If a new context is set when queues is full, error is triggered
4149 * by interruption "Injected Queue Overflow".
4150 * - Two behaviors are possible when all contexts have been processed:
4151 * the contexts queue can maintain the last context active perpetually
4152 * or can be empty and injected group triggers are disabled.
4153 * - Triggers can be only external (not internal SW start)
4154 * - Caution: The sequence must be fully configured in one time
4155 * (one write of register JSQR makes a check-in of a new context
4156 * into the queue).
4157 * Therefore functions to set separately injected trigger and
4158 * sequencer channels cannot be used, register JSQR must be set
4159 * using function @ref LL_ADC_INJ_ConfigQueueContext().
4160 * @note This parameter can be modified only when no conversion is on going
4161 * on either groups regular or injected.
4162 * @note A modification of the context mode (bit JQDIS) causes the contexts
4163 * queue to be flushed and the register JSQR is cleared.
4164 * @note On this STM32 series, setting of this feature is conditioned to
4165 * ADC state:
4166 * ADC must be disabled or enabled without conversion on going
4167 * on either groups regular or injected.
4168 * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
4169 * CFGR JQDIS LL_ADC_INJ_SetQueueMode
4170 * @param ADCx ADC instance
4171 * @param QueueMode This parameter can be one of the following values:
4172 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
4173 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4174 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4175 * @retval None
4176 */
LL_ADC_INJ_SetQueueMode(ADC_TypeDef * ADCx,uint32_t QueueMode)4177 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
4178 {
4179 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
4180 }
4181
4182 /**
4183 * @brief Get ADC group injected context queue mode.
4184 * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
4185 * CFGR JQDIS LL_ADC_INJ_GetQueueMode
4186 * @param ADCx ADC instance
4187 * @retval Returned value can be one of the following values:
4188 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
4189 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4190 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4191 */
LL_ADC_INJ_GetQueueMode(ADC_TypeDef * ADCx)4192 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
4193 {
4194 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
4195 }
4196
4197 /**
4198 * @brief Set one context on ADC group injected that will be checked in
4199 * contexts queue.
4200 * @note A context is a setting of group injected sequencer:
4201 * - group injected trigger
4202 * - sequencer length
4203 * - sequencer ranks
4204 * This function is intended to be used when contexts queue is enabled,
4205 * because the sequence must be fully configured in one time
4206 * (functions to set separately injected trigger and sequencer channels
4207 * cannot be used):
4208 * Refer to function @ref LL_ADC_INJ_SetQueueMode().
4209 * @note In the contexts queue, only the active context can be read.
4210 * The parameters of this function can be read using functions:
4211 * @arg @ref LL_ADC_INJ_GetTriggerSource()
4212 * @arg @ref LL_ADC_INJ_GetTriggerEdge()
4213 * @arg @ref LL_ADC_INJ_GetSequencerRanks()
4214 * @note On this STM32 series, to measure internal channels (VrefInt,
4215 * TempSensor, ...), measurement paths to internal channels must be
4216 * enabled separately.
4217 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4218 * @note On STM32MP1, some fast channels are available: fast analog inputs
4219 * coming from GPIO pads (ADC_IN0..5).
4220 * @note On this STM32 series, setting of this feature is conditioned to
4221 * ADC state:
4222 * ADC must not be disabled. Can be enabled with or without conversion
4223 * on going on either groups regular or injected.
4224 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
4225 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
4226 * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
4227 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
4228 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
4229 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
4230 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
4231 * @param ADCx ADC instance
4232 * @param TriggerSource This parameter can be one of the following values:
4233 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4234 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4235 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4236 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4237 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4238 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4239 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4240 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4241 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4242 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4243 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4244 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4245 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4246 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4247 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
4248 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4249 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4250 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT
4251 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT
4252 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT
4253 * @param ExternalTriggerEdge This parameter can be one of the following values:
4254 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4255 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4256 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4257 *
4258 * Note: This parameter is discarded in case of SW start:
4259 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
4260 * @param SequencerNbRanks This parameter can be one of the following values:
4261 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4262 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4263 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4264 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4265 * @param Rank1_Channel This parameter can be one of the following values:
4266 * @arg @ref LL_ADC_CHANNEL_0 (3)
4267 * @arg @ref LL_ADC_CHANNEL_1 (3)
4268 * @arg @ref LL_ADC_CHANNEL_2 (3)
4269 * @arg @ref LL_ADC_CHANNEL_3 (3)
4270 * @arg @ref LL_ADC_CHANNEL_4 (3)
4271 * @arg @ref LL_ADC_CHANNEL_5 (3)
4272 * @arg @ref LL_ADC_CHANNEL_6
4273 * @arg @ref LL_ADC_CHANNEL_7
4274 * @arg @ref LL_ADC_CHANNEL_8
4275 * @arg @ref LL_ADC_CHANNEL_9
4276 * @arg @ref LL_ADC_CHANNEL_10
4277 * @arg @ref LL_ADC_CHANNEL_11
4278 * @arg @ref LL_ADC_CHANNEL_12
4279 * @arg @ref LL_ADC_CHANNEL_13
4280 * @arg @ref LL_ADC_CHANNEL_14
4281 * @arg @ref LL_ADC_CHANNEL_15
4282 * @arg @ref LL_ADC_CHANNEL_16
4283 * @arg @ref LL_ADC_CHANNEL_17
4284 * @arg @ref LL_ADC_CHANNEL_18
4285 * @arg @ref LL_ADC_CHANNEL_19
4286 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4287 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
4288 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4289 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4290 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
4291 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
4292 *
4293 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
4294 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4295 * Other channels are slow channels (conversion rate: refer to reference manual).
4296 * @param Rank2_Channel This parameter can be one of the following values:
4297 * @arg @ref LL_ADC_CHANNEL_0 (3)
4298 * @arg @ref LL_ADC_CHANNEL_1 (3)
4299 * @arg @ref LL_ADC_CHANNEL_2 (3)
4300 * @arg @ref LL_ADC_CHANNEL_3 (3)
4301 * @arg @ref LL_ADC_CHANNEL_4 (3)
4302 * @arg @ref LL_ADC_CHANNEL_5 (3)
4303 * @arg @ref LL_ADC_CHANNEL_6
4304 * @arg @ref LL_ADC_CHANNEL_7
4305 * @arg @ref LL_ADC_CHANNEL_8
4306 * @arg @ref LL_ADC_CHANNEL_9
4307 * @arg @ref LL_ADC_CHANNEL_10
4308 * @arg @ref LL_ADC_CHANNEL_11
4309 * @arg @ref LL_ADC_CHANNEL_12
4310 * @arg @ref LL_ADC_CHANNEL_13
4311 * @arg @ref LL_ADC_CHANNEL_14
4312 * @arg @ref LL_ADC_CHANNEL_15
4313 * @arg @ref LL_ADC_CHANNEL_16
4314 * @arg @ref LL_ADC_CHANNEL_17
4315 * @arg @ref LL_ADC_CHANNEL_18
4316 * @arg @ref LL_ADC_CHANNEL_19
4317 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4318 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
4319 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4320 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4321 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
4322 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
4323 *
4324 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
4325 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4326 * Other channels are slow channels (conversion rate: refer to reference manual).
4327 * @param Rank3_Channel This parameter can be one of the following values:
4328 * @arg @ref LL_ADC_CHANNEL_0 (3)
4329 * @arg @ref LL_ADC_CHANNEL_1 (3)
4330 * @arg @ref LL_ADC_CHANNEL_2 (3)
4331 * @arg @ref LL_ADC_CHANNEL_3 (3)
4332 * @arg @ref LL_ADC_CHANNEL_4 (3)
4333 * @arg @ref LL_ADC_CHANNEL_5 (3)
4334 * @arg @ref LL_ADC_CHANNEL_6
4335 * @arg @ref LL_ADC_CHANNEL_7
4336 * @arg @ref LL_ADC_CHANNEL_8
4337 * @arg @ref LL_ADC_CHANNEL_9
4338 * @arg @ref LL_ADC_CHANNEL_10
4339 * @arg @ref LL_ADC_CHANNEL_11
4340 * @arg @ref LL_ADC_CHANNEL_12
4341 * @arg @ref LL_ADC_CHANNEL_13
4342 * @arg @ref LL_ADC_CHANNEL_14
4343 * @arg @ref LL_ADC_CHANNEL_15
4344 * @arg @ref LL_ADC_CHANNEL_16
4345 * @arg @ref LL_ADC_CHANNEL_17
4346 * @arg @ref LL_ADC_CHANNEL_18
4347 * @arg @ref LL_ADC_CHANNEL_19
4348 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4349 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
4350 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4351 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4352 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
4353 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
4354 *
4355 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
4356 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4357 * Other channels are slow channels (conversion rate: refer to reference manual).
4358 * @param Rank4_Channel This parameter can be one of the following values:
4359 * @arg @ref LL_ADC_CHANNEL_0 (3)
4360 * @arg @ref LL_ADC_CHANNEL_1 (3)
4361 * @arg @ref LL_ADC_CHANNEL_2 (3)
4362 * @arg @ref LL_ADC_CHANNEL_3 (3)
4363 * @arg @ref LL_ADC_CHANNEL_4 (3)
4364 * @arg @ref LL_ADC_CHANNEL_5 (3)
4365 * @arg @ref LL_ADC_CHANNEL_6
4366 * @arg @ref LL_ADC_CHANNEL_7
4367 * @arg @ref LL_ADC_CHANNEL_8
4368 * @arg @ref LL_ADC_CHANNEL_9
4369 * @arg @ref LL_ADC_CHANNEL_10
4370 * @arg @ref LL_ADC_CHANNEL_11
4371 * @arg @ref LL_ADC_CHANNEL_12
4372 * @arg @ref LL_ADC_CHANNEL_13
4373 * @arg @ref LL_ADC_CHANNEL_14
4374 * @arg @ref LL_ADC_CHANNEL_15
4375 * @arg @ref LL_ADC_CHANNEL_16
4376 * @arg @ref LL_ADC_CHANNEL_17
4377 * @arg @ref LL_ADC_CHANNEL_18
4378 * @arg @ref LL_ADC_CHANNEL_19
4379 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4380 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
4381 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4382 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4383 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
4384 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
4385 *
4386 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
4387 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4388 * Other channels are slow channels (conversion rate: refer to reference manual).
4389 * @retval None
4390 */
LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef * ADCx,uint32_t TriggerSource,uint32_t ExternalTriggerEdge,uint32_t SequencerNbRanks,uint32_t Rank1_Channel,uint32_t Rank2_Channel,uint32_t Rank3_Channel,uint32_t Rank4_Channel)4391 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
4392 uint32_t TriggerSource,
4393 uint32_t ExternalTriggerEdge,
4394 uint32_t SequencerNbRanks,
4395 uint32_t Rank1_Channel,
4396 uint32_t Rank2_Channel,
4397 uint32_t Rank3_Channel,
4398 uint32_t Rank4_Channel)
4399 {
4400 /* Set bits with content of parameter "Rankx_Channel" with bits position */
4401 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
4402 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
4403 /* because containing other bits reserved for other purpose. */
4404 /* If parameter "TriggerSource" is set to SW start, then parameter */
4405 /* "ExternalTriggerEdge" is discarded. */
4406 uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
4407 MODIFY_REG(ADCx->JSQR,
4408 ADC_JSQR_JEXTSEL |
4409 ADC_JSQR_JEXTEN |
4410 ADC_JSQR_JSQ4 |
4411 ADC_JSQR_JSQ3 |
4412 ADC_JSQR_JSQ2 |
4413 ADC_JSQR_JSQ1 |
4414 ADC_JSQR_JL,
4415 (TriggerSource & ADC_JSQR_JEXTSEL) |
4416 (ExternalTriggerEdge * (is_trigger_not_sw)) |
4417 (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4418 (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4419 (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4420 (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4421 SequencerNbRanks
4422 );
4423 }
4424
4425 /**
4426 * @}
4427 */
4428
4429 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
4430 * @{
4431 */
4432
4433 /**
4434 * @brief Set sampling time of the selected ADC channel
4435 * Unit: ADC clock cycles.
4436 * @note On this device, sampling time is on channel scope: independently
4437 * of channel mapped on ADC group regular or injected.
4438 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
4439 * converted:
4440 * sampling time constraints must be respected (sampling time can be
4441 * adjusted in function of ADC clock frequency and sampling time
4442 * setting).
4443 * Refer to device datasheet for timings values (parameters TS_vrefint,
4444 * TS_temp, ...).
4445 * @note Conversion time is the addition of sampling time and processing time.
4446 * On this STM32 series, ADC processing time is:
4447 * - 12.5 ADC clock cycles at ADC resolution 12 bits
4448 * - 10.5 ADC clock cycles at ADC resolution 10 bits
4449 * - 8.5 ADC clock cycles at ADC resolution 8 bits
4450 * - 6.5 ADC clock cycles at ADC resolution 6 bits
4451 * @note In case of ADC conversion of internal channel (VrefInt,
4452 * temperature sensor, ...), a sampling time minimum value
4453 * is required.
4454 * Refer to device datasheet.
4455 * @note On this STM32 series, setting of this feature is conditioned to
4456 * ADC state:
4457 * ADC must be disabled or enabled without conversion on going
4458 * on either groups regular or injected.
4459 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
4460 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
4461 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
4462 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
4463 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
4464 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
4465 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
4466 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
4467 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
4468 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
4469 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
4470 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
4471 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
4472 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
4473 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
4474 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
4475 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
4476 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
4477 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
4478 * @param ADCx ADC instance
4479 * @param Channel This parameter can be one of the following values:
4480 * @arg @ref LL_ADC_CHANNEL_0 (3)
4481 * @arg @ref LL_ADC_CHANNEL_1 (3)
4482 * @arg @ref LL_ADC_CHANNEL_2 (3)
4483 * @arg @ref LL_ADC_CHANNEL_3 (3)
4484 * @arg @ref LL_ADC_CHANNEL_4 (3)
4485 * @arg @ref LL_ADC_CHANNEL_5 (3)
4486 * @arg @ref LL_ADC_CHANNEL_6
4487 * @arg @ref LL_ADC_CHANNEL_7
4488 * @arg @ref LL_ADC_CHANNEL_8
4489 * @arg @ref LL_ADC_CHANNEL_9
4490 * @arg @ref LL_ADC_CHANNEL_10
4491 * @arg @ref LL_ADC_CHANNEL_11
4492 * @arg @ref LL_ADC_CHANNEL_12
4493 * @arg @ref LL_ADC_CHANNEL_13
4494 * @arg @ref LL_ADC_CHANNEL_14
4495 * @arg @ref LL_ADC_CHANNEL_15
4496 * @arg @ref LL_ADC_CHANNEL_16
4497 * @arg @ref LL_ADC_CHANNEL_17
4498 * @arg @ref LL_ADC_CHANNEL_18
4499 * @arg @ref LL_ADC_CHANNEL_19
4500 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4501 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
4502 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4503 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4504 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
4505 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
4506 *
4507 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
4508 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4509 * Other channels are slow channels (conversion rate: refer to reference manual).
4510 * @param SamplingTime This parameter can be one of the following values:
4511 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
4512 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
4513 * @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES_5
4514 * @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES_5
4515 * @arg @ref LL_ADC_SAMPLINGTIME_32CYCLES_5
4516 * @arg @ref LL_ADC_SAMPLINGTIME_64CYCLES_5
4517 * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5
4518 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5
4519 * @retval None
4520 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)4521 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
4522 {
4523 /* Set bits with content of parameter "SamplingTime" with bits position */
4524 /* in register and register position depending on parameter "Channel". */
4525 /* Parameter "Channel" is used with masks because containing */
4526 /* other bits reserved for other purpose. */
4527 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
4528
4529 MODIFY_REG(*preg,
4530 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
4531 SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
4532 }
4533
4534 /**
4535 * @brief Get sampling time of the selected ADC channel
4536 * Unit: ADC clock cycles.
4537 * @note On this device, sampling time is on channel scope: independently
4538 * of channel mapped on ADC group regular or injected.
4539 * @note Conversion time is the addition of sampling time and processing time.
4540 * On this STM32 series, ADC processing time is:
4541 * - 12.5 ADC clock cycles at ADC resolution 12 bits
4542 * - 10.5 ADC clock cycles at ADC resolution 10 bits
4543 * - 8.5 ADC clock cycles at ADC resolution 8 bits
4544 * - 6.5 ADC clock cycles at ADC resolution 6 bits
4545 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
4546 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
4547 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
4548 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
4549 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
4550 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
4551 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
4552 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
4553 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
4554 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
4555 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
4556 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
4557 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
4558 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
4559 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
4560 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
4561 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
4562 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
4563 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
4564 * @param ADCx ADC instance
4565 * @param Channel This parameter can be one of the following values:
4566 * @arg @ref LL_ADC_CHANNEL_0 (3)
4567 * @arg @ref LL_ADC_CHANNEL_1 (3)
4568 * @arg @ref LL_ADC_CHANNEL_2 (3)
4569 * @arg @ref LL_ADC_CHANNEL_3 (3)
4570 * @arg @ref LL_ADC_CHANNEL_4 (3)
4571 * @arg @ref LL_ADC_CHANNEL_5 (3)
4572 * @arg @ref LL_ADC_CHANNEL_6
4573 * @arg @ref LL_ADC_CHANNEL_7
4574 * @arg @ref LL_ADC_CHANNEL_8
4575 * @arg @ref LL_ADC_CHANNEL_9
4576 * @arg @ref LL_ADC_CHANNEL_10
4577 * @arg @ref LL_ADC_CHANNEL_11
4578 * @arg @ref LL_ADC_CHANNEL_12
4579 * @arg @ref LL_ADC_CHANNEL_13
4580 * @arg @ref LL_ADC_CHANNEL_14
4581 * @arg @ref LL_ADC_CHANNEL_15
4582 * @arg @ref LL_ADC_CHANNEL_16
4583 * @arg @ref LL_ADC_CHANNEL_17
4584 * @arg @ref LL_ADC_CHANNEL_18
4585 * @arg @ref LL_ADC_CHANNEL_19
4586 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4587 * @arg @ref LL_ADC_CHANNEL_VCORE (1)
4588 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
4589 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
4590 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (1)
4591 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (1)
4592 *
4593 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
4594 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
4595 * Other channels are slow channels (conversion rate: refer to reference manual).
4596 * @retval Returned value can be one of the following values:
4597 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
4598 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
4599 * @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES_5
4600 * @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES_5
4601 * @arg @ref LL_ADC_SAMPLINGTIME_32CYCLES_5
4602 * @arg @ref LL_ADC_SAMPLINGTIME_64CYCLES_5
4603 * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5
4604 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5
4605 */
LL_ADC_GetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel)4606 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
4607 {
4608 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
4609
4610 return (uint32_t)(READ_BIT(*preg,
4611 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
4612 >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
4613 );
4614 }
4615
4616 /**
4617 * @brief Set mode single-ended or differential input of the selected
4618 * ADC channel.
4619 * @note Channel ending is on channel scope: independently of channel mapped
4620 * on ADC group regular or injected.
4621 * In differential mode: Differential measurement is carried out
4622 * between the selected channel 'i' (positive input) and
4623 * channel 'i+1' (negative input). Only channel 'i' has to be
4624 * configured, channel 'i+1' is configured automatically.
4625 * @note Refer to Reference Manual to ensure the selected channel is
4626 * available in differential mode.
4627 * For example, internal channels (VrefInt, TempSensor, ...) are
4628 * not available in differential mode.
4629 * @note When configuring a channel 'i' in differential mode,
4630 * the channel 'i+1' is not usable separately.
4631 * @note On STM32MP1, some channels are internally fixed to single-ended inputs
4632 * configuration:
4633 * - ADC1: Channels 0, 6, 7, 8, 9, 14, 15, 16, 17, 19
4634 * - ADC2: Channels 0, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 19
4635 * @note For ADC channels configured in differential mode, both inputs
4636 * should be biased at (Vref+)/2 +/-200mV.
4637 * (Vref+ is the analog voltage reference)
4638 * @note On this STM32 series, setting of this feature is conditioned to
4639 * ADC state:
4640 * ADC must be ADC disabled.
4641 * @note One or several values can be selected.
4642 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
4643 * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
4644 * @param ADCx ADC instance
4645 * @param Channel This parameter can be one of the following values:
4646 * @arg @ref LL_ADC_CHANNEL_1
4647 * @arg @ref LL_ADC_CHANNEL_2
4648 * @arg @ref LL_ADC_CHANNEL_3
4649 * @arg @ref LL_ADC_CHANNEL_4
4650 * @arg @ref LL_ADC_CHANNEL_5
4651 * @arg @ref LL_ADC_CHANNEL_10
4652 * @arg @ref LL_ADC_CHANNEL_11
4653 * @arg @ref LL_ADC_CHANNEL_12
4654 * @arg @ref LL_ADC_CHANNEL_13
4655 * @param SingleDiff This parameter can be a combination of the following values:
4656 * @arg @ref LL_ADC_SINGLE_ENDED
4657 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
4658 * @retval None
4659 */
LL_ADC_SetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SingleDiff)4660 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
4661 {
4662 /* Bits of channels in single or differential mode are set only for */
4663 /* differential mode (for single mode, mask of bits allowed to be set is */
4664 /* shifted out of range of bits of channels in single or differential mode. */
4665 MODIFY_REG(ADCx->DIFSEL,
4666 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
4667 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
4668 }
4669
4670 /**
4671 * @brief Get mode single-ended or differential input of the selected
4672 * ADC channel.
4673 * @note When configuring a channel 'i' in differential mode,
4674 * the channel 'i+1' is not usable separately.
4675 * Therefore, to ensure a channel is configured in single-ended mode,
4676 * the configuration of channel itself and the channel 'i-1' must be
4677 * read back (to ensure that the selected channel channel has not been
4678 * configured in differential mode by the previous channel).
4679 * @note Refer to Reference Manual to ensure the selected channel is
4680 * available in differential mode.
4681 * For example, internal channels (VrefInt, TempSensor, ...) are
4682 * not available in differential mode.
4683 * @note When configuring a channel 'i' in differential mode,
4684 * the channel 'i+1' is not usable separately.
4685 * @note On STM32MP1, some channels are internally fixed to single-ended inputs
4686 * configuration:
4687 * - ADC1: Channels 0, 6, 7, 8, 9, 14, 15, 16, 17, 19
4688 * - ADC2: Channels 0, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 19
4689 * @note One or several values can be selected. In this case, the value
4690 * returned is null if all channels are in single ended-mode.
4691 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
4692 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
4693 * @param ADCx ADC instance
4694 * @param Channel This parameter can be a combination of the following values:
4695 * @arg @ref LL_ADC_CHANNEL_1
4696 * @arg @ref LL_ADC_CHANNEL_2
4697 * @arg @ref LL_ADC_CHANNEL_3
4698 * @arg @ref LL_ADC_CHANNEL_4
4699 * @arg @ref LL_ADC_CHANNEL_5
4700 * @arg @ref LL_ADC_CHANNEL_10
4701 * @arg @ref LL_ADC_CHANNEL_11
4702 * @arg @ref LL_ADC_CHANNEL_12
4703 * @arg @ref LL_ADC_CHANNEL_13
4704 * @retval 0: channel in single-ended mode, else: channel in differential mode
4705 */
LL_ADC_GetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel)4706 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
4707 {
4708 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
4709 }
4710
4711 /**
4712 * @}
4713 */
4714
4715 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
4716 * @{
4717 */
4718
4719 /**
4720 * @brief Set ADC analog watchdog monitored channels:
4721 * a single channel, multiple channels or all channels,
4722 * on ADC groups regular and-or injected.
4723 * @note Once monitored channels are selected, analog watchdog
4724 * is enabled.
4725 * @note In case of need to define a single channel to monitor
4726 * with analog watchdog from sequencer channel definition,
4727 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
4728 * @note On this STM32 series, there are 2 kinds of analog watchdog
4729 * instance:
4730 * - AWD standard (instance AWD1):
4731 * - channels monitored: can monitor 1 channel or all channels.
4732 * - groups monitored: ADC groups regular and-or injected.
4733 * - resolution: resolution is not limited (corresponds to
4734 * ADC resolution configured).
4735 * - AWD flexible (instances AWD2, AWD3):
4736 * - channels monitored: flexible on channels monitored, selection is
4737 * channel wise, from from 1 to all channels.
4738 * Specificity of this analog watchdog: Multiple channels can
4739 * be selected. For example:
4740 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
4741 * - groups monitored: not selection possible (monitoring on both
4742 * groups regular and injected).
4743 * Channels selected are monitored on groups regular and injected:
4744 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
4745 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
4746 * - resolution: resolution is limited to 8 bits: if ADC resolution is
4747 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
4748 * the 2 LSB are ignored.
4749 * @note On this STM32 series, setting of this feature is conditioned to
4750 * ADC state:
4751 * ADC must be disabled or enabled without conversion on going
4752 * on either groups regular or injected.
4753 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
4754 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
4755 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
4756 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
4757 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
4758 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
4759 * @param ADCx ADC instance
4760 * @param AWDy This parameter can be one of the following values:
4761 * @arg @ref LL_ADC_AWD1
4762 * @arg @ref LL_ADC_AWD2
4763 * @arg @ref LL_ADC_AWD3
4764 * @param AWDChannelGroup This parameter can be one of the following values:
4765 * @arg @ref LL_ADC_AWD_DISABLE
4766 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
4767 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
4768 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
4769 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
4770 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
4771 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
4772 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
4773 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
4774 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
4775 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
4776 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
4777 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
4778 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
4779 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
4780 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
4781 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
4782 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
4783 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
4784 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
4785 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
4786 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
4787 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
4788 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
4789 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
4790 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
4791 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
4792 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
4793 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
4794 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
4795 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
4796 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
4797 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
4798 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
4799 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
4800 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
4801 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
4802 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
4803 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
4804 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
4805 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
4806 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
4807 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
4808 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
4809 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
4810 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
4811 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
4812 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
4813 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
4814 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
4815 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
4816 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
4817 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
4818 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
4819 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
4820 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
4821 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
4822 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
4823 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
4824 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
4825 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
4826 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
4827 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
4828 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
4829 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
4830 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
4831 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
4832 * @arg @ref LL_ADC_AWD_CH_VCORE_REG (0)(1)
4833 * @arg @ref LL_ADC_AWD_CH_VCORE_INJ (0)(1)
4834 * @arg @ref LL_ADC_AWD_CH_VCORE_REG_INJ (1)
4835 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
4836 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
4837 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
4838 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
4839 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
4840 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
4841 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(1)
4842 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(1)
4843 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (1)
4844 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(1)
4845 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(1)
4846 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (1)
4847 *
4848 * (0) On STM32MP1, parameter available only on analog watchdog number: AWD1.\n
4849 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.
4850 * @retval None
4851 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)4852 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
4853 {
4854 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
4855 /* in register and register position depending on parameter "AWDy". */
4856 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
4857 /* containing other bits reserved for other purpose. */
4858 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
4859 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
4860
4861 MODIFY_REG(*preg,
4862 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
4863 AWDChannelGroup & AWDy);
4864 }
4865
4866 /**
4867 * @brief Get ADC analog watchdog monitored channel.
4868 * @note Usage of the returned channel number:
4869 * - To reinject this channel into another function LL_ADC_xxx:
4870 * the returned channel number is only partly formatted on definition
4871 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4872 * with parts of literals LL_ADC_CHANNEL_x or using
4873 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4874 * Then the selected literal LL_ADC_CHANNEL_x can be used
4875 * as parameter for another function.
4876 * - To get the channel number in decimal format:
4877 * process the returned value with the helper macro
4878 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4879 * Applicable only when the analog watchdog is set to monitor
4880 * one channel.
4881 * @note On this STM32 series, there are 2 kinds of analog watchdog
4882 * instance:
4883 * - AWD standard (instance AWD1):
4884 * - channels monitored: can monitor 1 channel or all channels.
4885 * - groups monitored: ADC groups regular and-or injected.
4886 * - resolution: resolution is not limited (corresponds to
4887 * ADC resolution configured).
4888 * - AWD flexible (instances AWD2, AWD3):
4889 * - channels monitored: flexible on channels monitored, selection is
4890 * channel wise, from from 1 to all channels.
4891 * Specificity of this analog watchdog: Multiple channels can
4892 * be selected. For example:
4893 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
4894 * - groups monitored: not selection possible (monitoring on both
4895 * groups regular and injected).
4896 * Channels selected are monitored on groups regular and injected:
4897 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
4898 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
4899 * - resolution: resolution is limited to 8 bits: if ADC resolution is
4900 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
4901 * the 2 LSB are ignored.
4902 * @note On this STM32 series, setting of this feature is conditioned to
4903 * ADC state:
4904 * ADC must be disabled or enabled without conversion on going
4905 * on either groups regular or injected.
4906 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
4907 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
4908 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
4909 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
4910 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
4911 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
4912 * @param ADCx ADC instance
4913 * @param AWDy This parameter can be one of the following values:
4914 * @arg @ref LL_ADC_AWD1
4915 * @arg @ref LL_ADC_AWD2 (1)
4916 * @arg @ref LL_ADC_AWD3 (1)
4917 *
4918 * (1) On this AWD number, monitored channel can be retrieved
4919 * if only 1 channel is programmed (or none or all channels).
4920 * This function cannot retrieve monitored channel if
4921 * multiple channels are programmed simultaneously
4922 * by bitfield.
4923 * @retval Returned value can be one of the following values:
4924 * @arg @ref LL_ADC_AWD_DISABLE
4925 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
4926 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
4927 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
4928 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
4929 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
4930 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
4931 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
4932 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
4933 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
4934 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
4935 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
4936 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
4937 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
4938 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
4939 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
4940 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
4941 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
4942 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
4943 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
4944 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
4945 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
4946 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
4947 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
4948 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
4949 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
4950 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
4951 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
4952 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
4953 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
4954 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
4955 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
4956 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
4957 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
4958 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
4959 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
4960 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
4961 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
4962 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
4963 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
4964 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
4965 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
4966 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
4967 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
4968 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
4969 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
4970 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
4971 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
4972 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
4973 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
4974 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
4975 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
4976 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
4977 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
4978 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
4979 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
4980 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
4981 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
4982 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
4983 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
4984 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
4985 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
4986 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
4987 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
4988 *
4989 * (0) On STM32MP1, parameter available only on analog watchdog number: AWD1.
4990 */
LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy)4991 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
4992 {
4993 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
4994 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
4995
4996 uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
4997
4998 /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */
4999 /* (parameter value LL_ADC_AWD_DISABLE). */
5000 /* Else, the selected AWD is enabled and is monitoring a group of channels */
5001 /* or a single channel. */
5002 if (analog_wd_monit_channels != 0UL)
5003 {
5004 if (AWDy == LL_ADC_AWD1)
5005 {
5006 if ((analog_wd_monit_channels & ADC_CFGR_AWD1SGL) == 0UL)
5007 {
5008 /* AWD monitoring a group of channels */
5009 analog_wd_monit_channels = ((analog_wd_monit_channels
5010 | (ADC_AWD_CR23_CHANNEL_MASK)
5011 )
5012 & (~(ADC_CFGR_AWD1CH))
5013 );
5014 }
5015 else
5016 {
5017 /* AWD monitoring a single channel */
5018 analog_wd_monit_channels = (analog_wd_monit_channels
5019 | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR_AWD1CH_Pos))
5020 );
5021 }
5022 }
5023 else
5024 {
5025 if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
5026 {
5027 /* AWD monitoring a group of channels */
5028 analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK
5029 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
5030 );
5031 }
5032 else
5033 {
5034 /* AWD monitoring a single channel */
5035 /* AWD monitoring a group of channels */
5036 analog_wd_monit_channels = (analog_wd_monit_channels
5037 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
5038 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR_AWD1CH_Pos)
5039 );
5040 }
5041 }
5042 }
5043
5044 return analog_wd_monit_channels;
5045 }
5046
5047 /**
5048 * @brief Set ADC analog watchdog threshold value of threshold
5049 * high or low.
5050 * @note In case of ADC resolution different of 12 bits,
5051 * analog watchdog thresholds data require a specific shift.
5052 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5053 * @note On this STM32 series, there are 2 kinds of analog watchdog
5054 * instance:
5055 * - AWD standard (instance AWD1):
5056 * - channels monitored: can monitor 1 channel or all channels.
5057 * - groups monitored: ADC groups regular and-or injected.
5058 * - resolution: resolution is not limited (corresponds to
5059 * ADC resolution configured).
5060 * - AWD flexible (instances AWD2, AWD3):
5061 * - channels monitored: flexible on channels monitored, selection is
5062 * channel wise, from from 1 to all channels.
5063 * Specificity of this analog watchdog: Multiple channels can
5064 * be selected. For example:
5065 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5066 * - groups monitored: not selection possible (monitoring on both
5067 * groups regular and injected).
5068 * Channels selected are monitored on groups regular and injected:
5069 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5070 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5071 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5072 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5073 * the 2 LSB are ignored.
5074 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
5075 * impacted: the comparison of analog watchdog thresholds is done
5076 * on oversampling intermediate computation (after ratio, before shift
5077 * application): intermediate register bitfield [32:7]
5078 * (26 most significant bits).
5079 * @note On this STM32 series, setting of this feature is conditioned to
5080 * ADC state:
5081 * ADC must be disabled or enabled without conversion on going
5082 * on either ADC groups regular or injected.
5083 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
5084 * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
5085 * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
5086 * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
5087 * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
5088 * TR3 LT3 LL_ADC_SetAnalogWDThresholds
5089 * @param ADCx ADC instance
5090 * @param AWDy This parameter can be one of the following values:
5091 * @arg @ref LL_ADC_AWD1
5092 * @arg @ref LL_ADC_AWD2
5093 * @arg @ref LL_ADC_AWD3
5094 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5095 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5096 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5097 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
5098 * @retval None
5099 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)5100 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
5101 uint32_t AWDThresholdValue)
5102 {
5103 /* Set bits with content of parameter "AWDThresholdValue" with bits */
5104 /* position in register and register position depending on parameters */
5105 /* "AWDThresholdsHighLow" and "AWDy". */
5106 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
5107 /* containing other bits reserved for other purpose. */
5108 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
5109 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
5110 + (AWDThresholdsHighLow));
5111
5112 MODIFY_REG(*preg, ADC_LTR1_LT1, AWDThresholdValue);
5113 }
5114
5115 /**
5116 * @brief Get ADC analog watchdog threshold value of threshold high,
5117 * threshold low or raw data with ADC thresholds high and low
5118 * concatenated.
5119 * @note In case of ADC resolution different of 12 bits,
5120 * analog watchdog thresholds data require a specific shift.
5121 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
5122 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
5123 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
5124 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
5125 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
5126 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
5127 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
5128 * @param ADCx ADC instance
5129 * @param AWDy This parameter can be one of the following values:
5130 * @arg @ref LL_ADC_AWD1
5131 * @arg @ref LL_ADC_AWD2
5132 * @arg @ref LL_ADC_AWD3
5133 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5134 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5135 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5136 * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF
5137 */
LL_ADC_GetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)5138 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
5139 {
5140 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
5141 + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
5142 + (AWDThresholdsHighLow));
5143
5144 return (uint32_t)(READ_BIT(*preg, ADC_LTR1_LT1));
5145 }
5146
5147 /**
5148 * @}
5149 */
5150
5151 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
5152 * @{
5153 */
5154
5155 /**
5156 * @brief Set ADC oversampling scope: ADC groups regular and-or injected
5157 * (availability of ADC group injected depends on STM32 families).
5158 * @note If both groups regular and injected are selected,
5159 * specify behavior of ADC group injected interrupting
5160 * group regular: when ADC group injected is triggered,
5161 * the oversampling on ADC group regular is either
5162 * temporary stopped and continued, or resumed from start
5163 * (oversampler buffer reset).
5164 * @note On this STM32 series, setting of this feature is conditioned to
5165 * ADC state:
5166 * ADC must be disabled or enabled without conversion on going
5167 * on either groups regular or injected.
5168 * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
5169 * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
5170 * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
5171 * @param ADCx ADC instance
5172 * @param OvsScope This parameter can be one of the following values:
5173 * @arg @ref LL_ADC_OVS_DISABLE
5174 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
5175 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
5176 * @arg @ref LL_ADC_OVS_GRP_INJECTED
5177 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
5178 * @retval None
5179 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)5180 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
5181 {
5182 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
5183 }
5184
5185 /**
5186 * @brief Get ADC oversampling scope: ADC groups regular and-or injected
5187 * (availability of ADC group injected depends on STM32 families).
5188 * @note If both groups regular and injected are selected,
5189 * specify behavior of ADC group injected interrupting
5190 * group regular: when ADC group injected is triggered,
5191 * the oversampling on ADC group regular is either
5192 * temporary stopped and continued, or resumed from start
5193 * (oversampler buffer reset).
5194 * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
5195 * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
5196 * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
5197 * @param ADCx ADC instance
5198 * @retval Returned value can be one of the following values:
5199 * @arg @ref LL_ADC_OVS_DISABLE
5200 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
5201 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
5202 * @arg @ref LL_ADC_OVS_GRP_INJECTED
5203 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
5204 */
LL_ADC_GetOverSamplingScope(ADC_TypeDef * ADCx)5205 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
5206 {
5207 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
5208 }
5209
5210 /**
5211 * @brief Set ADC oversampling discontinuous mode (triggered mode)
5212 * on the selected ADC group.
5213 * @note Number of oversampled conversions are done either in:
5214 * - continuous mode (all conversions of oversampling ratio
5215 * are done from 1 trigger)
5216 * - discontinuous mode (each conversion of oversampling ratio
5217 * needs a trigger)
5218 * @note On this STM32 series, setting of this feature is conditioned to
5219 * ADC state:
5220 * ADC must be disabled or enabled without conversion on going
5221 * on group regular.
5222 * @note On this STM32 series, oversampling discontinuous mode
5223 * (triggered mode) can be used only when oversampling is
5224 * set on group regular only and in resumed mode.
5225 * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
5226 * @param ADCx ADC instance
5227 * @param OverSamplingDiscont This parameter can be one of the following values:
5228 * @arg @ref LL_ADC_OVS_REG_CONT
5229 * @arg @ref LL_ADC_OVS_REG_DISCONT
5230 * @retval None
5231 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)5232 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
5233 {
5234 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
5235 }
5236
5237 /**
5238 * @brief Get ADC oversampling discontinuous mode (triggered mode)
5239 * on the selected ADC group.
5240 * @note Number of oversampled conversions are done either in:
5241 * - continuous mode (all conversions of oversampling ratio
5242 * are done from 1 trigger)
5243 * - discontinuous mode (each conversion of oversampling ratio
5244 * needs a trigger)
5245 * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
5246 * @param ADCx ADC instance
5247 * @retval Returned value can be one of the following values:
5248 * @arg @ref LL_ADC_OVS_REG_CONT
5249 * @arg @ref LL_ADC_OVS_REG_DISCONT
5250 */
LL_ADC_GetOverSamplingDiscont(ADC_TypeDef * ADCx)5251 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
5252 {
5253 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
5254 }
5255
5256 /**
5257 * @brief Set ADC oversampling
5258 * (impacting both ADC groups regular and injected)
5259 * @note This function set the 2 items of oversampling configuration:
5260 * - ratio
5261 * - shift
5262 * @note On this STM32 series, setting of this feature is conditioned to
5263 * ADC state:
5264 * ADC must be disabled or enabled without conversion on going
5265 * on either groups regular or injected.
5266 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
5267 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
5268 * @param ADCx ADC instance
5269 * @param Ratio This parameter can be in the range from 1 to 1024.
5270 * @param Shift This parameter can be one of the following values:
5271 * @arg @ref LL_ADC_OVS_SHIFT_NONE
5272 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
5273 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
5274 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
5275 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
5276 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
5277 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
5278 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
5279 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
5280 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9
5281 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10
5282 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11
5283 * @retval None
5284 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)5285 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
5286 {
5287 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OSR_Pos))));
5288 }
5289
5290 /**
5291 * @brief Get ADC oversampling ratio
5292 * (impacting both ADC groups regular and injected)
5293 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
5294 * @param ADCx ADC instance
5295 * @retval Ratio This parameter can be in the from 1 to 1024.
5296 */
LL_ADC_GetOverSamplingRatio(ADC_TypeDef * ADCx)5297 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
5298 {
5299 return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OSR))+(1UL << ADC_CFGR2_OSR_Pos)) >> ADC_CFGR2_OSR_Pos);
5300 }
5301
5302 /**
5303 * @brief Get ADC oversampling shift
5304 * (impacting both ADC groups regular and injected)
5305 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
5306 * @param ADCx ADC instance
5307 * @retval Shift This parameter can be one of the following values:
5308 * @arg @ref LL_ADC_OVS_SHIFT_NONE
5309 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
5310 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
5311 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
5312 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
5313 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
5314 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
5315 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
5316 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
5317 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9
5318 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10
5319 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11
5320 */
LL_ADC_GetOverSamplingShift(ADC_TypeDef * ADCx)5321 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
5322 {
5323 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
5324 }
5325
5326 /**
5327 * @}
5328 */
5329
5330 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
5331 * @{
5332 */
5333 /**
5334 * @brief Set ADC boost mode.
5335 * @note On this STM32 series, setting of this feature is conditioned to
5336 * ADC state:
5337 * ADC boost must be configured, without calibration on going, without conversion
5338 * on going on group regular.
5339 * @rmtoll CR BOOST LL_ADC_SetBoostMode
5340 * @param ADCx ADC instance
5341 * @param BoostMode This parameter can be one of the following values:
5342 * @arg @ref LL_ADC_BOOST_MODE_DISABLE
5343 * @arg @ref LL_ADC_BOOST_MODE_ENABLE
5344 * @retval None
5345 */
LL_ADC_SetBoostMode(ADC_TypeDef * ADCx,uint32_t BoostMode)5346 __STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode)
5347 {
5348 MODIFY_REG(ADCx->CR, ADC_CR_BOOST, BoostMode);
5349 }
5350
5351 /**
5352 * @brief Get ADC boost mode.
5353 * @note On this STM32 series, setting of this feature is conditioned to
5354 * ADC state:
5355 * ADC boost must be configured, without calibration on going, without conversion
5356 * on going on group regular.
5357 * @rmtoll CR BOOST LL_ADC_GetBoostMode
5358 * @param ADCx ADC instance
5359 * @retval Returned value can be one of the following values:
5360 * @arg @ref LL_ADC_BOOST_MODE_DISABLE
5361 * @arg @ref LL_ADC_BOOST_MODE_ENABLE
5362 */
LL_ADC_GetBoostMode(ADC_TypeDef * ADCx)5363 __STATIC_INLINE uint32_t LL_ADC_GetBoostMode(ADC_TypeDef *ADCx)
5364 {
5365 return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_BOOST));
5366 }
5367
5368 #if defined(ADC_MULTIMODE_SUPPORT)
5369 /**
5370 * @brief Set ADC multimode configuration to operate in independent mode
5371 * or multimode (for devices with several ADC instances).
5372 * @note If multimode configuration: the selected ADC instance is
5373 * either master or slave depending on hardware.
5374 * Refer to reference manual.
5375 * @note On this STM32 series, setting of this feature is conditioned to
5376 * ADC state:
5377 * All ADC instances of the ADC common group must be disabled.
5378 * This check can be done with function @ref LL_ADC_IsEnabled() for each
5379 * ADC instance or by using helper macro
5380 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
5381 * @rmtoll CCR DUAL LL_ADC_SetMultimode
5382 * @param ADCxy_COMMON ADC common instance
5383 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5384 * @param Multimode This parameter can be one of the following values:
5385 * @arg @ref LL_ADC_MULTI_INDEPENDENT
5386 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
5387 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
5388 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
5389 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
5390 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
5391 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
5392 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
5393 * @retval None
5394 */
LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)5395 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
5396 {
5397 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
5398 }
5399
5400 /**
5401 * @brief Get ADC multimode configuration to operate in independent mode
5402 * or multimode (for devices with several ADC instances).
5403 * @note If multimode configuration: the selected ADC instance is
5404 * either master or slave depending on hardware.
5405 * Refer to reference manual.
5406 * @rmtoll CCR DUAL LL_ADC_GetMultimode
5407 * @param ADCxy_COMMON ADC common instance
5408 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5409 * @retval Returned value can be one of the following values:
5410 * @arg @ref LL_ADC_MULTI_INDEPENDENT
5411 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
5412 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
5413 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
5414 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
5415 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
5416 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
5417 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
5418 */
LL_ADC_GetMultimode(ADC_Common_TypeDef * ADCxy_COMMON)5419 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
5420 {
5421 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
5422 }
5423
5424 /**
5425 * @brief Set ADC multimode conversion data transfer: no transfer
5426 * or transfer by DMA.
5427 * @note If ADC multimode transfer by DMA is not selected:
5428 * each ADC uses its own DMA channel, with its individual
5429 * DMA transfer settings.
5430 * If ADC multimode transfer by DMA is selected:
5431 * One DMA channel is used for both ADC (DMA of ADC master)
5432 * Specifies the DMA requests mode:
5433 * - Limited mode (One shot mode): DMA transfer requests are stopped
5434 * when number of DMA data transfers (number of
5435 * ADC conversions) is reached.
5436 * This ADC mode is intended to be used with DMA mode non-circular.
5437 * - Unlimited mode: DMA transfer requests are unlimited,
5438 * whatever number of DMA data transfers (number of
5439 * ADC conversions).
5440 * This ADC mode is intended to be used with DMA mode circular.
5441 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
5442 * mode non-circular:
5443 * when DMA transfers size will be reached, DMA will stop transfers of
5444 * ADC conversions data ADC will raise an overrun error
5445 * (overrun flag and interruption if enabled).
5446 * @note How to retrieve multimode conversion data:
5447 * Whatever multimode transfer by DMA setting: using function
5448 * @ref LL_ADC_REG_ReadMultiConversionData32().
5449 * If ADC multimode transfer by DMA is selected: conversion data
5450 * is a raw data with ADC master and slave concatenated.
5451 * A macro is available to get the conversion data of
5452 * ADC master or ADC slave: see helper macro
5453 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
5454 * @note On this STM32 series, setting of this feature is conditioned to
5455 * ADC state:
5456 * All ADC instances of the ADC common group must be disabled
5457 * or enabled without conversion on going on group regular.
5458 * @rmtoll CCR DAMDF LL_ADC_GetMultiDMATransfer\n
5459 * @param ADCxy_COMMON ADC common instance
5460 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5461 * @param MultiDMATransfer This parameter can be one of the following values:
5462 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
5463 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B
5464 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B
5465 * @retval None
5466 */
LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDMATransfer)5467 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
5468 {
5469 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DAMDF, MultiDMATransfer);
5470 }
5471
5472 /**
5473 * @brief Get ADC multimode conversion data transfer: no transfer
5474 * or transfer by DMA.
5475 * @note If ADC multimode transfer by DMA is not selected:
5476 * each ADC uses its own DMA channel, with its individual
5477 * DMA transfer settings.
5478 * If ADC multimode transfer by DMA is selected:
5479 * One DMA channel is used for both ADC (DMA of ADC master)
5480 * Specifies the DMA requests mode:
5481 * - Limited mode (One shot mode): DMA transfer requests are stopped
5482 * when number of DMA data transfers (number of
5483 * ADC conversions) is reached.
5484 * This ADC mode is intended to be used with DMA mode non-circular.
5485 * - Unlimited mode: DMA transfer requests are unlimited,
5486 * whatever number of DMA data transfers (number of
5487 * ADC conversions).
5488 * This ADC mode is intended to be used with DMA mode circular.
5489 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
5490 * mode non-circular:
5491 * when DMA transfers size will be reached, DMA will stop transfers of
5492 * ADC conversions data ADC will raise an overrun error
5493 * (overrun flag and interruption if enabled).
5494 * @note How to retrieve multimode conversion data:
5495 * Whatever multimode transfer by DMA setting: using function
5496 * @ref LL_ADC_REG_ReadMultiConversionData32().
5497 * If ADC multimode transfer by DMA is selected: conversion data
5498 * is a raw data with ADC master and slave concatenated.
5499 * A macro is available to get the conversion data of
5500 * ADC master or ADC slave: see helper macro
5501 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
5502 * @rmtoll CCR DAMDF LL_ADC_GetMultiDMATransfer\n
5503 * @param ADCxy_COMMON ADC common instance
5504 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5505 * @retval Returned value can be one of the following values:
5506 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
5507 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B
5508 * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B
5509 */
LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON)5510 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
5511 {
5512 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF));
5513 }
5514
5515 /**
5516 * @brief Set ADC multimode delay between 2 sampling phases.
5517 * @note The sampling delay range depends on ADC resolution:
5518 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
5519 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
5520 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
5521 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
5522 * @note On this STM32 series, setting of this feature is conditioned to
5523 * ADC state:
5524 * All ADC instances of the ADC common group must be disabled.
5525 * This check can be done with function @ref LL_ADC_IsEnabled() for each
5526 * ADC instance or by using helper macro helper macro
5527 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
5528 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
5529 * @param ADCxy_COMMON ADC common instance
5530 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5531 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
5532 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5
5533 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5
5534 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5
5535 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)
5536 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS
5537 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)
5538 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS
5539 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (3)
5540 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS
5541 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (4)
5542 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5_14_BITS
5543 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES_5 (5)
5544 *
5545 * (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.
5546 * (2) Parameter available only if ADC resolution is 16, 14 or 12 bits.
5547 * (3) Parameter available only if ADC resolution is 16 or 14 bits.
5548 * (4) Parameter available only if ADC resolution is 16 bits.
5549 * (5) Parameter available only if ADC resolution is 16 bits.
5550 * @retval None
5551 */
LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)5552 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
5553 {
5554 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
5555 }
5556
5557 /**
5558 * @brief Get ADC multimode delay between 2 sampling phases.
5559 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
5560 * @param ADCxy_COMMON ADC common instance
5561 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5562 * @retval Returned value can be one of the following values:
5563 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5
5564 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5
5565 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5
5566 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)
5567 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS
5568 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)
5569 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS
5570 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (3)
5571 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS
5572 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (4)
5573 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5_14_BITS
5574 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES_5 (5)
5575 *
5576 * (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.
5577 * (2) Parameter available only if ADC resolution is 16, 14 or 12 bits.
5578 * (3) Parameter available only if ADC resolution is 16 or 14 bits.
5579 * (4) Parameter available only if ADC resolution is 16 bits.
5580 * (5) Parameter available only if ADC resolution is 16 bits.
5581 */
LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON)5582 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
5583 {
5584 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
5585 }
5586 #endif /* ADC_MULTIMODE_SUPPORT */
5587
5588 /**
5589 * @}
5590 */
5591 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
5592 * @{
5593 */
5594
5595 /**
5596 * @brief Put ADC instance in deep power down state.
5597 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
5598 * state, the internal analog calibration is lost. After exiting from
5599 * deep power down, calibration must be relaunched or calibration factor
5600 * (preliminarily saved) must be set back into calibration register.
5601 * @note On this STM32 series, setting of this feature is conditioned to
5602 * ADC state:
5603 * ADC must be ADC disabled.
5604 * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
5605 * @param ADCx ADC instance
5606 * @retval None
5607 */
LL_ADC_EnableDeepPowerDown(ADC_TypeDef * ADCx)5608 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
5609 {
5610 /* Note: Write register with some additional bits forced to state reset */
5611 /* instead of modifying only the selected bit for this function, */
5612 /* to not interfere with bits with HW property "rs". */
5613 MODIFY_REG(ADCx->CR,
5614 ADC_CR_BITS_PROPERTY_RS,
5615 ADC_CR_DEEPPWD);
5616 }
5617
5618 /**
5619 * @brief Disable ADC deep power down mode.
5620 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
5621 * state, the internal analog calibration is lost. After exiting from
5622 * deep power down, calibration must be relaunched or calibration factor
5623 * (preliminarily saved) must be set back into calibration register.
5624 * @note On this STM32 series, setting of this feature is conditioned to
5625 * ADC state:
5626 * ADC must be ADC disabled.
5627 * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
5628 * @param ADCx ADC instance
5629 * @retval None
5630 */
LL_ADC_DisableDeepPowerDown(ADC_TypeDef * ADCx)5631 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
5632 {
5633 /* Note: Write register with some additional bits forced to state reset */
5634 /* instead of modifying only the selected bit for this function, */
5635 /* to not interfere with bits with HW property "rs". */
5636 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
5637 }
5638
5639 /**
5640 * @brief Get the selected ADC instance deep power down state.
5641 * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
5642 * @param ADCx ADC instance
5643 * @retval 0: deep power down is disabled, 1: deep power down is enabled.
5644 */
LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef * ADCx)5645 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
5646 {
5647 return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
5648 }
5649
5650 /**
5651 * @brief Enable ADC instance internal voltage regulator.
5652 * @note On this STM32 series, after ADC internal voltage regulator enable,
5653 * a delay for ADC internal voltage regulator stabilization
5654 * is required before performing a ADC calibration or ADC enable.
5655 * Refer to device datasheet, parameter tADCVREG_STUP.
5656 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
5657 * @note On this STM32 series, setting of this feature is conditioned to
5658 * ADC state:
5659 * ADC must be ADC disabled.
5660 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
5661 * @param ADCx ADC instance
5662 * @retval None
5663 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)5664 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
5665 {
5666 /* Note: Write register with some additional bits forced to state reset */
5667 /* instead of modifying only the selected bit for this function, */
5668 /* to not interfere with bits with HW property "rs". */
5669 MODIFY_REG(ADCx->CR,
5670 ADC_CR_BITS_PROPERTY_RS,
5671 ADC_CR_ADVREGEN);
5672 }
5673
5674 /**
5675 * @brief Disable ADC internal voltage regulator.
5676 * @note On this STM32 series, setting of this feature is conditioned to
5677 * ADC state:
5678 * ADC must be ADC disabled.
5679 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
5680 * @param ADCx ADC instance
5681 * @retval None
5682 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)5683 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
5684 {
5685 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
5686 }
5687
5688 /**
5689 * @brief Get the selected ADC instance internal voltage regulator state.
5690 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
5691 * @param ADCx ADC instance
5692 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
5693 */
LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef * ADCx)5694 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
5695 {
5696 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
5697 }
5698
5699 /**
5700 * @brief Enable the selected ADC instance.
5701 * @note On this STM32 series, after ADC enable, a delay for
5702 * ADC internal analog stabilization is required before performing a
5703 * ADC conversion start.
5704 * Refer to device datasheet, parameter tSTAB.
5705 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
5706 * is enabled and when conversion clock is active.
5707 * (not only core clock: this ADC has a dual clock domain)
5708 * @note On this STM32 series, setting of this feature is conditioned to
5709 * ADC state:
5710 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
5711 * @rmtoll CR ADEN LL_ADC_Enable
5712 * @param ADCx ADC instance
5713 * @retval None
5714 */
LL_ADC_Enable(ADC_TypeDef * ADCx)5715 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
5716 {
5717 /* Note: Write register with some additional bits forced to state reset */
5718 /* instead of modifying only the selected bit for this function, */
5719 /* to not interfere with bits with HW property "rs". */
5720 MODIFY_REG(ADCx->CR,
5721 ADC_CR_BITS_PROPERTY_RS,
5722 ADC_CR_ADEN);
5723 }
5724
5725 /**
5726 * @brief Disable the selected ADC instance.
5727 * @note On this STM32 series, setting of this feature is conditioned to
5728 * ADC state:
5729 * ADC must be not disabled. Must be enabled without conversion on going
5730 * on either groups regular or injected.
5731 * @rmtoll CR ADDIS LL_ADC_Disable
5732 * @param ADCx ADC instance
5733 * @retval None
5734 */
LL_ADC_Disable(ADC_TypeDef * ADCx)5735 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
5736 {
5737 /* Note: Write register with some additional bits forced to state reset */
5738 /* instead of modifying only the selected bit for this function, */
5739 /* to not interfere with bits with HW property "rs". */
5740 MODIFY_REG(ADCx->CR,
5741 ADC_CR_BITS_PROPERTY_RS,
5742 ADC_CR_ADDIS);
5743 }
5744
5745 /**
5746 * @brief Get the selected ADC instance enable state.
5747 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
5748 * is enabled and when conversion clock is active.
5749 * (not only core clock: this ADC has a dual clock domain)
5750 * @rmtoll CR ADEN LL_ADC_IsEnabled
5751 * @param ADCx ADC instance
5752 * @retval 0: ADC is disabled, 1: ADC is enabled.
5753 */
LL_ADC_IsEnabled(ADC_TypeDef * ADCx)5754 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
5755 {
5756 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
5757 }
5758
5759 /**
5760 * @brief Get the selected ADC instance disable state.
5761 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
5762 * @param ADCx ADC instance
5763 * @retval 0: no ADC disable command on going.
5764 */
LL_ADC_IsDisableOngoing(ADC_TypeDef * ADCx)5765 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
5766 {
5767 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
5768 }
5769
5770 /**
5771 * @brief Start ADC calibration in the mode single-ended
5772 * or differential (for devices with differential mode available).
5773 * @note On this STM32 series, a minimum number of ADC clock cycles
5774 * are required between ADC end of calibration and ADC enable.
5775 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
5776 * @note Calibration duration:
5777 * - Calibration of offset: 520 ADC clock cycles
5778 * - Calibration of linearity: 131072 ADC clock cycles
5779 * @note For devices with differential mode available:
5780 * Calibration of offset is specific to each of
5781 * single-ended and differential modes
5782 * (calibration run must be performed for each of these
5783 * differential modes, if used afterwards and if the application
5784 * requires their calibration).
5785 * Calibration of linearity is common to both
5786 * single-ended and differential modes
5787 * (calibration run can be performed only once).
5788 * @note On this STM32 series, setting of this feature is conditioned to
5789 * ADC state:
5790 * ADC must be ADC disabled.
5791 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
5792 * CR ADCALDIF LL_ADC_StartCalibration\n
5793 * CR ADCALLIN LL_ADC_StartCalibration
5794 * @param ADCx ADC instance
5795 * @param CalibrationMode This parameter can be one of the following values:
5796 * @arg @ref LL_ADC_CALIB_OFFSET
5797 * @arg @ref LL_ADC_CALIB_OFFSET_LINEARITY
5798 * @param SingleDiff This parameter can be one of the following values:
5799 * @arg @ref LL_ADC_SINGLE_ENDED
5800 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
5801 * @retval None
5802 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx,uint32_t CalibrationMode,uint32_t SingleDiff)5803 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t CalibrationMode, uint32_t SingleDiff)
5804 {
5805 /* Note: Write register with some additional bits forced to state reset */
5806 /* instead of modifying only the selected bit for this function, */
5807 /* to not interfere with bits with HW property "rs". */
5808 MODIFY_REG(ADCx->CR,
5809 ADC_CR_ADCALLIN | ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
5810 ADC_CR_ADCAL | (CalibrationMode & ADC_CALIB_MODE_MASK) | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
5811 }
5812
5813 /**
5814 * @brief Get ADC calibration state.
5815 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
5816 * @param ADCx ADC instance
5817 * @retval 0: calibration complete, 1: calibration in progress.
5818 */
LL_ADC_IsCalibrationOnGoing(ADC_TypeDef * ADCx)5819 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
5820 {
5821 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
5822 }
5823
5824 /**
5825 * @}
5826 */
5827
5828 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
5829 * @{
5830 */
5831
5832 /**
5833 * @brief Start ADC group regular conversion.
5834 * @note On this STM32 series, this function is relevant for both
5835 * internal trigger (SW start) and external trigger:
5836 * - If ADC trigger has been set to software start, ADC conversion
5837 * starts immediately.
5838 * - If ADC trigger has been set to external trigger, ADC conversion
5839 * will start at next trigger event (on the selected trigger edge)
5840 * following the ADC start conversion command.
5841 * @note On this STM32 series, setting of this feature is conditioned to
5842 * ADC state:
5843 * ADC must be enabled without conversion on going on group regular,
5844 * without conversion stop command on going on group regular,
5845 * without ADC disable command on going.
5846 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
5847 * @param ADCx ADC instance
5848 * @retval None
5849 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)5850 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
5851 {
5852 /* Note: Write register with some additional bits forced to state reset */
5853 /* instead of modifying only the selected bit for this function, */
5854 /* to not interfere with bits with HW property "rs". */
5855 MODIFY_REG(ADCx->CR,
5856 ADC_CR_BITS_PROPERTY_RS,
5857 ADC_CR_ADSTART);
5858 }
5859
5860 /**
5861 * @brief Stop ADC group regular conversion.
5862 * @note On this STM32 series, setting of this feature is conditioned to
5863 * ADC state:
5864 * ADC must be enabled with conversion on going on group regular,
5865 * without ADC disable command on going.
5866 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
5867 * @param ADCx ADC instance
5868 * @retval None
5869 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)5870 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
5871 {
5872 /* Note: Write register with some additional bits forced to state reset */
5873 /* instead of modifying only the selected bit for this function, */
5874 /* to not interfere with bits with HW property "rs". */
5875 MODIFY_REG(ADCx->CR,
5876 ADC_CR_BITS_PROPERTY_RS,
5877 ADC_CR_ADSTP);
5878 }
5879
5880 /**
5881 * @brief Get ADC group regular conversion state.
5882 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
5883 * @param ADCx ADC instance
5884 * @retval 0: no conversion is on going on ADC group regular.
5885 */
LL_ADC_REG_IsConversionOngoing(ADC_TypeDef * ADCx)5886 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
5887 {
5888 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
5889 }
5890
5891 /**
5892 * @brief Get ADC group regular command of conversion stop state
5893 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
5894 * @param ADCx ADC instance
5895 * @retval 0: no command of conversion stop is on going on ADC group regular.
5896 */
LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef * ADCx)5897 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
5898 {
5899 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
5900 }
5901
5902 /**
5903 * @brief Get ADC group regular conversion data, range fit for
5904 * all ADC configurations: all ADC resolutions and
5905 * all oversampling increased data width (for devices
5906 * with feature oversampling).
5907 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
5908 * @param ADCx ADC instance
5909 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
5910 */
LL_ADC_REG_ReadConversionData32(ADC_TypeDef * ADCx)5911 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
5912 {
5913 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
5914 }
5915
5916 /**
5917 * @brief Get ADC group regular conversion data, range fit for
5918 * ADC resolution 16 bits.
5919 * @note For devices with feature oversampling: Oversampling
5920 * can increase data width, function for extended range
5921 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
5922 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData16
5923 * @param ADCx ADC instance
5924 * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
5925 */
LL_ADC_REG_ReadConversionData16(ADC_TypeDef * ADCx)5926 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx)
5927 {
5928 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
5929 }
5930
5931 /**
5932 * @brief Get ADC group regular conversion data, range fit for
5933 * ADC resolution 14 bits.
5934 * @note For devices with feature oversampling: Oversampling
5935 * can increase data width, function for extended range
5936 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
5937 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData14
5938 * @param ADCx ADC instance
5939 * @retval Value between Min_Data=0x00 and Max_Data=0x3FF
5940 */
LL_ADC_REG_ReadConversionData14(ADC_TypeDef * ADCx)5941 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx)
5942 {
5943 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
5944 }
5945
5946 /**
5947 * @brief Get ADC group regular conversion data, range fit for
5948 * ADC resolution 12 bits.
5949 * @note For devices with feature oversampling: Oversampling
5950 * can increase data width, function for extended range
5951 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
5952 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
5953 * @param ADCx ADC instance
5954 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
5955 */
LL_ADC_REG_ReadConversionData12(ADC_TypeDef * ADCx)5956 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
5957 {
5958 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
5959 }
5960
5961 /**
5962 * @brief Get ADC group regular conversion data, range fit for
5963 * ADC resolution 10 bits.
5964 * @note For devices with feature oversampling: Oversampling
5965 * can increase data width, function for extended range
5966 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
5967 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
5968 * @param ADCx ADC instance
5969 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
5970 */
LL_ADC_REG_ReadConversionData10(ADC_TypeDef * ADCx)5971 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
5972 {
5973 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
5974 }
5975
5976 /**
5977 * @brief Get ADC group regular conversion data, range fit for
5978 * ADC resolution 8 bits.
5979 * @note For devices with feature oversampling: Oversampling
5980 * can increase data width, function for extended range
5981 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
5982 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
5983 * @param ADCx ADC instance
5984 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
5985 */
LL_ADC_REG_ReadConversionData8(ADC_TypeDef * ADCx)5986 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
5987 {
5988 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
5989 }
5990 #if defined(ADC_MULTIMODE_SUPPORT)
5991 /**
5992 * @brief Get ADC multimode conversion data of ADC master, ADC slave
5993 * or raw data with ADC master and slave concatenated.
5994 * @note If raw data with ADC master and slave concatenated is retrieved,
5995 * a macro is available to get the conversion data of
5996 * ADC master or ADC slave: see helper macro
5997 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
5998 * (however this macro is mainly intended for multimode
5999 * transfer by DMA, because this function can do the same
6000 * by getting multimode conversion data of ADC master or ADC slave
6001 * separately).
6002 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
6003 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
6004 * @param ADCxy_COMMON ADC common instance
6005 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6006 * @param ConversionData This parameter can be one of the following values:
6007 * @arg @ref LL_ADC_MULTI_MASTER
6008 * @arg @ref LL_ADC_MULTI_SLAVE
6009 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
6010 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6011 */
LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t ConversionData)6012 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
6013 {
6014 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
6015 ConversionData)
6016 >> (POSITION_VAL(ConversionData) & 0x1FUL)
6017 );
6018 }
6019 #endif /* ADC_MULTIMODE_SUPPORT */
6020
6021 /**
6022 * @}
6023 */
6024
6025 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
6026 * @{
6027 */
6028
6029 /**
6030 * @brief Start ADC group injected conversion.
6031 * @note On this STM32 series, this function is relevant for both
6032 * internal trigger (SW start) and external trigger:
6033 * - If ADC trigger has been set to software start, ADC conversion
6034 * starts immediately.
6035 * - If ADC trigger has been set to external trigger, ADC conversion
6036 * will start at next trigger event (on the selected trigger edge)
6037 * following the ADC start conversion command.
6038 * @note On this STM32 series, setting of this feature is conditioned to
6039 * ADC state:
6040 * ADC must be enabled without conversion on going on group injected,
6041 * without conversion stop command on going on group injected,
6042 * without ADC disable command on going.
6043 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
6044 * @param ADCx ADC instance
6045 * @retval None
6046 */
LL_ADC_INJ_StartConversion(ADC_TypeDef * ADCx)6047 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
6048 {
6049 /* Note: Write register with some additional bits forced to state reset */
6050 /* instead of modifying only the selected bit for this function, */
6051 /* to not interfere with bits with HW property "rs". */
6052 MODIFY_REG(ADCx->CR,
6053 ADC_CR_BITS_PROPERTY_RS,
6054 ADC_CR_JADSTART);
6055 }
6056
6057 /**
6058 * @brief Stop ADC group injected conversion.
6059 * @note On this STM32 series, setting of this feature is conditioned to
6060 * ADC state:
6061 * ADC must be enabled with conversion on going on group injected,
6062 * without ADC disable command on going.
6063 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
6064 * @param ADCx ADC instance
6065 * @retval None
6066 */
LL_ADC_INJ_StopConversion(ADC_TypeDef * ADCx)6067 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
6068 {
6069 /* Note: Write register with some additional bits forced to state reset */
6070 /* instead of modifying only the selected bit for this function, */
6071 /* to not interfere with bits with HW property "rs". */
6072 MODIFY_REG(ADCx->CR,
6073 ADC_CR_BITS_PROPERTY_RS,
6074 ADC_CR_JADSTP);
6075 }
6076
6077 /**
6078 * @brief Get ADC group injected conversion state.
6079 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
6080 * @param ADCx ADC instance
6081 * @retval 0: no conversion is on going on ADC group injected.
6082 */
LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef * ADCx)6083 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
6084 {
6085 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
6086 }
6087
6088 /**
6089 * @brief Get ADC group injected command of conversion stop state
6090 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
6091 * @param ADCx ADC instance
6092 * @retval 0: no command of conversion stop is on going on ADC group injected.
6093 */
LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef * ADCx)6094 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
6095 {
6096 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
6097 }
6098
6099 /**
6100 * @brief Get ADC group injected conversion data, range fit for
6101 * all ADC configurations: all ADC resolutions and
6102 * all oversampling increased data width (for devices
6103 * with feature oversampling).
6104 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
6105 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
6106 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
6107 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
6108 * @param ADCx ADC instance
6109 * @param Rank This parameter can be one of the following values:
6110 * @arg @ref LL_ADC_INJ_RANK_1
6111 * @arg @ref LL_ADC_INJ_RANK_2
6112 * @arg @ref LL_ADC_INJ_RANK_3
6113 * @arg @ref LL_ADC_INJ_RANK_4
6114 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6115 */
LL_ADC_INJ_ReadConversionData32(ADC_TypeDef * ADCx,uint32_t Rank)6116 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
6117 {
6118 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6119
6120 return (uint32_t)(READ_BIT(*preg,
6121 ADC_JDR1_JDATA)
6122 );
6123 }
6124
6125 /**
6126 * @brief Get ADC group injected conversion data, range fit for
6127 * ADC resolution 16 bits.
6128 * @note For devices with feature oversampling: Oversampling
6129 * can increase data width, function for extended range
6130 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6131 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData16\n
6132 * JDR2 JDATA LL_ADC_INJ_ReadConversionData16\n
6133 * JDR3 JDATA LL_ADC_INJ_ReadConversionData16\n
6134 * JDR4 JDATA LL_ADC_INJ_ReadConversionData16
6135 * @param ADCx ADC instance
6136 * @param Rank This parameter can be one of the following values:
6137 * @arg @ref LL_ADC_INJ_RANK_1
6138 * @arg @ref LL_ADC_INJ_RANK_2
6139 * @arg @ref LL_ADC_INJ_RANK_3
6140 * @arg @ref LL_ADC_INJ_RANK_4
6141 * @retval Value between Min_Data=0x000 and Max_Data=0xFFFF
6142 */
LL_ADC_INJ_ReadConversionData16(ADC_TypeDef * ADCx,uint32_t Rank)6143 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint32_t Rank)
6144 {
6145 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6146
6147 return (uint16_t)(READ_BIT(*preg,
6148 ADC_JDR1_JDATA)
6149 );
6150 }
6151
6152 /**
6153 * @brief Get ADC group injected conversion data, range fit for
6154 * ADC resolution 14 bits.
6155 * @note For devices with feature oversampling: Oversampling
6156 * can increase data width, function for extended range
6157 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6158 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData14\n
6159 * JDR2 JDATA LL_ADC_INJ_ReadConversionData14\n
6160 * JDR3 JDATA LL_ADC_INJ_ReadConversionData14\n
6161 * JDR4 JDATA LL_ADC_INJ_ReadConversionData14
6162 * @param ADCx ADC instance
6163 * @param Rank This parameter can be one of the following values:
6164 * @arg @ref LL_ADC_INJ_RANK_1
6165 * @arg @ref LL_ADC_INJ_RANK_2
6166 * @arg @ref LL_ADC_INJ_RANK_3
6167 * @arg @ref LL_ADC_INJ_RANK_4
6168 * @retval Value between Min_Data=0x000 and Max_Data=0x3FFF
6169 */
LL_ADC_INJ_ReadConversionData14(ADC_TypeDef * ADCx,uint32_t Rank)6170 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint32_t Rank)
6171 {
6172 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6173
6174 return (uint16_t)(READ_BIT(*preg,
6175 ADC_JDR1_JDATA)
6176 );
6177 }
6178
6179 /**
6180 * @brief Get ADC group injected conversion data, range fit for
6181 * ADC resolution 12 bits.
6182 * @note For devices with feature oversampling: Oversampling
6183 * can increase data width, function for extended range
6184 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6185 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
6186 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
6187 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
6188 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
6189 * @param ADCx ADC instance
6190 * @param Rank This parameter can be one of the following values:
6191 * @arg @ref LL_ADC_INJ_RANK_1
6192 * @arg @ref LL_ADC_INJ_RANK_2
6193 * @arg @ref LL_ADC_INJ_RANK_3
6194 * @arg @ref LL_ADC_INJ_RANK_4
6195 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6196 */
LL_ADC_INJ_ReadConversionData12(ADC_TypeDef * ADCx,uint32_t Rank)6197 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
6198 {
6199 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6200
6201 return (uint16_t)(READ_BIT(*preg,
6202 ADC_JDR1_JDATA)
6203 );
6204 }
6205
6206 /**
6207 * @brief Get ADC group injected conversion data, range fit for
6208 * ADC resolution 10 bits.
6209 * @note For devices with feature oversampling: Oversampling
6210 * can increase data width, function for extended range
6211 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6212 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
6213 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
6214 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
6215 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
6216 * @param ADCx ADC instance
6217 * @param Rank This parameter can be one of the following values:
6218 * @arg @ref LL_ADC_INJ_RANK_1
6219 * @arg @ref LL_ADC_INJ_RANK_2
6220 * @arg @ref LL_ADC_INJ_RANK_3
6221 * @arg @ref LL_ADC_INJ_RANK_4
6222 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
6223 */
LL_ADC_INJ_ReadConversionData10(ADC_TypeDef * ADCx,uint32_t Rank)6224 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
6225 {
6226 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6227
6228 return (uint16_t)(READ_BIT(*preg,
6229 ADC_JDR1_JDATA)
6230 );
6231 }
6232
6233 /**
6234 * @brief Get ADC group injected conversion data, range fit for
6235 * ADC resolution 8 bits.
6236 * @note For devices with feature oversampling: Oversampling
6237 * can increase data width, function for extended range
6238 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6239 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
6240 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
6241 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
6242 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
6243 * @param ADCx ADC instance
6244 * @param Rank This parameter can be one of the following values:
6245 * @arg @ref LL_ADC_INJ_RANK_1
6246 * @arg @ref LL_ADC_INJ_RANK_2
6247 * @arg @ref LL_ADC_INJ_RANK_3
6248 * @arg @ref LL_ADC_INJ_RANK_4
6249 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
6250 */
LL_ADC_INJ_ReadConversionData8(ADC_TypeDef * ADCx,uint32_t Rank)6251 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
6252 {
6253 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6254
6255 return (uint8_t)(READ_BIT(*preg,
6256 ADC_JDR1_JDATA)
6257 );
6258 }
6259
6260 /**
6261 * @}
6262 */
6263
6264 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
6265 * @{
6266 */
6267
6268 /**
6269 * @brief Get flag ADC ready.
6270 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6271 * is enabled and when conversion clock is active.
6272 * (not only core clock: this ADC has a dual clock domain)
6273 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
6274 * @param ADCx ADC instance
6275 * @retval State of bit (1 or 0).
6276 */
LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef * ADCx)6277 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
6278 {
6279 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
6280 }
6281
6282 /**
6283 * @brief Get flag ADC group regular end of unitary conversion.
6284 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
6285 * @param ADCx ADC instance
6286 * @retval State of bit (1 or 0).
6287 */
LL_ADC_IsActiveFlag_EOC(ADC_TypeDef * ADCx)6288 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
6289 {
6290 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
6291 }
6292
6293 /**
6294 * @brief Get flag ADC group regular end of sequence conversions.
6295 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
6296 * @param ADCx ADC instance
6297 * @retval State of bit (1 or 0).
6298 */
LL_ADC_IsActiveFlag_EOS(ADC_TypeDef * ADCx)6299 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
6300 {
6301 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
6302 }
6303
6304 /**
6305 * @brief Get flag ADC group regular overrun.
6306 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
6307 * @param ADCx ADC instance
6308 * @retval State of bit (1 or 0).
6309 */
LL_ADC_IsActiveFlag_OVR(ADC_TypeDef * ADCx)6310 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
6311 {
6312 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
6313 }
6314
6315 /**
6316 * @brief Get flag ADC group regular end of sampling phase.
6317 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
6318 * @param ADCx ADC instance
6319 * @retval State of bit (1 or 0).
6320 */
LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef * ADCx)6321 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
6322 {
6323 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
6324 }
6325
6326 /**
6327 * @brief Get flag ADC group injected end of unitary conversion.
6328 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
6329 * @param ADCx ADC instance
6330 * @retval State of bit (1 or 0).
6331 */
LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef * ADCx)6332 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
6333 {
6334 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
6335 }
6336
6337 /**
6338 * @brief Get flag ADC group injected end of sequence conversions.
6339 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
6340 * @param ADCx ADC instance
6341 * @retval State of bit (1 or 0).
6342 */
LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef * ADCx)6343 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
6344 {
6345 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
6346 }
6347
6348 /**
6349 * @brief Get flag ADC group injected contexts queue overflow.
6350 * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
6351 * @param ADCx ADC instance
6352 * @retval State of bit (1 or 0).
6353 */
LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef * ADCx)6354 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
6355 {
6356 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
6357 }
6358
6359 /**
6360 * @brief Get flag ADC analog watchdog 1 flag
6361 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
6362 * @param ADCx ADC instance
6363 * @retval State of bit (1 or 0).
6364 */
LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef * ADCx)6365 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
6366 {
6367 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
6368 }
6369
6370 /**
6371 * @brief Get flag ADC analog watchdog 2.
6372 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
6373 * @param ADCx ADC instance
6374 * @retval State of bit (1 or 0).
6375 */
LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef * ADCx)6376 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
6377 {
6378 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
6379 }
6380
6381 /**
6382 * @brief Get flag ADC analog watchdog 3.
6383 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
6384 * @param ADCx ADC instance
6385 * @retval State of bit (1 or 0).
6386 */
LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef * ADCx)6387 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
6388 {
6389 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
6390 }
6391
6392 /**
6393 * @brief Clear flag ADC ready.
6394 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6395 * is enabled and when conversion clock is active.
6396 * (not only core clock: this ADC has a dual clock domain)
6397 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
6398 * @param ADCx ADC instance
6399 * @retval None
6400 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)6401 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
6402 {
6403 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
6404 }
6405
6406 /**
6407 * @brief Clear flag ADC group regular end of unitary conversion.
6408 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
6409 * @param ADCx ADC instance
6410 * @retval None
6411 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)6412 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
6413 {
6414 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
6415 }
6416
6417 /**
6418 * @brief Clear flag ADC group regular end of sequence conversions.
6419 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
6420 * @param ADCx ADC instance
6421 * @retval None
6422 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)6423 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
6424 {
6425 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
6426 }
6427
6428 /**
6429 * @brief Clear flag ADC group regular overrun.
6430 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
6431 * @param ADCx ADC instance
6432 * @retval None
6433 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)6434 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
6435 {
6436 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
6437 }
6438
6439 /**
6440 * @brief Clear flag ADC group regular end of sampling phase.
6441 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
6442 * @param ADCx ADC instance
6443 * @retval None
6444 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)6445 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
6446 {
6447 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
6448 }
6449
6450 /**
6451 * @brief Clear flag ADC group injected end of unitary conversion.
6452 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
6453 * @param ADCx ADC instance
6454 * @retval None
6455 */
LL_ADC_ClearFlag_JEOC(ADC_TypeDef * ADCx)6456 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
6457 {
6458 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
6459 }
6460
6461 /**
6462 * @brief Clear flag ADC group injected end of sequence conversions.
6463 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
6464 * @param ADCx ADC instance
6465 * @retval None
6466 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)6467 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
6468 {
6469 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
6470 }
6471
6472 /**
6473 * @brief Clear flag ADC group injected contexts queue overflow.
6474 * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
6475 * @param ADCx ADC instance
6476 * @retval None
6477 */
LL_ADC_ClearFlag_JQOVF(ADC_TypeDef * ADCx)6478 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
6479 {
6480 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
6481 }
6482
6483 /**
6484 * @brief Clear flag ADC analog watchdog 1.
6485 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
6486 * @param ADCx ADC instance
6487 * @retval None
6488 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)6489 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
6490 {
6491 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
6492 }
6493
6494 /**
6495 * @brief Clear flag ADC analog watchdog 2.
6496 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
6497 * @param ADCx ADC instance
6498 * @retval None
6499 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)6500 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
6501 {
6502 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
6503 }
6504
6505 /**
6506 * @brief Clear flag ADC analog watchdog 3.
6507 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
6508 * @param ADCx ADC instance
6509 * @retval None
6510 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)6511 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
6512 {
6513 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
6514 }
6515
6516 #if defined(ADC_MULTIMODE_SUPPORT)
6517 /**
6518 * @brief Get flag multimode ADC ready of the ADC master.
6519 * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
6520 * @param ADCxy_COMMON ADC common instance
6521 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6522 * @retval State of bit (1 or 0).
6523 */
LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef * ADCxy_COMMON)6524 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
6525 {
6526 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
6527 }
6528
6529 /**
6530 * @brief Get flag multimode ADC ready of the ADC slave.
6531 * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
6532 * @param ADCxy_COMMON ADC common instance
6533 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6534 * @retval State of bit (1 or 0).
6535 */
LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef * ADCxy_COMMON)6536 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
6537 {
6538 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
6539 }
6540
6541 /**
6542 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
6543 * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
6544 * @param ADCxy_COMMON ADC common instance
6545 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6546 * @retval State of bit (1 or 0).
6547 */
LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef * ADCxy_COMMON)6548 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
6549 {
6550 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
6551 }
6552
6553 /**
6554 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
6555 * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
6556 * @param ADCxy_COMMON ADC common instance
6557 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6558 * @retval State of bit (1 or 0).
6559 */
LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef * ADCxy_COMMON)6560 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
6561 {
6562 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
6563 }
6564
6565 /**
6566 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
6567 * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
6568 * @param ADCxy_COMMON ADC common instance
6569 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6570 * @retval State of bit (1 or 0).
6571 */
LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef * ADCxy_COMMON)6572 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
6573 {
6574 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
6575 }
6576
6577 /**
6578 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
6579 * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
6580 * @param ADCxy_COMMON ADC common instance
6581 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6582 * @retval State of bit (1 or 0).
6583 */
LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef * ADCxy_COMMON)6584 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
6585 {
6586 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
6587 }
6588
6589 /**
6590 * @brief Get flag multimode ADC group regular overrun of the ADC master.
6591 * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
6592 * @param ADCxy_COMMON ADC common instance
6593 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6594 * @retval State of bit (1 or 0).
6595 */
LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef * ADCxy_COMMON)6596 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
6597 {
6598 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
6599 }
6600
6601 /**
6602 * @brief Get flag multimode ADC group regular overrun of the ADC slave.
6603 * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
6604 * @param ADCxy_COMMON ADC common instance
6605 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6606 * @retval State of bit (1 or 0).
6607 */
LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef * ADCxy_COMMON)6608 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
6609 {
6610 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
6611 }
6612
6613 /**
6614 * @brief Get flag multimode ADC group regular end of sampling of the ADC master.
6615 * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
6616 * @param ADCxy_COMMON ADC common instance
6617 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6618 * @retval State of bit (1 or 0).
6619 */
LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef * ADCxy_COMMON)6620 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
6621 {
6622 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
6623 }
6624
6625 /**
6626 * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
6627 * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
6628 * @param ADCxy_COMMON ADC common instance
6629 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6630 * @retval State of bit (1 or 0).
6631 */
LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef * ADCxy_COMMON)6632 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
6633 {
6634 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
6635 }
6636
6637 /**
6638 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
6639 * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
6640 * @param ADCxy_COMMON ADC common instance
6641 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6642 * @retval State of bit (1 or 0).
6643 */
LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef * ADCxy_COMMON)6644 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
6645 {
6646 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
6647 }
6648
6649 /**
6650 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
6651 * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
6652 * @param ADCxy_COMMON ADC common instance
6653 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6654 * @retval State of bit (1 or 0).
6655 */
LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef * ADCxy_COMMON)6656 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
6657 {
6658 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
6659 }
6660
6661 /**
6662 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
6663 * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
6664 * @param ADCxy_COMMON ADC common instance
6665 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6666 * @retval State of bit (1 or 0).
6667 */
LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)6668 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
6669 {
6670 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
6671 }
6672
6673 /**
6674 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
6675 * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
6676 * @param ADCxy_COMMON ADC common instance
6677 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6678 * @retval State of bit (1 or 0).
6679 */
LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)6680 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
6681 {
6682 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
6683 }
6684
6685 /**
6686 * @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
6687 * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
6688 * @param ADCxy_COMMON ADC common instance
6689 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6690 * @retval State of bit (1 or 0).
6691 */
LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef * ADCxy_COMMON)6692 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
6693 {
6694 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
6695 }
6696
6697 /**
6698 * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
6699 * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
6700 * @param ADCxy_COMMON ADC common instance
6701 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6702 * @retval State of bit (1 or 0).
6703 */
LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef * ADCxy_COMMON)6704 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
6705 {
6706 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
6707 }
6708
6709 /**
6710 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
6711 * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
6712 * @param ADCxy_COMMON ADC common instance
6713 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6714 * @retval State of bit (1 or 0).
6715 */
LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)6716 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
6717 {
6718 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
6719 }
6720
6721 /**
6722 * @brief Get flag multimode analog watchdog 1 of the ADC slave.
6723 * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
6724 * @param ADCxy_COMMON ADC common instance
6725 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6726 * @retval State of bit (1 or 0).
6727 */
LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)6728 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
6729 {
6730 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
6731 }
6732
6733 /**
6734 * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
6735 * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
6736 * @param ADCxy_COMMON ADC common instance
6737 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6738 * @retval State of bit (1 or 0).
6739 */
LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef * ADCxy_COMMON)6740 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
6741 {
6742 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
6743 }
6744
6745 /**
6746 * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
6747 * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
6748 * @param ADCxy_COMMON ADC common instance
6749 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6750 * @retval State of bit (1 or 0).
6751 */
LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef * ADCxy_COMMON)6752 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
6753 {
6754 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
6755 }
6756
6757 /**
6758 * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
6759 * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
6760 * @param ADCxy_COMMON ADC common instance
6761 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6762 * @retval State of bit (1 or 0).
6763 */
LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef * ADCxy_COMMON)6764 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
6765 {
6766 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
6767 }
6768
6769 /**
6770 * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
6771 * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
6772 * @param ADCxy_COMMON ADC common instance
6773 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6774 * @retval State of bit (1 or 0).
6775 */
LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef * ADCxy_COMMON)6776 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
6777 {
6778 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
6779 }
6780 #endif /* ADC_MULTIMODE_SUPPORT */
6781
6782 /**
6783 * @}
6784 */
6785
6786 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
6787 * @{
6788 */
6789
6790 /**
6791 * @brief Enable ADC ready.
6792 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
6793 * @param ADCx ADC instance
6794 * @retval None
6795 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)6796 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
6797 {
6798 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
6799 }
6800
6801 /**
6802 * @brief Enable interruption ADC group regular end of unitary conversion.
6803 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
6804 * @param ADCx ADC instance
6805 * @retval None
6806 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)6807 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
6808 {
6809 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
6810 }
6811
6812 /**
6813 * @brief Enable interruption ADC group regular end of sequence conversions.
6814 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
6815 * @param ADCx ADC instance
6816 * @retval None
6817 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)6818 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
6819 {
6820 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
6821 }
6822
6823 /**
6824 * @brief Enable ADC group regular interruption overrun.
6825 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
6826 * @param ADCx ADC instance
6827 * @retval None
6828 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)6829 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
6830 {
6831 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
6832 }
6833
6834 /**
6835 * @brief Enable interruption ADC group regular end of sampling.
6836 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
6837 * @param ADCx ADC instance
6838 * @retval None
6839 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)6840 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
6841 {
6842 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
6843 }
6844
6845 /**
6846 * @brief Enable interruption ADC group injected end of unitary conversion.
6847 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
6848 * @param ADCx ADC instance
6849 * @retval None
6850 */
LL_ADC_EnableIT_JEOC(ADC_TypeDef * ADCx)6851 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
6852 {
6853 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
6854 }
6855
6856 /**
6857 * @brief Enable interruption ADC group injected end of sequence conversions.
6858 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
6859 * @param ADCx ADC instance
6860 * @retval None
6861 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)6862 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
6863 {
6864 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
6865 }
6866
6867 /**
6868 * @brief Enable interruption ADC group injected context queue overflow.
6869 * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
6870 * @param ADCx ADC instance
6871 * @retval None
6872 */
LL_ADC_EnableIT_JQOVF(ADC_TypeDef * ADCx)6873 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
6874 {
6875 SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
6876 }
6877
6878 /**
6879 * @brief Enable interruption ADC analog watchdog 1.
6880 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
6881 * @param ADCx ADC instance
6882 * @retval None
6883 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)6884 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
6885 {
6886 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
6887 }
6888
6889 /**
6890 * @brief Enable interruption ADC analog watchdog 2.
6891 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
6892 * @param ADCx ADC instance
6893 * @retval None
6894 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)6895 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
6896 {
6897 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
6898 }
6899
6900 /**
6901 * @brief Enable interruption ADC analog watchdog 3.
6902 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
6903 * @param ADCx ADC instance
6904 * @retval None
6905 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)6906 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
6907 {
6908 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
6909 }
6910
6911 /**
6912 * @brief Disable interruption ADC ready.
6913 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
6914 * @param ADCx ADC instance
6915 * @retval None
6916 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)6917 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
6918 {
6919 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
6920 }
6921
6922 /**
6923 * @brief Disable interruption ADC group regular end of unitary conversion.
6924 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
6925 * @param ADCx ADC instance
6926 * @retval None
6927 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)6928 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
6929 {
6930 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
6931 }
6932
6933 /**
6934 * @brief Disable interruption ADC group regular end of sequence conversions.
6935 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
6936 * @param ADCx ADC instance
6937 * @retval None
6938 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)6939 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
6940 {
6941 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
6942 }
6943
6944 /**
6945 * @brief Disable interruption ADC group regular overrun.
6946 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
6947 * @param ADCx ADC instance
6948 * @retval None
6949 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)6950 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
6951 {
6952 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
6953 }
6954
6955 /**
6956 * @brief Disable interruption ADC group regular end of sampling.
6957 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
6958 * @param ADCx ADC instance
6959 * @retval None
6960 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)6961 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
6962 {
6963 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
6964 }
6965
6966 /**
6967 * @brief Disable interruption ADC group regular end of unitary conversion.
6968 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
6969 * @param ADCx ADC instance
6970 * @retval None
6971 */
LL_ADC_DisableIT_JEOC(ADC_TypeDef * ADCx)6972 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
6973 {
6974 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
6975 }
6976
6977 /**
6978 * @brief Disable interruption ADC group injected end of sequence conversions.
6979 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
6980 * @param ADCx ADC instance
6981 * @retval None
6982 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)6983 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
6984 {
6985 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
6986 }
6987
6988 /**
6989 * @brief Disable interruption ADC group injected context queue overflow.
6990 * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
6991 * @param ADCx ADC instance
6992 * @retval None
6993 */
LL_ADC_DisableIT_JQOVF(ADC_TypeDef * ADCx)6994 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
6995 {
6996 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
6997 }
6998
6999 /**
7000 * @brief Disable interruption ADC analog watchdog 1.
7001 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
7002 * @param ADCx ADC instance
7003 * @retval None
7004 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)7005 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
7006 {
7007 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7008 }
7009
7010 /**
7011 * @brief Disable interruption ADC analog watchdog 2.
7012 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
7013 * @param ADCx ADC instance
7014 * @retval None
7015 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)7016 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
7017 {
7018 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7019 }
7020
7021 /**
7022 * @brief Disable interruption ADC analog watchdog 3.
7023 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
7024 * @param ADCx ADC instance
7025 * @retval None
7026 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)7027 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
7028 {
7029 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7030 }
7031
7032 /**
7033 * @brief Get state of interruption ADC ready
7034 * (0: interrupt disabled, 1: interrupt enabled).
7035 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
7036 * @param ADCx ADC instance
7037 * @retval State of bit (1 or 0).
7038 */
LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef * ADCx)7039 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
7040 {
7041 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
7042 }
7043
7044 /**
7045 * @brief Get state of interruption ADC group regular end of unitary conversion
7046 * (0: interrupt disabled, 1: interrupt enabled).
7047 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
7048 * @param ADCx ADC instance
7049 * @retval State of bit (1 or 0).
7050 */
LL_ADC_IsEnabledIT_EOC(ADC_TypeDef * ADCx)7051 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
7052 {
7053 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
7054 }
7055
7056 /**
7057 * @brief Get state of interruption ADC group regular end of sequence conversions
7058 * (0: interrupt disabled, 1: interrupt enabled).
7059 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
7060 * @param ADCx ADC instance
7061 * @retval State of bit (1 or 0).
7062 */
LL_ADC_IsEnabledIT_EOS(ADC_TypeDef * ADCx)7063 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
7064 {
7065 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
7066 }
7067
7068 /**
7069 * @brief Get state of interruption ADC group regular overrun
7070 * (0: interrupt disabled, 1: interrupt enabled).
7071 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
7072 * @param ADCx ADC instance
7073 * @retval State of bit (1 or 0).
7074 */
LL_ADC_IsEnabledIT_OVR(ADC_TypeDef * ADCx)7075 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
7076 {
7077 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
7078 }
7079
7080 /**
7081 * @brief Get state of interruption ADC group regular end of sampling
7082 * (0: interrupt disabled, 1: interrupt enabled).
7083 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
7084 * @param ADCx ADC instance
7085 * @retval State of bit (1 or 0).
7086 */
LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef * ADCx)7087 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
7088 {
7089 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
7090 }
7091
7092 /**
7093 * @brief Get state of interruption ADC group injected end of unitary conversion
7094 * (0: interrupt disabled, 1: interrupt enabled).
7095 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
7096 * @param ADCx ADC instance
7097 * @retval State of bit (1 or 0).
7098 */
LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef * ADCx)7099 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
7100 {
7101 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
7102 }
7103
7104 /**
7105 * @brief Get state of interruption ADC group injected end of sequence conversions
7106 * (0: interrupt disabled, 1: interrupt enabled).
7107 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
7108 * @param ADCx ADC instance
7109 * @retval State of bit (1 or 0).
7110 */
LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef * ADCx)7111 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
7112 {
7113 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
7114 }
7115
7116 /**
7117 * @brief Get state of interruption ADC group injected context queue overflow interrupt state
7118 * (0: interrupt disabled, 1: interrupt enabled).
7119 * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
7120 * @param ADCx ADC instance
7121 * @retval State of bit (1 or 0).
7122 */
LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef * ADCx)7123 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
7124 {
7125 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
7126 }
7127
7128 /**
7129 * @brief Get state of interruption ADC analog watchdog 1
7130 * (0: interrupt disabled, 1: interrupt enabled).
7131 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
7132 * @param ADCx ADC instance
7133 * @retval State of bit (1 or 0).
7134 */
LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef * ADCx)7135 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
7136 {
7137 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
7138 }
7139
7140 /**
7141 * @brief Get state of interruption Get ADC analog watchdog 2
7142 * (0: interrupt disabled, 1: interrupt enabled).
7143 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
7144 * @param ADCx ADC instance
7145 * @retval State of bit (1 or 0).
7146 */
LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef * ADCx)7147 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
7148 {
7149 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
7150 }
7151
7152 /**
7153 * @brief Get state of interruption Get ADC analog watchdog 3
7154 * (0: interrupt disabled, 1: interrupt enabled).
7155 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
7156 * @param ADCx ADC instance
7157 * @retval State of bit (1 or 0).
7158 */
LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef * ADCx)7159 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
7160 {
7161 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
7162 }
7163
7164 /**
7165 * @}
7166 */
7167
7168 #if defined(USE_FULL_LL_DRIVER)
7169 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
7170 * @{
7171 */
7172
7173 /* Initialization of some features of ADC common parameters and multimode */
7174 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
7175 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
7176 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
7177
7178 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
7179 /* (availability of ADC group injected depends on STM32 families) */
7180 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
7181
7182 /* Initialization of some features of ADC instance */
7183 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
7184 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
7185
7186 /* Initialization of some features of ADC instance and ADC group regular */
7187 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
7188 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
7189
7190 /* Initialization of some features of ADC instance and ADC group injected */
7191 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
7192 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
7193
7194 /**
7195 * @}
7196 */
7197 #endif /* USE_FULL_LL_DRIVER */
7198
7199 /**
7200 * @}
7201 */
7202
7203 /**
7204 * @}
7205 */
7206
7207 #endif /* ADC1 || ADC2 */
7208
7209 /**
7210 * @}
7211 */
7212
7213 #ifdef __cplusplus
7214 }
7215 #endif
7216
7217 #endif /* STM32MP1xx_LL_ADC_H */
7218
