1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_pwr.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32MP1xx_HAL_PWR_H 22 #define __STM32MP1xx_HAL_PWR_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32mp1xx_hal_def.h" 30 31 /** @addtogroup STM32MP1xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup PWR 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup PWR_Exported_Types PWR Exported Types 41 * @{ 42 */ 43 /** 44 * @brief PWR PVD configuration structure definition 45 */ 46 typedef struct 47 { 48 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. 49 This parameter can be a value of @ref PWR_PVD_detection_level */ 50 51 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. 52 This parameter can be a value of @ref PWR_PVD_Mode */ 53 } PWR_PVDTypeDef; 54 /** 55 * @} 56 */ 57 58 /* Exported constants --------------------------------------------------------*/ 59 60 /** @defgroup PWR_Exported_Constants PWR Exported Constants 61 * @{ 62 */ 63 64 /** @defgroup PWR_PVD_detection_level PWR PVD detection level 65 * @{ 66 */ 67 #define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /* 1.95V */ 68 #define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /* 2.1V */ 69 #define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /* 2.25V */ 70 #define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /* 2.4V */ 71 #define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /* 2.55V */ 72 #define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /* 2.7V */ 73 #define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /* 2.85V */ 74 #define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /* External voltage level on PVD_IN 75 (compared to internal VREFINT) */ 76 77 #define IS_PWR_PVD_LEVEL(__LEVEL__) (((__LEVEL__) == PWR_PVDLEVEL_0) || ((__LEVEL__) == PWR_PVDLEVEL_1)|| \ 78 ((__LEVEL__) == PWR_PVDLEVEL_2) || ((__LEVEL__) == PWR_PVDLEVEL_3)|| \ 79 ((__LEVEL__) == PWR_PVDLEVEL_4) || ((__LEVEL__) == PWR_PVDLEVEL_5)|| \ 80 ((__LEVEL__) == PWR_PVDLEVEL_6) || ((__LEVEL__) == PWR_PVDLEVEL_7)) 81 /** 82 * @} 83 */ 84 85 /** @defgroup PWR_PVD_Mode PWR PVD Mode 86 * @{ 87 */ 88 #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Basic mode is used */ 89 #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ 90 #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ 91 #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 92 93 #define IS_PWR_PVD_MODE(__MODE__) (((__MODE__) == PWR_PVD_MODE_NORMAL) || ((__MODE__) == PWR_PVD_MODE_IT_RISING) || \ 94 ((__MODE__) == PWR_PVD_MODE_IT_FALLING) || ((__MODE__) == PWR_PVD_MODE_IT_RISING_FALLING)) 95 96 /** 97 * @} 98 */ 99 100 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP_mode 101 * @{ 102 */ 103 #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) 104 #define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS 105 106 #define IS_PWR_REGULATOR(__REGULATOR__) (((__REGULATOR__) == PWR_MAINREGULATOR_ON) || \ 107 ((__REGULATOR__) == PWR_LOWPOWERREGULATOR_ON)) 108 /** 109 * @} 110 */ 111 112 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry 113 * @{ 114 */ 115 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) 116 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) 117 #define IS_PWR_SLEEP_ENTRY(__ENTRY__) (((__ENTRY__) == PWR_SLEEPENTRY_WFI) || ((__ENTRY__) == PWR_SLEEPENTRY_WFE)) 118 /** 119 * @} 120 */ 121 122 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry 123 * @{ 124 */ 125 #define PWR_STOPENTRY_WFI ((uint8_t)0x01) 126 #define PWR_STOPENTRY_WFE ((uint8_t)0x02) 127 128 #define IS_PWR_STOP_ENTRY(__ENTRY__) (((__ENTRY__) == PWR_STOPENTRY_WFI) || ((__ENTRY__) == PWR_STOPENTRY_WFE)) 129 /** 130 * @} 131 */ 132 133 134 135 /** @defgroup PWR_Flag PWR Flag 136 * @{ 137 */ 138 #define PWR_FLAG_SB ((uint8_t)0x01U) /* System STANDBY Flag */ 139 #define PWR_FLAG_STOP ((uint8_t)0x02U) /* STOP Flag */ 140 #define PWR_FLAG_CSB ((uint8_t)0x03U) /* MPU CSTANBY flag */ 141 #define PWR_FLAG_AVDO ((uint8_t)0x06U) 142 #define PWR_FLAG_PVDO ((uint8_t)0x07U) 143 #define PWR_FLAG_BRR ((uint8_t)0x08U) 144 #define PWR_FLAG_RRR ((uint8_t)0x09U) 145 #define PWR_FLAG_VBATL ((uint8_t)0x0AU) 146 #define PWR_FLAG_VBATH ((uint8_t)0x0BU) 147 #define PWR_FLAG_TEMPL ((uint8_t)0x0CU) 148 #define PWR_FLAG_TEMPH ((uint8_t)0x0DU) 149 #define PWR_FLAG_11R ((uint8_t)0x0EU) 150 #define PWR_FLAG_18R ((uint8_t)0x0FU) 151 #define PWR_FLAG_USB ((uint8_t)0x10U) 152 /** 153 * @} 154 */ 155 156 /** 157 * @} 158 */ 159 160 161 /* Exported macro ------------------------------------------------------------*/ 162 163 /** @defgroup PWR_Exported_Macro PWR Exported Macro 164 * @{ 165 */ 166 167 /** @brief Check PWR flag is set or not. 168 * @param __FLAG__: specifies the flag to check. 169 * This parameter can be one of the following values: 170 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 171 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode 172 * @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled 173 * by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode 174 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was 175 * resumed from StandBy mode. 176 * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset 177 * when the device wakes up from Standby mode or by a system reset 178 * or power reset. 179 * @arg PWR_FLAG_RRR: Retention Regulator ready flag. This bit is not reset 180 * when the device wakes up from Standby mode or by a system reset 181 * or power reset. 182 * @arg PWR_FLAG_VBATL: 183 * @arg PWR_FLAG_VBATH: 184 * @arg PWR_FLAG_TEMPL: 185 * @arg PWR_FLAG_TEMPH: 186 * @arg PWR_FLAG_11R: 1V1 regulator supply ready 187 * @arg PWR_FLAG_18R: 1V8 regulator supply ready 188 * @arg PWR_FLAG_USB: USB 3.3V supply ready 189 * @arg PWR_FLAG_SB: StandBy flag 190 * @arg PWR_FLAG_STOP: STOP flag 191 * @arg PWR_FLAG_CSB_MPU: MPU CSTANBY flag 192 * 193 * @retval The new state of __FLAG__ (TRUE or FALSE). 194 */ 195 #ifdef CORE_CM4 196 #define __HAL_PWR_GET_FLAG(__FLAG__) ( \ 197 ((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \ 198 ((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \ 199 ((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \ 200 ((__FLAG__) == PWR_FLAG_RRR)?((PWR->CR2 & PWR_CR2_RRRDY) == PWR_CR2_RRRDY) : \ 201 ((__FLAG__) == PWR_FLAG_VBATL)?((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL) : \ 202 ((__FLAG__) == PWR_FLAG_VBATH)?((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) : \ 203 ((__FLAG__) == PWR_FLAG_TEMPL)?((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) : \ 204 ((__FLAG__) == PWR_FLAG_TEMPH)?((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) : \ 205 ((__FLAG__) == PWR_FLAG_11R)?((PWR->CR3 & PWR_CR3_REG11RDY) == PWR_CR3_REG11RDY) : \ 206 ((__FLAG__) == PWR_FLAG_18R)?((PWR->CR3 & PWR_CR3_REG18RDY) == PWR_CR3_REG18RDY) : \ 207 ((__FLAG__) == PWR_FLAG_USB)?((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) : \ 208 ((__FLAG__) == PWR_FLAG_SB)?((PWR->MCUCR & PWR_MCUCR_SBF) == PWR_MCUCR_SBF) : \ 209 ((__FLAG__) == PWR_FLAG_STOP)?((PWR->MCUCR & PWR_MCUCR_STOPF) == PWR_MCUCR_STOPF) : \ 210 ((PWR->MPUCR & PWR_MPUCR_SBF_MPU) == PWR_MPUCR_SBF_MPU)) 211 #elif defined (CORE_CA7) 212 #define __HAL_PWR_GET_FLAG(__FLAG__) ( \ 213 ((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \ 214 ((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \ 215 ((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \ 216 ((__FLAG__) == PWR_FLAG_RRR)?((PWR->CR2 & PWR_CR2_RRRDY) == PWR_CR2_RRRDY) : \ 217 ((__FLAG__) == PWR_FLAG_VBATL)?((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL) : \ 218 ((__FLAG__) == PWR_FLAG_VBATH)?((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) : \ 219 ((__FLAG__) == PWR_FLAG_TEMPL)?((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) : \ 220 ((__FLAG__) == PWR_FLAG_TEMPH)?((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) : \ 221 ((__FLAG__) == PWR_FLAG_11R)?((PWR->CR3 & PWR_CR3_REG11RDY) == PWR_CR3_REG11RDY) : \ 222 ((__FLAG__) == PWR_FLAG_18R)?((PWR->CR3 & PWR_CR3_REG18RDY) == PWR_CR3_REG18RDY) : \ 223 ((__FLAG__) == PWR_FLAG_USB)?((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) : \ 224 ((__FLAG__) == PWR_FLAG_SB)?((PWR->MPUCR & PWR_MPUCR_SBF) == PWR_MPUCR_SBF) : \ 225 ((__FLAG__) == PWR_FLAG_STOP)?((PWR->MPUCR & PWR_MPUCR_STOPF) == PWR_MPUCR_STOPF) : \ 226 ((PWR->MPUCR & PWR_MPUCR_SBF_MPU) == PWR_MPUCR_SBF_MPU)) 227 #endif /*CORE_CA7*/ 228 229 #ifdef CORE_CM4 230 /** @brief Clear the PWR's flags. 231 * @param __FLAG__: specifies the flag to clear. 232 * This parameter can be one of the following values: 233 * @arg @ref PWR_FLAG_STOP 234 * @arg @ref PWR_FLAG_SB 235 * @retval None. 236 */ 237 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->MCUCR, PWR_MCUCR_CSSF); 238 #elif defined (CORE_CA7) 239 /** @brief Clear the PWR's flags. 240 * @param __FLAG__: specifies the flag to clear. 241 * This parameter can be one of the following values: 242 * @arg @ref PWR_FLAG_STOP 243 * @arg @ref PWR_FLAG_SB 244 * @arg @ref PWR_FLAG_CSB flags 245 * @retval None. 246 */ 247 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->MPUCR, PWR_MPUCR_CSSF); 248 249 250 #endif /*CORE_CA7*/ 251 252 253 /** 254 * @brief Enable the PVD AVD Exti Line. 255 * @retval None. 256 */ 257 #ifdef CORE_CM4 258 #define __HAL_PWR_PVD_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI_C2->IMR1, PWR_EXTI_LINE_PVD_AVD) 259 #elif defined (CORE_CA7) 260 #define __HAL_PWR_PVD_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI_C1->IMR1, PWR_EXTI_LINE_PVD_AVD) 261 #endif /*CORE_CA7*/ 262 263 264 /** 265 * @brief Disable the PVD AVD EXTI Line. 266 * @retval None. 267 */ 268 #ifdef CORE_CM4 269 #define __HAL_PWR_PVD_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_C2->IMR1, PWR_EXTI_LINE_PVD_AVD) 270 #elif defined (CORE_CA7) 271 #define __HAL_PWR_PVD_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_C1->IMR1, PWR_EXTI_LINE_PVD_AVD) 272 #endif /*CORE_CA7*/ 273 274 275 /** 276 * @brief Enable the PVD AVD Extended Interrupt Rising Trigger. 277 * @retval None. 278 */ 279 #define __HAL_PWR_PVD_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD_AVD) 280 281 /** 282 * @brief Disable the PVD AVD Extended Interrupt Rising Trigger. 283 * @retval None. 284 */ 285 #define __HAL_PWR_PVD_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD_AVD) 286 287 288 /** 289 * @brief Enable the PVD AVD Extended Interrupt Falling Trigger. 290 * @retval None. 291 */ 292 #define __HAL_PWR_PVD_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD_AVD) 293 294 295 /** 296 * @brief Disable the PVD AVD Extended Interrupt Falling Trigger. 297 * @retval None. 298 */ 299 #define __HAL_PWR_PVD_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD_AVD) 300 301 302 /** 303 * @brief PVD AVD EXTI line configuration: set rising & falling edge trigger. 304 * @retval None. 305 */ 306 #define __HAL_PWR_PVD_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ 307 do { \ 308 __HAL_PWR_PVD_AVD_EXTI_ENABLE_RISING_EDGE(); \ 309 __HAL_PWR_PVD_AVD_EXTI_ENABLE_FALLING_EDGE(); \ 310 } while(0); 311 312 /** 313 * @brief Disable the PVD AVD Extended Interrupt Rising & Falling Trigger. 314 * @retval None. 315 */ 316 #define __HAL_PWR_PVD_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ 317 do { \ 318 __HAL_PWR_PVD_AVD_EXTI_DISABLE_RISING_EDGE(); \ 319 __HAL_PWR_PVD_AVD_EXTI_DISABLE_FALLING_EDGE(); \ 320 } while(0); 321 322 323 /** 324 * @brief Check whether the specified PVD AVD EXTI interrupt flag is set or not. 325 * @retval EXTI PVD AVD Line Status. 326 */ 327 #define __HAL_PWR_PVD_AVD_EXTI_GET_FLAG() \ 328 (((EXTI->RPR1 & PWR_EXTI_LINE_PVD_AVD) == PWR_EXTI_LINE_PVD_AVD) || \ 329 ((EXTI->FPR1 & PWR_EXTI_LINE_PVD_AVD) == PWR_EXTI_LINE_PVD_AVD)) 330 331 332 /** 333 * @brief Clear the PVD AVD Exti flag. 334 * @retval None. 335 */ 336 #define __HAL_PWR_PVD_AVD_EXTI_CLEAR_FLAG() \ 337 do { \ 338 SET_BIT(EXTI->RPR1, PWR_EXTI_LINE_PVD_AVD); \ 339 SET_BIT(EXTI->FPR1, PWR_EXTI_LINE_PVD_AVD); \ 340 } while(0); 341 342 343 /** 344 * @brief Generates a Software interrupt on selected EXTI line. 345 * @retval None 346 */ 347 /* PVD AVD Event in Bank1 */ 348 #define __HAL_PWR_PVD_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD_AVD ) 349 350 351 /* Include PWR HAL Extension module */ 352 #include "stm32mp1xx_hal_pwr_ex.h" 353 354 /** 355 * @brief Enable WKUPx pin wakeup interrupt on AIEC for core 2. 356 * @param __WKUP_LINE__: specifies the WKUP pin line. 357 * This parameter can be one of the following values: 358 * @arg AIEC_WKUP1_WAKEUP: Wakeup pin 1 line 359 * @arg AIEC_WKUP1_WAKEUP: Wakeup pin 2 line 360 * @arg AIEC_WKUP1_WAKEUP: Wakeup pin 3 line 361 * @arg AIEC_WKUP1_WAKEUP: Wakeup pin 4 line 362 * @arg AIEC_WKUP1_WAKEUP: Wakeup pin 5 line 363 * @arg AIEC_WKUP1_WAKEUP: Wakeup pin 6 line 364 * @retval None 365 */ 366 #ifdef CORE_CM4 367 #define __HAL_WKUP_EXTI_ENABLE_IT(__WKUP_LINE__) (EXTI_C2->IMR2 |= (__WKUP_LINE__)) 368 #elif defined(CORE_CA7) 369 #define __HAL_WKUP_EXTI_ENABLE_IT(__WKUP_LINE__) (EXTI_C1->IMR2 |= (__WKUP_LINE__)) 370 #endif /*CORE_CA7*/ 371 372 /** 373 * @brief Disable WKUPx pin wakeup interrupt on AIEC for core 2. 374 * * @param __WKUP_LINE__: specifies the WKUP pin line. 375 * This parameter can be one of the following values: 376 * @arg AIEC_WKUP1_WAKEUP: Wakeup pin 1 line 377 * @arg AIEC_WKUP2_WAKEUP: Wakeup pin 2 line 378 * @arg AIEC_WKUP3_WAKEUP: Wakeup pin 3 line 379 * @arg AIEC_WKUP4_WAKEUP: Wakeup pin 4 line 380 * @arg AIEC_WKUP5_WAKEUP: Wakeup pin 5 line 381 * @arg AIEC_WKUP6_WAKEUP: Wakeup pin 6 line 382 * @retval None 383 */ 384 #ifdef CORE_CM4 385 #define __HAL_WKUP_EXTI_DISABLE_IT(__WKUP_LINE__) CLEAR_BIT(EXTI_C2->IMR2, __WKUP_LINE__) 386 #elif defined(CORE_CA7) 387 #define __HAL_WKUP_EXTI_DISABLE_IT(__WKUP_LINE__) CLEAR_BIT(EXTI_C1->IMR2, __WKUP_LINE__) 388 #endif /*CORE_CA7*/ 389 390 /** 391 * @} 392 */ 393 394 395 396 /* Exported functions --------------------------------------------------------*/ 397 /** @defgroup PWR_Exported_Functions PWR Exported Functions 398 * @{ 399 */ 400 401 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 402 * @{ 403 */ 404 /* Initialization and de-initialization functions *****************************/ 405 void HAL_PWR_DeInit(void); 406 void HAL_PWR_EnableBkUpAccess(void); 407 void HAL_PWR_DisableBkUpAccess(void); 408 /** 409 * @} 410 */ 411 412 /* Peripheral Control functions **********************************************/ 413 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions 414 * @{ 415 */ 416 /* PVD configuration */ 417 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); 418 void HAL_PWR_EnablePVD(void); 419 void HAL_PWR_DisablePVD(void); 420 421 /* WakeUp pins configuration */ 422 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); 423 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); 424 425 /* WakeUp pin IT functions */ 426 void HAL_PWR_EnableWakeUpPinIT(uint32_t WakeUpPinx); 427 void HAL_PWR_DisableWakeUpPinIT(uint32_t WakeUpPinx); 428 429 430 /* Low Power modes entry */ 431 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); 432 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); 433 void HAL_PWR_EnterSTANDBYMode(void); 434 435 436 /* Power PVD IRQ Callback */ 437 void HAL_PWR_PVDCallback(void); 438 439 /** 440 * @} 441 */ 442 443 /* Cortex System Control functions *******************************************/ 444 /** @defgroup PWR_Exported_Functions_Group3 Cortex System Control functions 445 * @{ 446 */ 447 void HAL_PWR_EnableSleepOnExit(void); 448 void HAL_PWR_DisableSleepOnExit(void); 449 void HAL_PWR_EnableSEVOnPend(void); 450 void HAL_PWR_DisableSEVOnPend(void); 451 /** 452 * @} 453 */ 454 455 /** 456 * @} 457 */ 458 459 460 /* Private constants ---------------------------------------------------------*/ 461 462 /** @defgroup PWR_Private_Constants PWR Private Constants 463 * @{ 464 */ 465 466 /** @defgroup PWR_EXTI_LINE_PVD_AVD PWR EXTI Line PVD AVD 467 * @{ 468 */ 469 #define PWR_EXTI_LINE_PVD_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16 470 Connected to the PVD AVD EXTI 471 Line */ 472 /** 473 * @} 474 */ 475 476 /** 477 * @} 478 */ 479 480 /** 481 * @} 482 */ 483 484 /** 485 * @} 486 */ 487 #ifdef __cplusplus 488 } 489 #endif 490 491 #endif /* __STM32MP1xx_HAL_PWR_H */ 492
