1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_mdma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32MP1xx_HAL_MDMA_H 21 #define STM32MP1xx_HAL_MDMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32mp1xx_hal_def.h" 29 30 /** @addtogroup STM32MP1xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup MDMA 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup MDMA_Exported_Types MDMA Exported Types 41 * @brief MDMA Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief MDMA Configuration Structure definition 47 */ 48 typedef struct 49 { 50 51 uint32_t Request; /*!< Specifies the MDMA request. 52 This parameter can be a value of @ref MDMA_Request_selection*/ 53 54 uint32_t TransferTriggerMode; /*!< Specifies the Trigger Transfer mode : each request triggers a : 55 a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer 56 This parameter can be a value of @ref MDMA_Transfer_TriggerMode */ 57 58 uint32_t Priority; /*!< Specifies the software priority for the MDMAy channelx. 59 This parameter can be a value of @ref MDMA_Priority_level */ 60 61 uint32_t SecureMode; /*!< Specifies if the MDMA master transactions are done in secure mode. 62 This parameter can be a value of @ref MDMA_Secure_Mode */ 63 64 uint32_t Endianness; /*!< Specifies if the MDMA transactions preserve the Little endianness. 65 This parameter can be a value of @ref MDMA_Endianness */ 66 67 uint32_t SourceInc; /*!< Specifies if the Source increment mode . 68 This parameter can be a value of @ref MDMA_Source_increment_mode */ 69 70 uint32_t DestinationInc; /*!< Specifies if the Destination increment mode . 71 This parameter can be a value of @ref MDMA_Destination_increment_mode */ 72 73 uint32_t SourceDataSize; /*!< Specifies the source data size. 74 This parameter can be a value of @ref MDMA_Source_data_size */ 75 76 uint32_t DestDataSize; /*!< Specifies the destination data size. 77 This parameter can be a value of @ref MDMA_Destination_data_size */ 78 79 80 uint32_t DataAlignment; /*!< Specifies the source to destination Memory data packing/padding mode. 81 This parameter can be a value of @ref MDMA_data_Alignment */ 82 83 uint32_t BufferTransferLength; /*!< Specifies the buffer Transfer Length (number of bytes), 84 this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/ 85 86 uint32_t SourceBurst; /*!< Specifies the Burst transfer configuration for the source memory transfers. 87 It specifies the amount of data to be transferred in a single non interruptable 88 transaction. 89 This parameter can be a value of @ref MDMA_Source_burst 90 @note : the burst may be FIXED/INCR based on SourceInc value , 91 the BURST must be programmed as to ensure that the burst size will be lower than than 92 BufferTransferLength */ 93 94 uint32_t DestBurst; /*!< Specifies the Burst transfer configuration for the destination memory transfers. 95 It specifies the amount of data to be transferred in a single non interruptable 96 transaction. 97 This parameter can be a value of @ref MDMA_Destination_burst 98 @note : the burst may be FIXED/INCR based on DestinationInc value , 99 the BURST must be programmed as to ensure that the burst size will be lower than than 100 BufferTransferLength */ 101 102 int32_t SourceBlockAddressOffset; /*!< this field specifies the Next block source address offset 103 signed value : if > 0 then increment the next block source Address by offset from where the last block ends 104 if < 0 then decrement the next block source Address by offset from where the last block ends 105 if == 0, the next block source address starts from where the last block ends 106 */ 107 108 109 int32_t DestBlockAddressOffset; /*!< this field specifies the Next block destination address offset 110 signed value : if > 0 then increment the next block destination Address by offset from where the last block ends 111 if < 0 then decrement the next block destination Address by offset from where the last block ends 112 if == 0, the next block destination address starts from where the last block ends 113 */ 114 115 }MDMA_InitTypeDef; 116 117 /** 118 * @brief HAL MDMA linked list node structure definition 119 * @note The Linked list node allows to define a new MDMA configuration 120 * (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers). 121 * When CLAR register is configured to a non NULL value , each time a transfer ends, 122 * a new configuration (linked list node) is automatically loaded from the address given in CLAR register. 123 */ 124 typedef struct 125 { 126 __IO uint32_t CTCR; /*!< New CTCR register configuration for the given MDMA linked list node */ 127 __IO uint32_t CBNDTR; /*!< New CBNDTR register configuration for the given MDMA linked list node */ 128 __IO uint32_t CSAR; /*!< New CSAR register configuration for the given MDMA linked list node */ 129 __IO uint32_t CDAR; /*!< New CDAR register configuration for the given MDMA linked list node */ 130 __IO uint32_t CBRUR; /*!< New CBRUR register configuration for the given MDMA linked list node */ 131 __IO uint32_t CLAR; /*!< New CLAR register configuration for the given MDMA linked list node */ 132 __IO uint32_t CTBR; /*!< New CTBR register configuration for the given MDMA linked list node */ 133 __IO uint32_t Reserved; /*!< Reserved register */ 134 __IO uint32_t CMAR; /*!< New CMAR register configuration for the given MDMA linked list node */ 135 __IO uint32_t CMDR; /*!< New CMDR register configuration for the given MDMA linked list node */ 136 137 }MDMA_LinkNodeTypeDef; 138 139 /** 140 * @brief HAL MDMA linked list node configuration structure definition 141 * @note used with HAL_MDMA_LinkedList_CreateNode function 142 */ 143 typedef struct 144 { 145 MDMA_InitTypeDef Init; /*!< configuration of the specified MDMA Linked List Node */ 146 uint32_t SrcAddress; /*!< The source memory address for the Linked list Node */ 147 uint32_t DstAddress; /*!< The destination memory address for the Linked list Node */ 148 uint32_t BlockDataLength; /*!< The data length of a block in bytes */ 149 uint32_t BlockCount; /*!< The number of blocks to be transferred */ 150 151 uint32_t PostRequestMaskAddress; /*!< specifies the address to be updated (written) with PostRequestMaskData after a request is served. 152 PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */ 153 154 uint32_t PostRequestMaskData; /*!< specifies the value to be written to PostRequestMaskAddress after a request is served. 155 PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */ 156 157 158 }MDMA_LinkNodeConfTypeDef; 159 160 161 /** 162 * @brief HAL MDMA State structure definition 163 */ 164 typedef enum 165 { 166 HAL_MDMA_STATE_RESET = 0x00U, /*!< MDMA not yet initialized or disabled */ 167 HAL_MDMA_STATE_READY = 0x01U, /*!< MDMA initialized and ready for use */ 168 HAL_MDMA_STATE_BUSY = 0x02U, /*!< MDMA process is ongoing */ 169 HAL_MDMA_STATE_ERROR = 0x03U, /*!< MDMA error state */ 170 HAL_MDMA_STATE_ABORT = 0x04U, /*!< MDMA Abort state */ 171 HAL_MDMA_STATE_TIMEOUT = 0x05U, /*!< MDMA timeout state */ 172 173 }HAL_MDMA_StateTypeDef; 174 175 /** 176 * @brief HAL MDMA Level Complete structure definition 177 */ 178 typedef enum 179 { 180 HAL_MDMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 181 HAL_MDMA_BUFFER_TRANSFER = 0x01U, /*!< Buffer Transfer */ 182 HAL_MDMA_BLOCK_TRANSFER = 0x02U, /*!< Block Transfer */ 183 HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U /*!< repeat block Transfer */ 184 185 }HAL_MDMA_LevelCompleteTypeDef; 186 187 /** 188 * @brief HAL MDMA Callbacks IDs structure definition 189 */ 190 typedef enum 191 { 192 HAL_MDMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 193 HAL_MDMA_XFER_BUFFERCPLT_CB_ID = 0x01U, /*!< Buffer Transfer */ 194 HAL_MDMA_XFER_BLOCKCPLT_CB_ID = 0x02U, /*!< Block Transfer */ 195 HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID = 0x03U, /*!< Repeated Block Transfer */ 196 HAL_MDMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ 197 HAL_MDMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ 198 HAL_MDMA_XFER_ALL_CB_ID = 0x06U /*!< All */ 199 200 }HAL_MDMA_CallbackIDTypeDef; 201 202 203 /** 204 * @brief MDMA handle Structure definition 205 */ 206 typedef struct __MDMA_HandleTypeDef 207 { 208 MDMA_Channel_TypeDef *Instance; /*!< Register base address */ 209 210 MDMA_InitTypeDef Init; /*!< MDMA communication parameters */ 211 212 HAL_LockTypeDef Lock; /*!< MDMA locking object */ 213 214 __IO HAL_MDMA_StateTypeDef State; /*!< MDMA transfer state */ 215 216 void *Parent; /*!< Parent object state */ 217 218 void (* XferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer complete callback */ 219 220 void (* XferBufferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA buffer transfer complete callback */ 221 222 void (* XferBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer complete callback */ 223 224 void (* XferRepeatBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer repeat callback */ 225 226 void (* XferErrorCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer error callback */ 227 228 void (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer Abort callback */ 229 230 231 MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress; /*!< specifies the first node address of the transfer list 232 (after the initial node defined by the Init struct) 233 this parameter is used internally by the MDMA driver 234 to construct the linked list node 235 */ 236 237 MDMA_LinkNodeTypeDef *LastLinkedListNodeAddress; /*!< specifies the last node address of the transfer list 238 this parameter is used internally by the MDMA driver 239 to construct the linked list node 240 */ 241 uint32_t LinkedListNodeCounter; /*!< Number of nodes in the MDMA linked list */ 242 243 __IO uint32_t ErrorCode; /*!< MDMA Error code */ 244 245 } MDMA_HandleTypeDef; 246 247 /** 248 * @} 249 */ 250 251 /* Exported constants --------------------------------------------------------*/ 252 253 /** @defgroup MDMA_Exported_Constants MDMA Exported Constants 254 * @brief MDMA Exported constants 255 * @{ 256 */ 257 258 /** @defgroup MDMA_Error_Codes MDMA Error Codes 259 * @brief MDMA Error Codes 260 * @{ 261 */ 262 #define HAL_MDMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 263 #define HAL_MDMA_ERROR_READ_XFER ((uint32_t)0x00000001U) /*!< Read Transfer error */ 264 #define HAL_MDMA_ERROR_WRITE_XFER ((uint32_t)0x00000002U) /*!< Write Transfer error */ 265 #define HAL_MDMA_ERROR_MASK_DATA ((uint32_t)0x00000004U) /*!< Error Mask Data error */ 266 #define HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U) /*!< Linked list Data error */ 267 #define HAL_MDMA_ERROR_ALIGNMENT ((uint32_t)0x00000010U) /*!< Address/Size alignment error */ 268 #define HAL_MDMA_ERROR_BLOCK_SIZE ((uint32_t)0x00000020U) /*!< Block Size error */ 269 #define HAL_MDMA_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */ 270 #define HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort or SW trigger requested with no Xfer ongoing */ 271 #define HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U) /*!< DeInit or SW trigger requested with Xfer ongoing */ 272 273 /** 274 * @} 275 */ 276 277 /** @defgroup MDMA_Request_selection MDMA Request selection 278 * @brief MDMA_Request_selection 279 * @{ 280 */ 281 282 #define MDMA_REQUEST_DMA1_Stream0_TC ((uint32_t)0x00000000U) /*!< MDMA HW request is DMA1 Stream 0 Transfer Complete Flag */ 283 #define MDMA_REQUEST_DMA1_Stream1_TC ((uint32_t)0x00000001U) /*!< MDMA HW request is DMA1 Stream 1 Transfer Complete Flag */ 284 #define MDMA_REQUEST_DMA1_Stream2_TC ((uint32_t)0x00000002U) /*!< MDMA HW request is DMA1 Stream 2 Transfer Complete Flag */ 285 #define MDMA_REQUEST_DMA1_Stream3_TC ((uint32_t)0x00000003U) /*!< MDMA HW request is DMA1 Stream 3 Transfer Complete Flag */ 286 #define MDMA_REQUEST_DMA1_Stream4_TC ((uint32_t)0x00000004U) /*!< MDMA HW request is DMA1 Stream 4 Transfer Complete Flag */ 287 #define MDMA_REQUEST_DMA1_Stream5_TC ((uint32_t)0x00000005U) /*!< MDMA HW request is DMA1 Stream 5 Transfer Complete Flag */ 288 #define MDMA_REQUEST_DMA1_Stream6_TC ((uint32_t)0x00000006U) /*!< MDMA HW request is DMA1 Stream 6 Transfer Complete Flag */ 289 #define MDMA_REQUEST_DMA1_Stream7_TC ((uint32_t)0x00000007U) /*!< MDMA HW request is DMA1 Stream 7 Transfer Complete Flag */ 290 #define MDMA_REQUEST_DMA2_Stream0_TC ((uint32_t)0x00000008U) /*!< MDMA HW request is DMA2 Stream 0 Transfer Complete Flag */ 291 #define MDMA_REQUEST_DMA2_Stream1_TC ((uint32_t)0x00000009U) /*!< MDMA HW request is DMA2 Stream 1 Transfer Complete Flag */ 292 #define MDMA_REQUEST_DMA2_Stream2_TC ((uint32_t)0x0000000AU) /*!< MDMA HW request is DMA2 Stream 2 Transfer Complete Flag */ 293 #define MDMA_REQUEST_DMA2_Stream3_TC ((uint32_t)0x0000000BU) /*!< MDMA HW request is DMA2 Stream 3 Transfer Complete Flag */ 294 #define MDMA_REQUEST_DMA2_Stream4_TC ((uint32_t)0x0000000CU) /*!< MDMA HW request is DMA2 Stream 4 Transfer Complete Flag */ 295 #define MDMA_REQUEST_DMA2_Stream5_TC ((uint32_t)0x0000000DU) /*!< MDMA HW request is DMA2 Stream 5 Transfer Complete Flag */ 296 #define MDMA_REQUEST_DMA2_Stream6_TC ((uint32_t)0x0000000EU) /*!< MDMA HW request is DMA2 Stream 6 Transfer Complete Flag */ 297 #define MDMA_REQUEST_DMA2_Stream7_TC ((uint32_t)0x0000000FU) /*!< MDMA HW request is DMA2 Stream 7 Transfer Complete Flag */ 298 #define MDMA_REQUEST_FMC_DATA ((uint32_t)0x00000014U) /*!< MDMA HW request is NAND data transfer (Tx or Rx) channel */ 299 #define MDMA_REQUEST_FMC_ERROR ((uint32_t)0x00000015U) /*!< MDMA HW request is NAND ECC/BCH Error channel */ 300 #define MDMA_REQUEST_QUADSPI_FIFO_TH ((uint32_t)0x00000016U) /*!< MDMA HW request is QSPI FIFO threshold Flag */ 301 #define MDMA_REQUEST_QUADSPI_TC ((uint32_t)0x00000017U) /*!< MDMA HW request is QSPI Transfer complete Flag */ 302 #if defined(CRYP1) 303 #define MDMA_REQUEST_CRYP1_IN ((uint32_t)0x0000001DU) /*!< MDMA HW request is CRYP1 4 word request from input */ 304 #define MDMA_REQUEST_CRYP1_OUT ((uint32_t)0x0000001EU) /*!< MDMA HW request is CRYP1 4 word request from output */ 305 #endif 306 #define MDMA_REQUEST_HASH1_IN ((uint32_t)0x0000001FU) /*!< MDMA HW request is HASH1 16 word request from input */ 307 #define MDMA_REQUEST_USART1_RX ((uint32_t)0x00000020U) /*!< MDMA HW request is USART1 Rx Transfer Complete Flag */ 308 #define MDMA_REQUEST_USART1_TX ((uint32_t)0x00000021U) /*!< MDMA HW request is USART1 Tx Transfer Complete Flag */ 309 #define MDMA_REQUEST_SPI6_RX ((uint32_t)0x00000022U) /*!< MDMA HW request is SPI6 Rx Transfer Complete Flag */ 310 #define MDMA_REQUEST_SPI6_TX ((uint32_t)0x00000023U) /*!< MDMA HW request is SPI6 Tx Transfer Complete Flag */ 311 #define MDMA_REQUEST_I2C4_RX ((uint32_t)0x00000024U) /*!< MDMA HW request is I2C4 Rx Transfer Complete Flag */ 312 #define MDMA_REQUEST_I2C4_TX ((uint32_t)0x00000025U) /*!< MDMA HW request is I2C4 Tx Transfer Complete Flag */ 313 #define MDMA_REQUEST_I2C6_RX ((uint32_t)0x00000026U) /*!< MDMA HW request is I2C6 Rx Transfer Complete Flag */ 314 #define MDMA_REQUEST_I2C6_TX ((uint32_t)0x00000027U) /*!< MDMA HW request is I2C6 Tx Transfer Complete Flag */ 315 #define MDMA_REQUEST_SW ((uint32_t)0x40000000U) /*!< MDMA SW request */ 316 /** 317 * @} 318 */ 319 320 /** @defgroup MDMA_Transfer_TriggerMode MDMA Transfer Trigger Mode 321 * @brief MDMA Transfer Trigger Mode 322 * @{ 323 */ 324 #define MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U) /*!< Each MDMA request (SW or HW) triggers a buffer transfer */ 325 #define MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0) /*!< Each MDMA request (SW or HW) triggers a block transfer */ 326 #define MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1) /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */ 327 #define MDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM) /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */ 328 329 /** 330 * @} 331 */ 332 333 /** @defgroup MDMA_Priority_level MDMA Priority level 334 * @brief MDMA Priority level 335 * @{ 336 */ 337 #define MDMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */ 338 #define MDMA_PRIORITY_MEDIUM ((uint32_t)MDMA_CCR_PL_0) /*!< Priority level: Medium */ 339 #define MDMA_PRIORITY_HIGH ((uint32_t)MDMA_CCR_PL_1) /*!< Priority level: High */ 340 #define MDMA_PRIORITY_VERY_HIGH ((uint32_t)MDMA_CCR_PL) /*!< Priority level: Very High */ 341 342 /** 343 * @} 344 */ 345 346 /** @defgroup MDMA_Secure_Mode MDMA Secure Mode 347 * @brief MDMA Secure Mode 348 * @{ 349 */ 350 #define MDMA_SECURE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< Secure Mode disabled */ 351 #define MDMA_SECURE_MODE_ENABLE ((uint32_t)MDMA_CCR_SM) /*!< Secure Mode enabled */ 352 353 /** 354 * @} 355 */ 356 357 /** @defgroup MDMA_Endianness MDMA Endianness 358 * @brief MDMA Endianness 359 * @{ 360 */ 361 #define MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U) /*!< little endianness preserve */ 362 #define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX) /*!< BYTEs endianness exchange when destination data size is > Byte */ 363 #define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX) /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD */ 364 #define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX) /*!< WORDs endianness exchange when destination data size is > DOUBLE WORD */ 365 366 /** 367 * @} 368 */ 369 370 /** @defgroup MDMA_Source_increment_mode MDMA Source increment mode 371 * @brief MDMA Source increment mode 372 * @{ 373 */ 374 #define MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */ 375 #define MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */ 376 #define MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */ 377 #define MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */ 378 #define MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */ 379 #define MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */ 380 #define MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */ 381 #define MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */ 382 #define MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */ 383 384 /** 385 * @} 386 */ 387 388 /** @defgroup MDMA_Destination_increment_mode MDMA Destination increment mode 389 * @brief MDMA Destination increment mode 390 * @{ 391 */ 392 #define MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */ 393 #define MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */ 394 #define MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */ 395 #define MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */ 396 #define MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */ 397 #define MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */ 398 #define MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */ 399 #define MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */ 400 #define MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */ 401 402 /** 403 * @} 404 */ 405 406 /** @defgroup MDMA_Source_data_size MDMA Source data size 407 * @brief MDMA Source data size 408 * @{ 409 */ 410 #define MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Source data size is Byte */ 411 #define MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0) /*!< Source data size is half word */ 412 #define MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1) /*!< Source data size is word */ 413 #define MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE) /*!< Source data size is double word */ 414 415 /** 416 * @} 417 */ 418 419 /** @defgroup MDMA_Destination_data_size MDMA Destination data size 420 * @brief MDMA Destination data size 421 * @{ 422 */ 423 #define MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Destination data size is Byte */ 424 #define MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0) /*!< Destination data size is half word */ 425 #define MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1) /*!< Destination data size is word */ 426 #define MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE) /*!< Destination data size is double word */ 427 428 /** 429 * @} 430 */ 431 432 /** @defgroup MDMA_data_Alignment MDMA data alignment 433 * @brief MDMA data alignment 434 * @{ 435 */ 436 #define MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE) /*!< The source data is packed/un-packed into the destination data size 437 All data are right aligned, in Little Endien mode. */ 438 #define MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< Right Aligned, padded w/ 0s (default) */ 439 #define MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0) /*!< Right Aligned, Sign extended , 440 Note : this mode is allowed only if the Source data size is smaller than Destination data size */ 441 #define MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1) /*!< Left Aligned (padded with 0s) */ 442 443 /** 444 * @} 445 */ 446 447 /** @defgroup MDMA_Source_burst MDMA Source burst 448 * @brief MDMA Source burst 449 * @{ 450 */ 451 #define MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */ 452 #define MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0) /*!< Burst 2 beats */ 453 #define MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 4 beats */ 454 #define MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */ 455 #define MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 16 beats */ 456 #define MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */ 457 #define MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */ 458 #define MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST) /*!< Burst 128 beats */ 459 460 /** 461 * @} 462 */ 463 464 /** @defgroup MDMA_Destination_burst MDMA Destination burst 465 * @brief MDMA Destination burst 466 * @{ 467 */ 468 #define MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */ 469 #define MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0) /*!< Burst 2 beats */ 470 #define MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 4 beats */ 471 #define MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 8 beats */ 472 #define MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 16 beats */ 473 #define MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 32 beats */ 474 #define MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 64 beats */ 475 #define MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST) /*!< Burst 128 beats */ 476 477 /** 478 * @} 479 */ 480 481 /** @defgroup MDMA_interrupt_enable_definitions MDMA interrupt enable definitions 482 * @brief MDMA interrupt enable definitions 483 * @{ 484 */ 485 #define MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE) /*!< Transfer Error interrupt */ 486 #define MDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE) /*!< Channel Transfer Complete interrupt */ 487 #define MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE) /*!< Block Repeat Transfer interrupt */ 488 #define MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE) /*!< Block Transfer interrupt */ 489 #define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE) /*!< Buffer Transfer Complete interrupt */ 490 491 /** 492 * @} 493 */ 494 495 /** @defgroup MDMA_flag_definitions MDMA flag definitions 496 * @brief MDMA flag definitions 497 * @{ 498 */ 499 #define MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF) /*!< Transfer Error flag */ 500 #define MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */ 501 #define MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */ 502 #define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) /*!< Block Transfer complete flag */ 503 #define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) /*!< BuFfer Transfer complete flag */ 504 #define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel ReQest Active flag */ 505 506 /** 507 * @} 508 */ 509 510 /** 511 * @} 512 */ 513 514 /* Exported macro ------------------------------------------------------------*/ 515 516 /** @defgroup MDMA_Exported_Macros MDMA Exported Macros 517 * @{ 518 */ 519 520 /** 521 * @brief Enable the specified MDMA Channel. 522 * @param __HANDLE__: MDMA handle 523 * @retval None 524 */ 525 #define __HAL_MDMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= MDMA_CCR_EN) 526 527 /** 528 * @brief Disable the specified MDMA Channel. 529 * @param __HANDLE__: MDMA handle 530 * @retval None 531 */ 532 #define __HAL_MDMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~MDMA_CCR_EN) 533 534 /** 535 * @brief Get the MDMA Channel pending flags. 536 * @param __HANDLE__: MDMA handle 537 * @param __FLAG__: Get the specified flag. 538 * This parameter can be any combination of the following values: 539 * @arg MDMA_FLAG_TE : Transfer Error flag. 540 * @arg MDMA_FLAG_CTC : Channel Transfer Complete flag. 541 * @arg MDMA_FLAG_BRT : Block Repeat Transfer flag. 542 * @arg MDMA_FLAG_BT : Block Transfer complete flag. 543 * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag. 544 * @arg MDMA_FLAG_CRQA : Channel ReQest Active flag. 545 * @retval The state of FLAG (SET or RESET). 546 */ 547 #define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__)) 548 549 /** 550 * @brief Clear the MDMA Stream pending flags. 551 * @param __HANDLE__: MDMA handle 552 * @param __FLAG__: specifies the flag to clear. 553 * This parameter can be any combination of the following values: 554 * @arg MDMA_FLAG_TE : Transfer Error flag. 555 * @arg MDMA_FLAG_CTC : Channel Transfer Complete flag. 556 * @arg MDMA_FLAG_BRT : Block Repeat Transfer flag. 557 * @arg MDMA_FLAG_BT : Block Transfer complete flag. 558 * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag. 559 * @retval None 560 */ 561 #define __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__)) 562 563 /** 564 * @brief Enables the specified MDMA Channel interrupts. 565 * @param __HANDLE__: MDMA handle 566 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 567 * This parameter can be any combination of the following values: 568 * @arg MDMA_IT_TE : Transfer Error interrupt mask 569 * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask 570 * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask 571 * @arg MDMA_IT_BT : Block Transfer interrupt mask 572 * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask 573 * @retval None 574 */ 575 #define __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 576 577 /** 578 * @brief Disables the specified MDMA Channel interrupts. 579 * @param __HANDLE__: MDMA handle 580 * @param __INTERRUPT__: specifies the MDMA interrupt sources to be enabled or disabled. 581 * This parameter can be any combination of the following values: 582 * @arg MDMA_IT_TE : Transfer Error interrupt mask 583 * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask 584 * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask 585 * @arg MDMA_IT_BT : Block Transfer interrupt mask 586 * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask 587 * @retval None 588 */ 589 #define __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 590 591 /** 592 * @brief Checks whether the specified MDMA Channel interrupt is enabled or not. 593 * @param __HANDLE__: MDMA handle 594 * @param __INTERRUPT__: specifies the MDMA interrupt source to check. 595 * @arg MDMA_IT_TE : Transfer Error interrupt mask 596 * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask 597 * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask 598 * @arg MDMA_IT_BT : Block Transfer interrupt mask 599 * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask 600 * @retval The state of MDMA_IT (SET or RESET). 601 */ 602 #define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 603 604 /** 605 * @brief Writes the number of data in bytes to be transferred on the MDMA Channelx. 606 * @param __HANDLE__ : MDMA handle 607 * @param __COUNTER__: Number of data in bytes to be transferred. 608 * @retval None 609 */ 610 #define __HAL_MDMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CBNDTR |= ((__COUNTER__) & MDMA_CBNDTR_BNDT)) 611 612 /** 613 * @brief Returns the number of remaining data in bytes in the current MDMA Channelx transfer. 614 * @param __HANDLE__ : MDMA handle 615 * @retval The number of remaining data in bytes in the current MDMA Channelx transfer. 616 */ 617 #define __HAL_MDMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CBNDTR & MDMA_CBNDTR_BNDT) 618 619 /** 620 * @} 621 */ 622 623 /* Exported functions --------------------------------------------------------*/ 624 /** @defgroup MDMA_Exported_Functions MDMA Exported Functions 625 * @{ 626 */ 627 628 /* Initialization and de-initialization functions *****************************/ 629 /** @defgroup MDMA_Exported_Functions_Group1 Initialization and de-initialization functions 630 * @brief Initialization and de-initialization functions 631 * @{ 632 */ 633 HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma); 634 HAL_StatusTypeDef HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma); 635 HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData); 636 637 HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma)); 638 HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID); 639 640 /** 641 * @} 642 */ 643 644 /* Linked list operation functions ********************************************/ 645 /** @defgroup MDMA_Exported_Functions_Group2 Linked List operation functions 646 * @brief Linked list operation functions 647 * @{ 648 */ 649 650 HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig); 651 HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode); 652 HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode); 653 HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma); 654 HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma); 655 656 657 /** 658 * @} 659 */ 660 661 /* IO operation functions *****************************************************/ 662 /** @defgroup MDMA_Exported_Functions_Group3 I/O operation functions 663 * @brief I/O operation functions 664 * @{ 665 */ 666 HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount); 667 HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount); 668 HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma); 669 HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma); 670 HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 671 HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma); 672 void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma); 673 674 /** 675 * @} 676 */ 677 678 /* Peripheral State and Error functions ***************************************/ 679 /** @defgroup MDMA_Exported_Functions_Group4 Peripheral State functions 680 * @brief Peripheral State functions 681 * @{ 682 */ 683 HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma); 684 uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma); 685 686 void HAL_MDMA_MspInit(MDMA_HandleTypeDef *hmdma); 687 void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma); 688 689 /** 690 * @} 691 */ 692 693 /** 694 * @} 695 */ 696 697 /* Private types -------------------------------------------------------------*/ 698 /** @defgroup MDMA_Private_Types MDMA Private Types 699 * @{ 700 */ 701 702 /** 703 * @} 704 */ 705 706 /* Private defines -----------------------------------------------------------*/ 707 /** @defgroup MDMA_Private_Defines MDMA Private Defines 708 * @{ 709 */ 710 711 /** 712 * @} 713 */ 714 715 /* Private variables ---------------------------------------------------------*/ 716 /** @defgroup MDMA_Private_Variables MDMA Private Variables 717 * @{ 718 */ 719 720 /** 721 * @} 722 */ 723 724 /* Private constants ---------------------------------------------------------*/ 725 /** @defgroup MDMA_Private_Constants MDMA Private Constants 726 * @{ 727 */ 728 729 /** 730 * @} 731 */ 732 733 /* Private macros ------------------------------------------------------------*/ 734 /** @defgroup MDMA_Private_Macros MDMA Private Macros 735 * @{ 736 */ 737 738 #define IS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER ) || \ 739 ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \ 740 ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \ 741 ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER )) 742 743 744 #define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW ) || \ 745 ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \ 746 ((__PRIORITY__) == MDMA_PRIORITY_HIGH) || \ 747 ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH)) 748 749 #define IS_MDMA_SECURE_MODE(__SECURE_MODE__) (((__SECURE_MODE__) == MDMA_SECURE_MODE_DISABLE ) || \ 750 ((__SECURE_MODE__) == MDMA_SECURE_MODE_ENABLE)) 751 #define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE ) || \ 752 ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE) || \ 753 ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \ 754 ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE)) 755 756 #define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_I2C6_TX)) 757 758 #define IS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE ) || \ 759 ((__INC__) == MDMA_SRC_INC_BYTE ) || \ 760 ((__INC__) == MDMA_SRC_INC_HALFWORD ) || \ 761 ((__INC__) == MDMA_SRC_INC_WORD ) || \ 762 ((__INC__) == MDMA_SRC_INC_DOUBLEWORD) || \ 763 ((__INC__) == MDMA_SRC_DEC_BYTE) || \ 764 ((__INC__) == MDMA_SRC_DEC_HALFWORD) || \ 765 ((__INC__) == MDMA_SRC_DEC_WORD) || \ 766 ((__INC__) == MDMA_SRC_DEC_DOUBLEWORD)) 767 768 #define IS_MDMA_DESTINATION_INC(__INC__) (((__INC__) == MDMA_DEST_INC_DISABLE ) || \ 769 ((__INC__) == MDMA_DEST_INC_BYTE ) || \ 770 ((__INC__) == MDMA_DEST_INC_HALFWORD ) || \ 771 ((__INC__) == MDMA_DEST_INC_WORD ) || \ 772 ((__INC__) == MDMA_DEST_INC_DOUBLEWORD) || \ 773 ((__INC__) == MDMA_DEST_DEC_BYTE) || \ 774 ((__INC__) == MDMA_DEST_DEC_HALFWORD) || \ 775 ((__INC__) == MDMA_DEST_DEC_WORD) || \ 776 ((__INC__) == MDMA_DEST_DEC_DOUBLEWORD)) 777 778 #define IS_MDMA_SOURCE_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_SRC_DATASIZE_BYTE ) || \ 779 ((__SIZE__) == MDMA_SRC_DATASIZE_HALFWORD ) || \ 780 ((__SIZE__) == MDMA_SRC_DATASIZE_WORD ) || \ 781 ((__SIZE__) == MDMA_SRC_DATASIZE_DOUBLEWORD)) 782 783 #define IS_MDMA_DESTINATION_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_DEST_DATASIZE_BYTE ) || \ 784 ((__SIZE__) == MDMA_DEST_DATASIZE_HALFWORD ) || \ 785 ((__SIZE__) == MDMA_DEST_DATASIZE_WORD ) || \ 786 ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD)) 787 788 #define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE ) || \ 789 ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT ) || \ 790 ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED ) || \ 791 ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT)) 792 793 794 #define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \ 795 ((__BURST__) == MDMA_SOURCE_BURST_2BEATS ) || \ 796 ((__BURST__) == MDMA_SOURCE_BURST_4BEATS ) || \ 797 ((__BURST__) == MDMA_SOURCE_BURST_8BEATS) || \ 798 ((__BURST__) == MDMA_SOURCE_BURST_16BEATS) || \ 799 ((__BURST__) == MDMA_SOURCE_BURST_32BEATS) || \ 800 ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \ 801 ((__BURST__) == MDMA_SOURCE_BURST_128BEATS)) 802 803 804 #define IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \ 805 ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \ 806 ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \ 807 ((__BURST__) == MDMA_DEST_BURST_8BEATS) || \ 808 ((__BURST__) == MDMA_DEST_BURST_16BEATS) || \ 809 ((__BURST__) == MDMA_DEST_BURST_32BEATS) || \ 810 ((__BURST__) == MDMA_DEST_BURST_64BEATS) || \ 811 ((__BURST__) == MDMA_DEST_BURST_128BEATS)) 812 813 #define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER ) || \ 814 ((__MODE__) == MDMA_BLOCK_TRANSFER ) || \ 815 ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \ 816 ((__MODE__) == MDMA_FULL_TRANSFER)) 817 818 #define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU)) 819 820 #define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0U ) && ((__COUNT__) <= 4096U)) 821 822 #define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0U) && ((SIZE) <= 65536U)) 823 824 #define IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536)) 825 826 /** 827 * @} 828 */ 829 830 /* Private functions prototypes ----------------------------------------------*/ 831 /** @defgroup MDMA_Private_Functions_Prototypes MDMA Private Functions Prototypes 832 * @{ 833 */ 834 835 /** 836 * @} 837 */ 838 839 /* Private functions ---------------------------------------------------------*/ 840 /** @defgroup MDMA_Private_Functions MDMA Private Functions 841 * @{ 842 */ 843 844 /** 845 * @} 846 */ 847 848 /** 849 * @} 850 */ 851 852 /** 853 * @} 854 */ 855 856 #ifdef __cplusplus 857 } 858 #endif 859 860 #endif /* STM32MP1xx_HAL_MDMA_H */ 861
