1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32MP1xx_HAL_DMA_H 21 #define __STM32MP1xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32mp1xx_hal_def.h" 29 30 /** @addtogroup STM32MP1xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup DMA_Exported_Types DMA Exported Types 41 * @brief DMA Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief DMA Configuration Structure definition 47 */ 48 typedef struct 49 { 50 uint32_t Request; /*!< Specifies the request selected for the specified stream. 51 This parameter can be a value of @ref DMA_Request_selection */ 52 53 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 54 from memory to memory or from peripheral to memory. 55 This parameter can be a value of @ref DMA_Data_transfer_direction */ 56 57 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 58 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 59 60 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 61 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 62 63 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 64 This parameter can be a value of @ref DMA_Peripheral_data_size */ 65 66 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 67 This parameter can be a value of @ref DMA_Memory_data_size */ 68 69 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. 70 This parameter can be a value of @ref DMA_mode 71 @note The circular buffer mode cannot be used if the memory-to-memory 72 data transfer is configured on the selected Stream */ 73 74 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. 75 This parameter can be a value of @ref DMA_Priority_level */ 76 77 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. 78 This parameter can be a value of @ref DMA_FIFO_direct_mode 79 @note The Direct mode (FIFO mode disabled) cannot be used if the 80 memory-to-memory data transfer is configured on the selected stream */ 81 82 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. 83 This parameter can be a value of @ref DMA_FIFO_threshold_level */ 84 85 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. 86 It specifies the amount of data to be transferred in a single non interruptible 87 transaction. 88 This parameter can be a value of @ref DMA_Memory_burst 89 @note The burst mode is possible only if the address Increment mode is enabled. */ 90 91 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. 92 It specifies the amount of data to be transferred in a single non interruptible 93 transaction. 94 This parameter can be a value of @ref DMA_Peripheral_burst 95 @note The burst mode is possible only if the address Increment mode is enabled. */ 96 } DMA_InitTypeDef; 97 98 /** 99 * @brief HAL DMA State structures definition 100 */ 101 typedef enum 102 { 103 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 104 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 105 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 106 HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */ 107 HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */ 108 } HAL_DMA_StateTypeDef; 109 110 /** 111 * @brief HAL DMA Transfer complete level structure definition 112 */ 113 typedef enum 114 { 115 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 116 HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ 117 } HAL_DMA_LevelCompleteTypeDef; 118 119 /** 120 * @brief HAL DMA Callbacks IDs structure definition 121 */ 122 typedef enum 123 { 124 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 125 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ 126 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ 127 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ 128 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ 129 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ 130 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ 131 } HAL_DMA_CallbackIDTypeDef; 132 133 /** 134 * @brief DMA handle Structure definition 135 */ 136 typedef struct __DMA_HandleTypeDef 137 { 138 DMA_Stream_TypeDef *Instance; /*!< Register base address */ 139 140 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 141 142 HAL_LockTypeDef Lock; /*!< DMA locking object */ 143 144 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 145 146 void *Parent; /*!< Parent object state */ 147 148 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 149 150 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ 151 152 void (* XferM1CpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete Memory1 callback */ 153 154 void (* XferM1HalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Half complete Memory1 callback */ 155 156 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 157 158 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Abort callback */ 159 160 __IO uint32_t ErrorCode; /*!< DMA Error code */ 161 162 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ 163 164 uint32_t StreamIndex; /*!< DMA Stream Index */ 165 166 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< DMAMUX Channel Base Address */ 167 168 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 169 170 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 171 172 173 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 174 175 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Status Address */ 176 177 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 178 179 } DMA_HandleTypeDef; 180 181 /** 182 * @} 183 */ 184 185 186 /* Exported constants --------------------------------------------------------*/ 187 188 /** @defgroup DMA_Exported_Constants DMA Exported Constants 189 * @brief DMA Exported constants 190 * @{ 191 */ 192 193 /** @defgroup DMA_Error_Code DMA Error Code 194 * @brief DMA Error Code 195 * @{ 196 */ 197 #define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */ 198 #define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */ 199 #define HAL_DMA_ERROR_FE (0x00000002U) /*!< FIFO error */ 200 #define HAL_DMA_ERROR_DME (0x00000004U) /*!< Direct Mode error */ 201 #define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ 202 #define HAL_DMA_ERROR_PARAM (0x00000040U) /*!< Parameter error */ 203 #define HAL_DMA_ERROR_NO_XFER (0x00000080U) /*!< Abort requested with no Xfer ongoing */ 204 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */ 205 #define HAL_DMA_ERROR_SYNC (0x00000200U) /*!< DMAMUX sync overrun error */ 206 #define HAL_DMA_ERROR_REQGEN (0x00000400U) /*!< DMAMUX request generator overrun error */ 207 #define HAL_DMA_ERROR_BUSY (0x00000800U) /*!< DMA Busy error */ 208 209 /** 210 * @} 211 */ 212 213 /** @defgroup DMA_Request_selection DMA Request selection 214 * @brief DMA Request selection 215 * @{ 216 */ 217 /* DMAMUX1 requests */ 218 #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ 219 220 #define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ 221 #define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ 222 #define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ 223 #define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ 224 #define DMA_REQUEST_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */ 225 #define DMA_REQUEST_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */ 226 #define DMA_REQUEST_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */ 227 #define DMA_REQUEST_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */ 228 229 #define DMA_REQUEST_ADC1 9U /*!< DMAMUX1 ADC1 request */ 230 #define DMA_REQUEST_ADC2 10U /*!< DMAMUX1 ADC2 request */ 231 232 #define DMA_REQUEST_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */ 233 #define DMA_REQUEST_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */ 234 #define DMA_REQUEST_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */ 235 #define DMA_REQUEST_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */ 236 #define DMA_REQUEST_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */ 237 #define DMA_REQUEST_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */ 238 #define DMA_REQUEST_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */ 239 240 #define DMA_REQUEST_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */ 241 #define DMA_REQUEST_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */ 242 #define DMA_REQUEST_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */ 243 #define DMA_REQUEST_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */ 244 #define DMA_REQUEST_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */ 245 246 #define DMA_REQUEST_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */ 247 #define DMA_REQUEST_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */ 248 #define DMA_REQUEST_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */ 249 #define DMA_REQUEST_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */ 250 #define DMA_REQUEST_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */ 251 #define DMA_REQUEST_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */ 252 253 #define DMA_REQUEST_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */ 254 #define DMA_REQUEST_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */ 255 #define DMA_REQUEST_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */ 256 #define DMA_REQUEST_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */ 257 258 #define DMA_REQUEST_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */ 259 #define DMA_REQUEST_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */ 260 #define DMA_REQUEST_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */ 261 #define DMA_REQUEST_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */ 262 263 #define DMA_REQUEST_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */ 264 #define DMA_REQUEST_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */ 265 #define DMA_REQUEST_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */ 266 #define DMA_REQUEST_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */ 267 268 269 #define DMA_REQUEST_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */ 270 #define DMA_REQUEST_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */ 271 #define DMA_REQUEST_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */ 272 #define DMA_REQUEST_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */ 273 274 #define DMA_REQUEST_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */ 275 #define DMA_REQUEST_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */ 276 #define DMA_REQUEST_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */ 277 #define DMA_REQUEST_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */ 278 #define DMA_REQUEST_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */ 279 #define DMA_REQUEST_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */ 280 #define DMA_REQUEST_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */ 281 282 #define DMA_REQUEST_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */ 283 #define DMA_REQUEST_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */ 284 #define DMA_REQUEST_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */ 285 #define DMA_REQUEST_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */ 286 #define DMA_REQUEST_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */ 287 #define DMA_REQUEST_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */ 288 289 #define DMA_REQUEST_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */ 290 #define DMA_REQUEST_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */ 291 292 #define DMA_REQUEST_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */ 293 #define DMA_REQUEST_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */ 294 #define DMA_REQUEST_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */ 295 #define DMA_REQUEST_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */ 296 297 #if defined (DAC1) 298 #define DMA_REQUEST_DAC1 67U /*!< DMAMUX1 DAC1 request */ 299 #define DMA_REQUEST_DAC2 68U /*!< DMAMUX1 DAC2 request */ 300 #endif 301 302 #define DMA_REQUEST_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */ 303 #define DMA_REQUEST_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */ 304 305 #define DMA_REQUEST_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */ 306 #define DMA_REQUEST_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */ 307 308 #define DMA_REQUEST_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */ 309 #define DMA_REQUEST_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */ 310 311 #if defined (DCMI) 312 #define DMA_REQUEST_DCMI 75U /*!< DMAMUX1 DCMI request */ 313 #endif 314 315 #if defined(CRYP2) 316 #define DMA_REQUEST_CRYP2_IN 76U /*!< DMAMUX1 CRYP2 IN request */ 317 #define DMA_REQUEST_CRYP2_OUT 77U /*!< DMAMUX1 CRYP2 OUT request */ 318 #endif 319 320 321 #if defined (HASH2) 322 #define DMA_REQUEST_HASH2_IN 78U /*!< DMAMUX1 HASH2 IN request */ 323 #endif 324 325 #define DMA_REQUEST_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */ 326 #define DMA_REQUEST_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */ 327 #define DMA_REQUEST_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */ 328 #define DMA_REQUEST_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */ 329 330 #define DMA_REQUEST_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */ 331 #define DMA_REQUEST_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */ 332 #define DMA_REQUEST_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */ 333 #define DMA_REQUEST_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */ 334 335 #define DMA_REQUEST_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */ 336 #define DMA_REQUEST_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */ 337 #define DMA_REQUEST_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */ 338 #define DMA_REQUEST_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */ 339 340 #define DMA_REQUEST_DFSDM1_FLT4 91U /*!< DMAMUX1 DFSDM1 Filter4 request */ 341 #define DMA_REQUEST_DFSDM1_FLT5 92U /*!< DMAMUX1 DFSDM1 Filter5 request */ 342 343 #define DMA_REQUEST_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request*/ 344 #define DMA_REQUEST_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request*/ 345 346 #if defined (SAI4) 347 #define DMA_REQUEST_SAI4_A 99U /*!< DMAMUX1 SAI4 A request */ 348 #define DMA_REQUEST_SAI4_B 100U /*!< DMAMUX1 SAI4 B request */ 349 #endif 350 351 #define DMA_REQUEST_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */ 352 #define DMA_REQUEST_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM Filter1 request */ 353 #define DMA_REQUEST_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM Filter2 request */ 354 #define DMA_REQUEST_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM Filter3 request */ 355 356 #define DMA_REQUEST_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */ 357 #define DMA_REQUEST_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */ 358 #define DMA_REQUEST_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */ 359 #define DMA_REQUEST_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */ 360 361 #define DMA_REQUEST_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */ 362 #define DMA_REQUEST_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */ 363 364 #define DMA_REQUEST_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */ 365 #define DMA_REQUEST_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */ 366 367 #if defined (SAI3) 368 #define DMA_REQUEST_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */ 369 #define DMA_REQUEST_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */ 370 #endif 371 372 #define DMA_REQUEST_I2C5_RX 115U /*!< DMAMUX1 I2C5 RX request */ 373 #define DMA_REQUEST_I2C5_TX 116U /*!< DMAMUX1 I2C5 TX request */ 374 375 376 377 /** 378 * @} 379 */ 380 381 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 382 * @brief DMA data transfer direction 383 * @{ 384 */ 385 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ 386 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ 387 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ 388 /** 389 * @} 390 */ 391 392 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 393 * @brief DMA peripheral incremented mode 394 * @{ 395 */ 396 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ 397 #define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */ 398 /** 399 * @} 400 */ 401 402 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 403 * @brief DMA memory incremented mode 404 * @{ 405 */ 406 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ 407 #define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */ 408 /** 409 * @} 410 */ 411 412 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 413 * @brief DMA peripheral data size 414 * @{ 415 */ 416 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */ 417 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ 418 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ 419 /** 420 * @} 421 */ 422 423 /** @defgroup DMA_Memory_data_size DMA Memory data size 424 * @brief DMA memory data size 425 * @{ 426 */ 427 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */ 428 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ 429 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ 430 /** 431 * @} 432 */ 433 434 /** @defgroup DMA_mode DMA mode 435 * @brief DMA mode 436 * @{ 437 */ 438 #define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ 439 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ 440 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ 441 /** 442 * @} 443 */ 444 445 /** @defgroup DMA_Priority_level DMA Priority level 446 * @brief DMA priority levels 447 * @{ 448 */ 449 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */ 450 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ 451 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ 452 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ 453 /** 454 * @} 455 */ 456 457 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode 458 * @brief DMA FIFO direct mode 459 * @{ 460 */ 461 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */ 462 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ 463 /** 464 * @} 465 */ 466 467 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level 468 * @brief DMA FIFO level 469 * @{ 470 */ 471 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */ 472 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ 473 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ 474 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ 475 /** 476 * @} 477 */ 478 479 /** @defgroup DMA_Memory_burst DMA Memory burst 480 * @brief DMA memory burst 481 * @{ 482 */ 483 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000U) 484 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) 485 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) 486 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) 487 /** 488 * @} 489 */ 490 491 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst 492 * @brief DMA peripheral burst 493 * @{ 494 */ 495 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000U) 496 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) 497 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) 498 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) 499 /** 500 * @} 501 */ 502 503 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 504 * @brief DMA interrupts definition 505 * @{ 506 */ 507 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) 508 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) 509 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) 510 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) 511 #define DMA_IT_FE ((uint32_t)0x00000080U) 512 /** 513 * @} 514 */ 515 516 /** @defgroup DMA_flag_definitions DMA flag definitions 517 * @brief DMA flag definitions 518 * @{ 519 */ 520 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00000001U) 521 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00000004U) 522 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U) 523 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U) 524 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U) 525 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U) 526 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U) 527 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U) 528 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U) 529 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U) 530 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U) 531 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U) 532 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U) 533 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U) 534 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U) 535 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U) 536 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U) 537 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U) 538 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U) 539 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U) 540 /** 541 * @} 542 */ 543 544 545 /** 546 * @} 547 */ 548 549 /* Exported macro ------------------------------------------------------------*/ 550 /** @defgroup DMA_Exported_Macros DMA Exported Macros 551 * @{ 552 */ 553 554 /** @brief Reset DMA handle state 555 * @param __HANDLE__: specifies the DMA handle. 556 * @retval None 557 */ 558 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 559 560 /** 561 * @brief Return the current DMA Stream FIFO filled level. 562 * @param __HANDLE__: DMA handle 563 * @retval The FIFO filling state. 564 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 565 * and not empty. 566 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. 567 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. 568 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. 569 * - DMA_FIFOStatus_Empty: when FIFO is empty 570 * - DMA_FIFOStatus_Full: when FIFO is full 571 */ 572 #define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_INSTANCE(__HANDLE__))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0) 573 574 /** 575 * @brief Enable the specified DMA Stream. 576 * @param __HANDLE__: DMA handle 577 * @retval None 578 */ 579 #define __HAL_DMA_ENABLE(__HANDLE__) (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= DMA_SxCR_EN) 580 581 /** 582 * @brief Disable the specified DMA Stream. 583 * @param __HANDLE__: DMA handle 584 * @retval None 585 */ 586 #define __HAL_DMA_DISABLE(__HANDLE__) (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~DMA_SxCR_EN) 587 588 /* Interrupt & Flag management */ 589 590 /** 591 * @brief Return the current DMA Stream transfer complete flag. 592 * @param __HANDLE__: DMA handle 593 * @retval The specified transfer complete flag index. 594 */ 595 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 596 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ 597 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ 598 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ 599 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ 600 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ 601 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ 602 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ 603 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ 604 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ 605 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ 606 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ 607 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ 608 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\ 609 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\ 610 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\ 611 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\ 612 (uint32_t)0x00000000) 613 /** 614 * @brief Return the current DMA Stream half transfer complete flag. 615 * @param __HANDLE__: DMA handle 616 * @retval The specified half transfer complete flag index. 617 */ 618 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 619 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ 620 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ 621 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ 622 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ 623 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ 624 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ 625 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ 626 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ 627 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ 628 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ 629 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ 630 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ 631 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\ 632 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\ 633 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\ 634 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\ 635 (uint32_t)0x00000000) 636 /** 637 * @brief Return the current DMA Stream transfer error flag. 638 * @param __HANDLE__: DMA handle 639 * @retval The specified transfer error flag index. 640 */ 641 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 642 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ 643 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ 644 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ 645 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ 646 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ 647 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ 648 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ 649 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ 650 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ 651 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ 652 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ 653 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ 654 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\ 655 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\ 656 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\ 657 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\ 658 (uint32_t)0x00000000) 659 /** 660 * @brief Return the current DMA Stream FIFO error flag. 661 * @param __HANDLE__: DMA handle 662 * @retval The specified FIFO error flag index. 663 */ 664 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ 665 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ 666 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ 667 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ 668 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ 669 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ 670 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ 671 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ 672 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ 673 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ 674 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ 675 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ 676 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ 677 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\ 678 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\ 679 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\ 680 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\ 681 (uint32_t)0x00000000) 682 683 /** 684 * @brief Return the current DMA Stream direct mode error flag. 685 * @param __HANDLE__: DMA handle 686 * @retval The specified direct mode error flag index. 687 */ 688 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ 689 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ 690 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ 691 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ 692 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ 693 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ 694 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ 695 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ 696 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ 697 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ 698 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ 699 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ 700 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ 701 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\ 702 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\ 703 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\ 704 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\ 705 (uint32_t)0x00000000) 706 707 /** 708 * @brief Get the DMA Stream pending flags. 709 * @param __HANDLE__: DMA handle 710 * @param __FLAG__: Get the specified flag. 711 * This parameter can be any combination of the following values: 712 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 713 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 714 * @arg DMA_FLAG_TEIFx: Transfer error flag. 715 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 716 * @arg DMA_FLAG_FEIFx: FIFO error flag. 717 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 718 * @retval The state of FLAG (SET or RESET). 719 */ 720 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ 721 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ 722 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ 723 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) 724 725 /** 726 * @brief Clear the DMA Stream pending flags. 727 * @param __HANDLE__: DMA handle 728 * @param __FLAG__: specifies the flag to clear. 729 * This parameter can be any combination of the following values: 730 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 731 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 732 * @arg DMA_FLAG_TEIFx: Transfer error flag. 733 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 734 * @arg DMA_FLAG_FEIFx: FIFO error flag. 735 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 736 * @retval None 737 */ 738 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 739 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ 740 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ 741 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) 742 743 /** 744 * @brief Enable the specified DMA Stream interrupts. 745 * @param __HANDLE__: DMA handle 746 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 747 * This parameter can be one of the following values: 748 * @arg DMA_IT_TC: Transfer complete interrupt mask. 749 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 750 * @arg DMA_IT_TE: Transfer error interrupt mask. 751 * @arg DMA_IT_FE: FIFO error interrupt mask. 752 * @arg DMA_IT_DME: Direct mode error interrupt. 753 * @retval None 754 */ 755 756 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 757 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__))) 758 759 /** 760 * @brief Disable the specified DMA Stream interrupts. 761 * @param __HANDLE__: DMA handle 762 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 763 * This parameter can be one of the following values: 764 * @arg DMA_IT_TC: Transfer complete interrupt mask. 765 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 766 * @arg DMA_IT_TE: Transfer error interrupt mask. 767 * @arg DMA_IT_FE: FIFO error interrupt mask. 768 * @arg DMA_IT_DME: Direct mode error interrupt. 769 * @retval None 770 */ 771 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 772 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__))) 773 774 /** 775 * @brief Check whether the specified DMA Stream interrupt is enabled or not. 776 * @param __HANDLE__: DMA handle 777 * @param __INTERRUPT__: specifies the DMA interrupt source to check. 778 * This parameter can be one of the following values: 779 * @arg DMA_IT_TC: Transfer complete interrupt mask. 780 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 781 * @arg DMA_IT_TE: Transfer error interrupt mask. 782 * @arg DMA_IT_FE: FIFO error interrupt mask. 783 * @arg DMA_IT_DME: Direct mode error interrupt. 784 * @retval The state of DMA_IT. 785 */ 786 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 787 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \ 788 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__))) 789 790 /** 791 * @brief Writes the number of data units to be transferred on the DMA Stream. 792 * @param __HANDLE__: DMA handle 793 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) 794 * Number of data items depends only on the Peripheral data format. 795 * 796 * @note If Peripheral data format is Bytes: number of data units is equal 797 * to total number of bytes to be transferred. 798 * 799 * @note If Peripheral data format is Half-Word: number of data units is 800 * equal to total number of bytes to be transferred / 2. 801 * 802 * @note If Peripheral data format is Word: number of data units is equal 803 * to total number of bytes to be transferred / 4. 804 * 805 * @retval The number of remaining data units in the current DMAy Streamx transfer. 806 */ 807 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) 808 809 /** 810 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. 811 * @param __HANDLE__: DMA handle 812 * 813 * @retval The number of remaining data units in the current DMA Stream transfer. 814 */ 815 #define __HAL_DMA_GET_COUNTER(__HANDLE__) (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) 816 /** 817 * @} 818 */ 819 820 /* Include DMA HAL Extension module */ 821 #include "stm32mp1xx_hal_dma_ex.h" 822 823 /* Exported functions --------------------------------------------------------*/ 824 825 /** @defgroup DMA_Exported_Functions DMA Exported Functions 826 * @brief DMA Exported functions 827 * @{ 828 */ 829 830 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions 831 * @brief Initialization and de-initialization functions 832 * @{ 833 */ 834 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 835 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 836 /** 837 * @} 838 */ 839 840 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions 841 * @brief I/O operation functions 842 * @{ 843 */ 844 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 845 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 846 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 847 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 848 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 849 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 850 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); 851 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 852 853 /** 854 * @} 855 */ 856 857 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions 858 * @brief Peripheral State functions 859 * @{ 860 */ 861 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 862 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 863 /** 864 * @} 865 */ 866 /** 867 * @} 868 */ 869 /* Private Constants -------------------------------------------------------------*/ 870 /** @defgroup DMA_Private_Constants DMA Private Constants 871 * @brief DMA private defines and constants 872 * @{ 873 */ 874 /** 875 * @} 876 */ 877 878 /* Private macros ------------------------------------------------------------*/ 879 /** @defgroup DMA_Private_Macros DMA Private Macros 880 * @brief DMA private macros 881 * @{ 882 */ 883 #define IS_DMA_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_I2C5_TX) 884 885 886 #define IS_DMA_INSTANCE(__HANDLE__) ( \ 887 (((uint32_t)((__HANDLE__)->Instance) >= ((uint32_t)DMA1_Stream0)) && \ 888 ((uint32_t)((__HANDLE__)->Instance) <= ((uint32_t)DMA2_Stream7))) \ 889 ) 890 891 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 892 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 893 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 894 895 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) 896 897 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 898 ((STATE) == DMA_PINC_DISABLE)) 899 900 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 901 ((STATE) == DMA_MINC_DISABLE)) 902 903 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 904 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 905 ((SIZE) == DMA_PDATAALIGN_WORD)) 906 907 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 908 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 909 ((SIZE) == DMA_MDATAALIGN_WORD )) 910 911 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 912 ((MODE) == DMA_CIRCULAR) || \ 913 ((MODE) == DMA_PFCTRL)) 914 915 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 916 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 917 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 918 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 919 920 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ 921 ((STATE) == DMA_FIFOMODE_ENABLE)) 922 923 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ 924 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ 925 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ 926 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) 927 928 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ 929 ((BURST) == DMA_MBURST_INC4) || \ 930 ((BURST) == DMA_MBURST_INC8) || \ 931 ((BURST) == DMA_MBURST_INC16)) 932 933 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ 934 ((BURST) == DMA_PBURST_INC4) || \ 935 ((BURST) == DMA_PBURST_INC8) || \ 936 ((BURST) == DMA_PBURST_INC16)) 937 /** 938 * @} 939 */ 940 941 /* Private functions ---------------------------------------------------------*/ 942 /** @defgroup DMA_Private_Functions DMA Private Functions 943 * @brief DMA private functions 944 * @{ 945 */ 946 /** 947 * @} 948 */ 949 950 /** 951 * @} 952 */ 953 954 /** 955 * @} 956 */ 957 958 #ifdef __cplusplus 959 } 960 #endif 961 962 #endif /* __STM32MP1xx_HAL_DMA_H */ 963
