1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_dfsdm.h 4 * @author MCD Application Team 5 * @brief Header file of DFSDM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32MP1xx_HAL_DFSDM_H 21 #define STM32MP1xx_HAL_DFSDM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32mp1xx_hal_def.h" 29 30 /** @addtogroup STM32MP1xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DFSDM 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief HAL DFSDM Channel states definition 45 */ 46 typedef enum 47 { 48 HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */ 49 HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */ 50 HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */ 51 }HAL_DFSDM_Channel_StateTypeDef; 52 53 /** 54 * @brief DFSDM channel output clock structure definition 55 */ 56 typedef struct 57 { 58 FunctionalState Activation; /*!< Output clock enable/disable */ 59 uint32_t Selection; /*!< Output clock is system clock or audio clock. 60 This parameter can be a value of @ref DFSDM_Channel_OuputClock */ 61 uint32_t Divider; /*!< Output clock divider. 62 This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ 63 }DFSDM_Channel_OutputClockTypeDef; 64 65 /** 66 * @brief DFSDM channel input structure definition 67 */ 68 typedef struct 69 { 70 uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output. 71 This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ 72 uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. 73 This parameter can be a value of @ref DFSDM_Channel_DataPacking */ 74 uint32_t Pins; /*!< Input pins are taken from same or following channel. 75 This parameter can be a value of @ref DFSDM_Channel_InputPins */ 76 }DFSDM_Channel_InputTypeDef; 77 78 /** 79 * @brief DFSDM channel serial interface structure definition 80 */ 81 typedef struct 82 { 83 uint32_t Type; /*!< SPI or Manchester modes. 84 This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ 85 uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). 86 This parameter can be a value of @ref DFSDM_Channel_SpiClock */ 87 }DFSDM_Channel_SerialInterfaceTypeDef; 88 89 /** 90 * @brief DFSDM channel analog watchdog structure definition 91 */ 92 typedef struct 93 { 94 uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. 95 This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ 96 uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. 97 This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ 98 }DFSDM_Channel_AwdTypeDef; 99 100 /** 101 * @brief DFSDM channel init structure definition 102 */ 103 typedef struct 104 { 105 DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ 106 DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */ 107 DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */ 108 DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */ 109 int32_t Offset; /*!< DFSDM channel offset. 110 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 111 uint32_t RightBitShift; /*!< DFSDM channel right bit shift. 112 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 113 }DFSDM_Channel_InitTypeDef; 114 115 /** 116 * @brief DFSDM channel handle structure definition 117 */ 118 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 119 typedef struct __DFSDM_Channel_HandleTypeDef 120 #else 121 typedef struct 122 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ 123 { 124 DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ 125 DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ 126 HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ 127 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 128 void (*CkabCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */ 129 void (*ScdCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */ 130 void (*MspInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */ 131 void (*MspDeInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */ 132 #endif 133 }DFSDM_Channel_HandleTypeDef; 134 135 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 136 /** 137 * @brief DFSDM channel callback ID enumeration definition 138 */ 139 typedef enum 140 { 141 HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U, /*!< DFSDM channel clock absence detection callback ID */ 142 HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, /*!< DFSDM channel short circuit detection callback ID */ 143 HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, /*!< DFSDM channel MSP init callback ID */ 144 HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U /*!< DFSDM channel MSP de-init callback ID */ 145 }HAL_DFSDM_Channel_CallbackIDTypeDef; 146 147 /** 148 * @brief DFSDM channel callback pointer definition 149 */ 150 typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 151 #endif 152 153 /** 154 * @brief HAL DFSDM Filter states definition 155 */ 156 typedef enum 157 { 158 HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */ 159 HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */ 160 HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */ 161 HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */ 162 HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */ 163 HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */ 164 }HAL_DFSDM_Filter_StateTypeDef; 165 166 /** 167 * @brief DFSDM filter regular conversion parameters structure definition 168 */ 169 typedef struct 170 { 171 uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. 172 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 173 FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ 174 FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ 175 }DFSDM_Filter_RegularParamTypeDef; 176 177 /** 178 * @brief DFSDM filter injected conversion parameters structure definition 179 */ 180 typedef struct 181 { 182 uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. 183 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 184 FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */ 185 FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */ 186 uint32_t ExtTrigger; /*!< External trigger. 187 This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ 188 uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. 189 This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ 190 }DFSDM_Filter_InjectedParamTypeDef; 191 192 /** 193 * @brief DFSDM filter parameters structure definition 194 */ 195 typedef struct 196 { 197 uint32_t SincOrder; /*!< Sinc filter order. 198 This parameter can be a value of @ref DFSDM_Filter_SincOrder */ 199 uint32_t Oversampling; /*!< Filter oversampling ratio. 200 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ 201 uint32_t IntOversampling; /*!< Integrator oversampling ratio. 202 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ 203 }DFSDM_Filter_FilterParamTypeDef; 204 205 /** 206 * @brief DFSDM filter init structure definition 207 */ 208 typedef struct 209 { 210 DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ 211 DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ 212 DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ 213 }DFSDM_Filter_InitTypeDef; 214 215 /** 216 * @brief DFSDM filter handle structure definition 217 */ 218 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 219 typedef struct __DFSDM_Filter_HandleTypeDef 220 #else 221 typedef struct 222 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ 223 { 224 DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ 225 DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ 226 DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */ 227 DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */ 228 uint32_t RegularContMode; /*!< Regular conversion continuous mode */ 229 uint32_t RegularTrigger; /*!< Trigger used for regular conversion */ 230 uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */ 231 uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */ 232 FunctionalState InjectedScanMode; /*!< Injected scanning mode */ 233 uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ 234 uint32_t InjConvRemaining; /*!< Injected conversions remaining */ 235 HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ 236 uint32_t ErrorCode; /*!< DFSDM filter error code */ 237 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 238 void (*AwdCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 239 uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */ 240 void (*RegConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */ 241 void (*RegConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */ 242 void (*InjConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */ 243 void (*InjConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half injected conversion complete callback */ 244 void (*ErrorCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter error callback */ 245 void (*MspInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP init callback */ 246 void (*MspDeInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP de-init callback */ 247 #endif 248 }DFSDM_Filter_HandleTypeDef; 249 250 /** 251 * @brief DFSDM filter analog watchdog parameters structure definition 252 */ 253 typedef struct 254 { 255 uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. 256 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */ 257 uint32_t Channel; /*!< Analog watchdog channel selection. 258 This parameter can be a values combination of @ref DFSDM_Channel_Selection */ 259 int32_t HighThreshold; /*!< High threshold for the analog watchdog. 260 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 261 int32_t LowThreshold; /*!< Low threshold for the analog watchdog. 262 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 263 uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event. 264 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 265 uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. 266 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 267 }DFSDM_Filter_AwdParamTypeDef; 268 269 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 270 /** 271 * @brief DFSDM filter callback ID enumeration definition 272 */ 273 typedef enum 274 { 275 HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */ 276 HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */ 277 HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */ 278 HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */ 279 HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, /*!< DFSDM filter error callback ID */ 280 HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, /*!< DFSDM filter MSP init callback ID */ 281 HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U /*!< DFSDM filter MSP de-init callback ID */ 282 }HAL_DFSDM_Filter_CallbackIDTypeDef; 283 284 /** 285 * @brief DFSDM filter callback pointer definition 286 */ 287 typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 288 typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 289 #endif 290 291 /** 292 * @} 293 */ 294 /* End of exported types -----------------------------------------------------*/ 295 296 /* Exported constants --------------------------------------------------------*/ 297 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants 298 * @{ 299 */ 300 301 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection 302 * @{ 303 */ 304 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */ 305 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ 306 /** 307 * @} 308 */ 309 310 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer 311 * @{ 312 */ 313 #define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U /*!< Data are taken from external inputs */ 314 #define DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0 /*!< Data are taken from ADC output */ 315 #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ 316 /** 317 * @} 318 */ 319 320 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing 321 * @{ 322 */ 323 #define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U /*!< Standard data packing mode */ 324 #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ 325 #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ 326 /** 327 * @} 328 */ 329 330 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins 331 * @{ 332 */ 333 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /*!< Input from pins on same channel */ 334 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ 335 /** 336 * @} 337 */ 338 339 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type 340 * @{ 341 */ 342 #define DFSDM_CHANNEL_SPI_RISING 0x00000000U /*!< SPI with rising edge */ 343 #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ 344 #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ 345 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ 346 /** 347 * @} 348 */ 349 350 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection 351 * @{ 352 */ 353 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U /*!< External SPI clock */ 354 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ 355 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ 356 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ 357 /** 358 * @} 359 */ 360 361 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order 362 * @{ 363 */ 364 #define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ 365 #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ 366 #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ 367 #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */ 368 /** 369 * @} 370 */ 371 372 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger 373 * @{ 374 */ 375 #define DFSDM_FILTER_SW_TRIGGER 0x00000000U /*!< Software trigger */ 376 #define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */ 377 #define DFSDM_FILTER_EXT_TRIGGER 0x00000002U /*!< External trigger (only for injected conversion) */ 378 /** 379 * @} 380 */ 381 382 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger 383 * @{ 384 */ 385 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For all DFSDM filters */ 386 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For all DFSDM filters */ 387 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For all DFSDM filters */ 388 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */ 389 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For all DFSDM filters */ 390 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ 391 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ 392 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \ 393 DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ 394 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For all DFSDM filters */ 395 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 396 #define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \ 397 DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 398 #define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \ 399 DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 400 #define DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \ 401 DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 402 #define DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT (DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_3 | \ 403 DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 404 /** 405 * @} 406 */ 407 408 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge 409 * @{ 410 */ 411 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */ 412 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */ 413 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */ 414 /** 415 * @} 416 */ 417 418 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order 419 * @{ 420 */ 421 #define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ 422 #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */ 423 #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */ 424 #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */ 425 #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */ 426 #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */ 427 /** 428 * @} 429 */ 430 431 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source 432 * @{ 433 */ 434 #define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /*!< From digital filter */ 435 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */ 436 /** 437 * @} 438 */ 439 440 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code 441 * @{ 442 */ 443 #define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */ 444 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */ 445 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */ 446 #define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */ 447 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 448 #define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */ 449 #endif 450 /** 451 * @} 452 */ 453 454 /** @defgroup DFSDM_BreakSignals DFSDM break signals 455 * @{ 456 */ 457 #define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */ 458 #define DFSDM_BREAK_SIGNAL_0 0x00000001U /*!< Break signal 0 */ 459 #define DFSDM_BREAK_SIGNAL_1 0x00000002U /*!< Break signal 1 */ 460 #define DFSDM_BREAK_SIGNAL_2 0x00000004U /*!< Break signal 2 */ 461 #define DFSDM_BREAK_SIGNAL_3 0x00000008U /*!< Break signal 3 */ 462 /** 463 * @} 464 */ 465 466 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection 467 * @{ 468 */ 469 /* DFSDM Channels ------------------------------------------------------------*/ 470 /* The DFSDM channels are defined as follows: 471 - in 16-bit LSB the channel mask is set 472 - in 16-bit MSB the channel number is set 473 e.g. for channel 5 definition: 474 - the channel mask is 0x00000020 (bit 5 is set) 475 - the channel number 5 is 0x00050000 476 --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ 477 #define DFSDM_CHANNEL_0 0x00000001U 478 #define DFSDM_CHANNEL_1 0x00010002U 479 #define DFSDM_CHANNEL_2 0x00020004U 480 #define DFSDM_CHANNEL_3 0x00030008U 481 #define DFSDM_CHANNEL_4 0x00040010U 482 #define DFSDM_CHANNEL_5 0x00050020U 483 #define DFSDM_CHANNEL_6 0x00060040U 484 #define DFSDM_CHANNEL_7 0x00070080U 485 /** 486 * @} 487 */ 488 489 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode 490 * @{ 491 */ 492 #define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U /*!< Conversion are not continuous */ 493 #define DFSDM_CONTINUOUS_CONV_ON 0x00000001U /*!< Conversion are continuous */ 494 /** 495 * @} 496 */ 497 498 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold 499 * @{ 500 */ 501 #define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U /*!< Analog watchdog high threshold */ 502 #define DFSDM_AWD_LOW_THRESHOLD 0x00000001U /*!< Analog watchdog low threshold */ 503 /** 504 * @} 505 */ 506 507 /** 508 * @} 509 */ 510 /* End of exported constants -------------------------------------------------*/ 511 512 /* Exported macros -----------------------------------------------------------*/ 513 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros 514 * @{ 515 */ 516 517 /** @brief Reset DFSDM channel handle state. 518 * @param __HANDLE__ DFSDM channel handle. 519 * @retval None 520 */ 521 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 522 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \ 523 (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \ 524 (__HANDLE__)->MspInitCallback = NULL; \ 525 (__HANDLE__)->MspDeInitCallback = NULL; \ 526 } while(0) 527 #else 528 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) 529 #endif 530 531 /** @brief Reset DFSDM filter handle state. 532 * @param __HANDLE__ DFSDM filter handle. 533 * @retval None 534 */ 535 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 536 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \ 537 (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \ 538 (__HANDLE__)->MspInitCallback = NULL; \ 539 (__HANDLE__)->MspDeInitCallback = NULL; \ 540 } while(0) 541 #else 542 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) 543 #endif 544 545 /** 546 * @} 547 */ 548 /* End of exported macros ----------------------------------------------------*/ 549 550 /* Include DFSDM HAL Extension module */ 551 #include "stm32mp1xx_hal_dfsdm_ex.h" 552 553 /* Exported functions --------------------------------------------------------*/ 554 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions 555 * @{ 556 */ 557 558 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions 559 * @{ 560 */ 561 /* Channel initialization and de-initialization functions *********************/ 562 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 563 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 564 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 565 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 566 567 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 568 /* Channel callbacks register/unregister functions ****************************/ 569 HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 570 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, 571 pDFSDM_Channel_CallbackTypeDef pCallback); 572 HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 573 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID); 574 #endif 575 /** 576 * @} 577 */ 578 579 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions 580 * @{ 581 */ 582 /* Channel operation functions ************************************************/ 583 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 584 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 585 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 586 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 587 588 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 589 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 590 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 591 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 592 593 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 594 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); 595 596 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 597 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 598 599 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 600 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 601 /** 602 * @} 603 */ 604 605 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function 606 * @{ 607 */ 608 /* Channel state function *****************************************************/ 609 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 610 /** 611 * @} 612 */ 613 614 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions 615 * @{ 616 */ 617 /* Filter initialization and de-initialization functions *********************/ 618 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 619 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 620 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 621 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 622 623 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 624 /* Filter callbacks register/unregister functions ****************************/ 625 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 626 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, 627 pDFSDM_Filter_CallbackTypeDef pCallback); 628 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 629 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID); 630 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 631 pDFSDM_Filter_AwdCallbackTypeDef pCallback); 632 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 633 #endif 634 /** 635 * @} 636 */ 637 638 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions 639 * @{ 640 */ 641 /* Filter control functions *********************/ 642 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 643 uint32_t Channel, 644 uint32_t ContinuousMode); 645 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 646 uint32_t Channel); 647 /** 648 * @} 649 */ 650 651 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions 652 * @{ 653 */ 654 /* Filter operation functions *********************/ 655 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 656 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 657 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 658 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 659 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 660 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 661 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 662 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 663 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 664 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 665 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 666 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 667 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 668 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 669 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 670 DFSDM_Filter_AwdParamTypeDef* awdParam); 671 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 672 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); 673 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 674 675 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 676 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 677 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 678 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 679 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 680 681 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 682 683 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 684 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 685 686 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 687 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 688 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 689 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 690 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 691 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 692 /** 693 * @} 694 */ 695 696 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions 697 * @{ 698 */ 699 /* Filter state functions *****************************************************/ 700 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 701 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 702 /** 703 * @} 704 */ 705 706 /** 707 * @} 708 */ 709 /* End of exported functions -------------------------------------------------*/ 710 711 /* Private macros ------------------------------------------------------------*/ 712 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros 713 * @{ 714 */ 715 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ 716 ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) 717 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U)) 718 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ 719 ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \ 720 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) 721 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ 722 ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ 723 ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) 724 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \ 725 ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS)) 726 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \ 727 ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \ 728 ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \ 729 ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING)) 730 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \ 731 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \ 732 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \ 733 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING)) 734 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \ 735 ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ 736 ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ 737 ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) 738 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U)) 739 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 740 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU) 741 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU) 742 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 743 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) 744 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 745 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \ 746 ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) 747 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 748 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ 749 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ 750 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \ 751 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 752 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ 753 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ 754 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 755 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ 756 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 757 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \ 758 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT) || \ 759 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT) || \ 760 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT)) 761 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \ 762 ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \ 763 ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) 764 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \ 765 ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \ 766 ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \ 767 ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ 768 ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ 769 ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) 770 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U)) 771 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U)) 772 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ 773 ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) 774 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 775 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU) 776 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ 777 ((CHANNEL) == DFSDM_CHANNEL_1) || \ 778 ((CHANNEL) == DFSDM_CHANNEL_2) || \ 779 ((CHANNEL) == DFSDM_CHANNEL_3) || \ 780 ((CHANNEL) == DFSDM_CHANNEL_4) || \ 781 ((CHANNEL) == DFSDM_CHANNEL_5) || \ 782 ((CHANNEL) == DFSDM_CHANNEL_6) || \ 783 ((CHANNEL) == DFSDM_CHANNEL_7)) 784 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU)) 785 #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ 786 ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) 787 /** 788 * @} 789 */ 790 /* End of private macros -----------------------------------------------------*/ 791 792 /** 793 * @} 794 */ 795 796 /** 797 * @} 798 */ 799 800 #ifdef __cplusplus 801 } 802 #endif 803 804 #endif /* STM32MP1xx_HAL_DFSDM_H */ 805
