1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_cec.h 4 * @author MCD Application Team 5 * @brief Header file of CEC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32MP1xx_HAL_CEC_H 21 #define STM32MP1xx_HAL_CEC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32mp1xx_hal_def.h" 29 30 #if defined (CEC) 31 32 /** @addtogroup STM32MP1xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup CEC 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup CEC_Exported_Types CEC Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief CEC Init Structure definition 47 */ 48 typedef struct 49 { 50 uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time. 51 It can be one of @ref CEC_Signal_Free_Time 52 and belongs to the set {0,...,7} where 53 0x0 is the default configuration 54 else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */ 55 56 uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms, 57 it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE 58 or CEC_EXTENDED_TOLERANCE */ 59 60 uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception. 61 CEC_NO_RX_STOP_ON_BRE: reception is not stopped. 62 CEC_RX_STOP_ON_BRE: reception is stopped. */ 63 64 uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the 65 CEC line upon Bit Rising Error detection. 66 CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation. 67 CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */ 68 69 uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the 70 CEC line upon Long Bit Period Error detection. 71 CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation. 72 CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */ 73 74 uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line 75 upon an error detected on a broadcast message. 76 77 It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values: 78 79 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION. 80 a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE 81 and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. 82 b) LBPE detection: error-bit generation on the CEC line 83 if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION. 84 85 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION. 86 no error-bit generation in case neither a) nor b) are satisfied. Additionally, 87 there is no error-bit generation in case of Short Bit Period Error detection in 88 a broadcast message while LSTN bit is set. */ 89 90 uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts. 91 CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software. 92 CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */ 93 94 uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values: 95 96 CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its 97 own address (OAR). Messages addressed to different destination are ignored. 98 Broadcast messages are always received. 99 100 CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own 101 address (OAR) with positive acknowledge. Messages addressed to different destination 102 are received, but without interfering with the CEC bus: no acknowledge sent. */ 103 104 uint16_t OwnAddress; /*!< Own addresses configuration 105 This parameter can be a value of @ref CEC_OWN_ADDRESS */ 106 107 uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */ 108 109 110 } CEC_InitTypeDef; 111 112 /** 113 * @brief HAL CEC State definition 114 * @note HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition). 115 * - gState contains CEC state information related to global Handle management 116 * and also information related to Tx operations. 117 * gState value coding follow below described bitmap : 118 * b7 (not used) 119 * x : Should be set to 0 120 * b6 Error information 121 * 0 : No Error 122 * 1 : Error 123 * b5 IP initilisation status 124 * 0 : Reset (IP not initialized) 125 * 1 : Init done (IP initialized. HAL CEC Init function already called) 126 * b4-b3 (not used) 127 * xx : Should be set to 00 128 * b2 Intrinsic process state 129 * 0 : Ready 130 * 1 : Busy (IP busy with some configuration or internal operations) 131 * b1 (not used) 132 * x : Should be set to 0 133 * b0 Tx state 134 * 0 : Ready (no Tx operation ongoing) 135 * 1 : Busy (Tx operation ongoing) 136 * - RxState contains information related to Rx operations. 137 * RxState value coding follow below described bitmap : 138 * b7-b6 (not used) 139 * xx : Should be set to 00 140 * b5 IP initilisation status 141 * 0 : Reset (IP not initialized) 142 * 1 : Init done (IP initialized) 143 * b4-b2 (not used) 144 * xxx : Should be set to 000 145 * b1 Rx state 146 * 0 : Ready (no Rx operation ongoing) 147 * 1 : Busy (Rx operation ongoing) 148 * b0 (not used) 149 * x : Should be set to 0. 150 */ 151 typedef uint32_t HAL_CEC_StateTypeDef; 152 153 /** 154 * @brief CEC handle Structure definition 155 */ 156 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 157 typedef struct __CEC_HandleTypeDef 158 #else 159 typedef struct 160 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ 161 { 162 CEC_TypeDef *Instance; /*!< CEC registers base address */ 163 164 CEC_InitTypeDef Init; /*!< CEC communication parameters */ 165 166 uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */ 167 168 uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */ 169 170 uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */ 171 172 HAL_LockTypeDef Lock; /*!< Locking object */ 173 174 HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management 175 and also related to Tx operations. 176 This parameter can be a value of @ref HAL_CEC_StateTypeDef */ 177 178 HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations. 179 This parameter can be a value of @ref HAL_CEC_StateTypeDef */ 180 181 uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register 182 in case error is reported */ 183 184 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 185 void (* TxCpltCallback)(struct __CEC_HandleTypeDef 186 *hcec); /*!< CEC Tx Transfer completed callback */ 187 void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec, 188 uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */ 189 void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */ 190 191 void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */ 192 void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */ 193 194 #endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */ 195 } CEC_HandleTypeDef; 196 197 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 198 /** 199 * @brief HAL CEC Callback ID enumeration definition 200 */ 201 typedef enum 202 { 203 HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */ 204 HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */ 205 HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */ 206 HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */ 207 HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */ 208 } HAL_CEC_CallbackIDTypeDef; 209 210 /** 211 * @brief HAL CEC Callback pointer definition 212 */ 213 typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */ 214 typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, 215 uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */ 216 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ 217 /** 218 * @} 219 */ 220 221 /* Exported constants --------------------------------------------------------*/ 222 /** @defgroup CEC_Exported_Constants CEC Exported Constants 223 * @{ 224 */ 225 /** @defgroup CEC_State_Definition CEC State Code Definition 226 * @{ 227 */ 228 #define HAL_CEC_STATE_RESET ((uint32_t)0x00000000) /*!< Peripheral is not yet Initialized 229 Value is allowed for gState and RxState */ 230 #define HAL_CEC_STATE_READY ((uint32_t)0x00000020) /*!< Peripheral Initialized and ready for use 231 Value is allowed for gState and RxState */ 232 #define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024) /*!< an internal process is ongoing 233 Value is allowed for gState only */ 234 #define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022) /*!< Data Reception process is ongoing 235 Value is allowed for RxState only */ 236 #define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021) /*!< Data Transmission process is ongoing 237 Value is allowed for gState only */ 238 #define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023) /*!< an internal process is ongoing 239 Value is allowed for gState only */ 240 #define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050) /*!< Error Value is allowed for gState only */ 241 /** 242 * @} 243 */ 244 /** @defgroup CEC_Error_Code CEC Error Code 245 * @{ 246 */ 247 #define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */ 248 #define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */ 249 #define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */ 250 #define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */ 251 #define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */ 252 #define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */ 253 #define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */ 254 #define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */ 255 #define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */ 256 #define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */ 257 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 258 #define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U) /*!< Invalid Callback Error */ 259 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ 260 /** 261 * @} 262 */ 263 264 /** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter 265 * @{ 266 */ 267 #define CEC_DEFAULT_SFT ((uint32_t)0x00000000U) 268 #define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U) 269 #define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U) 270 #define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U) 271 #define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U) 272 #define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U) 273 #define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U) 274 #define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U) 275 /** 276 * @} 277 */ 278 279 /** @defgroup CEC_Tolerance CEC Receiver Tolerance 280 * @{ 281 */ 282 #define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U) 283 #define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL) 284 /** 285 * @} 286 */ 287 288 /** @defgroup CEC_BRERxStop CEC Reception Stop on Error 289 * @{ 290 */ 291 #define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U) 292 #define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP) 293 /** 294 * @} 295 */ 296 297 /** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported 298 * @{ 299 */ 300 #define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U) 301 #define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN) 302 /** 303 * @} 304 */ 305 306 /** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported 307 * @{ 308 */ 309 #define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U) 310 #define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN) 311 /** 312 * @} 313 */ 314 315 /** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message 316 * @{ 317 */ 318 #define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U) 319 #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN) 320 /** 321 * @} 322 */ 323 324 /** @defgroup CEC_SFT_Option CEC Signal Free Time start option 325 * @{ 326 */ 327 #define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U) 328 #define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT) 329 /** 330 * @} 331 */ 332 333 /** @defgroup CEC_Listening_Mode CEC Listening mode option 334 * @{ 335 */ 336 #define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U) 337 #define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN) 338 /** 339 * @} 340 */ 341 342 /** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register 343 * @{ 344 */ 345 #define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U) 346 /** 347 * @} 348 */ 349 350 /** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header 351 * @{ 352 */ 353 #define CEC_INITIATOR_LSB_POS ((uint32_t) 4U) 354 /** 355 * @} 356 */ 357 358 /** @defgroup CEC_OWN_ADDRESS CEC Own Address 359 * @{ 360 */ 361 #define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */ 362 #define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */ 363 #define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */ 364 #define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */ 365 #define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */ 366 #define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */ 367 #define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */ 368 #define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */ 369 #define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */ 370 #define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */ 371 #define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */ 372 #define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */ 373 #define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */ 374 #define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */ 375 #define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */ 376 #define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */ 377 /** 378 * @} 379 */ 380 381 /** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition 382 * @{ 383 */ 384 #define CEC_IT_TXACKE CEC_IER_TXACKEIE 385 #define CEC_IT_TXERR CEC_IER_TXERRIE 386 #define CEC_IT_TXUDR CEC_IER_TXUDRIE 387 #define CEC_IT_TXEND CEC_IER_TXENDIE 388 #define CEC_IT_TXBR CEC_IER_TXBRIE 389 #define CEC_IT_ARBLST CEC_IER_ARBLSTIE 390 #define CEC_IT_RXACKE CEC_IER_RXACKEIE 391 #define CEC_IT_LBPE CEC_IER_LBPEIE 392 #define CEC_IT_SBPE CEC_IER_SBPEIE 393 #define CEC_IT_BRE CEC_IER_BREIE 394 #define CEC_IT_RXOVR CEC_IER_RXOVRIE 395 #define CEC_IT_RXEND CEC_IER_RXENDIE 396 #define CEC_IT_RXBR CEC_IER_RXBRIE 397 /** 398 * @} 399 */ 400 401 /** @defgroup CEC_Flags_Definitions CEC Flags definition 402 * @{ 403 */ 404 #define CEC_FLAG_TXACKE CEC_ISR_TXACKE 405 #define CEC_FLAG_TXERR CEC_ISR_TXERR 406 #define CEC_FLAG_TXUDR CEC_ISR_TXUDR 407 #define CEC_FLAG_TXEND CEC_ISR_TXEND 408 #define CEC_FLAG_TXBR CEC_ISR_TXBR 409 #define CEC_FLAG_ARBLST CEC_ISR_ARBLST 410 #define CEC_FLAG_RXACKE CEC_ISR_RXACKE 411 #define CEC_FLAG_LBPE CEC_ISR_LBPE 412 #define CEC_FLAG_SBPE CEC_ISR_SBPE 413 #define CEC_FLAG_BRE CEC_ISR_BRE 414 #define CEC_FLAG_RXOVR CEC_ISR_RXOVR 415 #define CEC_FLAG_RXEND CEC_ISR_RXEND 416 #define CEC_FLAG_RXBR CEC_ISR_RXBR 417 /** 418 * @} 419 */ 420 421 /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags 422 * @{ 423 */ 424 #define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\ 425 CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) 426 /** 427 * @} 428 */ 429 430 /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag 431 * @{ 432 */ 433 #define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) 434 /** 435 * @} 436 */ 437 438 /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag 439 * @{ 440 */ 441 #define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) 442 /** 443 * @} 444 */ 445 446 /** 447 * @} 448 */ 449 450 /* Exported macros -----------------------------------------------------------*/ 451 /** @defgroup CEC_Exported_Macros CEC Exported Macros 452 * @{ 453 */ 454 455 /** @brief Reset CEC handle gstate & RxState 456 * @param __HANDLE__ CEC handle. 457 * @retval None 458 */ 459 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 460 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 461 (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \ 462 (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \ 463 (__HANDLE__)->MspInitCallback = NULL; \ 464 (__HANDLE__)->MspDeInitCallback = NULL; \ 465 } while(0) 466 #else 467 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 468 (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \ 469 (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \ 470 } while(0) 471 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ 472 /** @brief Checks whether or not the specified CEC interrupt flag is set. 473 * @param __HANDLE__ specifies the CEC Handle. 474 * @param __FLAG__ specifies the flag to check. 475 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error 476 * @arg CEC_FLAG_TXERR: Tx Error. 477 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. 478 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). 479 * @arg CEC_FLAG_TXBR: Tx-Byte Request. 480 * @arg CEC_FLAG_ARBLST: Arbitration Lost 481 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge 482 * @arg CEC_FLAG_LBPE: Rx Long period Error 483 * @arg CEC_FLAG_SBPE: Rx Short period Error 484 * @arg CEC_FLAG_BRE: Rx Bit Rising Error 485 * @arg CEC_FLAG_RXOVR: Rx Overrun. 486 * @arg CEC_FLAG_RXEND: End Of Reception. 487 * @arg CEC_FLAG_RXBR: Rx-Byte Received. 488 * @retval ITStatus 489 */ 490 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 491 492 /** @brief Clears the interrupt or status flag when raised (write at 1) 493 * @param __HANDLE__ specifies the CEC Handle. 494 * @param __FLAG__ specifies the interrupt/status flag to clear. 495 * This parameter can be one of the following values: 496 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error 497 * @arg CEC_FLAG_TXERR: Tx Error. 498 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. 499 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). 500 * @arg CEC_FLAG_TXBR: Tx-Byte Request. 501 * @arg CEC_FLAG_ARBLST: Arbitration Lost 502 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge 503 * @arg CEC_FLAG_LBPE: Rx Long period Error 504 * @arg CEC_FLAG_SBPE: Rx Short period Error 505 * @arg CEC_FLAG_BRE: Rx Bit Rising Error 506 * @arg CEC_FLAG_RXOVR: Rx Overrun. 507 * @arg CEC_FLAG_RXEND: End Of Reception. 508 * @arg CEC_FLAG_RXBR: Rx-Byte Received. 509 * @retval none 510 */ 511 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__)) 512 513 /** @brief Enables the specified CEC interrupt. 514 * @param __HANDLE__ specifies the CEC Handle. 515 * @param __INTERRUPT__ specifies the CEC interrupt to enable. 516 * This parameter can be one of the following values: 517 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable 518 * @arg CEC_IT_TXERR: Tx Error IT Enable 519 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable 520 * @arg CEC_IT_TXEND: End of transmission IT Enable 521 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable 522 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable 523 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable 524 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable 525 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable 526 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable 527 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable 528 * @arg CEC_IT_RXEND: End Of Reception IT Enable 529 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable 530 * @retval none 531 */ 532 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 533 534 /** @brief Disables the specified CEC interrupt. 535 * @param __HANDLE__ specifies the CEC Handle. 536 * @param __INTERRUPT__ specifies the CEC interrupt to disable. 537 * This parameter can be one of the following values: 538 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable 539 * @arg CEC_IT_TXERR: Tx Error IT Enable 540 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable 541 * @arg CEC_IT_TXEND: End of transmission IT Enable 542 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable 543 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable 544 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable 545 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable 546 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable 547 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable 548 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable 549 * @arg CEC_IT_RXEND: End Of Reception IT Enable 550 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable 551 * @retval none 552 */ 553 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 554 555 /** @brief Checks whether or not the specified CEC interrupt is enabled. 556 * @param __HANDLE__ specifies the CEC Handle. 557 * @param __INTERRUPT__ specifies the CEC interrupt to check. 558 * This parameter can be one of the following values: 559 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable 560 * @arg CEC_IT_TXERR: Tx Error IT Enable 561 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable 562 * @arg CEC_IT_TXEND: End of transmission IT Enable 563 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable 564 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable 565 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable 566 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable 567 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable 568 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable 569 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable 570 * @arg CEC_IT_RXEND: End Of Reception IT Enable 571 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable 572 * @retval FlagStatus 573 */ 574 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) 575 576 /** @brief Enables the CEC device 577 * @param __HANDLE__ specifies the CEC Handle. 578 * @retval none 579 */ 580 #define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN) 581 582 /** @brief Disables the CEC device 583 * @param __HANDLE__ specifies the CEC Handle. 584 * @retval none 585 */ 586 #define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN) 587 588 /** @brief Set Transmission Start flag 589 * @param __HANDLE__ specifies the CEC Handle. 590 * @retval none 591 */ 592 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM) 593 594 /** @brief Set Transmission End flag 595 * @param __HANDLE__ specifies the CEC Handle. 596 * @retval none 597 * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. 598 */ 599 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM) 600 601 /** @brief Get Transmission Start flag 602 * @param __HANDLE__ specifies the CEC Handle. 603 * @retval FlagStatus 604 */ 605 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM) 606 607 /** @brief Get Transmission End flag 608 * @param __HANDLE__ specifies the CEC Handle. 609 * @retval FlagStatus 610 */ 611 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM) 612 613 /** @brief Clear OAR register 614 * @param __HANDLE__ specifies the CEC Handle. 615 * @retval none 616 */ 617 #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR) 618 619 /** @brief Set OAR register (without resetting previously set address in case of multi-address mode) 620 * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand 621 * @param __HANDLE__ specifies the CEC Handle. 622 * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position) 623 * @retval none 624 */ 625 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) 626 627 /** 628 * @} 629 */ 630 631 /* Exported functions --------------------------------------------------------*/ 632 /** @addtogroup CEC_Exported_Functions 633 * @{ 634 */ 635 636 /** @addtogroup CEC_Exported_Functions_Group1 637 * @{ 638 */ 639 /* Initialization and de-initialization functions ****************************/ 640 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec); 641 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec); 642 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress); 643 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec); 644 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec); 645 646 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 647 HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, 648 pCEC_CallbackTypeDef pCallback); 649 HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID); 650 651 HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback); 652 HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec); 653 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ 654 /** 655 * @} 656 */ 657 658 /** @addtogroup CEC_Exported_Functions_Group2 659 * @{ 660 */ 661 /* I/O operation functions ***************************************************/ 662 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, 663 uint8_t *pData, uint32_t Size); 664 uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec); 665 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer); 666 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); 667 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec); 668 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize); 669 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec); 670 /** 671 * @} 672 */ 673 674 /** @addtogroup CEC_Exported_Functions_Group3 675 * @{ 676 */ 677 /* Peripheral State functions ************************************************/ 678 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec); 679 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); 680 /** 681 * @} 682 */ 683 684 /** 685 * @} 686 */ 687 688 /* Private types -------------------------------------------------------------*/ 689 /** @defgroup CEC_Private_Types CEC Private Types 690 * @{ 691 */ 692 693 /** 694 * @} 695 */ 696 697 /* Private variables ---------------------------------------------------------*/ 698 /** @defgroup CEC_Private_Variables CEC Private Variables 699 * @{ 700 */ 701 702 /** 703 * @} 704 */ 705 706 /* Private constants ---------------------------------------------------------*/ 707 /** @defgroup CEC_Private_Constants CEC Private Constants 708 * @{ 709 */ 710 711 /** 712 * @} 713 */ 714 715 /* Private macros ------------------------------------------------------------*/ 716 /** @defgroup CEC_Private_Macros CEC Private Macros 717 * @{ 718 */ 719 720 #define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT) 721 722 #define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \ 723 ((__RXTOL__) == CEC_EXTENDED_TOLERANCE)) 724 725 #define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \ 726 ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE)) 727 728 #define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \ 729 ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION)) 730 731 #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \ 732 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION)) 733 734 #define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \ 735 ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION)) 736 737 #define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \ 738 ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END)) 739 740 #define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \ 741 ((__MODE__) == CEC_FULL_LISTENING_MODE)) 742 743 /** @brief Check CEC message size. 744 * The message size is the payload size: without counting the header, 745 * it varies from 0 byte (ping operation, one header only, no payload) to 746 * 15 bytes (1 opcode and up to 14 operands following the header). 747 * @param __SIZE__ CEC message size. 748 * @retval Test result (TRUE or FALSE). 749 */ 750 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U) 751 752 /** @brief Check CEC device Own Address Register (OAR) setting. 753 * OAR address is written in a 15-bit field within CEC_CFGR register. 754 * @param __ADDRESS__ CEC own address. 755 * @retval Test result (TRUE or FALSE). 756 */ 757 #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU) 758 759 /** @brief Check CEC initiator or destination logical address setting. 760 * Initiator and destination addresses are coded over 4 bits. 761 * @param __ADDRESS__ CEC initiator or logical address. 762 * @retval Test result (TRUE or FALSE). 763 */ 764 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU) 765 /** 766 * @} 767 */ 768 /* Private functions ---------------------------------------------------------*/ 769 /** @defgroup CEC_Private_Functions CEC Private Functions 770 * @{ 771 */ 772 773 /** 774 * @} 775 */ 776 777 /** 778 * @} 779 */ 780 781 /** 782 * @} 783 */ 784 785 #endif /* CEC */ 786 787 #ifdef __cplusplus 788 } 789 #endif 790 791 #endif /* STM32MP1xxHAL_CEC_H */ 792
