1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_adc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32MP1xx_HAL_ADC_EX_H 21 #define STM32MP1xx_HAL_ADC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32mp1xx_hal_def.h" 29 30 /** @addtogroup STM32MP1xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup ADCEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief ADC Injected Conversion Oversampling structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Ratio; /*!< Configures the oversampling ratio. 49 This parameter can be a value between 1 and 1024 */ 50 51 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 52 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 53 } ADC_InjOversamplingTypeDef; 54 55 /** 56 * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected 57 * @note Parameters of this structure are shared within 2 scopes: 58 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset 59 * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, 60 * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling. 61 * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 62 * ADC state can be either: 63 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') 64 * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. 65 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. 66 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going 67 * on ADC groups regular and injected. 68 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 69 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 70 */ 71 typedef struct 72 { 73 uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. 74 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 75 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 76 77 uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. 78 This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. 79 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 80 the new channel setting (or parameter number of conversions adjusted) */ 81 82 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 83 Unit: ADC clock cycles. 84 Conversion time is the addition of sampling time and processing time 85 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 86 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. 87 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 88 It overwrites the last setting. 89 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 90 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 91 Refer to device datasheet for timings values. */ 92 93 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. 94 In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 95 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 96 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. 97 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 98 It overwrites the last setting. 99 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 100 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 101 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 102 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 103 of another parameter update on the fly) */ 104 105 uint32_t InjectedOffsetNumber; /*!< Selects the offset number. 106 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. 107 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 108 109 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. 110 Offset value must be a positive number. 111 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 112 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 113 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 114 without continuous mode or external trigger that could launch a conversion). */ 115 116 uint32_t InjectedOffsetRightShift; /*!< Specifies whether the 1 bit Right-shift feature is used or not. 117 This parameter is applied only for 16-bit or 8-bit resolution. 118 This parameter can be set to ENABLE or DISABLE. */ 119 120 FunctionalState InjectedOffsetSignedSaturation; /*!< Specifies whether the Signed saturation feature is used or not. 121 This parameter is applied only for 16-bit or 8-bit resolution. 122 This parameter can be set to ENABLE or DISABLE. */ 123 uint32_t InjectedLeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling. 124 This parameter can be a value of @ref ADCEx_Left_Bit_Shift */ 125 126 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. 127 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 128 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 129 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 130 configure a channel on injected group can impact the configuration of other channels previously set. */ 131 132 FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence 133 (main sequence subdivided in successive parts). 134 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 135 Discontinuous mode can be enabled only if continuous mode is disabled. 136 This parameter can be set to ENABLE or DISABLE. 137 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 138 Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). 139 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 140 configure a channel on injected group can impact the configuration of other channels previously set. */ 141 142 FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one 143 This parameter can be set to ENABLE or DISABLE. 144 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) 145 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) 146 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. 147 To maintain JAUTO always enabled, DMA must be configured in circular mode. 148 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 149 configure a channel on injected group can impact the configuration of other channels previously set. */ 150 151 FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. 152 This parameter can be set to ENABLE or DISABLE. 153 If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a 154 new injected context is set when queue is full, error is triggered by interruption and through function 155 'HAL_ADCEx_InjectedQueueOverflowCallback'. 156 Caution: This feature request that the sequence is fully configured before injected conversion start. 157 Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. 158 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 159 configure a channel on injected group can impact the configuration of other channels previously set. 160 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ 161 162 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. 163 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 164 This parameter can be a value of @ref ADC_injected_external_trigger_source. 165 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 166 configure a channel on injected group can impact the configuration of other channels previously set. */ 167 168 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 169 This parameter can be a value of @ref ADC_injected_external_trigger_edge. 170 If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. 171 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 172 configure a channel on injected group can impact the configuration of other channels previously set. */ 173 174 FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. 175 This parameter can be set to ENABLE or DISABLE. 176 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 177 178 ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. 179 Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. 180 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 181 } ADC_InjectionConfTypeDef; 182 183 #if defined(ADC_MULTIMODE_SUPPORT) 184 /** 185 * @brief Structure definition of ADC multimode 186 * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). 187 * Both Master and Slave ADCs must be disabled. 188 */ 189 typedef struct 190 { 191 uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. 192 This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ 193 194 uint32_t DualModeData; /*!< Configures the Dual ADC Mode Data Format: 195 This parameter can be a value of @ref ADCEx_Dual_Mode_Data_Format */ 196 197 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. 198 This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. 199 Delay range depends on selected resolution: 200 from 1 to 9 clock cycles for 16 bits, 201 from 1 to 9 clock cycles for 14 bits 202 from 1 to 8 clock cycles for 12 bits 203 from 1 to 6 clock cycles for 10 bits 204 from 1 to 6 clock cycles for 8 bits */ 205 } ADC_MultiModeTypeDef; 206 #endif /* ADC_MULTIMODE_SUPPORT */ 207 208 /** 209 * @} 210 */ 211 212 /* Exported constants --------------------------------------------------------*/ 213 214 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants 215 * @{ 216 */ 217 218 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source 219 * @{ 220 */ 221 /* ADC group regular trigger sources for all ADC instances */ 222 #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */ 223 #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */ 224 #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 225 #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */ 226 #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 227 #define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 228 #define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */ 229 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 230 #define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 231 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */ 232 #define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */ 233 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */ 234 #define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 235 #define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */ 236 #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 237 #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */ 238 #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */ 239 #define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */ 240 #define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */ 241 #define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. Trigger edge set to rising edge (default setting). */ 242 /** 243 * @} 244 */ 245 246 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) 247 * @{ 248 */ 249 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ 250 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ 251 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ 252 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ 253 /** 254 * @} 255 */ 256 257 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending 258 * @{ 259 */ 260 #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ 261 #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ 262 /** 263 * @} 264 */ 265 266 /** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number 267 * @{ 268 */ 269 #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ 270 #define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 271 #define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 272 #define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 273 #define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 274 /** 275 * @} 276 */ 277 278 /** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 279 * @{ 280 */ 281 #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ 282 #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ 283 #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ 284 #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ 285 /** 286 * @} 287 */ 288 289 #if defined(ADC_MULTIMODE_SUPPORT) 290 /** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode 291 * @{ 292 */ 293 #define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */ 294 #define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */ 295 #define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */ 296 #define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */ 297 #define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 298 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ 299 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 300 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ 301 302 /** @defgroup ADCEx_Dual_Mode_Data_Format ADC Extended Dual Mode Data Formatting 303 * @{ 304 */ 305 #define ADC_DUALMODEDATAFORMAT_DISABLED (0x00000000UL) /*!< Dual ADC mode without data packing: ADCx_CDR and ADCx_CDR2 registers not used */ 306 #define ADC_DUALMODEDATAFORMAT_32_10_BITS (ADC_CCR_DAMDF_1) /*!< Data formatting mode for 32 down to 10-bit resolution */ 307 #define ADC_DUALMODEDATAFORMAT_8_BITS ((ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1)) /*!< Data formatting mode for 8-bit resolution */ 308 /** 309 * @} 310 */ 311 312 /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 313 * @{ 314 */ 315 #define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ 316 #define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ 317 #define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ 318 #define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ 319 #define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ 320 #define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ 321 #define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ 322 #define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES_5) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ 323 /** 324 * @} 325 */ 326 327 /** 328 * @} 329 */ 330 #endif /* ADC_MULTIMODE_SUPPORT */ 331 332 /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups 333 * @{ 334 */ 335 #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ 336 #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/ 337 #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ 338 /** 339 * @} 340 */ 341 342 /** @defgroup ADC_CFGR_fields ADCx CFGR fields 343 * @{ 344 */ 345 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 346 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 347 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 348 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 349 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | |\ 350 ADC_CFGR_RES | ADC_CFGR_DMNGT ) 351 /** 352 * @} 353 */ 354 355 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields 356 * @{ 357 */ 358 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 359 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 360 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 361 ADC_SMPR1_SMP0) 362 /** 363 * @} 364 */ 365 366 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 367 * @{ 368 */ 369 /* ADC_CFGR fields of parameters that can be updated when no conversion 370 (neither regular nor injected) is on-going */ 371 #define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY)) 372 /** 373 * @} 374 */ 375 376 377 /** 378 * @} 379 */ 380 381 /* Exported macros -----------------------------------------------------------*/ 382 383 #if defined(ADC_MULTIMODE_SUPPORT) 384 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros 385 * @{ 386 */ 387 388 /** @brief Force ADC instance in multimode mode independent (multimode disable). 389 * @note This macro must be used only in case of transition from multimode 390 * to mode independent and in case of unknown previous state, 391 * to ensure ADC configuration is in mode independent. 392 * @note Standard way of multimode configuration change is done from 393 * HAL ADC handle of ADC master using function 394 * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". 395 * Usage of this macro is not the Standard way of multimode 396 * configuration and can lead to have HAL ADC handles status 397 * misaligned. Usage of this macro must be limited to cases 398 * mentioned above. 399 * @param __HANDLE__ ADC handle. 400 * @retval None 401 */ 402 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ 403 LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) 404 405 /** 406 * @} 407 */ 408 #endif /* ADC_MULTIMODE_SUPPORT */ 409 410 /* Private macros ------------------------------------------------------------*/ 411 412 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros 413 * @{ 414 */ 415 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 416 /* code of final user. */ 417 418 /** 419 * @brief Test if conversion trigger of injected group is software start 420 * or external trigger. 421 * @param __HANDLE__ ADC handle. 422 * @retval SET (software start) or RESET (external trigger). 423 */ 424 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 425 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) 426 427 /** 428 * @brief Check whether or not ADC is independent. 429 * @param __HANDLE__ ADC handle. 430 * @note When multimode feature is not available, the macro always returns SET. 431 * @retval SET (ADC is independent) or RESET (ADC is not). 432 */ 433 #define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) 434 435 /** 436 * @brief Set the selected injected Channel rank. 437 * @param __CHANNELNB__ Channel number. 438 * @param __RANKNB__ Rank number. 439 * @retval None 440 */ 441 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\ 442 & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) 443 444 /** 445 * @brief Configure ADC injected context queue 446 * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. 447 * @retval None 448 */ 449 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) 450 451 /** 452 * @brief Configure ADC discontinuous conversion mode for injected group 453 * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. 454 * @retval None 455 */ 456 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) 457 458 /** 459 * @brief Configure ADC discontinuous conversion mode for regular group 460 * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. 461 * @retval None 462 */ 463 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) 464 465 /** 466 * @brief Configure the number of discontinuous conversions for regular group. 467 * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. 468 * @retval None 469 */ 470 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) 471 472 /** 473 * @brief Configure the ADC auto delay mode. 474 * @param __AUTOWAIT__ Auto delay bit enable or disable. 475 * @retval None 476 */ 477 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) 478 479 /** 480 * @brief Configure ADC continuous conversion mode. 481 * @param __CONTINUOUS_MODE__ Continuous mode. 482 * @retval None 483 */ 484 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) 485 486 /** 487 * @brief Enable the ADC DMA continuous request. 488 * @param __DMACONTREQ_MODE__: DMA continuous request mode. 489 * @retval None 490 */ 491 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__)) 492 493 /** 494 * @brief Configure the channel number into offset OFRx register. 495 * @param __CHANNEL__ ADC Channel. 496 * @retval None 497 */ 498 #define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos) 499 500 /** 501 * @brief Configure the channel number into differential mode selection register. 502 * @param __CHANNEL__ ADC Channel. 503 * @retval None 504 */ 505 #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__)) 506 507 /** 508 * @brief Configure calibration factor in differential mode to be set into calibration register. 509 * @param __CALIBRATION_FACTOR__ Calibration factor value. 510 * @retval None 511 */ 512 #define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__)\ 513 & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos) 514 515 /** 516 * @brief Calibration factor in differential mode to be retrieved from calibration register. 517 * @param __CALIBRATION_FACTOR__ Calibration factor value. 518 * @retval None 519 */ 520 #define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos) 521 522 /** 523 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. 524 * @param __THRESHOLD__ Threshold value. 525 * @retval None 526 */ 527 #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL) 528 529 #if defined(ADC_MULTIMODE_SUPPORT) 530 /** 531 * @brief Configure the ADC DMA continuous request for ADC multimode. 532 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 533 * @retval None 534 */ 535 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) 536 #endif /* ADC_MULTIMODE_SUPPORT */ 537 538 /** 539 * @brief Shift the offset in function of the selected ADC resolution. 540 * @note Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0 541 * If resolution 16 bits, no shift. 542 * If resolution 14 bits, shift of 2 ranks on the left. 543 * If resolution 12 bits, shift of 4 ranks on the left. 544 * If resolution 10 bits, shift of 6 ranks on the left. 545 * If resolution 8 bits, shift of 8 ranks on the left. 546 * therefore, shift = (16 - resolution) = 16 - (16 - (((RES[2:0]) >> 2)*2)) 547 * @param __HANDLE__: ADC handle 548 * @param __OFFSET__: Value to be shifted 549 * @retval None 550 */ 551 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 552 ( ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 553 ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 554 : \ 555 ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 556 ) 557 558 /** 559 * @brief Shift the AWD1 threshold in function of the selected ADC resolution. 560 * @note Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0. 561 * If resolution 16 bits, no shift. 562 * If resolution 14 bits, shift of 2 ranks on the left. 563 * If resolution 12 bits, shift of 4 ranks on the left. 564 * If resolution 10 bits, shift of 6 ranks on the left. 565 * If resolution 8 bits, shift of 8 ranks on the left. 566 * therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2)) 567 * @param __HANDLE__: ADC handle 568 * @param __THRESHOLD__: Value to be shifted 569 * @retval None 570 */ 571 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 572 ( ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 573 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 574 : \ 575 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 576 ) 577 578 /** 579 * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution. 580 * @note Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0. 581 * If resolution 16 bits, no shift. 582 * If resolution 14 bits, shift of 2 ranks on the left. 583 * If resolution 12 bits, shift of 4 ranks on the left. 584 * If resolution 10 bits, shift of 6 ranks on the left. 585 * If resolution 8 bits, shift of 8 ranks on the left. 586 * therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2)) 587 * @param __HANDLE__: ADC handle 588 * @param __THRESHOLD__: Value to be shifted 589 * @retval None 590 */ 591 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 592 ( ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 593 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 594 : \ 595 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 596 ) 597 /** 598 * @brief Clear Common Control Register. 599 * @param __HANDLE__ ADC handle. 600 * @retval None 601 */ 602 /** 603 * @brief Report common register to ADC1 and ADC2 604 * @param __HANDLE__: ADC handle 605 * @retval Common control register 606 */ 607 #define ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON) 608 609 /** 610 * @brief Report Master Instance 611 * @param __HANDLE__: ADC handle 612 * @note return same instance if ADC of input handle is independent ADC 613 * @retval Master Instance 614 */ 615 #define ADC_MASTER_REGISTER(__HANDLE__) \ 616 ( ( (((__HANDLE__)->Instance) == ADC1) \ 617 )? \ 618 ((__HANDLE__)->Instance) \ 619 : \ 620 (ADC1) \ 621 ) 622 623 /** 624 * @brief Check whether or not dual regular conversions are enabled 625 * @param __HANDLE__: ADC handle 626 * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled) 627 */ 628 #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \ 629 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ 630 )? \ 631 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \ 632 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \ 633 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \ 634 : \ 635 RESET \ 636 ) 637 638 /** 639 * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master 640 * @param __HANDLE__: ADC handle 641 * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode) 642 */ 643 #define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ 644 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2) \ 645 )? \ 646 SET \ 647 : \ 648 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET) \ 649 ) 650 651 /** 652 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled 653 * @param __HANDLE__: ADC handle 654 * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled) 655 */ 656 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \ 657 ( ( ((__HANDLE__)->Instance == ADC1) \ 658 )? \ 659 SET \ 660 : \ 661 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 662 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \ 663 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) )) 664 665 /** 666 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled 667 * @param __HANDLE__: ADC handle 668 * @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled) 669 */ 670 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \ 671 ( ( ((__HANDLE__)->Instance == ADC1) \ 672 )? \ 673 SET \ 674 : \ 675 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 676 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \ 677 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) )) 678 679 680 681 #if defined(ADC_MULTIMODE_SUPPORT) 682 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \ 683 ADC_CCR_PRESC | \ 684 ADC_CCR_VBATEN | \ 685 ADC_CCR_VSENSEEN | \ 686 ADC_CCR_VREFEN | \ 687 ADC_CCR_DAMDF | \ 688 ADC_CCR_DELAY | \ 689 ADC_CCR_DUAL ) 690 #endif /* ADC_MULTIMODE_SUPPORT */ 691 692 /** 693 * @brief Set handle instance of the ADC slave associated to the ADC master. 694 * @param __HANDLE_MASTER__ ADC master handle. 695 * @param __HANDLE_SLAVE__ ADC slave handle. 696 * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. 697 * @retval None 698 */ 699 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ 700 ( ((__HANDLE_MASTER__)->Instance == ADC1) ? \ 701 ((__HANDLE_SLAVE__)->Instance = ADC2) \ 702 : \ 703 ((__HANDLE_SLAVE__)->Instance = NULL) \ 704 ) 705 706 707 /** 708 * @brief Verify the ADC instance connected to the temperature sensor. 709 * @param __HANDLE__ ADC handle. 710 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 711 */ 712 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) 713 714 /** 715 * @brief Verify the ADC instance connected to the battery voltage VBAT. 716 * @param __HANDLE__ ADC handle. 717 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 718 */ 719 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) 720 721 /** 722 * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. 723 * @param __HANDLE__ ADC handle. 724 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 725 */ 726 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) 727 728 /** 729 * @brief Verify the ADC instance connected to the internal voltage reference VDDCORE. 730 * @param __HANDLE__ ADC handle. 731 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 732 */ 733 /* The internal voltage reference VDDCORE measurement path (channel 0) is available on ADC2 */ 734 #define ADC_VDDCORE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) 735 736 /** 737 * @brief Verify the length of scheduled injected conversions group. 738 * @param __LENGTH__ number of programmed conversions. 739 * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) 740 */ 741 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) 742 743 /** 744 * @brief Calibration factor size verification (7 bits maximum). 745 * @param __CALIBRATION_FACTOR__ Calibration factor value. 746 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) 747 */ 748 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) 749 750 751 /** 752 * @brief Verify the ADC channel setting. 753 * @param __CHANNEL__ programmed ADC channel. 754 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 755 */ 756 #define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \ 757 ((__CHANNEL__) == ADC_CHANNEL_1) || \ 758 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 759 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 760 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 761 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 762 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 763 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 764 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 765 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 766 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 767 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 768 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 769 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 770 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 771 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 772 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 773 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 774 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 775 ((__CHANNEL__) == ADC_CHANNEL_19) || \ 776 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 777 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 778 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2)|| \ 779 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2)|| \ 780 ((__CHANNEL__) == ADC_CHANNEL_VCORE) || \ 781 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) ) 782 783 /** 784 * @brief Verify the ADC channel setting in differential mode for ADC1. 785 * @param __CHANNEL__: programmed ADC channel. 786 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 787 */ 788 #define IS_ADC1_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 789 ((__CHANNEL__) == ADC_CHANNEL_2) ||\ 790 ((__CHANNEL__) == ADC_CHANNEL_3) ||\ 791 ((__CHANNEL__) == ADC_CHANNEL_4) ||\ 792 ((__CHANNEL__) == ADC_CHANNEL_5) ||\ 793 ((__CHANNEL__) == ADC_CHANNEL_10) ||\ 794 ((__CHANNEL__) == ADC_CHANNEL_11) ||\ 795 ((__CHANNEL__) == ADC_CHANNEL_12) ||\ 796 ((__CHANNEL__) == ADC_CHANNEL_16) ||\ 797 ((__CHANNEL__) == ADC_CHANNEL_18) ) 798 799 /** 800 * @brief Verify the ADC channel setting in differential mode for ADC2. 801 * @param __CHANNEL__: programmed ADC channel. 802 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 803 */ 804 #define IS_ADC2_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 805 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 806 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 807 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 808 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 809 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 810 ((__CHANNEL__) == ADC_CHANNEL_18) ) 811 812 /** 813 * @brief Verify the ADC single-ended input or differential mode setting. 814 * @param __SING_DIFF__ programmed channel setting. 815 * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) 816 */ 817 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ 818 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) 819 820 /** 821 * @brief Verify the ADC offset management setting. 822 * @param __OFFSET_NUMBER__ ADC offset management. 823 * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) 824 */ 825 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ 826 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ 827 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ 828 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ 829 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) 830 831 /** 832 * @brief Verify the ADC injected channel setting. 833 * @param __CHANNEL__ programmed ADC injected channel. 834 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 835 */ 836 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ 837 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ 838 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ 839 ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) 840 841 /** 842 * @brief Verify the ADC injected conversions external trigger. 843 * @param __INJTRIG__ programmed ADC injected conversions external trigger. 844 * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) 845 */ 846 #define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 847 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 848 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 849 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 850 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 851 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 852 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 853 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 854 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 855 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 856 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 857 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 858 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 859 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 860 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 861 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 862 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT) || \ 863 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT) || \ 864 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT) || \ 865 \ 866 ((__INJTRIG__) == ADC_SOFTWARE_START) ) 867 868 /** 869 * @brief Verify the ADC edge trigger setting for injected group. 870 * @param __EDGE__ programmed ADC edge trigger setting. 871 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 872 */ 873 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 874 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 875 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 876 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 877 878 #if defined(ADC_MULTIMODE_SUPPORT) 879 /** 880 * @brief Verify the ADC multimode setting. 881 * @param __MODE__ programmed ADC multimode setting. 882 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 883 */ 884 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ 885 ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ 886 ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ 887 ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ 888 ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ 889 ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ 890 ((__MODE__) == ADC_DUALMODE_INTERL) || \ 891 ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) 892 893 /** 894 * @brief Verify the ADC dual data mode setting. 895 * @param MODE: programmed ADC dual mode setting. 896 * @retval SET (MODE is valid) or RESET (MODE is invalid) 897 */ 898 #define IS_ADC_DUAL_DATA_MODE(MODE) (((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED) || \ 899 ((MODE) == ADC_DUALMODEDATAFORMAT_32_10_BITS) || \ 900 ((MODE) == ADC_DUALMODEDATAFORMAT_8_BITS) ) 901 902 /** 903 * @brief Verify the ADC multimode delay setting. 904 * @param __DELAY__ programmed ADC multimode delay setting. 905 * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) 906 */ 907 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ 908 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ 909 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ 910 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ 911 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 912 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 913 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 914 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) ) 915 #endif /* ADC_MULTIMODE_SUPPORT */ 916 917 /** 918 * @brief Verify the ADC analog watchdog setting. 919 * @param __WATCHDOG__ programmed ADC analog watchdog setting. 920 * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) 921 */ 922 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ 923 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ 924 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) 925 926 /** 927 * @brief Verify the ADC analog watchdog mode setting. 928 * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. 929 * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) 930 */ 931 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ 932 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 933 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 934 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 935 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 936 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 937 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 938 939 /** 940 * @brief Verify the ADC conversion (regular or injected or both). 941 * @param __CONVERSION__ ADC conversion group. 942 * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) 943 */ 944 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ 945 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ 946 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) 947 948 /** 949 * @brief Verify the ADC event type. 950 * @param __EVENT__ ADC event. 951 * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) 952 */ 953 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ 954 ((__EVENT__) == ADC_AWD_EVENT) || \ 955 ((__EVENT__) == ADC_AWD2_EVENT) || \ 956 ((__EVENT__) == ADC_AWD3_EVENT) || \ 957 ((__EVENT__) == ADC_OVR_EVENT) || \ 958 ((__EVENT__) == ADC_JQOVF_EVENT) ) 959 960 /** 961 * @brief Verify the ADC oversampling ratio. 962 * @param RATIO: programmed ADC oversampling ratio. 963 * @retval SET (RATIO is a valid value) or RESET (RATIO is invalid) 964 */ 965 #define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) >= 1UL) && ((RATIO) <= 1024UL)) 966 967 /** 968 * @brief Verify the ADC oversampling shift. 969 * @param __SHIFT__ programmed ADC oversampling shift. 970 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) 971 */ 972 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ 973 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ 974 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ 975 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ 976 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ 977 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ 978 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ 979 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ 980 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) 981 982 /** 983 * @brief Verify the ADC oversampling triggered mode. 984 * @param __MODE__ programmed ADC oversampling triggered mode. 985 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 986 */ 987 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 988 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 989 990 /** 991 * @brief Verify the ADC oversampling regular conversion resumed or continued mode. 992 * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. 993 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 994 */ 995 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ 996 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) 997 998 /** 999 * @brief Verify the DFSDM mode configuration. 1000 * @param __HANDLE__ ADC handle. 1001 * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For 1002 * this reason, the input parameter is the ADC handle and not the configuration parameter 1003 * directly. 1004 * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) 1005 */ 1006 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) 1007 1008 /** 1009 * @brief Return the DFSDM configuration mode. 1010 * @param __HANDLE__ ADC handle. 1011 * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). 1012 * For this reason, the input parameter is the ADC handle and not the configuration parameter 1013 * directly. 1014 * @retval DFSDM configuration mode 1015 */ 1016 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) 1017 1018 /** 1019 * @} 1020 */ 1021 1022 1023 /* Exported functions --------------------------------------------------------*/ 1024 /** @addtogroup ADCEx_Exported_Functions 1025 * @{ 1026 */ 1027 1028 /** @addtogroup ADCEx_Exported_Functions_Group1 1029 * @{ 1030 */ 1031 /* IO operation functions *****************************************************/ 1032 1033 /* ADC calibration */ 1034 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff); 1035 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 1036 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer); 1037 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); 1038 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer); 1039 1040 /* Blocking mode: Polling */ 1041 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); 1042 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); 1043 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1044 1045 /* Non-blocking mode: Interruption */ 1046 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); 1047 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); 1048 1049 #if defined(ADC_MULTIMODE_SUPPORT) 1050 /* ADC multimode */ 1051 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1052 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1053 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); 1054 #endif /* ADC_MULTIMODE_SUPPORT */ 1055 1056 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1057 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); 1058 1059 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 1060 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); 1061 void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); 1062 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); 1063 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); 1064 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); 1065 1066 /* ADC group regular conversions stop */ 1067 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); 1068 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); 1069 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); 1070 #if defined(ADC_MULTIMODE_SUPPORT) 1071 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1072 #endif /* ADC_MULTIMODE_SUPPORT */ 1073 1074 /** 1075 * @} 1076 */ 1077 1078 /** @addtogroup ADCEx_Exported_Functions_Group2 1079 * @{ 1080 */ 1081 /* Peripheral Control functions ***********************************************/ 1082 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, 1083 ADC_InjectionConfTypeDef *sConfigInjected); 1084 #if defined(ADC_MULTIMODE_SUPPORT) 1085 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *pmultimode); 1086 #endif /* ADC_MULTIMODE_SUPPORT */ 1087 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); 1088 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); 1089 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); 1090 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); 1091 1092 /** 1093 * @} 1094 */ 1095 1096 /** 1097 * @} 1098 */ 1099 1100 /** 1101 * @} 1102 */ 1103 1104 /** 1105 * @} 1106 */ 1107 1108 #ifdef __cplusplus 1109 } 1110 #endif 1111 1112 #endif /* STM32MP1xx_HAL_ADC_EX_H */ 1113
