1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2019 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32MP1xx_HAL_H 22 #define STM32MP1xx_HAL_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32mp1xx_hal_conf.h" 30 31 /** @addtogroup STM32MP1xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup HAL 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup HAL_Exported_Types HAL Exported Types 41 * @{ 42 */ 43 /** @defgroup HAL_Exported_Types_Group1 Tick Frequency 44 * @{ 45 */ 46 typedef enum 47 { 48 HAL_TICK_FREQ_10HZ = 100U, 49 HAL_TICK_FREQ_100HZ = 10U, 50 HAL_TICK_FREQ_1KHZ = 1U, 51 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 52 } HAL_TickFreqTypeDef; 53 /** 54 * @} 55 */ 56 57 /** @defgroup HAL_Exported_Types_Group2 HDP SW Signal 58 * @{ 59 */ 60 61 /** 62 * @brief HDP SW Signal SET and Bit RESET enumeration 63 */ 64 typedef enum 65 { 66 HDP_SW_SIGNAL_RESET = 0, 67 HDP_SW_SIGNAL_SET 68 }HDP_SwSignalState; 69 /** 70 * @} 71 */ 72 73 /** 74 * @} 75 */ 76 77 /* Exported constants --------------------------------------------------------*/ 78 79 /** @defgroup HAL_Exported_Constants HAL Exported Constants 80 * @{ 81 */ 82 83 /** @defgroup HAL_Exported_Constants_Group1 SYSCFG VREFBUF Voltage Scale 84 * @{ 85 */ 86 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 0 (VREF_OUT2) */ 87 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 1 (VREF_OUT1) */ 88 #define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 2 (VREF_OUT4) */ 89 #define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 3 (VREF_OUT3) */ 90 91 92 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 93 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \ 94 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \ 95 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3)) 96 97 98 /** 99 * @} 100 */ 101 102 /** @defgroup HAL_Exported_Constants_Group2 SYSCFG VREFBUF High Impedance 103 * @{ 104 */ 105 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ 106 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 107 108 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 109 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 110 111 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 112 113 /** 114 * @} 115 */ 116 117 118 /** @defgroup HAL_Exported_Constants_Group3 SYSCFG Ethernet Config 119 * @{ 120 */ 121 122 #define SYSCFG_ETH_MII SYSCFG_PMCSETR_ETH_SELMII_SEL /*!< Select the Media Independent Interface */ 123 #define SYSCFG_ETH_GMII ((uint32_t)0x00000000) /*!< Select the Gigabit Media Independent Interface */ 124 #define SYSCFG_ETH_RMII SYSCFG_PMCSETR_ETH_SEL_2 /*!< Select the Reduced Media Independent Interface */ 125 #define SYSCFG_ETH_RGMII SYSCFG_PMCSETR_ETH_SEL_0 /*!< Select the Reduced Gigabit Media Independent Interface */ 126 127 #define IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH_MII) || \ 128 ((CONFIG) == SYSCFG_ETH_RMII) || \ 129 ((CONFIG) == SYSCFG_ETH_GMII) || \ 130 ((CONFIG) == SYSCFG_ETH_RGMII)) 131 132 /** 133 * @} 134 */ 135 136 137 /** @defgroup HAL_Exported_Constants_Group4 SYSCFG Analog Switch Config 138 * @{ 139 */ 140 #define SYSCFG_SWITCH_PA0 SYSCFG_PMCSETR_ANA0_SEL_SEL /*!< Select PA0 analog switch */ 141 #define SYSCFG_SWITCH_PA1 SYSCFG_PMCSETR_ANA1_SEL_SEL /*!< Select PA1 analog switch */ 142 143 144 #define IS_SYSCFG_ANALOG_SWITCH(SWITCH) ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \ 145 (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1)) 146 147 148 #define SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCSETR_ANA0_SEL_SEL /*!< PA0 analog switch opened */ 149 #define SYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000) /*!< PA0 analog switch closed */ 150 #define SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCSETR_ANA1_SEL_SEL /*!< PA1 analog switch opened */ 151 #define SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000) /*!< PA1 analog switch closed*/ 152 153 #define IS_SYSCFG_SWITCH_STATE(STATE) ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN) || \ 154 (((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE) || \ 155 (((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN) || \ 156 (((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE)) 157 /** 158 * @} 159 */ 160 161 /** @defgroup HAL_Exported_Constants_Group5 SYSCFG IOCompenstionCell Config 162 * @{ 163 */ 164 #define SYSCFG_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */ 165 #define SYSCFG_REGISTER_CODE SYSCFG_CMPCR_SW_CTRL /*!< Code from the SYSCFG compensation cell code register */ 166 167 #define IS_SYSCFG_CODE_SELECT(SELECT) (((SELECT) == SYSCFG_CELL_CODE)|| \ 168 ((SELECT) == SYSCFG_REGISTER_CODE)) 169 170 #define IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10)) 171 172 /** @brief Check SYSCFG Compensation Cell Ready flag is set or not. 173 * @retval State of bit (1 or 0) 174 */ 175 #define __HAL_SYSCFG_CMP_CELL_GET_FLAG() ((READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY)) ? 1U : 0U) 176 177 /** 178 * @brief Get I/O compensation cell value for PMOS transistors 179 * @retval The I/O compensation cell value for PMOS transistors 180 */ 181 #define __HAL_SYSCFG_GET_PMOS_CMP() (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_APSRC)) 182 183 /** 184 * @brief Get I/O compensation cell value for NMOS transistors 185 * @retval Returned value is the I/O compensation cell value for NMOS transistors 186 */ 187 #define __HAL_SYSCFG_GET_NMOS_CMP() (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_ANSRC)) 188 189 /** 190 * @} 191 */ 192 193 /** @defgroup HAL_Exported_Constants_Group6 SYSCFG IOControl HighSpeed Config 194 * @{ 195 */ 196 197 #define SYSCFG_HIGHSPEED_TRACE_SIGNAL SYSCFG_IOCTRLSETR_HSLVEN_TRACE /*!< High Speed Low Voltage Pad mode Enable when a TRACEx signal is selected in AFMUX */ 198 #define SYSCFG_HIGHSPEED_QUADSPI_SIGNAL SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI /*!< High Speed Low Voltage Pad mode Enable when a QUADSPI_x signal is selected in AFMUX */ 199 #define SYSCFG_HIGHSPEED_ETH_SIGNAL SYSCFG_IOCTRLSETR_HSLVEN_ETH /*!< High Speed Low Voltage Pad mode Enable when a ETH_x signal is selected in AFMUX */ 200 #define SYSCFG_HIGHSPEED_SDMMC_SIGNAL SYSCFG_IOCTRLSETR_HSLVEN_SDMMC /*!< High Speed Low Voltage Pad mode Enable when a SDMMCy_x signal is selected in AFMUX */ 201 #define SYSCFG_HIGHSPEED_SPI_SIGNAL SYSCFG_IOCTRLSETR_HSLVEN_SPI /*!< High Speed Low Voltage Pad mode Enable when a SPIy_x signal is selected in AFMUX */ 202 203 204 /** 205 * @} 206 */ 207 208 209 /** @defgroup HAL_Exported_Constants_Group7 HDP Software signal define 210 * @{ 211 */ 212 #define HDP_SW_SIGNAL_0 ((uint8_t)0x01U) /* HDP Software signal 0 selected */ 213 #define HDP_SW_SIGNAL_1 ((uint8_t)0x02U) /* HDP Software signal 1 selected */ 214 #define HDP_SW_SIGNAL_2 ((uint8_t)0x04U) /* HDP Software signal 2 selected */ 215 #define HDP_SW_SIGNAL_3 ((uint8_t)0x08U) /* HDP Software signal 3 selected */ 216 #define HDP_SW_SIGNAL_4 ((uint8_t)0x10U) /* HDP Software signal 4 selected */ 217 #define HDP_SW_SIGNAL_5 ((uint8_t)0x20U) /* HDP Software signal 5 selected */ 218 #define HDP_SW_SIGNAL_6 ((uint8_t)0x40U) /* HDP Software signal 6 selected */ 219 #define HDP_SW_SIGNAL_7 ((uint8_t)0x80U) /* HDP Software signal 7 selected */ 220 221 /** 222 * @} 223 */ 224 225 /** 226 * @} 227 */ 228 229 /* Exported macro ------------------------------------------------------------*/ 230 231 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 232 * @{ 233 */ 234 235 /** @brief Freeze/Unfreeze Peripherals in Debug mode 236 */ 237 #if defined (CORE_CM4) 238 #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) 239 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM2_STOP) 240 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM2_STOP) 241 #endif 242 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP) 243 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM3_STOP) 244 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM3_STOP) 245 #endif 246 #if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP) 247 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM4_STOP) 248 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM4_STOP) 249 #endif 250 #if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP) 251 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM5_STOP) 252 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM5_STOP) 253 #endif 254 #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) 255 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM6_STOP) 256 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM6_STOP) 257 #endif 258 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) 259 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM7_STOP) 260 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM7_STOP) 261 #endif 262 #if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP) 263 #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM12_STOP) 264 #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM12_STOP) 265 #endif 266 #if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP) 267 #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM13_STOP) 268 #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM13_STOP) 269 #endif 270 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP) 271 #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM14_STOP) 272 #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM14_STOP) 273 #endif 274 #if defined(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP) 275 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_LPTIM1_STOP) 276 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_LPTIM1_STOP) 277 #endif 278 #if defined(DBGMCU_APB1_FZ_DBG_WWDG1_STOP) 279 #define __HAL_DBGMCU_FREEZE_WWDG1() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_WWDG1_STOP) 280 #define __HAL_DBGMCU_UNFREEZE_WWDG1() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_WWDG1_STOP) 281 #endif 282 #if defined(DBGMCU_APB1_FZ_DBG_I2C1_STOP) 283 #define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C1_STOP) 284 #define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C1_STOP) 285 #endif 286 #if defined(DBGMCU_APB1_FZ_DBG_I2C2_STOP) 287 #define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C2_STOP) 288 #define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C2_STOP) 289 #endif 290 #if defined(DBGMCU_APB1_FZ_DBG_I2C3_STOP) 291 #define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C3_STOP) 292 #define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C3_STOP) 293 #endif 294 #if defined(DBGMCU_APB1_FZ_DBG_I2C5_STOP) 295 #define __HAL_DBGMCU_FREEZE_I2C5() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C5_STOP) 296 #define __HAL_DBGMCU_UNFREEZE_I2C5() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C5_STOP) 297 #endif 298 299 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP) 300 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM1_STOP) 301 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM1_STOP) 302 #endif 303 #if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP) 304 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM8_STOP) 305 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM8_STOP) 306 #endif 307 #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) 308 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM15_STOP) 309 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM15_STOP) 310 #endif 311 #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP) 312 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM16_STOP) 313 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM16_STOP) 314 #endif 315 #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP) 316 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM17_STOP) 317 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM17_STOP) 318 #endif 319 #if defined(DBGMCU_APB2_FZ_DBG_FDCAN_STOP) 320 #define __HAL_DBGMCU_FREEZE_FDCAN() SET_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_FDCAN_STOP) 321 #define __HAL_DBGMCU_UNFREEZE_FDCAN() CLEAR_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_FDCAN_STOP) 322 #endif 323 324 #if defined(DBGMCU_APB3_FZ_DBG_LPTIM2_STOP) 325 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM2_STOP) 326 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM2_STOP) 327 #endif 328 #if defined(DBGMCU_APB3_FZ_DBG_LPTIM3_STOP) 329 #define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM3_STOP) 330 #define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM3_STOP) 331 #endif 332 #if defined(DBGMCU_APB3_FZ_DBG_LPTIM4_STOP) 333 #define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM4_STOP) 334 #define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM4_STOP) 335 #endif 336 #if defined(DBGMCU_APB3_FZ_DBG_LPTIM5_STOP) 337 #define __HAL_DBGMCU_FREEZE_LPTIM5() SET_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM5_STOP) 338 #define __HAL_DBGMCU_UNFREEZE_LPTIM5() CLEAR_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM5_STOP) 339 #endif 340 341 #if defined(DBGMCU_APB5_FZ_DBG_I2C4_STOP) 342 #define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB5FZ2, DBGMCU_APB5_FZ_DBG_I2C4_STOP) 343 #define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB5FZ2, DBGMCU_APB5_FZ_DBG_I2C4_STOP) 344 #endif 345 #if defined(DBGMCU_APB5_FZ_DBG_RTC_STOP) 346 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB5FZ2, DBGMCU_APB5_FZ_DBG_RTC_STOP) 347 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB5FZ2, DBGMCU_APB5_FZ_DBG_RTC_STOP) 348 #endif 349 #if defined(DBGMCU_APB5_FZ_DBG_I2C6_STOP) 350 #define __HAL_DBGMCU_FREEZE_I2C6() SET_BIT(DBGMCU->APB5FZ2, DBGMCU_APB5_FZ_DBG_I2C6_STOP) 351 #define __HAL_DBGMCU_UNFREEZE_I2C6() CLEAR_BIT(DBGMCU->APB5FZ2, DBGMCU_APB5_FZ_DBG_I2C6_STOP) 352 #endif 353 #elif defined(CORE_CA7) 354 355 #if defined(DBGMCU_APB4_FZ_DBG_IWDG2_STOP) 356 #define __HAL_DBGMCU_FREEZE_IWDG2() SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4_FZ_DBG_IWDG2_STOP) 357 #define __HAL_DBGMCU_UNFREEZE_IWDG2() CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4_FZ_DBG_IWDG2_STOP) 358 #endif 359 360 #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) 361 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM2_STOP) 362 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM2_STOP) 363 #endif 364 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP) 365 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM3_STOP) 366 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM3_STOP) 367 #endif 368 #if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP) 369 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM4_STOP) 370 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM4_STOP) 371 #endif 372 #if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP) 373 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM5_STOP) 374 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM5_STOP) 375 #endif 376 #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) 377 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM6_STOP) 378 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM6_STOP) 379 #endif 380 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) 381 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM7_STOP) 382 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM7_STOP) 383 #endif 384 #if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP) 385 #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM12_STOP) 386 #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM12_STOP) 387 #endif 388 #if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP) 389 #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM13_STOP) 390 #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM13_STOP) 391 #endif 392 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP) 393 #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM14_STOP) 394 #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM14_STOP) 395 #endif 396 #if defined(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP) 397 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_LPTIM1_STOP) 398 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_LPTIM1_STOP) 399 #endif 400 #if defined(DBGMCU_APB1_FZ_DBG_WWDG1_STOP) 401 #define __HAL_DBGMCU_FREEZE_WWDG1() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_WWDG1_STOP) 402 #define __HAL_DBGMCU_UNFREEZE_WWDG1() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_WWDG1_STOP) 403 #endif 404 #if defined(DBGMCU_APB1_FZ_DBG_I2C1_STOP) 405 #define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C1_STOP) 406 #define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C1_STOP) 407 #endif 408 #if defined(DBGMCU_APB1_FZ_DBG_I2C2_STOP) 409 #define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C2_STOP) 410 #define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C2_STOP) 411 #endif 412 #if defined(DBGMCU_APB1_FZ_DBG_I2C3_STOP) 413 #define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C3_STOP) 414 #define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C3_STOP) 415 #endif 416 #if defined(DBGMCU_APB1_FZ_DBG_I2C5_STOP) 417 #define __HAL_DBGMCU_FREEZE_I2C5() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C5_STOP) 418 #define __HAL_DBGMCU_UNFREEZE_I2C5() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C5_STOP) 419 #endif 420 421 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP) 422 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM1_STOP) 423 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM1_STOP) 424 #endif 425 #if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP) 426 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM8_STOP) 427 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM8_STOP) 428 #endif 429 #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) 430 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM15_STOP) 431 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM15_STOP) 432 #endif 433 #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP) 434 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM16_STOP) 435 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM16_STOP) 436 #endif 437 #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP) 438 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM17_STOP) 439 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM17_STOP) 440 #endif 441 #if defined(DBGMCU_APB2_FZ_DBG_FDCAN_STOP) 442 #define __HAL_DBGMCU_FREEZE_FDCAN() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_FDCAN_STOP) 443 #define __HAL_DBGMCU_UNFREEZE_FDCAN() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_FDCAN_STOP) 444 #endif 445 446 #if defined(DBGMCU_APB3_FZ_DBG_LPTIM2_STOP) 447 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM2_STOP) 448 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM2_STOP) 449 #endif 450 #if defined(DBGMCU_APB3_FZ_DBG_LPTIM3_STOP) 451 #define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM3_STOP) 452 #define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM3_STOP) 453 #endif 454 #if defined(DBGMCU_APB3_FZ_DBG_LPTIM4_STOP) 455 #define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM4_STOP) 456 #define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM4_STOP) 457 #endif 458 #if defined(DBGMCU_APB3_FZ_DBG_LPTIM5_STOP) 459 #define __HAL_DBGMCU_FREEZE_LPTIM5() SET_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM5_STOP) 460 #define __HAL_DBGMCU_UNFREEZE_LPTIM5() CLEAR_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM5_STOP) 461 #endif 462 463 #if defined(DBGMCU_APB5_FZ_DBG_I2C4_STOP) 464 #define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_I2C4_STOP) 465 #define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_I2C4_STOP) 466 #endif 467 #if defined(DBGMCU_APB5_FZ_DBG_IWDG1_STOP) 468 #define __HAL_DBGMCU_FREEZE_IWDG1() SET_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_IWDG1_STOP) 469 #define __HAL_DBGMCU_UNFREEZE_IWDG1() CLEAR_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_IWDG1_STOP) 470 #endif 471 #if defined(DBGMCU_APB5_FZ_DBG_RTC_STOP) 472 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_RTC_STOP) 473 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_RTC_STOP) 474 #endif 475 #if defined(DBGMCU_APB5_FZ_DBG_I2C6_STOP) 476 #define __HAL_DBGMCU_FREEZE_I2C6() SET_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_I2C6_STOP) 477 #define __HAL_DBGMCU_UNFREEZE_I2C6() CLEAR_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_I2C6_STOP) 478 #endif 479 480 #endif 481 482 /** 483 * @} 484 */ 485 486 /** @defgroup HDP_Exported_Macros HDP Exported Macros 487 * @{ 488 */ 489 490 /** @addtogroup HDP_Enable 491 * @{ 492 */ 493 #define __HAL_HDP_ENABLE() SET_BIT(HDP->HDP_CTRL, HDP_CTRL_EN) 494 /** 495 * @} 496 */ 497 498 499 500 /** @addtogroup HDP_Configure_SW_Programmable_Signals 501 * @{ 502 */ 503 504 /** @brief This macros allows atomic write of HDP_GPOVAL register 505 It uses HDP_GPOSET and HDP_GPOCLR regsiters to toogle 506 * 507 * @param __HDP_SW_Signal__: specifies the sw signal bit to be written. 508 * This parameter can be one of HDP_SW_SIGNAL_x(s) where x can be (0..7). 509 * @param __HDP_SwSignalState__: specifies the value to be written to the selected bit. 510 * This parameter can be one of the HDP_SwSignalState enum values: 511 * @arg HDP_SW_SIGNAL_RESET: to clear the signal pin 512 * @arg HDP_SW_SIGNAL_SET: to set the signal pin 513 */ 514 #define __HAL_HDP_ATOMIC_WRITE_GPOVAL(__HDP_SW_Signal__, __HDP_SwSignalState__) \ 515 do { \ 516 if ((__HDP_SwSignalState__) != HDP_SW_SIGNAL_RESET) \ 517 { \ 518 WRITE_REG(HDP->HDP_GPOSET, (uint8_t)(__HDP_SW_Signal__)); \ 519 } \ 520 else \ 521 { \ 522 WRITE_REG(HDP->HDP_GPOCLR, (uint8_t)(__HDP_SW_Signal__)); \ 523 } \ 524 } while(0) 525 526 /** @brief This macros allows non-atomic write of HDP_GPOVAL register 527 * 528 * @param __GPOValue__: specifies the value to set in HDP_GPOVAL register 529 * 530 */ 531 #define __HAL_HDP_NON_ATOMIC_WRITE_GPOVAL(__GPOValue__) WRITE_REG(HDP->HDP_GPOVAL, (uint8_t)(__GPOValue__)) 532 533 /** @brief This macros returns value of HDP_GPOVAL register 534 * 535 * @retval the value to set in HDP_GPOVAL register 536 */ 537 #define __HAL_HDP_READ_GPOVAL() READ_REG(HDP->HDP_GPOVAL) 538 539 /** 540 * @} 541 */ 542 543 /** @addtogroup HDP0_MUX0_Config 544 * @{ 545 */ 546 #define __HAL_HDP0_SELECT_PWR_PWRWAKE_SYS() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) 0x00000000)) 547 #define __HAL_HDP0_SELECT_CM4_SLEEPDEEP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_0)) 548 #define __HAL_HDP0_SELECT_PWR_STDBY_WKUP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_1)) 549 #define __HAL_HDP0_SELECT_PWR_ENCOMP_VDDCORE() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_1 | HDP_MUX_MUX0_0)) 550 #define __HAL_HDP0_SELECT_BSEC_OUT_SEC_NIDEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_2)) 551 #define __HAL_HDP0_SELECT_RCC_CM4_SLEEPDEEP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_2 | HDP_MUX_MUX0_1)) 552 #define __HAL_HDP0_SELECT_GPU_DBG7() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_2 | HDP_MUX_MUX0_1 | HDP_MUX_MUX0_0)) 553 #define __HAL_HDP0_SELECT_DDRCTRL_IP_REQ() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_3)) 554 #define __HAL_HDP0_SELECT_PWR_DDR_RET_ENABLE_N() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_3 | HDP_MUX_MUX0_0)) 555 #define __HAL_HDP0_SELECT_GPOVAL_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_3 | HDP_MUX_MUX0_2 | HDP_MUX_MUX0_1 | HDP_MUX_MUX0_0)) 556 557 /** 558 * @} 559 */ 560 561 /** @addtogroup HDP1_MUX1_Config 562 * @{ 563 */ 564 #define __HAL_HDP1_SELECT_PWR_PWRWAKE_MCU() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) 0x00000000)) 565 #define __HAL_HDP1_SELECT_CM4_HALTED() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_0)) 566 #define __HAL_HDP1_SELECT_CA7_nAXIERRIRQ() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_1)) 567 #define __HAL_HDP1_SELECT_PWR_OKIN_MR() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_1 | HDP_MUX_MUX1_0)) 568 #define __HAL_HDP1_SELECT_BSEC_OUT_SEC_DBGEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_2)) 569 #define __HAL_HDP1_SELECT_EXTI_SYS_WAKEUP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_2 | HDP_MUX_MUX1_0)) 570 #define __HAL_HDP1_SELECT_RCC_PWRDS_MPU() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_2 | HDP_MUX_MUX1_1)) 571 #define __HAL_HDP1_SELECT_GPU_DBG6() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_2 | HDP_MUX_MUX1_1 | HDP_MUX_MUX1_0)) 572 #define __HAL_HDP1_SELECT_DDRCTRL_DFI_CTRLUPD_REQ() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_3)) 573 #define __HAL_HDP1_SELECT_DDRCTRL_CACTIVE_DDRC_ASR() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_3 | HDP_MUX_MUX1_0)) 574 #define __HAL_HDP1_SELECT_GPOVAL_1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_3 | HDP_MUX_MUX1_2 | HDP_MUX_MUX1_1 | HDP_MUX_MUX1_0)) 575 576 /** 577 * @} 578 */ 579 580 /** @addtogroup HDP2_MUX2_Config 581 * @{ 582 */ 583 #define __HAL_HDP2_SELECT_PWR_PWRWAKE_MPU() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) 0x00000000)) 584 #define __HAL_HDP2_SELECT_CM4_RXEV() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_0)) 585 #define __HAL_HDP2_SELECT_CA7_nPMUIRQ1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_1)) 586 #define __HAL_HDP2_SELECT_CA7_nFIQOUT1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_1 | HDP_MUX_MUX2_0)) 587 #define __HAL_HDP2_SELECT_BSEC_IN_RSTCORE_n() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_2)) 588 #define __HAL_HDP2_SELECT_EXTI_C2_WAKEUP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_2 | HDP_MUX_MUX2_0)) 589 #define __HAL_HDP2_SELECT_RCC_PWRDS_MCU() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_2 | HDP_MUX_MUX2_1)) 590 #define __HAL_HDP2_SELECT_GPU_DBG5() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_2 | HDP_MUX_MUX2_1 | HDP_MUX_MUX2_0)) 591 #define __HAL_HDP2_SELECT_DDRCTRL_DFI_INIT_COMPLETE() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_3)) 592 #define __HAL_HDP2_SELECT_DDRCTRL_PERF_OP_IS_REFRESH() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_3 | HDP_MUX_MUX2_0)) 593 #define __HAL_HDP2_SELECT_DDRCTRL_GSKP_DFI_LP_REQ() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_3 | HDP_MUX_MUX2_1)) 594 #define __HAL_HDP2_SELECT_GPOVAL_2() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_3 | HDP_MUX_MUX2_2 | HDP_MUX_MUX2_1 | HDP_MUX_MUX2_0)) 595 596 /** 597 * @} 598 */ 599 600 /** @addtogroup HDP3_MUX3_Config 601 * @{ 602 */ 603 #define __HAL_HDP3_SELECT_PWR_SEL_VTH_VDD_CORE() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) 0x00000000)) 604 #define __HAL_HDP3_SELECT_CM4_TXEV() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_0)) 605 #define __HAL_HDP3_SELECT_CA7_nPMUIRQ0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_1)) 606 #define __HAL_HDP3_SELECT_CA7_nFIQOUT0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_1 | HDP_MUX_MUX3_0)) 607 #define __HAL_HDP3_SELECT_BSEC_OUT_SEC_DFTLOCK() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_2)) 608 #define __HAL_HDP3_SELECT_EXTI_C1_WAKEUP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_2 | HDP_MUX_MUX3_0)) 609 #define __HAL_HDP3_SELECT_RCC_PWRDS_SYS() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_2 | HDP_MUX_MUX3_1)) 610 #define __HAL_HDP3_SELECT_GPU_DBG4() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_2 | HDP_MUX_MUX3_1 | HDP_MUX_MUX3_0)) 611 #define __HAL_HDP3_SELECT_DDRCTRL_STAT_DDRC_REG_SELREF_TYPE_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_3)) 612 #define __HAL_HDP3_SELECT_DDRCTRL_CACTIVE_1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_3 | HDP_MUX_MUX3_0)) 613 #define __HAL_HDP3_SELECT_GPOVAL_3() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_3 | HDP_MUX_MUX3_2 | HDP_MUX_MUX3_1 | HDP_MUX_MUX3_0)) 614 615 /** 616 * @} 617 */ 618 619 /** @addtogroup HDP4_MUX4_Config 620 * @{ 621 */ 622 #define __HAL_HDP4_SELECT_PWR_MPUCR() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) 0x00000000)) 623 #define __HAL_HDP4_SELECT_CM4_SLEEPING() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_0)) 624 #define __HAL_HDP4_SELECT_CA7_nRESET1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_1)) 625 #define __HAL_HDP4_SELECT_CA7_nIRQOUT1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_1 | HDP_MUX_MUX4_0)) 626 #define __HAL_HDP4_SELECT_BSEC_OUT_SEC_DFTEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_2)) 627 #define __HAL_HDP4_SELECT_BSEC_OUT_SEC_DBGSWENABLE() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_2 | HDP_MUX_MUX4_0)) 628 #define __HAL_HDP4_SELECT_ETH_OUT_PMT_INTR_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_2 | HDP_MUX_MUX4_1)) 629 #define __HAL_HDP4_SELECT_GPU_DBG3() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_2 | HDP_MUX_MUX4_1 | HDP_MUX_MUX4_0)) 630 #define __HAL_HDP4_SELECT_DDRCTRL_STAT_DDRC_REG_SELREF_TYPE_1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_3)) 631 #define __HAL_HDP4_SELECT_DDRCTRL_CACTIVE_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_3 | HDP_MUX_MUX4_0)) 632 #define __HAL_HDP4_SELECT_GPOVAL_4() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_3 | HDP_MUX_MUX4_2 | HDP_MUX_MUX4_1 | HDP_MUX_MUX4_0)) 633 634 /** 635 * @} 636 */ 637 638 /** @addtogroup HDP5_MUX5_Config 639 * @{ 640 */ 641 #define __HAL_HDP5_SELECT_CA7_STANDBYWFIL2() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) 0x00000000)) 642 #define __HAL_HDP5_SELECT_PWR_VTH_VDDCORE_ACK() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_0)) 643 #define __HAL_HDP5_SELECT_CA7_nRESET0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_1)) 644 #define __HAL_HDP5_SELECT_CA7_nIRQOUT0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_1 | HDP_MUX_MUX5_0)) 645 #define __HAL_HDP5_SELECT_BSEC_IN_PWROK() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_2)) 646 #define __HAL_HDP5_SELECT_BSEC_OUT_SEC_DEVICEEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_2 | HDP_MUX_MUX5_0)) 647 #define __HAL_HDP5_SELECT_ETH_OUT_LPI_INTR_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_2 | HDP_MUX_MUX5_1)) 648 #define __HAL_HDP5_SELECT_GPU_DBG2() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_2 | HDP_MUX_MUX5_1 | HDP_MUX_MUX5_0)) 649 #define __HAL_HDP5_SELECT_DDRCTRL_CACTIVE_DDRC() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_3)) 650 #define __HAL_HDP5_SELECT_DDRCTRL_WR_CREDIT_CNT_4_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_3 | HDP_MUX_MUX5_0))) 651 #define __HAL_HDP5_SELECT_GPOVAL_5() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_3 | HDP_MUX_MUX5_2 | HDP_MUX_MUX5_1 | HDP_MUX_MUX5_0)) 652 /** 653 * @} 654 */ 655 656 /** @addtogroup HDP6_MUX6_Config 657 * @{ 658 */ 659 #define __HAL_HDP6_SELECT_CA7_STANDBYWFI1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) 0x00000000)) 660 #define __HAL_HDP6_SELECT_CA7_STANDBYWFE1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_0)) 661 #define __HAL_HDP6_SELECT_CA7_EVENTO() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_1)) 662 #define __HAL_HDP6_SELECT_CA7_DBGACK1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_1 | HDP_MUX_MUX6_0)) 663 #define __HAL_HDP6_SELECT_BSEC_OUT_SEC_SPNIDEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_2 | HDP_MUX_MUX6_0)) 664 #define __HAL_HDP6_SELECT_ETH_OUT_MAC_SPEED_O1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_2 | HDP_MUX_MUX6_1)) 665 #define __HAL_HDP6_SELECT_GPU_DBG1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_2 | HDP_MUX_MUX6_1 | HDP_MUX_MUX6_0)) 666 #define __HAL_HDP6_SELECT_DDRCTRL_CSYSACK_DDRC() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_3)) 667 #define __HAL_HDP6_SELECT_DDRCTRL_LPR_CREDIT_CNT_4_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_3 | HDP_MUX_MUX6_0)) 668 #define __HAL_HDP6_SELECT_GPOVAL_6() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_3 | HDP_MUX_MUX6_2 | HDP_MUX_MUX6_1 | HDP_MUX_MUX6_0)) 669 670 /** 671 * @} 672 */ 673 674 /** @addtogroup HDP7_MUX7_Config 675 * @{ 676 */ 677 #define __HAL_HDP7_SELECT_CA7_STANDBYWFI0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) 0x00000000)) 678 #define __HAL_HDP7_SELECT_CA7_STANDBYWFE0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_0)) 679 #define __HAL_HDP7_SELECT_CA7_DBGACK0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_1 | HDP_MUX_MUX7_0)) 680 #define __HAL_HDP7_SELECT_BSEC_OUT_FUSE_OK() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_2)) 681 #define __HAL_HDP7_SELECT_BSEC_OUT_SEC_SPIDEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_2 | HDP_MUX_MUX7_0)) 682 #define __HAL_HDP7_SELECT_ETH_OUT_MAC_SPEED_O0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_2 | HDP_MUX_MUX7_1)) 683 #define __HAL_HDP7_SELECT_GPU_DBG0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_2 | HDP_MUX_MUX7_1 | HDP_MUX_MUX7_0)) 684 #define __HAL_HDP7_SELECT_DDRCTRL_CSYSREQ_DDRC() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_3)) 685 #define __HAL_HDP7_SELECT_DDRCTRL_HPR_CREDIT_CNT_4_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_3 | HDP_MUX_MUX7_0)) 686 #define __HAL_HDP7_SELECT_GPOVAL_7() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_3 | HDP_MUX_MUX7_2 | HDP_MUX_MUX7_1 | HDP_MUX_MUX7_0)) 687 /** 688 * @} 689 */ 690 691 /** 692 * @} 693 */ 694 695 696 /** @defgroup HAL_Private_Macros HAL Private Macros 697 * @{ 698 */ 699 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 700 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 701 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 702 /** 703 * @} 704 */ 705 706 /* Exported variables --------------------------------------------------------*/ 707 708 /** @addtogroup HAL_Exported_Variables 709 * @{ 710 */ 711 extern __IO uint32_t uwTick; 712 extern uint32_t uwTickPrio; 713 extern HAL_TickFreqTypeDef uwTickFreq; 714 /** 715 * @} 716 */ 717 718 /* Exported functions --------------------------------------------------------*/ 719 /** @defgroup HAL_Exported_Functions HAL Exported Functions 720 * @{ 721 */ 722 723 /* Initialization and de-initialization functions ******************************/ 724 /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization functions 725 * @{ 726 */ 727 HAL_StatusTypeDef HAL_Init(void); 728 HAL_StatusTypeDef HAL_DeInit(void); 729 void HAL_MspInit(void); 730 void HAL_MspDeInit(void); 731 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); 732 733 void HAL_EnableDBGWakeUp(void); 734 void HAL_DisableDBGWakeUp(void); 735 /** 736 * @} 737 */ 738 739 /* Peripheral Control functions ************************************************/ 740 /** @defgroup HAL_Exported_Functions_Group2 Peripheral Control functions 741 * @{ 742 */ 743 void HAL_IncTick(void); 744 void HAL_Delay(uint32_t Delay); 745 uint32_t HAL_GetTick(void); 746 uint32_t HAL_GetTickPrio(void); 747 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 748 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 749 void HAL_SuspendTick(void); 750 void HAL_ResumeTick(void); 751 uint32_t HAL_GetHalVersion(void); 752 uint32_t HAL_GetREVID(void); 753 uint32_t HAL_GetDEVID(void); 754 uint32_t HAL_GetUIDw0(void); 755 uint32_t HAL_GetUIDw1(void); 756 uint32_t HAL_GetUIDw2(void); 757 void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface); 758 void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ); 759 void HAL_SYSCFG_EnableBOOST(void); 760 void HAL_SYSCFG_DisableBOOST(void); 761 void HAL_EnableCompensationCell(void); 762 void HAL_DisableCompensationCell(void); 763 void HAL_SYSCFG_EnableIOSpeedOptimize(uint32_t SYSCFG_HighSpeedSignal); 764 void HAL_SYSCFG_DisableIOSpeedOptimize(uint32_t SYSCFG_HighSpeedSignal); 765 void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode); 766 void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode); 767 HAL_StatusTypeDef HAL_SYSCFG_EnableIOCompensation(void); 768 void HAL_SYSCFG_DisableIOCompensation(void); 769 void HAL_EnableDBGSleepMode(void); 770 void HAL_DisableDBGSleepMode(void); 771 void HAL_EnableDBGStopMode(void); 772 void HAL_DisableDBGStopMode(void); 773 void HAL_EnableDBGStandbyMode(void); 774 void HAL_DisableDBGStandbyMode(void); 775 void HAL_EnableDBGWakeUp(void); 776 void HAL_DisableDBGWakeUp(void); 777 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 778 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 779 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 780 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 781 void HAL_SYSCFG_DisableVREFBUF(void); 782 /** 783 * @} 784 */ 785 786 /** 787 * @} 788 */ 789 790 /** 791 * @} 792 */ 793 794 /** 795 * @} 796 */ 797 798 #ifdef __cplusplus 799 } 800 #endif 801 802 #endif /* STM32MP1xx_HAL_H */ 803
