1 /**
2 ******************************************************************************
3 * @file partition_stm32l562xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32L562xx Device Initial Setup for Secure / Non-Secure Zones
6 * for ARMCM33 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template.
7 *
8 * This file contains:
9 * - Initialize Security Attribution Unit (SAU) CTRL register
10 * - Setup behavior of Sleep and Exception Handling
11 * - Setup behavior of Floating Point Unit
12 * - Setup Interrupt Target
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2019 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 */
26
27 #ifndef PARTITION_STM32L562XX_H
28 #define PARTITION_STM32L562XX_H
29
30 /*
31 //-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
32 */
33
34 /*
35 // <e>Initialize Security Attribution Unit (SAU) CTRL register
36 */
37 #define SAU_INIT_CTRL 1
38
39 /*
40 // <q> Enable SAU
41 // <i> Value for SAU->CTRL register bit ENABLE
42 */
43 #define SAU_INIT_CTRL_ENABLE 1
44
45 /*
46 // <o> When SAU is disabled
47 // <0=> All Memory is Secure
48 // <1=> All Memory is Non-Secure
49 // <i> Value for SAU->CTRL register bit ALLNS
50 // <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
51 */
52 #define SAU_INIT_CTRL_ALLNS 0
53
54 /*
55 // </e>
56 */
57
58 /*
59 // <h>Initialize Security Attribution Unit (SAU) Address Regions
60 // <i>SAU configuration specifies regions to be one of:
61 // <i> - Secure and Non-Secure Callable
62 // <i> - Non-Secure
63 // <i>Note: All memory regions not configured by SAU are Secure
64 */
65 #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
66
67 /*
68 // <e>Initialize SAU Region 0
69 // <i> Setup SAU Region 0 memory attributes
70 */
71 #define SAU_INIT_REGION0 1
72
73 /*
74 // <o>Start Address <0-0xFFFFFFE0>
75 */
76 #define SAU_INIT_START0 0x0C03E000 /* start address of SAU region 0 */
77
78 /*
79 // <o>End Address <0x1F-0xFFFFFFFF>
80 */
81 #define SAU_INIT_END0 0x0C03FFFF /* end address of SAU region 0 */
82
83 /*
84 // <o>Region is
85 // <0=>Non-Secure
86 // <1=>Secure, Non-Secure Callable
87 */
88 #define SAU_INIT_NSC0 1
89 /*
90 // </e>
91 */
92
93 /*
94 // <e>Initialize SAU Region 1
95 // <i> Setup SAU Region 1 memory attributes
96 */
97 #define SAU_INIT_REGION1 1
98
99 /*
100 // <o>Start Address <0-0xFFFFFFE0>
101 */
102 #define SAU_INIT_START1 0x08040000 /* start address of SAU region 1 */
103
104 /*
105 // <o>End Address <0x1F-0xFFFFFFFF>
106 */
107 #define SAU_INIT_END1 0x0807FFFF /* end address of SAU region 1 */
108
109 /*
110 // <o>Region is
111 // <0=>Non-Secure
112 // <1=>Secure, Non-Secure Callable
113 */
114 #define SAU_INIT_NSC1 0
115 /*
116 // </e>
117 */
118
119 /*
120 // <e>Initialize SAU Region 2
121 // <i> Setup SAU Region 2 memory attributes
122 */
123 #define SAU_INIT_REGION2 1
124
125 /*
126 // <o>Start Address <0-0xFFFFFFE0>
127 */
128 #define SAU_INIT_START2 0x20018000 /* start address of SAU region 2 */
129
130 /*
131 // <o>End Address <0x1F-0xFFFFFFFF>
132 */
133 #define SAU_INIT_END2 0x2003FFFF /* end address of SAU region 2 */
134
135 /*
136 // <o>Region is
137 // <0=>Non-Secure
138 // <1=>Secure, Non-Secure Callable
139 */
140 #define SAU_INIT_NSC2 0
141 /*
142 // </e>
143 */
144
145 /*
146 // <e>Initialize SAU Region 3
147 // <i> Setup SAU Region 3 memory attributes
148 */
149 #define SAU_INIT_REGION3 1
150
151 /*
152 // <o>Start Address <0-0xFFFFFFE0>
153 */
154 #define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */
155
156 /*
157 // <o>End Address <0x1F-0xFFFFFFFF>
158 */
159 #define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */
160
161 /*
162 // <o>Region is
163 // <0=>Non-Secure
164 // <1=>Secure, Non-Secure Callable
165 */
166 #define SAU_INIT_NSC3 0
167 /*
168 // </e>
169 */
170
171 /*
172 // <e>Initialize SAU Region 4
173 // <i> Setup SAU Region 4 memory attributes
174 */
175 #define SAU_INIT_REGION4 1
176
177 /*
178 // <o>Start Address <0-0xFFFFFFE0>
179 */
180 #define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */
181
182 /*
183 // <o>End Address <0x1F-0xFFFFFFFF>
184 */
185 #define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */
186
187 /*
188 // <o>Region is
189 // <0=>Non-Secure
190 // <1=>Secure, Non-Secure Callable
191 */
192 #define SAU_INIT_NSC4 0
193 /*
194 // </e>
195 */
196
197 /*
198 // <e>Initialize SAU Region 5
199 // <i> Setup SAU Region 5 memory attributes
200 */
201 #define SAU_INIT_REGION5 1
202
203 /*
204 // <o>Start Address <0-0xFFFFFFE0>
205 */
206 #define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */
207
208 /*
209 // <o>End Address <0x1F-0xFFFFFFFF>
210 */
211 #define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */
212
213 /*
214 // <o>Region is
215 // <0=>Non-Secure
216 // <1=>Secure, Non-Secure Callable
217 */
218 #define SAU_INIT_NSC5 0
219 /*
220 // </e>
221 */
222
223 /*
224 // <e>Initialize SAU Region 6
225 // <i> Setup SAU Region 6 memory attributes
226 */
227 #define SAU_INIT_REGION6 0
228
229 /*
230 // <o>Start Address <0-0xFFFFFFE0>
231 */
232 #define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */
233
234 /*
235 // <o>End Address <0x1F-0xFFFFFFFF>
236 */
237 #define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */
238
239 /*
240 // <o>Region is
241 // <0=>Non-Secure
242 // <1=>Secure, Non-Secure Callable
243 */
244 #define SAU_INIT_NSC6 0
245 /*
246 // </e>
247 */
248
249 /*
250 // <e>Initialize SAU Region 7
251 // <i> Setup SAU Region 7 memory attributes
252 */
253 #define SAU_INIT_REGION7 0
254
255 /*
256 // <o>Start Address <0-0xFFFFFFE0>
257 */
258 #define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */
259
260 /*
261 // <o>End Address <0x1F-0xFFFFFFFF>
262 */
263 #define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */
264
265 /*
266 // <o>Region is
267 // <0=>Non-Secure
268 // <1=>Secure, Non-Secure Callable
269 */
270 #define SAU_INIT_NSC7 0
271 /*
272 // </e>
273 */
274
275 /*
276 // </h>
277 */
278
279 /*
280 // <e>Setup behaviour of Sleep and Exception Handling
281 */
282 #define SCB_CSR_AIRCR_INIT 0
283
284 /*
285 // <o> Deep Sleep can be enabled by
286 // <0=>Secure and Non-Secure state
287 // <1=>Secure state only
288 // <i> Value for SCB->CSR register bit DEEPSLEEPS
289 */
290 #define SCB_CSR_DEEPSLEEPS_VAL 0
291
292 /*
293 // <o>System reset request accessible from
294 // <0=> Secure and Non-Secure state
295 // <1=> Secure state only
296 // <i> Value for SCB->AIRCR register bit SYSRESETREQS
297 */
298 #define SCB_AIRCR_SYSRESETREQS_VAL 0
299
300 /*
301 // <o>Priority of Non-Secure exceptions is
302 // <0=> Not altered
303 // <1=> Lowered to 0x04-0x07
304 // <i> Value for SCB->AIRCR register bit PRIS
305 */
306 #define SCB_AIRCR_PRIS_VAL 0
307
308 /*
309 // <o>BusFault, HardFault, and NMI target
310 // <0=> Secure state
311 // <1=> Non-Secure state
312 // <i> Value for SCB->AIRCR register bit BFHFNMINS
313 */
314 #define SCB_AIRCR_BFHFNMINS_VAL 0
315
316 /*
317 // </e>
318 */
319
320 /*
321 // <e>Setup behaviour of Floating Point Unit
322 */
323 #define TZ_FPU_NS_USAGE 1
324
325 /*
326 // <o>Floating Point Unit usage
327 // <0=> Secure state only
328 // <3=> Secure and Non-Secure state
329 // <i> Value for SCB->NSACR register bits CP10, CP11
330 */
331 #define SCB_NSACR_CP10_11_VAL 3
332
333 /*
334 // <o>Treat floating-point registers as Secure
335 // <0=> Disabled
336 // <1=> Enabled
337 // <i> Value for FPU->FPCCR register bit TS
338 */
339 #define FPU_FPCCR_TS_VAL 0
340
341 /*
342 // <o>Clear on return (CLRONRET) accessibility
343 // <0=> Secure and Non-Secure state
344 // <1=> Secure state only
345 // <i> Value for FPU->FPCCR register bit CLRONRETS
346 */
347 #define FPU_FPCCR_CLRONRETS_VAL 0
348
349 /*
350 // <o>Clear floating-point caller saved registers on exception return
351 // <0=> Disabled
352 // <1=> Enabled
353 // <i> Value for FPU->FPCCR register bit CLRONRET
354 */
355 #define FPU_FPCCR_CLRONRET_VAL 1
356
357 /*
358 // </e>
359 */
360
361 /*
362 // <h>Setup Interrupt Target
363 */
364
365 /*
366 // <e>Initialize ITNS 0 (Interrupts 0..31)
367 */
368 #define NVIC_INIT_ITNS0 1
369
370 /*
371 // Interrupts 0..31
372 // <o.0> WWDG_IRQn <0=> Secure state <1=> Non-Secure state
373 // <o.1> PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state
374 // <o.2> RTC_IRQn <0=> Secure state <1=> Non-Secure state
375 // <o.3> RTC_S_IRQn <0=> Secure state <1=> Non-Secure state
376 // <o.4> TAMP_IRQn <0=> Secure state <1=> Non-Secure state
377 // <o.5> TAMP_S_IRQn <0=> Secure state <1=> Non-Secure state
378 // <o.6> FLASH_IRQn <0=> Secure state <1=> Non-Secure state
379 // <o.7> FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state
380 // <o.8> GTZC_IRQn <0=> Secure state <1=> Non-Secure state
381 // <o.9> RCC_IRQn <0=> Secure state <1=> Non-Secure state
382 // <o.10> RCC_S_IRQn <0=> Secure state <1=> Non-Secure state
383 // <o.11> EXTI0_IRQn <0=> Secure state <1=> Non-Secure state
384 // <o.12> EXTI1_IRQn <0=> Secure state <1=> Non-Secure state
385 // <o.13> EXTI2_IRQn <0=> Secure state <1=> Non-Secure state
386 // <o.14> EXTI3_IRQn <0=> Secure state <1=> Non-Secure state
387 // <o.15> EXTI4_IRQn <0=> Secure state <1=> Non-Secure state
388 // <o.16> EXTI5_IRQn <0=> Secure state <1=> Non-Secure state
389 // <o.17> EXTI6_IRQn <0=> Secure state <1=> Non-Secure state
390 // <o.18> EXTI7_IRQn <0=> Secure state <1=> Non-Secure state
391 // <o.19> EXTI8_IRQn <0=> Secure state <1=> Non-Secure state
392 // <o.20> EXTI9_IRQn <0=> Secure state <1=> Non-Secure state
393 // <o.21> EXTI10_IRQn <0=> Secure state <1=> Non-Secure state
394 // <o.22> EXTI11_IRQn <0=> Secure state <1=> Non-Secure state
395 // <o.23> EXTI12_IRQn <0=> Secure state <1=> Non-Secure state
396 // <o.24> EXTI13_IRQn <0=> Secure state <1=> Non-Secure state
397 // <o.25> EXTI14_IRQn <0=> Secure state <1=> Non-Secure state
398 // <o.26> EXTI15_IRQn <0=> Secure state <1=> Non-Secure state
399 // <o.27> DMAMUX1_IRQn <0=> Secure state <1=> Non-Secure state
400 // <o.28> DMAMUX1_S_IRQn <0=> Secure state <1=> Non-Secure state
401 // <o.29> DMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
402 // <o.30> DMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
403 // <o.31> DMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
404 */
405 #define NVIC_INIT_ITNS0_VAL 0x00000000
406
407 /*
408 // </e>
409 */
410
411 /*
412 // <e>Initialize ITNS 1 (Interrupts 32..63)
413 */
414 #define NVIC_INIT_ITNS1 1
415
416 /*
417 // Interrupts 32..63
418 // <o.0> DMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
419 // <o.1> DMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
420 // <o.2> DMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
421 // <o.3> DMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
422 // <o.4> DMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state
423 // <o.5> ADC1_2_IRQn <0=> Secure state <1=> Non-Secure state
424 // <o.6> DAC_IRQn <0=> Secure state <1=> Non-Secure state
425 // <o.7> FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state
426 // <o.8> FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state
427 // <o.9> TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state
428 // <o.10> TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state
429 // <o.11> TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
430 // <o.12> TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state
431 // <o.13> TIM2_IRQn <0=> Secure state <1=> Non-Secure state
432 // <o.14> TIM3_IRQn <0=> Secure state <1=> Non-Secure state
433 // <o.15> TIM4_IRQn <0=> Secure state <1=> Non-Secure state
434 // <o.16> TIM5_IRQn <0=> Secure state <1=> Non-Secure state
435 // <o.17> TIM6_IRQn <0=> Secure state <1=> Non-Secure state
436 // <o.18> TIM7_IRQn <0=> Secure state <1=> Non-Secure state
437 // <o.19> TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state
438 // <o.20> TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state
439 // <o.21> TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
440 // <o.22> TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state
441 // <o.23> I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
442 // <o.24> I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
443 // <o.25> I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state
444 // <o.26> I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state
445 // <o.27> SPI1_IRQn <0=> Secure state <1=> Non-Secure state
446 // <o.28> SPI2_IRQn <0=> Secure state <1=> Non-Secure state
447 // <o.29> USART1_IRQn <0=> Secure state <1=> Non-Secure state
448 // <o.30> USART2_IRQn <0=> Secure state <1=> Non-Secure state
449 // <o.31> USART3_IRQn <0=> Secure state <1=> Non-Secure state
450 */
451 #define NVIC_INIT_ITNS1_VAL 0x00000000
452
453 /*
454 // </e>
455 */
456
457 /*
458 // <e>Initialize ITNS 2 (Interrupts 64..95)
459 */
460 #define NVIC_INIT_ITNS2 1
461
462 /*
463 // Interrupts 64..95
464 // <o.0> UART4_IRQn <0=> Secure state <1=> Non-Secure state
465 // <o.1> UART5_IRQn <0=> Secure state <1=> Non-Secure state
466 // <o.2> LPUART1_IRQn <0=> Secure state <1=> Non-Secure state
467 // <o.3> LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state
468 // <o.4> LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state
469 // <o.5> TIM15_IRQn <0=> Secure state <1=> Non-Secure state
470 // <o.6> TIM16_IRQn <0=> Secure state <1=> Non-Secure state
471 // <o.7> TIM17_IRQn <0=> Secure state <1=> Non-Secure state
472 // <o.8> COMP_IRQn <0=> Secure state <1=> Non-Secure state
473 // <o.9> USB_FS_IRQn <0=> Secure state <1=> Non-Secure state
474 // <o.10> CRS_IRQn <0=> Secure state <1=> Non-Secure state
475 // <o.11> FMC_IRQn <0=> Secure state <1=> Non-Secure state
476 // <o.12> OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state
477 // <o.13> Reserved <0=> Secure state <1=> Non-Secure state
478 // <o.14> SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state
479 // <o.15> Reserved <0=> Secure state <1=> Non-Secure state
480 // <o.16> DMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
481 // <o.17> DMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
482 // <o.18> DMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
483 // <o.19> DMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
484 // <o.20> DMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
485 // <o.21> DMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
486 // <o.22> DMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
487 // <o.23> DMA2_Channel8_IRQn <0=> Secure state <1=> Non-Secure state
488 // <o.24> I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state
489 // <o.25> I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state
490 // <o.26> SAI1_IRQn <0=> Secure state <1=> Non-Secure state
491 // <o.27> SAI2_IRQn <0=> Secure state <1=> Non-Secure state
492 // <o.28> TSC_IRQn <0=> Secure state <1=> Non-Secure state
493 // <o.29> AES_IRQn <0=> Secure state <1=> Non-Secure state
494 // <o.30> RNG_IRQn <0=> Secure state <1=> Non-Secure state
495 // <o.31> FPU_IRQn <0=> Secure state <1=> Non-Secure state
496 */
497 #define NVIC_INIT_ITNS2_VAL 0x00000000
498
499 /*
500 // </e>
501 */
502
503 /*
504 // <e>Initialize ITNS 3 (Interrupts 96..108)
505 */
506 #define NVIC_INIT_ITNS3 1
507
508 /*
509 // Interrupts 96..108
510 // <o.0> HASH_IRQn <0=> Secure state <1=> Non-Secure state
511 // <o.1> PKA_IRQn <0=> Secure state <1=> Non-Secure state
512 // <o.2> LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state
513 // <o.3> SPI3_IRQn <0=> Secure state <1=> Non-Secure state
514 // <o.4> I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state
515 // <o.5> I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state
516 // <o.6> DFSDM1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state
517 // <o.7> DFSDM1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state
518 // <o.8> DFSDM1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state
519 // <o.9> DFSDM1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state
520 // <o.10> UCPD1_IRQn <0=> Secure state <1=> Non-Secure state
521 // <o.11> ICACHE_IRQn <0=> Secure state <1=> Non-Secure state
522 // <o.12> OTFDEC1_IRQn <0=> Secure state <1=> Non-Secure state
523 */
524 #define NVIC_INIT_ITNS3_VAL 0x00000000
525
526 /*
527 // </e>
528 */
529
530 /*
531 // </h>
532 */
533
534
535
536 /*
537 max 8 SAU regions.
538 SAU regions are defined in partition.h
539 */
540
541 #define SAU_INIT_REGION(n) \
542 SAU->RNR = (n & SAU_RNR_REGION_Msk); \
543 SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
544 SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
545 ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
546
547 /**
548 \brief Setup a SAU Region
549 \details Writes the region information contained in SAU_Region to the
550 registers SAU_RNR, SAU_RBAR, and SAU_RLAR
551 */
TZ_SAU_Setup(void)552 __STATIC_INLINE void TZ_SAU_Setup (void)
553 {
554
555 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
556
557 #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
558 SAU_INIT_REGION(0);
559 #endif
560
561 #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
562 SAU_INIT_REGION(1);
563 #endif
564
565 #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
566 SAU_INIT_REGION(2);
567 #endif
568
569 #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
570 SAU_INIT_REGION(3);
571 #endif
572
573 #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
574 SAU_INIT_REGION(4);
575 #endif
576
577 #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
578 SAU_INIT_REGION(5);
579 #endif
580
581 #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
582 SAU_INIT_REGION(6);
583 #endif
584
585 #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
586 SAU_INIT_REGION(7);
587 #endif
588
589 /* repeat this for all possible SAU regions */
590
591 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
592
593
594 #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
595 SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
596 ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
597 #endif
598
599 #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
600 SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
601 ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
602
603 SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
604 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
605 ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
606 ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
607 ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
608 ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
609 #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
610
611 #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
612 defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
613
614 SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
615 ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
616
617 FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
618 ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
619 ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
620 ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
621 #endif
622
623 #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
624 NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
625 #endif
626
627 #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
628 NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
629 #endif
630
631 #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
632 NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
633 #endif
634
635 #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
636 NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
637 #endif
638
639 }
640
641 #endif /* PARTITION_STM32L562XX_H */
642
