1 /**
2   ******************************************************************************
3   * @file    stm32l5xx_ll_spi.c
4   * @author  MCD Application Team
5   * @brief   SPI LL module driver.
6   ******************************************************************************
7   * @attention
8   *
9   * Copyright (c) 2019 STMicroelectronics.
10   * All rights reserved.
11   *
12   * This software is licensed under terms that can be found in the LICENSE file
13   * in the root directory of this software component.
14   * If no LICENSE file comes with this software, it is provided AS-IS.
15   *
16   ******************************************************************************
17   */
18 #if defined(USE_FULL_LL_DRIVER)
19 
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32l5xx_ll_spi.h"
22 #include "stm32l5xx_ll_bus.h"
23 
24 #ifdef  USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29 
30 /** @addtogroup STM32L5xx_LL_Driver
31   * @{
32   */
33 
34 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
35 
36 /** @addtogroup SPI_LL
37   * @{
38   */
39 
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
45   * @{
46   */
47 /* SPI registers Masks */
48 #define SPI_CR1_CLEAR_MASK                 (SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
49                                             SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
50                                             SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_CRCL   | \
51                                             SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
52                                             SPI_CR1_BIDIMODE)
53 /**
54   * @}
55   */
56 
57 /* Private macros ------------------------------------------------------------*/
58 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
59   * @{
60   */
61 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX)       \
62                                                  || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
63                                                  || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
64                                                  || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
65 
66 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
67                                    || ((__VALUE__) == LL_SPI_MODE_SLAVE))
68 
69 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)     \
70                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)  \
71                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)  \
72                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)  \
73                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
74                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)  \
75                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
76                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
77                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
78                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
79                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
80                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
81                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
82 
83 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
84                                        || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
85 
86 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
87                                     || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
88 
89 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT)          \
90                                   || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
91                                   || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
92 
93 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)      \
94                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
95                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
96                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
97                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
98                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
99                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
100                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
101 
102 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
103                                        || ((__VALUE__) == LL_SPI_MSB_FIRST))
104 
105 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
106                                              || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
107 
108 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
109 
110 /**
111   * @}
112   */
113 
114 /* Private function prototypes -----------------------------------------------*/
115 
116 /* Exported functions --------------------------------------------------------*/
117 /** @addtogroup SPI_LL_Exported_Functions
118   * @{
119   */
120 
121 /** @addtogroup SPI_LL_EF_Init
122   * @{
123   */
124 
125 /**
126   * @brief  De-initialize the SPI registers to their default reset values.
127   * @param  SPIx SPI Instance
128   * @retval An ErrorStatus enumeration value:
129   *          - SUCCESS: SPI registers are de-initialized
130   *          - ERROR: SPI registers are not de-initialized
131   */
LL_SPI_DeInit(SPI_TypeDef * SPIx)132 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
133 {
134   ErrorStatus status = ERROR;
135 
136   /* Check the parameters */
137   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
138 
139 #if defined(SPI1)
140   if (SPIx == SPI1)
141   {
142     /* Force reset of SPI clock */
143     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
144 
145     /* Release reset of SPI clock */
146     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
147 
148     status = SUCCESS;
149   }
150 #endif /* SPI1 */
151 #if defined(SPI2)
152   if (SPIx == SPI2)
153   {
154     /* Force reset of SPI clock */
155     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
156 
157     /* Release reset of SPI clock */
158     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
159 
160     status = SUCCESS;
161   }
162 #endif /* SPI2 */
163 #if defined(SPI3)
164   if (SPIx == SPI3)
165   {
166     /* Force reset of SPI clock */
167     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
168 
169     /* Release reset of SPI clock */
170     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
171 
172     status = SUCCESS;
173   }
174 #endif /* SPI3 */
175 
176   return status;
177 }
178 
179 /**
180   * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
181   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
182   *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
183   * @param  SPIx SPI Instance
184   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
185   * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
186   */
LL_SPI_Init(SPI_TypeDef * SPIx,LL_SPI_InitTypeDef * SPI_InitStruct)187 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
188 {
189   ErrorStatus status = ERROR;
190 
191   /* Check the SPI Instance SPIx*/
192   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
193 
194   /* Check the SPI parameters from SPI_InitStruct*/
195   assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
196   assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
197   assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
198   assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
199   assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
200   assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
201   assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
202   assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
203   assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
204 
205   if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
206   {
207     /*---------------------------- SPIx CR1 Configuration ------------------------
208      * Configure SPIx CR1 with parameters:
209      * - TransferDirection:  SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
210      * - Master/Slave Mode:  SPI_CR1_MSTR bit
211      * - ClockPolarity:      SPI_CR1_CPOL bit
212      * - ClockPhase:         SPI_CR1_CPHA bit
213      * - NSS management:     SPI_CR1_SSM bit
214      * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
215      * - BitOrder:           SPI_CR1_LSBFIRST bit
216      * - CRCCalculation:     SPI_CR1_CRCEN bit
217      */
218     MODIFY_REG(SPIx->CR1,
219                SPI_CR1_CLEAR_MASK,
220                SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
221                SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
222                SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
223                SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
224 
225     /*---------------------------- SPIx CR2 Configuration ------------------------
226      * Configure SPIx CR2 with parameters:
227      * - DataWidth:          DS[3:0] bits
228      * - NSS management:     SSOE bit
229      */
230     MODIFY_REG(SPIx->CR2,
231                SPI_CR2_DS | SPI_CR2_SSOE,
232                SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
233 
234     /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
235     if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
236     {
237       LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
238     }
239 
240     /*---------------------------- SPIx CRCPR Configuration ----------------------
241      * Configure SPIx CRCPR with parameters:
242      * - CRCPoly:            CRCPOLY[15:0] bits
243      */
244     if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
245     {
246       assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
247       LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
248     }
249     status = SUCCESS;
250   }
251 
252   return status;
253 }
254 
255 /**
256   * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
257   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
258   * whose fields will be set to default values.
259   * @retval None
260   */
LL_SPI_StructInit(LL_SPI_InitTypeDef * SPI_InitStruct)261 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
262 {
263   /* Set SPI_InitStruct fields to default values */
264   SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
265   SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
266   SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
267   SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
268   SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
269   SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
270   SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
271   SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
272   SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
273   SPI_InitStruct->CRCPoly           = 7U;
274 }
275 
276 /**
277   * @}
278   */
279 
280 /**
281   * @}
282   */
283 
284 /**
285   * @}
286   */
287 
288 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
289 
290 /**
291   * @}
292   */
293 
294 #endif /* USE_FULL_LL_DRIVER */
295 
296