1 /**
2 ******************************************************************************
3 * @file stm32l5xx_hal_pwr_ex.c
4 * @author MCD Application Team
5 * @brief Extended PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Extended Initialization and de-initialization functions
9 * + Extended Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2019 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file in
18 * the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 ******************************************************************************
21 */
22
23 /* Includes ------------------------------------------------------------------*/
24 #include "stm32l5xx_hal.h"
25
26 /** @addtogroup STM32L5xx_HAL_Driver
27 * @{
28 */
29
30 /** @defgroup PWREx PWREx
31 * @brief PWR Extended HAL module driver
32 * @{
33 */
34
35 #ifdef HAL_PWR_MODULE_ENABLED
36
37 /* Private typedef -----------------------------------------------------------*/
38 /* Private define ------------------------------------------------------------*/
39
40 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
41 * @{
42 */
43
44 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */
45
46 /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
47 * @{
48 */
49 #define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */
50 #define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */
51 #define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */
52 #define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */
53 /**
54 * @}
55 */
56
57 /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
58 * @{
59 */
60 #define PWR_REGLP_SETTING_DELAY_VALUE 300UL /*!< Time out value for REGLPF flag setting */
61
62 #define PWR_VOSF_SETTING_DELAY_VALUE 50UL /*!< Time out value for VOSF flag setting */
63
64 #define PWR_MODE_CHANGE_DELAY_VALUE 1000UL /*!< Time out for step down converter operating mode */
65
66 /**
67 * @}
68 */
69
70 /**
71 * @}
72 */
73
74 /* Private macro -------------------------------------------------------------*/
75 /* Private variables ---------------------------------------------------------*/
76 /* Private function prototypes -----------------------------------------------*/
77 /* Exported functions --------------------------------------------------------*/
78
79 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
80 * @{
81 */
82
83 /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
84 * @brief Extended Peripheral Control functions
85 *
86 @verbatim
87 ===============================================================================
88 ##### Extended Peripheral Initialization and de-initialization functions #####
89 ===============================================================================
90 [..]
91
92 @endverbatim
93 * @{
94 */
95
96
97 /**
98 * @brief Return Voltage Scaling Range.
99 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE0, PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2)
100 */
HAL_PWREx_GetVoltageRange(void)101 uint32_t HAL_PWREx_GetVoltageRange(void)
102 {
103 return (PWR->CR1 & PWR_CR1_VOS);
104 }
105
106 /**
107 * @brief Configure the main internal regulator output voltage.
108 * @param VoltageScaling specifies the regulator output voltage to achieve
109 * a tradeoff between performance and power consumption.
110 * This parameter can be one of the following values:
111 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE0 Regulator voltage output range 0 mode,
112 * typical output voltage at 1.28 V,
113 * system frequency up to 100 MHz.
114 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
115 * typical output voltage at 1.2 V,
116 * system frequency up to 80 MHz.
117 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
118 * typical output voltage at 1.0 V,
119 * system frequency up to 26 MHz.
120 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
121 * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
122 * When moving from Range 2 to Range 1, the system frequency can be increased to
123 * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
124 * @note When moving from one Range to another , the API waits for VOSF flag to be
125 * cleared before returning the status. If the flag is not cleared within limited time duration,
126 * HAL_TIMEOUT status is reported.
127 * @note The VOS shall NOT be changed in LP Mode of if LP mode is asked.
128 * @note The function shall not be called in Low-power run mode (meaningless and misleading).
129 * @retval HAL Status
130 */
HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)131 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
132 {
133 uint32_t wait_loop_index;
134
135 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
136
137 uint32_t vos_old = READ_BIT(PWR->CR1, PWR_CR1_VOS);
138
139 /* VOS shall not be changed in LP Mode */
140 /* or if LP Mode is asked but not yet established */
141 if (HAL_PWREx_SMPS_GetEffectiveMode() == PWR_SMPS_LOW_POWER)
142 {
143 return HAL_ERROR;
144 }
145 if (READ_BIT(PWR->CR4, PWR_CR4_SMPSLPEN) == PWR_CR4_SMPSLPEN)
146 {
147 return HAL_ERROR;
148 }
149
150 /* No change, nothing to do */
151 if (vos_old == VoltageScaling)
152 {
153 return HAL_OK;
154 }
155
156 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
157
158 /* Wait until VOSF is cleared */
159 /* and at least one iteration loop */
160 wait_loop_index = ((PWR_VOSF_SETTING_DELAY_VALUE * (SystemCoreClock / 100000U)) / 10U) + 1U;
161
162 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
163 {
164 wait_loop_index--;
165 }
166
167 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
168 {
169 return HAL_TIMEOUT;
170 }
171
172 return HAL_OK;
173 }
174
175 /**
176 * @brief Enable battery charging.
177 * When VDD is present, charge the external battery on VBAT through an internal resistor.
178 * @param ResistorSelection specifies the resistor impedance.
179 * This parameter can be one of the following values:
180 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
181 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
182 * @retval None
183 */
HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)184 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
185 {
186 assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
187
188 /* Specify resistor selection */
189 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
190
191 /* Enable battery charging */
192 SET_BIT(PWR->CR4, PWR_CR4_VBE);
193 }
194
195
196 /**
197 * @brief Disable battery charging.
198 * @retval None
199 */
HAL_PWREx_DisableBatteryCharging(void)200 void HAL_PWREx_DisableBatteryCharging(void)
201 {
202 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
203 }
204
205
206 #if defined(PWR_CR2_USV)
207 /**
208 * @brief Enable VDDUSB supply.
209 * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
210 * @retval None
211 */
HAL_PWREx_EnableVddUSB(void)212 void HAL_PWREx_EnableVddUSB(void)
213 {
214 SET_BIT(PWR->CR2, PWR_CR2_USV);
215 }
216
217
218 /**
219 * @brief Disable VDDUSB supply.
220 * @retval None
221 */
HAL_PWREx_DisableVddUSB(void)222 void HAL_PWREx_DisableVddUSB(void)
223 {
224 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
225 }
226 #endif /* PWR_CR2_USV */
227
228 /**
229 * @brief Enable VDDIO2 supply.
230 * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present.
231 * @retval None
232 */
HAL_PWREx_EnableVddIO2(void)233 void HAL_PWREx_EnableVddIO2(void)
234 {
235 SET_BIT(PWR->CR2, PWR_CR2_IOSV);
236 }
237
238 /**
239 * @brief Disable VDDIO2 supply.
240 * @retval None
241 */
HAL_PWREx_DisableVddIO2(void)242 void HAL_PWREx_DisableVddIO2(void)
243 {
244 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
245 }
246
247 /**
248 * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
249 * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in
250 * pull-up state in Standby and Shutdown modes.
251 * @note This state is effective in Standby and Shutdown modes only if APC bit
252 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
253 * @note The configuration is lost when exiting the Shutdown mode due to the
254 * power-on reset, maintained when exiting the Standby mode.
255 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
256 * PDy bit of PWR_PDCRx register is cleared unless it is reserved.
257 * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input
258 * parameter at the same time are set.
259 * @param GPIO specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
260 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
261 * @param GPIONumber specifies the I/O pins numbers.
262 * This parameter can be one of the following values:
263 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
264 * I/O pins are available) or the logical OR of several of them to set
265 * several bits for a given port in a single API call.
266 * @retval HAL Status
267 */
HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)268 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
269 {
270 HAL_StatusTypeDef status = HAL_OK;
271
272 assert_param(IS_PWR_GPIO(GPIO));
273 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
274
275 switch (GPIO)
276 {
277 case PWR_GPIO_A:
278 SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
279 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
280 break;
281 case PWR_GPIO_B:
282 SET_BIT(PWR->PUCRB, GPIONumber);
283 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
284 break;
285 case PWR_GPIO_C:
286 SET_BIT(PWR->PUCRC, GPIONumber);
287 CLEAR_BIT(PWR->PDCRC, GPIONumber);
288 break;
289 case PWR_GPIO_D:
290 SET_BIT(PWR->PUCRD, GPIONumber);
291 CLEAR_BIT(PWR->PDCRD, GPIONumber);
292 break;
293 case PWR_GPIO_E:
294 SET_BIT(PWR->PUCRE, GPIONumber);
295 CLEAR_BIT(PWR->PDCRE, GPIONumber);
296 break;
297 case PWR_GPIO_F:
298 SET_BIT(PWR->PUCRF, GPIONumber);
299 CLEAR_BIT(PWR->PDCRF, GPIONumber);
300 break;
301 case PWR_GPIO_G:
302 SET_BIT(PWR->PUCRG, GPIONumber);
303 CLEAR_BIT(PWR->PDCRG, GPIONumber);
304 break;
305 case PWR_GPIO_H:
306 SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
307 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
308 break;
309 default:
310 status = HAL_ERROR;
311 break;
312 }
313
314 return status;
315 }
316
317
318 /**
319 * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
320 * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
321 * in pull-up state in Standby and Shutdown modes.
322 * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input
323 * parameter at the same time are reset.
324 * @param GPIO specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
325 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
326 * @param GPIONumber specifies the I/O pins numbers.
327 * This parameter can be one of the following values:
328 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
329 * I/O pins are available) or the logical OR of several of them to reset
330 * several bits for a given port in a single API call.
331 * @retval HAL Status
332 */
HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)333 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
334 {
335 HAL_StatusTypeDef status = HAL_OK;
336
337 assert_param(IS_PWR_GPIO(GPIO));
338 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
339
340 switch (GPIO)
341 {
342 case PWR_GPIO_A:
343 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
344 break;
345 case PWR_GPIO_B:
346 CLEAR_BIT(PWR->PUCRB, GPIONumber);
347 break;
348 case PWR_GPIO_C:
349 CLEAR_BIT(PWR->PUCRC, GPIONumber);
350 break;
351 case PWR_GPIO_D:
352 CLEAR_BIT(PWR->PUCRD, GPIONumber);
353 break;
354 case PWR_GPIO_E:
355 CLEAR_BIT(PWR->PUCRE, GPIONumber);
356 break;
357 case PWR_GPIO_F:
358 CLEAR_BIT(PWR->PUCRF, GPIONumber);
359 break;
360 case PWR_GPIO_G:
361 CLEAR_BIT(PWR->PUCRG, GPIONumber);
362 break;
363 case PWR_GPIO_H:
364 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
365 break;
366 default:
367 status = HAL_ERROR;
368 break;
369 }
370
371 return status;
372 }
373
374
375
376 /**
377 * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
378 * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in
379 * pull-down state in Standby and Shutdown modes.
380 * @note This state is effective in Standby and Shutdown modes only if APC bit
381 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
382 * @note The configuration is lost when exiting the Shutdown mode due to the
383 * power-on reset, maintained when exiting the Standby mode.
384 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
385 * PUy bit of PWR_PUCRx register is cleared unless it is reserved.
386 * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input
387 * parameter at the same time are set.
388 * @param GPIO specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
389 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
390 * @param GPIONumber specifies the I/O pins numbers.
391 * This parameter can be one of the following values:
392 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
393 * I/O pins are available) or the logical OR of several of them to set
394 * several bits for a given port in a single API call.
395 * @retval HAL Status
396 */
HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)397 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
398 {
399 HAL_StatusTypeDef status = HAL_OK;
400
401 assert_param(IS_PWR_GPIO(GPIO));
402 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
403
404 switch (GPIO)
405 {
406 case PWR_GPIO_A:
407 SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
408 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
409 break;
410 case PWR_GPIO_B:
411 SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
412 CLEAR_BIT(PWR->PUCRB, GPIONumber);
413 break;
414 case PWR_GPIO_C:
415 SET_BIT(PWR->PDCRC, GPIONumber);
416 CLEAR_BIT(PWR->PUCRC, GPIONumber);
417 break;
418 case PWR_GPIO_D:
419 SET_BIT(PWR->PDCRD, GPIONumber);
420 CLEAR_BIT(PWR->PUCRD, GPIONumber);
421 break;
422 case PWR_GPIO_E:
423 SET_BIT(PWR->PDCRE, GPIONumber);
424 CLEAR_BIT(PWR->PUCRE, GPIONumber);
425 break;
426 case PWR_GPIO_F:
427 SET_BIT(PWR->PDCRF, GPIONumber);
428 CLEAR_BIT(PWR->PUCRF, GPIONumber);
429 break;
430 case PWR_GPIO_G:
431 SET_BIT(PWR->PDCRG, GPIONumber);
432 CLEAR_BIT(PWR->PUCRG, GPIONumber);
433 break;
434 case PWR_GPIO_H:
435 SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
436 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
437 break;
438 default:
439 status = HAL_ERROR;
440 break;
441 }
442
443 return status;
444 }
445
446
447 /**
448 * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
449 * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
450 * in pull-down state in Standby and Shutdown modes.
451 * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input
452 * parameter at the same time are reset.
453 * @param GPIO specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
454 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
455 * @param GPIONumber specifies the I/O pins numbers.
456 * This parameter can be one of the following values:
457 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
458 * I/O pins are available) or the logical OR of several of them to reset
459 * several bits for a given port in a single API call.
460 * @retval HAL Status
461 */
HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)462 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
463 {
464 HAL_StatusTypeDef status = HAL_OK;
465
466 assert_param(IS_PWR_GPIO(GPIO));
467 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
468
469 switch (GPIO)
470 {
471 case PWR_GPIO_A:
472 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
473 break;
474 case PWR_GPIO_B:
475 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
476 break;
477 case PWR_GPIO_C:
478 CLEAR_BIT(PWR->PDCRC, GPIONumber);
479 break;
480 case PWR_GPIO_D:
481 CLEAR_BIT(PWR->PDCRD, GPIONumber);
482 break;
483 case PWR_GPIO_E:
484 CLEAR_BIT(PWR->PDCRE, GPIONumber);
485 break;
486 case PWR_GPIO_F:
487 CLEAR_BIT(PWR->PDCRF, GPIONumber);
488 break;
489 case PWR_GPIO_G:
490 CLEAR_BIT(PWR->PDCRG, GPIONumber);
491 break;
492 case PWR_GPIO_H:
493 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
494 break;
495 default:
496 status = HAL_ERROR;
497 break;
498 }
499
500 return status;
501 }
502
503
504
505 /**
506 * @brief Enable pull-up and pull-down configuration.
507 * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in
508 * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
509 * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
510 * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
511 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there
512 * is no conflict when setting PUy or PDy bit.
513 * @retval None
514 */
HAL_PWREx_EnablePullUpPullDownConfig(void)515 void HAL_PWREx_EnablePullUpPullDownConfig(void)
516 {
517 SET_BIT(PWR->CR3, PWR_CR3_APC);
518 }
519
520
521 /**
522 * @brief Disable pull-up and pull-down configuration.
523 * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
524 * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
525 * @retval None
526 */
HAL_PWREx_DisablePullUpPullDownConfig(void)527 void HAL_PWREx_DisablePullUpPullDownConfig(void)
528 {
529 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
530 }
531
532
533 /**
534 * @brief Configure SRAM2 content retention in Standby mode.
535 * @param SRAM2ContentRetention This parameter can be one of the following values:
536 * @arg @ref PWR_NO_SRAM2_RETENTION
537 * @arg @ref PWR_FULL_SRAM2_RETENTION
538 * @arg @ref PWR_4KBYTES_SRAM2_RETENTION
539 * @note This feature is secured by SMLPM bit when system implements security (TZEN=1).
540 * @retval HAL Status
541 */
HAL_PWREx_ConfigSRAM2ContentRetention(uint32_t SRAM2ContentRetention)542 HAL_StatusTypeDef HAL_PWREx_ConfigSRAM2ContentRetention(uint32_t SRAM2ContentRetention)
543 {
544 /* Check the parameters */
545 assert_param(IS_PWR_SRAM2CONTENT_RETENTION(SRAM2ContentRetention));
546
547 /* Set RRS bits */
548 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, SRAM2ContentRetention);
549
550 return HAL_OK;
551 }
552
553
554 /**
555 * @brief Enable SRAM2 content retention in Standby mode.
556 * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in
557 * Standby mode and its content is kept.
558 * @retval None
559 */
HAL_PWREx_EnableSRAM2ContentRetention(void)560 void HAL_PWREx_EnableSRAM2ContentRetention(void)
561 {
562 (void) HAL_PWREx_ConfigSRAM2ContentRetention(PWR_FULL_SRAM2_RETENTION);
563 }
564
565
566 /**
567 * @brief Disable SRAM2 content retention in Standby mode.
568 * @note When RRS bit is reset, SRAM2 is powered off in Standby mode
569 * and its content is lost.
570 * @retval None
571 */
HAL_PWREx_DisableSRAM2ContentRetention(void)572 void HAL_PWREx_DisableSRAM2ContentRetention(void)
573 {
574 (void) HAL_PWREx_ConfigSRAM2ContentRetention(PWR_NO_SRAM2_RETENTION);
575 }
576
577
578 /**
579 * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2 V.
580 * @retval None
581 */
HAL_PWREx_EnablePVM1(void)582 void HAL_PWREx_EnablePVM1(void)
583 {
584 SET_BIT(PWR->CR2, PWR_PVM_1);
585 }
586
587 /**
588 * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2 V.
589 * @retval None
590 */
HAL_PWREx_DisablePVM1(void)591 void HAL_PWREx_DisablePVM1(void)
592 {
593 CLEAR_BIT(PWR->CR2, PWR_PVM_1);
594 }
595
596 /**
597 * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9 V.
598 * @retval None
599 */
HAL_PWREx_EnablePVM2(void)600 void HAL_PWREx_EnablePVM2(void)
601 {
602 SET_BIT(PWR->CR2, PWR_PVM_2);
603 }
604
605 /**
606 * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9 V.
607 * @retval None
608 */
HAL_PWREx_DisablePVM2(void)609 void HAL_PWREx_DisablePVM2(void)
610 {
611 CLEAR_BIT(PWR->CR2, PWR_PVM_2);
612 }
613
614
615 /**
616 * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62 V.
617 * @retval None
618 */
HAL_PWREx_EnablePVM3(void)619 void HAL_PWREx_EnablePVM3(void)
620 {
621 SET_BIT(PWR->CR2, PWR_PVM_3);
622 }
623
624 /**
625 * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62 V.
626 * @retval None
627 */
HAL_PWREx_DisablePVM3(void)628 void HAL_PWREx_DisablePVM3(void)
629 {
630 CLEAR_BIT(PWR->CR2, PWR_PVM_3);
631 }
632
633
634 /**
635 * @brief Enable the Power Voltage Monitoring 4: VDDA versus 1.8 V.
636 * @retval None
637 */
HAL_PWREx_EnablePVM4(void)638 void HAL_PWREx_EnablePVM4(void)
639 {
640 SET_BIT(PWR->CR2, PWR_PVM_4);
641 }
642
643 /**
644 * @brief Disable the Power Voltage Monitoring 4: VDDA versus 1.8 V.
645 * @retval None
646 */
HAL_PWREx_DisablePVM4(void)647 void HAL_PWREx_DisablePVM4(void)
648 {
649 CLEAR_BIT(PWR->CR2, PWR_PVM_4);
650 }
651
652
653
654
655 /**
656 * @brief Configure the Peripheral Voltage Monitoring (PVM).
657 * @param sConfigPVM pointer to a PWR_PVMTypeDef structure that contains the
658 * PVM configuration information.
659 * @note The API configures a single PVM according to the information contained
660 * in the input structure. To configure several PVMs, the API must be singly
661 * called for each PVM used.
662 * @note Refer to the electrical characteristics of your device datasheet for
663 * more details about the voltage thresholds corresponding to each
664 * detection level and to each monitored supply.
665 * @retval HAL status
666 */
HAL_PWREx_ConfigPVM(PWR_PVMTypeDef * sConfigPVM)667 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
668 {
669 HAL_StatusTypeDef status = HAL_OK;
670
671 /* Check the parameters */
672 assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
673 assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
674
675
676 /* Configure EXTI 35 to 38 interrupts if so required:
677 scan through PVMType to detect which PVMx is set and
678 configure the corresponding EXTI line accordingly. */
679 switch (sConfigPVM->PVMType)
680 {
681 case PWR_PVM_1:
682 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
683 __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
684 __HAL_PWR_PVM1_EXTI_DISABLE_IT();
685 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
686 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
687
688 /* Configure interrupt mode */
689 if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
690 {
691 __HAL_PWR_PVM1_EXTI_ENABLE_IT();
692 }
693
694 /* Configure event mode */
695 if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
696 {
697 __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
698 }
699
700 /* Configure the edge */
701 if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
702 {
703 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
704 }
705
706 if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
707 {
708 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
709 }
710 break;
711
712 case PWR_PVM_2:
713 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
714 __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
715 __HAL_PWR_PVM2_EXTI_DISABLE_IT();
716 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();
717 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
718
719 /* Configure interrupt mode */
720 if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
721 {
722 __HAL_PWR_PVM2_EXTI_ENABLE_IT();
723 }
724
725 /* Configure event mode */
726 if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
727 {
728 __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
729 }
730
731 /* Configure the edge */
732 if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
733 {
734 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
735 }
736
737 if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
738 {
739 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
740 }
741 break;
742
743 case PWR_PVM_3:
744 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
745 __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
746 __HAL_PWR_PVM3_EXTI_DISABLE_IT();
747 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
748 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
749
750 /* Configure interrupt mode */
751 if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
752 {
753 __HAL_PWR_PVM3_EXTI_ENABLE_IT();
754 }
755
756 /* Configure event mode */
757 if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
758 {
759 __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
760 }
761
762 /* Configure the edge */
763 if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
764 {
765 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
766 }
767
768 if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
769 {
770 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
771 }
772 break;
773
774 case PWR_PVM_4:
775 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
776 __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
777 __HAL_PWR_PVM4_EXTI_DISABLE_IT();
778 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();
779 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
780
781 /* Configure interrupt mode */
782 if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
783 {
784 __HAL_PWR_PVM4_EXTI_ENABLE_IT();
785 }
786
787 /* Configure event mode */
788 if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
789 {
790 __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
791 }
792
793 /* Configure the edge */
794 if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
795 {
796 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
797 }
798
799 if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
800 {
801 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
802 }
803 break;
804
805 default:
806 status = HAL_ERROR;
807 break;
808 }
809
810 return status;
811 }
812
813
814
815 /**
816 * @brief Enter Low-power Run mode
817 * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode.
818 * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
819 * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.
820 * Additionally, the clock frequency must be reduced below 2 MHz.
821 * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must
822 * be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
823 * @retval None
824 */
HAL_PWREx_EnableLowPowerRunMode(void)825 void HAL_PWREx_EnableLowPowerRunMode(void)
826 {
827 /* Set Regulator parameter */
828 SET_BIT(PWR->CR1, PWR_CR1_LPR);
829 }
830
831
832 /**
833 * @brief Exit Low-power Run mode.
834 * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
835 * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
836 * returns HAL_TIMEOUT status). The system clock frequency can then be
837 * increased above 2 MHz.
838 * @retval HAL Status
839 */
HAL_PWREx_DisableLowPowerRunMode(void)840 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
841 {
842 uint32_t wait_loop_index;
843
844 /* Clear LPR bit */
845 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
846
847 /* Wait until REGLPF is reset */
848 /* and at least one iteration loop */
849 wait_loop_index = ((PWR_REGLP_SETTING_DELAY_VALUE * (SystemCoreClock / 100000U)) / 10U) + 1U;
850
851 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))
852 {
853 wait_loop_index--;
854 }
855 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
856 {
857 return HAL_TIMEOUT;
858 }
859
860 return HAL_OK;
861 }
862
863
864 /**
865 * @brief Enter Stop 0 mode.
866 * @note In Stop 0 mode, main and low voltage regulators are ON.
867 * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode.
868 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
869 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
870 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
871 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
872 * only to the peripheral requesting it.
873 * SRAM1, SRAM2 and register contents are preserved.
874 * The BOR is available.
875 * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
876 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
877 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
878 * @note By keeping the internal regulator ON during Stop 0 mode, the consumption
879 * is higher although the startup time is reduced.
880 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
881 * This parameter can be one of the following values:
882 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
883 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
884 * @retval None
885 */
HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)886 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
887 {
888 /* Check the parameters */
889 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
890
891 /* Stop 0 mode with Main Regulator */
892 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);
893
894 /* Set SLEEPDEEP bit of Cortex System Control Register */
895 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
896
897 /* Select Stop mode entry --------------------------------------------------*/
898 if (STOPEntry == PWR_STOPENTRY_WFI)
899 {
900 /* Request Wait For Interrupt */
901 __WFI();
902 }
903 else
904 {
905 /* Request Wait For Event */
906 __SEV();
907 __WFE();
908 __WFE();
909 }
910
911 /* Reset SLEEPDEEP bit of Cortex System Control Register */
912 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
913 }
914
915
916 /**
917 * @brief Enter Stop 1 mode.
918 * @note In Stop 1 mode, only low power voltage regulator is ON.
919 * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode.
920 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
921 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
922 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
923 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
924 * only to the peripheral requesting it.
925 * SRAM1, SRAM2 and register contents are preserved.
926 * The BOR is available.
927 * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
928 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
929 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
930 * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
931 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
932 * This parameter can be one of the following values:
933 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
934 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
935 * @retval None
936 */
HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)937 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
938 {
939 /* Check the parameters */
940 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
941
942 /* Stop 1 mode with Low-Power Regulator */
943 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);
944
945 /* Set SLEEPDEEP bit of Cortex System Control Register */
946 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
947
948 /* Select Stop mode entry --------------------------------------------------*/
949 if (STOPEntry == PWR_STOPENTRY_WFI)
950 {
951 /* Request Wait For Interrupt */
952 __WFI();
953 }
954 else
955 {
956 /* Request Wait For Event */
957 __SEV();
958 __WFE();
959 __WFE();
960 }
961
962 /* Reset SLEEPDEEP bit of Cortex System Control Register */
963 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
964 }
965
966
967 /**
968 * @brief Enter Stop 2 mode.
969 * @note In Stop 2 mode, only low power voltage regulator is ON.
970 * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode.
971 * @note All clocks in the VCORE domain are stopped, the PLL, the MSI,
972 * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability
973 * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after
974 * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only
975 * to the peripheral requesting it.
976 * SRAM1, SRAM2 and register contents are preserved.
977 * The BOR is available.
978 * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.
979 * Otherwise, Stop 1 mode is entered.
980 * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event,
981 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
982 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
983 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
984 * This parameter can be one of the following values:
985 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
986 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
987 * @retval None
988 */
HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)989 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
990 {
991 /* Check the parameter */
992 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
993
994 /* Set Stop mode 2 */
995 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2);
996
997 /* Set SLEEPDEEP bit of Cortex System Control Register */
998 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
999
1000 /* Select Stop mode entry --------------------------------------------------*/
1001 if (STOPEntry == PWR_STOPENTRY_WFI)
1002 {
1003 /* Request Wait For Interrupt */
1004 __WFI();
1005 }
1006 else
1007 {
1008 /* Request Wait For Event */
1009 __SEV();
1010 __WFE();
1011 __WFE();
1012 }
1013
1014 /* Reset SLEEPDEEP bit of Cortex System Control Register */
1015 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1016 }
1017
1018
1019
1020
1021
1022 /**
1023 * @brief Enter Shutdown mode.
1024 * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched
1025 * off. The voltage regulator is disabled and Vcore domain is powered off.
1026 * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
1027 * The BOR is not available.
1028 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
1029 * @retval None
1030 */
HAL_PWREx_EnterSHUTDOWNMode(void)1031 void HAL_PWREx_EnterSHUTDOWNMode(void)
1032 {
1033
1034 /* Set Shutdown mode */
1035 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
1036
1037 /* Set SLEEPDEEP bit of Cortex System Control Register */
1038 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1039
1040 /* This option is used to ensure that store operations are completed */
1041 #if defined ( __CC_ARM)
1042 __force_stores();
1043 #endif
1044 /* Request Wait For Interrupt */
1045 __WFI();
1046 }
1047
1048
1049
1050
1051 /**
1052 * @brief This function handles the PWR PVD/PVMx interrupt request.
1053 * @note This API should be called under the PVD_PVM_IRQHandler().
1054 * @retval None
1055 */
HAL_PWREx_PVD_PVM_IRQHandler(void)1056 void HAL_PWREx_PVD_PVM_IRQHandler(void)
1057 {
1058 uint32_t rising_flag;
1059 uint32_t falling_flag;
1060
1061 rising_flag = READ_REG(EXTI->RPR1);
1062 falling_flag = READ_REG(EXTI->FPR1);
1063
1064 /* Check PWR exti flags for PVD */
1065 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVD) != 0x0U)
1066 {
1067 /* PWR PVD interrupt user callback */
1068 HAL_PWR_PVDCallback();
1069
1070 /* Clear PVD exti pending bit */
1071 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD);
1072 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD);
1073 }
1074
1075 /* Next, successively check PVMx exti flags */
1076 rising_flag = READ_REG(EXTI->RPR2);
1077 falling_flag = READ_REG(EXTI->FPR2);
1078
1079 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVM1) != 0x0U)
1080 {
1081 /* PWR PVM1 interrupt user callback */
1082 HAL_PWREx_PVM1Callback();
1083
1084 /* Clear PVM1 exti pending bit */
1085 WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM1);
1086 WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM1);
1087 }
1088 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVM2) != 0x0U)
1089 {
1090 /* PWR PVM2 interrupt user callback */
1091 HAL_PWREx_PVM2Callback();
1092
1093 /* Clear PVM2 exti pending bit */
1094 WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM2);
1095 WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM2);
1096 }
1097 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVM3) != 0x0U)
1098 {
1099 /* PWR PVM3 interrupt user callback */
1100 HAL_PWREx_PVM3Callback();
1101
1102 /* Clear PVM3 exti pending bit */
1103 WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM3);
1104 WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM3);
1105 }
1106 if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVM4) != 0x0U)
1107 {
1108 /* PWR PVM4 interrupt user callback */
1109 HAL_PWREx_PVM4Callback();
1110
1111 /* Clear PVM4 exti pending bit */
1112 WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM4);
1113 WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM4);
1114 }
1115 }
1116
1117
1118 /**
1119 * @brief PWR PVM1 interrupt callback
1120 * @retval None
1121 */
HAL_PWREx_PVM1Callback(void)1122 __weak void HAL_PWREx_PVM1Callback(void)
1123 {
1124 /* NOTE : This function should not be modified; when the callback is needed,
1125 HAL_PWREx_PVM1Callback() API can be implemented in the user file
1126 */
1127 }
1128
1129 /**
1130 * @brief PWR PVM2 interrupt callback
1131 * @retval None
1132 */
HAL_PWREx_PVM2Callback(void)1133 __weak void HAL_PWREx_PVM2Callback(void)
1134 {
1135 /* NOTE : This function should not be modified; when the callback is needed,
1136 HAL_PWREx_PVM2Callback() API can be implemented in the user file
1137 */
1138 }
1139
1140 /**
1141 * @brief PWR PVM3 interrupt callback
1142 * @retval None
1143 */
HAL_PWREx_PVM3Callback(void)1144 __weak void HAL_PWREx_PVM3Callback(void)
1145 {
1146 /* NOTE : This function should not be modified; when the callback is needed,
1147 HAL_PWREx_PVM3Callback() API can be implemented in the user file
1148 */
1149 }
1150
1151 /**
1152 * @brief PWR PVM4 interrupt callback
1153 * @retval None
1154 */
HAL_PWREx_PVM4Callback(void)1155 __weak void HAL_PWREx_PVM4Callback(void)
1156 {
1157 /* NOTE : This function should not be modified; when the callback is needed,
1158 HAL_PWREx_PVM4Callback() API can be implemented in the user file
1159 */
1160 }
1161
1162 /**
1163 * @brief Enable UCPD configuration memorization in Standby.
1164 * @note This feature is secured by secured UCPD1 when system implements security (TZEN=1).
1165 * @retval None
1166 */
HAL_PWREx_EnableUCPDStandbyMode(void)1167 void HAL_PWREx_EnableUCPDStandbyMode(void)
1168 {
1169 /* Memorize UCPD configuration when entering standby mode */
1170 SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
1171 }
1172
1173 /**
1174 * @brief Disable UCPD configuration memorization in Standby.
1175 * @note This function must be called on exiting the Standby mode and before any UCPD
1176 * configuration update.
1177 * @note This feature is secured by secured UCPD1 when system implements security (TZEN=1).
1178 * @retval None
1179 */
HAL_PWREx_DisableUCPDStandbyMode(void)1180 void HAL_PWREx_DisableUCPDStandbyMode(void)
1181 {
1182 /* Write 0 immediately after Standby exit when using UCPD,
1183 and before writing any UCPD registers */
1184 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
1185 }
1186
1187 /**
1188 * @brief Enable the USB Type-C dead battery pull-down behavior
1189 * on UCPDx_CC1 and UCPDx_CC2 pins
1190 * @note This feature is secured by secured UCPD1 when system implements security (TZEN=1).
1191 * @retval None
1192 */
HAL_PWREx_EnableUCPDDeadBattery(void)1193 void HAL_PWREx_EnableUCPDDeadBattery(void)
1194 {
1195 /* Write 0 to enable the USB Type-C dead battery pull-down behavior */
1196 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
1197 }
1198
1199 /**
1200 * @brief Disable the USB Type-C dead battery pull-down behavior
1201 * on UCPDx_CC1 and UCPDx_CC2 pins
1202 * @note This feature is secured by secured UCPD1 when system implements security (TZEN=1).
1203 * @note After exiting reset, the USB Type-C dead battery behavior will be enabled,
1204 * which may have a pull-down effect on CC1 and CC2 pins.
1205 * It is recommended to disable it in all cases, either to stop this pull-down
1206 * or to hand over control to the UCPD (which should therefore be
1207 * initialized before doing the disable).
1208 * @retval None
1209 */
HAL_PWREx_DisableUCPDDeadBattery(void)1210 void HAL_PWREx_DisableUCPDDeadBattery(void)
1211 {
1212 /* Write 1 to disable the USB Type-C dead battery pull-down behavior */
1213 SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
1214 }
1215
1216 /**
1217 * @brief Enable ultra low power mode.
1218 * Enable ultra low power BORL, BORH and PVD in Standby/Shutdown mode.
1219 * @note This feature is secured by VDMSEC bit when system implements security (TZEN=1).
1220 * @retval None
1221 */
HAL_PWREx_EnableUltraLowPowerMode(void)1222 void HAL_PWREx_EnableUltraLowPowerMode(void)
1223 {
1224 /* Enable ultra low power mode */
1225 SET_BIT(PWR->CR3, PWR_CR3_ULPMEN);
1226 }
1227
1228 /**
1229 * @brief Disable ultra low power mode.
1230 * @note This feature is secured by VDMSEC bit when system implements security (TZEN=1).
1231 * @retval None
1232 */
HAL_PWREx_DisableUltraLowPowerMode(void)1233 void HAL_PWREx_DisableUltraLowPowerMode(void)
1234 {
1235 /* Disable ultra low power mode */
1236 CLEAR_BIT(PWR->CR3, PWR_CR3_ULPMEN);
1237 }
1238
1239 /**
1240 * @}
1241 */
1242
1243 /** @defgroup PWREx_Exported_Functions_Group2 Extended Power Control SMPS functions
1244 * @brief Extended Power Control SMPS functions
1245 *
1246 @verbatim
1247 ===============================================================================
1248 ##### Extended Power Control SMPS functions #####
1249 ===============================================================================
1250 [..]
1251 This subsection provides a set of functions allowing to control the
1252 SMPS mode.
1253
1254 @endverbatim
1255 * @{
1256 */
1257
1258 /**
1259 * @brief Set SMPS step down converter operating mode.
1260 * @param OperatingMode This parameter can be one of the following values:
1261 * @arg @ref PWR_SMPS_HIGH_POWER SMPS step down converter in high-power mode (default)
1262 * @arg @ref PWR_SMPS_LOW_POWER SMPS step down converter in low-power mode
1263 * @arg @ref PWR_SMPS_BYPASS SMPS step down converter in bypass mode
1264 * @note The High-power mode achieves the high efficiency at high current load.
1265 * @note The Low-power mode achieves the high efficiency at low current load.
1266 * @note The Low-power mode can be enabled only when the main regulator voltage is in range 2 mode.
1267 * When Low-power mode is enabled, the voltage scaling must not be modified. This mode can be
1268 * only selected when power consumption does not exceed 30 mA.
1269 * @note When switching from one power mode to another, HAL_PWREx_SMPS_SetMode() waits for the new
1270 * mode to be effective within a limited time duration before returning the status HAL_OK
1271 * else it returns HAL_TIMEOUT. A request for Low power mode when the voltage regulator is not
1272 * in range 2 is rejected with HAL_ERROR.
1273 * @note The Bypass mode can be enabled or disabled on the fly whatever the selected operation mode.
1274 * @note The function shall not be called in Low-power run mode (meaningless and misleading).
1275 * @retval HAL Status
1276 */
1277
HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode)1278 HAL_StatusTypeDef HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode)
1279 {
1280 HAL_StatusTypeDef status;
1281 uint32_t pwr_sr1;
1282 uint32_t wait_loop_index;
1283
1284 /* Check the parameters */
1285 assert_param(IS_PWR_SMPS_MODE(OperatingMode));
1286
1287 if (OperatingMode == PWR_SMPS_HIGH_POWER)
1288 {
1289 MODIFY_REG(PWR->CR4, (PWR_CR4_SMPSBYP | PWR_CR4_SMPSLPEN), 0U);
1290 }
1291 else if (OperatingMode == PWR_SMPS_LOW_POWER)
1292 {
1293 /* ------------------------------------------------------------------------ */
1294 /* SMPS Low-power mode can only be set in range 2 */
1295 if (HAL_PWREx_GetVoltageRange() != PWR_REGULATOR_VOLTAGE_SCALE2)
1296 {
1297 return HAL_ERROR;
1298 }
1299 else
1300 {
1301 pwr_sr1 = READ_REG(PWR->SR1);
1302
1303 if (READ_BIT(pwr_sr1, PWR_SR1_SMPSHPRDY | PWR_SR1_SMPSBYPRDY) == 0U)
1304 {
1305 /* Already in SMPS Low-power mode */
1306 /* Nothing to configure */
1307 }
1308 else
1309 {
1310 /* Switch to Low-power mode */
1311 MODIFY_REG(PWR->CR4, (PWR_CR4_SMPSBYP | PWR_CR4_SMPSLPEN), PWR_CR4_SMPSLPEN);
1312 }
1313 }
1314 }
1315 else /* PWR_SMPS_BYPASS */
1316 {
1317 HAL_PWREx_SMPS_EnableBypassMode();
1318 }
1319
1320 /* Wait until SMPS step down converter operating mode change */
1321 /* and at least one iteration loop */
1322 wait_loop_index = ((PWR_MODE_CHANGE_DELAY_VALUE * (SystemCoreClock / 100000U)) / 10U) + 1U;
1323
1324 while ((HAL_PWREx_SMPS_GetEffectiveMode() != OperatingMode) && (wait_loop_index != 0U))
1325 {
1326 wait_loop_index--;
1327 }
1328
1329 if (HAL_PWREx_SMPS_GetEffectiveMode() == OperatingMode)
1330 {
1331 status = HAL_OK;
1332 }
1333 else
1334 {
1335 status = HAL_TIMEOUT;
1336 }
1337 return status;
1338 }
1339
1340 /**
1341 * @brief Get SMPS effective step down converter operating mode
1342 * @retval Returned value can be one of the following values:
1343 * @arg @ref PWR_SMPS_HIGH_POWER SMPS step down converter in high-power mode (default)
1344 * @arg @ref PWR_SMPS_LOW_POWER SMPS step down converter in low-power mode
1345 * @arg @ref PWR_SMPS_BYPASS SMPS step down converter in bypass mode
1346 */
HAL_PWREx_SMPS_GetEffectiveMode(void)1347 uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void)
1348 {
1349 uint32_t mode;
1350 uint32_t pwr_sr1;
1351
1352 pwr_sr1 = READ_REG(PWR->SR1);
1353 if (READ_BIT(pwr_sr1, PWR_SR1_SMPSBYPRDY) != 0U)
1354 {
1355 mode = PWR_SMPS_BYPASS;
1356 }
1357 else if (READ_BIT(pwr_sr1, PWR_SR1_SMPSHPRDY) == 0U)
1358 {
1359 mode = PWR_SMPS_LOW_POWER;
1360 }
1361 else
1362 {
1363 mode = PWR_SMPS_HIGH_POWER;
1364 }
1365
1366 return mode;
1367 }
1368
1369 /**
1370 * @brief Enable SMPS step down converter fast start.
1371 * @note This feature is secured by VDMSEC bit when system implements security (TZEN=1).
1372 * @retval None
1373 */
HAL_PWREx_SMPS_EnableFastStart(void)1374 void HAL_PWREx_SMPS_EnableFastStart(void)
1375 {
1376 SET_BIT(PWR->CR4, PWR_CR4_SMPSFSTEN);
1377 }
1378
1379 /**
1380 * @brief Disable SMPS step down converter fast start.
1381 * @note This feature is secured by VDMSEC bit when system implements security (TZEN=1).
1382 * @retval None
1383 */
HAL_PWREx_SMPS_DisableFastStart(void)1384 void HAL_PWREx_SMPS_DisableFastStart(void)
1385 {
1386 CLEAR_BIT(PWR->CR4, PWR_CR4_SMPSFSTEN);
1387 }
1388
1389 /**
1390 * @brief Disable the SMPS Bypass.
1391 * @note This feature is secured by VDMSEC bit when system implements security (TZEN=1).
1392 * @retval None
1393 */
HAL_PWREx_SMPS_DisableBypassMode(void)1394 void HAL_PWREx_SMPS_DisableBypassMode(void)
1395 {
1396 CLEAR_BIT(PWR->CR4, PWR_CR4_SMPSBYP);
1397 }
1398
1399 /**
1400 * @brief Enable the SMPS Bypass.
1401 * @note This feature is secured by VDMSEC bit when system implements security (TZEN=1).
1402 * @retval None
1403 */
HAL_PWREx_SMPS_EnableBypassMode(void)1404 void HAL_PWREx_SMPS_EnableBypassMode(void)
1405 {
1406 SET_BIT(PWR->CR4, PWR_CR4_SMPSBYP);
1407 }
1408
1409
1410 /**
1411 * @brief Enable external SMPS when external SMPS switch closed.
1412 * @note This feature is secured by VDMSEC bit when system implements security (TZEN=1).
1413 * @retval None
1414 */
HAL_PWREx_SMPS_EnableExternal(void)1415 void HAL_PWREx_SMPS_EnableExternal(void)
1416 {
1417 SET_BIT(PWR->CR4, PWR_CR4_EXTSMPSEN);
1418 }
1419
1420 /**
1421 * @brief Disable external SMPS when external SMPS switch closed.
1422 * @note This feature is secured by VDMSEC bit when system implements security (TZEN=1).
1423 * @retval None
1424 */
HAL_PWREx_SMPS_DisableExternal(void)1425 void HAL_PWREx_SMPS_DisableExternal(void)
1426 {
1427 CLEAR_BIT(PWR->CR4, PWR_CR4_EXTSMPSEN);
1428 }
1429
1430 /**
1431 * @brief Get Main Regulator status for use with external SMPS
1432 * @retval Returned value can be one of the following values:
1433 * @arg @ref PWR_MAINREG_READY_FOR_EXTSMPS Main regulator ready for use with external SMPS
1434 * @arg @ref PWR_MAINREG_NOT_READY_FOR_EXTSMPS Main regulator not ready for use with external SMPS
1435 */
HAL_PWREx_SMPS_GetMainRegulatorExtSMPSReadyStatus(void)1436 uint32_t HAL_PWREx_SMPS_GetMainRegulatorExtSMPSReadyStatus(void)
1437 {
1438 uint32_t main_regulator_status;
1439 uint32_t pwr_sr1;
1440
1441 pwr_sr1 = READ_REG(PWR->SR1);
1442 if (READ_BIT(pwr_sr1, PWR_SR1_EXTSMPSRDY) != 0U)
1443 {
1444 main_regulator_status = PWR_MAINREG_READY_FOR_EXTSMPS;
1445 }
1446 else
1447 {
1448 main_regulator_status = PWR_MAINREG_NOT_READY_FOR_EXTSMPS;
1449 }
1450 return main_regulator_status;
1451 }
1452
1453 /**
1454 * @}
1455 */
1456
1457 /**
1458 * @}
1459 */
1460
1461 #endif /* HAL_PWR_MODULE_ENABLED */
1462 /**
1463 * @}
1464 */
1465
1466 /**
1467 * @}
1468 */
1469
