1 /**
2 ******************************************************************************
3 * @file stm32l5xx_hal_flash_ex.c
4 * @author MCD Application Team
5 * @brief Extended FLASH HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the FLASH extended peripheral:
8 * + Extended programming operations functions
9 *
10 ******************************************************************************
11 * @attention
12 *
13 * Copyright (c) 2019 STMicroelectronics.
14 * All rights reserved.
15 *
16 * This software is licensed under terms that can be found in the LICENSE file in
17 * the root directory of this software component.
18 * If no LICENSE file comes with this software, it is provided AS-IS.
19 ******************************************************************************
20 @verbatim
21 ==============================================================================
22 ##### Flash Extended features #####
23 ==============================================================================
24
25 [..] Comparing to other previous devices, the FLASH interface for STM32L5xx
26 devices contains the following additional features
27
28 (+) Capacity up to 512 Kbytes with dual bank architecture supporting read-while-write
29 capability (RWW)
30 (+) Dual bank memory organization with possibility of 128-bits single bank
31 (+) Watermark-based secure area including secure hide areas
32 (+) Block-based secure pages
33
34 ##### How to use this driver #####
35 ==============================================================================
36 [..] This driver provides functions to configure and program the FLASH memory
37 of all STM32L5xx devices. It includes
38 (#) Flash Memory Erase functions:
39 (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
40 HAL_FLASH_Lock() functions
41 (++) Erase function: Erase page, mass erase of one or two banks
42 (++) There are two modes of erase :
43 (+++) Polling Mode using HAL_FLASHEx_Erase()
44 (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
45
46 (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to :
47 (++) Configure the write protection for each area
48 (++) Set the Read protection Level
49 (++) Program the user Option Bytes
50 (++) Configure the watermark security for each area including secure hide areas
51 (++) Configure the boot lock (BOOT_LOCK)
52 (++) Configure the Boot addresses
53
54 (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to :
55 (++) Get the value of a write protection area
56 (++) Know if the read protection is activated
57 (++) Get the value of the user Option Bytes
58 (++) Get the configuration of a watermark security area including secure hide areas
59 (++) Get the boot lock (BOOT_LOCK) configuration
60 (++) Get the value of a boot address
61
62 (#) Block-based secure area configuration function: Use HAL_FLASHEx_ConfigBBAttributes()
63 (++) Bit-field allowing to secure or un-secure each page
64
65 (#) Get the block-based secure area configuration function: Use HAL_FLASHEx_GetConfigBBAttributes()
66 (++) Returns the configuration of the block-based security for all the pages
67
68 (#) Activation of the secure hide area function: Use HAL_FLASHEx_EnableSecHideProtection()
69 (++) Deny the access to the secure hide area
70
71 (#) Privilege mode configuration function: Use HAL_FLASHEx_ConfigPrivMode()
72 (++) FLASH register can be protected against non-privilege accesses
73
74 (#) Get the privilege mode configuration function: Use HAL_FLASHEx_GetPrivMode()
75 (++) Returns if the FLASH registers are protected against non-privilege accesses
76
77 (#) Security inversion configuration function: Use HAL_FLASHEx_ConfigSecInversion()
78 (++) FLASH secure state can be override
79
80 (#) Get the security inversion configuration function: Use HAL_FLASHEx_GetSecInversion()
81 (++) Returns if FLASH secure state is override
82
83 (#) LVE pin management configuration function: Use HAL_FLASHEx_ConfigLVEPin()
84 (++) LVE FLASH pin can be controlled either by power controller or enforced
85 to low in order to use external SMPS
86
87 (#) Get LVE pin management configuration function: Use HAL_FLASHEx_GetLVEPin()
88 (++) Returns if LVE FLASH pin is controlled by power controller or enforced to low
89
90 @endverbatim
91 ******************************************************************************
92 */
93
94 /* Includes ------------------------------------------------------------------*/
95 #include "stm32l5xx_hal.h"
96
97 /** @addtogroup STM32L5xx_HAL_Driver
98 * @{
99 */
100
101 /** @defgroup FLASHEx FLASHEx
102 * @brief FLASH Extended HAL module driver
103 * @{
104 */
105
106 #ifdef HAL_FLASH_MODULE_ENABLED
107
108 /* Private typedef -----------------------------------------------------------*/
109 /* Private define ------------------------------------------------------------*/
110 /* Private macro -------------------------------------------------------------*/
111 /* Private variables ---------------------------------------------------------*/
112 /* Private function prototypes -----------------------------------------------*/
113 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
114 * @{
115 */
116 static void FLASH_MassErase(uint32_t Banks);
117 static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRPEndOffset);
118 static void FLASH_OB_RDPConfig(uint32_t RDPLevel);
119 static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
120 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
121 static void FLASH_OB_WMSECConfig(uint32_t WMSecConfig, uint32_t WMSecStartPage, uint32_t WMSecEndPage, uint32_t WMHDPEndPage);
122 static void FLASH_OB_BootLockConfig(uint32_t BootLockConfig);
123 #endif
124 static void FLASH_OB_BootAddrConfig(uint32_t BootAddrConfig, uint32_t BootAddr);
125 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRPEndOffset);
126 static uint32_t FLASH_OB_GetRDP(void);
127 static uint32_t FLASH_OB_GetUser(void);
128 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
129 static void FLASH_OB_GetWMSEC(uint32_t * WMSecConfig, uint32_t * WMSecStartPage, uint32_t * WMSecEndPage, uint32_t * WMHDPEndPage);
130 static uint32_t FLASH_OB_GetBootLock(void);
131 #endif
132 static void FLASH_OB_GetBootAddr(uint32_t BootAddrConfig, uint32_t * BootAddr);
133 /**
134 * @}
135 */
136
137 /* Exported functions -------------------------------------------------------*/
138 /** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions
139 * @{
140 */
141
142 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended Programming Operation functions
143 * @brief Extended Programming Operation functions
144 *
145 @verbatim
146 ===============================================================================
147 ##### Extended Programming Operation functions #####
148 ===============================================================================
149 [..]
150 This subsection provides a set of functions allowing to manage the Extended FLASH
151 programming operations Operations.
152
153 @endverbatim
154 * @{
155 */
156
157 /**
158 * @brief Perform a mass erase or erase the specified FLASH memory pages.
159 * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
160 * contains the configuration information for the erasing.
161 *
162 * @param[out] PageError pointer to variable that contains the configuration
163 * information on faulty page in case of error (0xFFFFFFFF means that all
164 * the pages have been correctly erased)
165 *
166 * @retval HAL Status
167 */
HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef * pEraseInit,uint32_t * PageError)168 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
169 {
170 HAL_StatusTypeDef status;
171 uint32_t page_index;
172 __IO uint32_t *reg;
173
174 /* Check the parameters */
175 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
176
177 /* Process Locked */
178 __HAL_LOCK(&pFlash);
179
180 /* Reset error code */
181 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
182
183 /* Wait for last operation to be completed */
184 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
185
186 if (status == HAL_OK)
187 {
188 pFlash.ProcedureOnGoing = pEraseInit->TypeErase;
189
190 reg = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
191
192 if ((pFlash.ProcedureOnGoing & ~(FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE)
193 {
194 /* Mass erase to be done */
195 FLASH_MassErase(pEraseInit->Banks);
196
197 /* Wait for last operation to be completed */
198 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
199 }
200 else
201 {
202 /*Initialization of PageError variable*/
203 *PageError = 0xFFFFFFFFU;
204
205 for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
206 {
207 FLASH_PageErase(page_index, pEraseInit->Banks);
208
209 /* Wait for last operation to be completed */
210 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
211
212 if (status != HAL_OK)
213 {
214 /* In case of error, stop erase procedure and return the faulty page */
215 *PageError = page_index;
216 break;
217 }
218 }
219 }
220
221 /* If the erase operation is completed, disable the associated bits */
222 CLEAR_BIT((*reg), (pFlash.ProcedureOnGoing & ~(FLASH_NON_SECURE_MASK)));
223 }
224
225 /* Process Unlocked */
226 __HAL_UNLOCK(&pFlash);
227
228 return status;
229 }
230
231 /**
232 * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
233 * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
234 * contains the configuration information for the erasing.
235 *
236 * @retval HAL Status
237 */
HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef * pEraseInit)238 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
239 {
240 HAL_StatusTypeDef status;
241 __IO uint32_t *reg_cr;
242
243 /* Check the parameters */
244 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
245
246 /* Process Locked */
247 __HAL_LOCK(&pFlash);
248
249 /* Reset error code */
250 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
251
252 /* Wait for last operation to be completed */
253 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
254
255 if (status != HAL_OK)
256 {
257 /* Process Unlocked */
258 __HAL_UNLOCK(&pFlash);
259 }
260 else
261 {
262 /* Set internal variables used by the IRQ handler */
263 pFlash.ProcedureOnGoing = pEraseInit->TypeErase;
264 pFlash.Bank = pEraseInit->Banks;
265
266 /* Access to SECCR or NSCR depends on operation type */
267 reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH->NSCR);
268
269 /* Enable End of Operation and Error interrupts */
270 (*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_OPERR);
271
272 if ((pFlash.ProcedureOnGoing & ~(FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE)
273 {
274 /* Mass erase to be done */
275 FLASH_MassErase(pEraseInit->Banks);
276 }
277 else
278 {
279 /* Erase by page to be done */
280 pFlash.NbPagesToErase = pEraseInit->NbPages;
281 pFlash.Page = pEraseInit->Page;
282
283 /*Erase 1st page and wait for IT */
284 FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);
285 }
286 }
287
288 return status;
289 }
290
291 /**
292 * @brief Program Option bytes.
293 * @param pOBInit pointer to an FLASH_OBInitStruct structure that
294 * contains the configuration information for the programming.
295 *
296 * @note To configure any option bytes, the option lock bit OPTLOCK must be
297 * cleared with the call of HAL_FLASH_OB_Unlock() function.
298 * @note New option bytes configuration will be taken into account in two cases:
299 * - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
300 * - after a power reset (BOR reset or exit from Standby/Shutdown modes)
301 *
302 * @retval HAL Status
303 */
HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef * pOBInit)304 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
305 {
306 HAL_StatusTypeDef status;
307
308 /* Check the parameters */
309 assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
310
311 /* Process Locked */
312 __HAL_LOCK(&pFlash);
313
314 /* Reset error code */
315 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
316
317 /* Wait for last operation to be completed */
318 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
319
320 if(status == HAL_OK)
321 {
322 /* Write protection configuration */
323 if((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U)
324 {
325 /* Configure of Write protection on the selected area */
326 FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset);
327 }
328
329 /* Read protection configuration */
330 if((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
331 {
332 /* Configure the Read protection level */
333 FLASH_OB_RDPConfig(pOBInit->RDPLevel);
334 }
335
336 /* User Configuration */
337 if((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
338 {
339 /* Configure the user option bytes */
340 FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
341 }
342
343 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
344 /* Watermark secure configuration */
345 if((pOBInit->OptionType & OPTIONBYTE_WMSEC) != 0U)
346 {
347 /* Configure the watermark-based secure area */
348 FLASH_OB_WMSECConfig(pOBInit->WMSecConfig, pOBInit->WMSecStartPage, pOBInit->WMSecEndPage, pOBInit->WMHDPEndPage);
349 }
350
351 /* Unique boot entry point configuration */
352 if((pOBInit->OptionType & OPTIONBYTE_BOOT_LOCK) != 0U)
353 {
354 /* Configure the unique boot entry point */
355 FLASH_OB_BootLockConfig(pOBInit->BootLock);
356 }
357 #endif
358
359 /* Boot address configuration */
360 if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR) != 0U)
361 {
362 /* Configure the boot address */
363 FLASH_OB_BootAddrConfig(pOBInit->BootAddrConfig, pOBInit->BootAddr);
364 }
365
366 /* Set OPTSTRT Bit */
367 SET_BIT(FLASH->NSCR, FLASH_NSCR_OPTSTRT);
368
369 /* Wait for last operation to be completed */
370 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
371 }
372
373 /* Process Unlocked */
374 __HAL_UNLOCK(&pFlash);
375
376 return status;
377 }
378
379 /**
380 * @brief Get the Option bytes configuration.
381 * @param pOBInit pointer to an FLASH_OBInitStruct structure that contains the
382 * configuration information.
383 * @note The fields pOBInit->WRPArea, pOBInit->WMSecConfig and pOBInit->BootAddrConfig
384 * should indicate which area/address is requested for the WRP, WM Security or
385 * Boot Address, else no information will be returned
386 *
387 * @retval None
388 */
HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef * pOBInit)389 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
390 {
391 pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);
392
393 if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) ||
394 (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB))
395 {
396 pOBInit->OptionType |= OPTIONBYTE_WRP;
397 /* Get write protection on the selected area */
398 FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
399 }
400
401 /* Get Read protection level */
402 pOBInit->RDPLevel = FLASH_OB_GetRDP();
403
404 /* Get the user option bytes */
405 pOBInit->USERConfig = FLASH_OB_GetUser();
406
407 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
408 /* Get the configuration of the watermark secure area for the selected area */
409 if ((pOBInit->WMSecConfig == OB_WMSEC_AREA1) || (pOBInit->WMSecConfig == OB_WMSEC_AREA2))
410 {
411 pOBInit->OptionType |= OPTIONBYTE_WMSEC;
412 FLASH_OB_GetWMSEC(&(pOBInit->WMSecConfig), &(pOBInit->WMSecStartPage), &(pOBInit->WMSecEndPage), &(pOBInit->WMHDPEndPage));
413 }
414
415 pOBInit->OptionType |= OPTIONBYTE_BOOT_LOCK;
416
417 /* Get the configuration of the unique boot entry point */
418 pOBInit->BootLock = FLASH_OB_GetBootLock();
419 #endif
420
421 /* Get the value of the selected boot address */
422 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
423 if ((pOBInit->BootAddrConfig == OB_BOOTADDR_NS0) || (pOBInit->BootAddrConfig == OB_BOOTADDR_NS1) ||
424 (pOBInit->BootAddrConfig == OB_BOOTADDR_SEC0))
425 #else
426 if ((pOBInit->BootAddrConfig == OB_BOOTADDR_NS0) || (pOBInit->BootAddrConfig == OB_BOOTADDR_NS1))
427 #endif
428 {
429 pOBInit->OptionType |= OPTIONBYTE_BOOTADDR;
430 FLASH_OB_GetBootAddr(pOBInit->BootAddrConfig, &(pOBInit->BootAddr));
431 }
432 }
433
434 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
435 /**
436 * @brief Configure the block-based secure area.
437 *
438 * @param pBBAttributes pointer to an FLASH_BBAttributesTypeDef structure that
439 * contains the configuration information for the programming.
440 *
441 * @retval HAL Status
442 */
HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef * pBBAttributes)443 HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes)
444 {
445 HAL_StatusTypeDef status;
446 uint8_t index;
447 __IO uint32_t *reg;
448
449 /* Check the parameters */
450 assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank));
451
452 /* Wait for last operation to be completed */
453 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
454
455 if (status == HAL_OK)
456 {
457 if (pBBAttributes->BBAttributesType == FLASH_BB_SEC)
458 {
459 if (pBBAttributes->Bank == FLASH_BANK_1)
460 {
461 reg = &(FLASH->SECBB1R1);
462 }
463 else
464 {
465 reg = &(FLASH->SECBB2R1);
466 }
467
468 /* Modify the register values and check that new attributes are taken in account */
469 for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++)
470 {
471 *reg = pBBAttributes->BBAttributes_array[index];
472 if (*reg != pBBAttributes->BBAttributes_array[index])
473 {
474 status = HAL_ERROR;
475 }
476 reg++;
477 }
478 }
479
480 /* ISB instruction is called to be sure next instructions are performed with correct attributes */
481 __ISB();
482 }
483
484 /* Process Unlocked */
485 __HAL_UNLOCK(&pFlash);
486
487 return status;
488 }
489
490 /**
491 * @brief Return the block-based secure area.
492 *
493 * @param pBBAttributes [in/out] pointer to an FLASH_BBAttributesTypeDef structure
494 * that contains theconfiguration information.
495 * @note The fields pBBAttributes->BBSecConfig should indicate which area is requested
496 * for the block-based security, else no information will be returned
497 *
498 * @retval None
499 */
HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef * pBBAttributes)500 void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes)
501 {
502 uint8_t index;
503 __IO uint32_t *reg;
504
505 /* Check the parameters */
506 assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank));
507
508 if (pBBAttributes->BBAttributesType == FLASH_BB_SEC)
509 {
510 if (pBBAttributes->Bank == FLASH_BANK_1)
511 {
512 reg = &(FLASH->SECBB1R1);
513 }
514 else
515 {
516 reg = &(FLASH->SECBB2R1);
517 }
518
519 for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++)
520 {
521 pBBAttributes->BBAttributes_array[index] = *reg;
522 reg++;
523 }
524 }
525 }
526
527 /**
528 * @brief Activation of the protection of the secure hide area.
529 *
530 * @param Banks indicate the bank concerned by the activation
531 * This parameter can be one of the following values:
532 * @arg FLASH_BANK_1: Bank1
533 * @arg FLASH_BANK_2: Bank2
534 * @arg FLASH_BANK_BOTH: Bank1 & Bank2
535 *
536 * @retval None
537 */
HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks)538 void HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks)
539 {
540 /* Check the parameters */
541 assert_param(IS_FLASH_BANK(Banks));
542
543 if ((Banks & FLASH_BANK_1) != 0U)
544 {
545 SET_BIT(FLASH->SECHDPCR, FLASH_SECHDPCR_HDP1_ACCDIS);
546 }
547 if((Banks & FLASH_BANK_2) != 0U)
548 {
549 SET_BIT(FLASH->SECHDPCR, FLASH_SECHDPCR_HDP2_ACCDIS);
550 }
551 }
552 #endif
553
554 /**
555 * @}
556 */
557
558 /** @defgroup FLASHEx_Exported_Functions_Group2 Extended Peripheral Control functions
559 * @brief Extended Peripheral Control functions
560 *
561 @verbatim
562 ===============================================================================
563 ##### Extended Peripheral Control functions #####
564 ===============================================================================
565 [..]
566 This subsection provides a set of functions allowing to control the FLASH
567 memory operations.
568
569 @endverbatim
570 * @{
571 */
572
573 /**
574 * @brief Configuration of the privilege attribute.
575 *
576 * @param PrivMode indicate privilege mode configuration
577 * This parameter can be one of the following values:
578 * @arg FLASH_PRIV_GRANTED: access to Flash registers is granted
579 * @arg FLASH_PRIV_DENIED: access to Flash registers is denied to non-privilege access
580 *
581 * @retval None
582 */
HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode)583 void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode)
584 {
585 /* Check the parameters */
586 assert_param(IS_FLASH_CFGPRIVMODE(PrivMode));
587
588 MODIFY_REG(FLASH->PRIVCFGR, FLASH_PRIVCFGR_PRIV, PrivMode);
589 }
590
591 /**
592 * @brief Return the value of the privilege attribute.
593 *
594 * @retval It indicates privilege mode configuration.
595 * This return value can be one of the following values:
596 * @arg FLASH_PRIV_GRANTED: access to Flash registers is granted
597 * @arg FLASH_PRIV_DENIED: access to Flash registers is denied to non-privilege access
598 */
HAL_FLASHEx_GetPrivMode(void)599 uint32_t HAL_FLASHEx_GetPrivMode(void)
600 {
601 return (FLASH->PRIVCFGR & FLASH_PRIVCFGR_PRIV);
602 }
603
604 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
605 /**
606 * @brief Configuration of the security inversion.
607 *
608 * @param SecInvState indicate the flash security state configuration
609 * This parameter can be one of the following values:
610 * @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted
611 * @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted
612 *
613 * @retval HAL Status
614 */
HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState)615 HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState)
616 {
617 HAL_StatusTypeDef status;
618
619 /* Check the parameters */
620 assert_param(IS_FLASH_CFGSECINV(SecInvState));
621
622 /* Process Locked */
623 __HAL_LOCK(&pFlash);
624
625 /* Wait for last operation to be completed */
626 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
627
628 if (status == HAL_OK)
629 {
630 MODIFY_REG(FLASH->SECCR, FLASH_SECCR_SECINV, SecInvState);
631 }
632
633 /* Process Unlocked */
634 __HAL_UNLOCK(&pFlash);
635
636 return status;
637 }
638
639 /**
640 * @brief Return the value of the security inversion.
641 *
642 * @retval It indicates the flash security state configuration
643 * This return value can be one of the following values:
644 * @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted
645 * @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted
646 */
HAL_FLASHEx_GetSecInversion(void)647 uint32_t HAL_FLASHEx_GetSecInversion(void)
648 {
649 return (FLASH->SECCR & FLASH_SECCR_SECINV);
650 }
651 #endif
652
653 /**
654 * @brief Configuration of the LVE pin management.
655 *
656 * @param ConfigLVE indicate the LVE pin management configuration
657 * This parameter can be one of the following values:
658 * @arg FLASH_LVE_PIN_CTRL: LVEA/B FLASH pin controlled by power controller
659 * @arg FLASH_LVE_PIN_FORCED: LVEA/B FLASH pin enforced to low
660 *
661 * @retval HAL Status
662 */
HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE)663 HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE)
664 {
665 HAL_StatusTypeDef status;
666
667 /* Check the parameters */
668 assert_param(IS_FLASH_CFGLVEPIN(ConfigLVE));
669
670 /* Process Locked */
671 __HAL_LOCK(&pFlash);
672
673 /* Wait for last operation to be completed */
674 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
675
676 if (status == HAL_OK)
677 {
678 /* Check that the voltage scaling is range 2 */
679 if (HAL_PWREx_GetVoltageRange() == PWR_REGULATOR_VOLTAGE_SCALE2)
680 {
681 /* Unlock the bit LVEN */
682 FLASH->LVEKEYR = FLASH_LVEKEY1;
683 FLASH->LVEKEYR = FLASH_LVEKEY2;
684
685 /* Modify the value of LVEN bit */
686 MODIFY_REG(FLASH->ACR, FLASH_ACR_LVEN, ConfigLVE);
687
688 /* Check that the bit has been correctly configured */
689 if (READ_BIT(FLASH->ACR, FLASH_ACR_LVEN) != ConfigLVE)
690 {
691 status = HAL_ERROR;
692 }
693 }
694 else
695 {
696 /* Not allow to force Flash LVE pin if not in voltage range 2 */
697 status = HAL_ERROR;
698 }
699 }
700
701 /* Process Unlocked */
702 __HAL_UNLOCK(&pFlash);
703
704 return status;
705 }
706
707 /**
708 * @brief Return the value of the LVE pin management.
709 *
710 * @retval It indicates the LVE pin management configuration
711 * This return value can be one of the following values:
712 * @arg FLASH_LVE_PIN_CTRL: LVEA/B FLASH pin controlled by power controller
713 * @arg FLASH_LVE_PIN_FORCED: LVEA/B FLASH pin enforces to low
714 */
HAL_FLASHEx_GetLVEPin(void)715 uint32_t HAL_FLASHEx_GetLVEPin(void)
716 {
717 return (FLASH->ACR & FLASH_ACR_LVEN);
718 }
719
720 /**
721 * @}
722 */
723
724 /**
725 * @}
726 */
727
728 /* Private functions ---------------------------------------------------------*/
729
730 /** @addtogroup FLASHEx_Private_Functions
731 * @{
732 */
733 /**
734 * @brief Mass erase of FLASH memory.
735 * @param Banks Banks to be erased
736 * This parameter can be one of the following values:
737 * @arg FLASH_BANK_1: Bank1 to be erased
738 * @arg FLASH_BANK_2: Bank2 to be erased
739 * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
740 * @retval None
741 */
FLASH_MassErase(uint32_t Banks)742 static void FLASH_MassErase(uint32_t Banks)
743 {
744 __IO uint32_t *reg;
745
746 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
747 uint32_t primask_bit;
748
749 /* Disable interrupts to avoid any interruption */
750 primask_bit = __get_PRIMASK();
751 __disable_irq();
752 #endif
753
754 /* Access to SECCR or NSCR registers depends on operation type */
755 reg = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
756
757 if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U)
758 {
759 /* Check the parameters */
760 assert_param(IS_FLASH_BANK(Banks));
761
762 /* Set the Mass Erase Bit for the bank 1 if requested */
763 if((Banks & FLASH_BANK_1) != 0U)
764 {
765 SET_BIT((*reg), FLASH_NSCR_NSMER1);
766 }
767
768 /* Set the Mass Erase Bit for the bank 2 if requested */
769 if((Banks & FLASH_BANK_2) != 0U)
770 {
771 SET_BIT((*reg), FLASH_NSCR_NSMER2);
772 }
773 }
774 else
775 {
776 SET_BIT((*reg), (FLASH_NSCR_NSMER1 | FLASH_NSCR_NSMER2));
777 }
778
779 /* Proceed to erase all sectors */
780 SET_BIT((*reg), FLASH_NSCR_NSSTRT);
781
782 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
783 /* Re-enable the interrupts */
784 __set_PRIMASK(primask_bit);
785 #endif
786 }
787
788 /**
789 * @brief Erase the specified FLASH memory page.
790 * @param Page FLASH page to erase
791 * This parameter must be a value between 0 and (max number of pages in the bank - 1)
792 * @param Banks Bank(s) where the page will be erased
793 * This parameter can be one of the following values:
794 * @arg FLASH_BANK_1: Page in bank 1 to be erased
795 * @arg FLASH_BANK_2: Page in bank 2 to be erased
796 * @retval None
797 */
FLASH_PageErase(uint32_t Page,uint32_t Banks)798 void FLASH_PageErase(uint32_t Page, uint32_t Banks)
799 {
800 __IO uint32_t *reg;
801 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
802 uint32_t primask_bit;
803 #endif
804 /* Check the parameters */
805 assert_param(IS_FLASH_PAGE(Page));
806
807 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
808 /* Disable interrupts to avoid any interruption */
809 primask_bit = __get_PRIMASK();
810 __disable_irq();
811 #endif
812
813 /* Access to SECCR or NSCR registers depends on operation type */
814 reg = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
815
816 if(READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)
817 {
818 CLEAR_BIT((*reg), FLASH_NSCR_NSBKER);
819 }
820 else
821 {
822 assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
823
824 if((Banks & FLASH_BANK_1) != 0U)
825 {
826 CLEAR_BIT((*reg), FLASH_NSCR_NSBKER);
827 }
828 else
829 {
830 SET_BIT((*reg), FLASH_NSCR_NSBKER);
831 }
832 }
833
834 /* Proceed to erase the page */
835 MODIFY_REG((*reg), (FLASH_NSCR_NSPNB | FLASH_NSCR_NSPER), ((Page << FLASH_NSCR_NSPNB_Pos) | FLASH_NSCR_NSPER));
836 SET_BIT((*reg), FLASH_NSCR_NSSTRT);
837
838 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
839 /* Re-enable the interrupts */
840 __set_PRIMASK(primask_bit);
841 #endif
842 }
843
844 /**
845 * @brief Configure the write protection of the desired pages.
846 *
847 * @note When the memory read protection level is selected (RDP level = 1),
848 * it is not possible to program or erase Flash memory if the CPU debug
849 * features are connected (JTAG or single wire) or boot code is being
850 * executed from RAM or System flash, even if WRP is not activated.
851 * @note To configure the WRP options, the option lock bit OPTLOCK must be
852 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
853 * @note To validate the WRP options, the option bytes must be reloaded
854 * through the call of the HAL_FLASH_OB_Launch() function.
855 *
856 * @param WRPArea specifies the area to be configured.
857 * This parameter can be one of the following values:
858 * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
859 * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
860 * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A
861 * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B
862 *
863 * @param WRPStartOffset specifies the start page of the write protected area
864 * This parameter can be page number between 0 and (max number of pages in the bank - 1)
865 *
866 * @param WRPEndOffset specifies the end page of the write protected area
867 * This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1)
868 *
869 * @retval None
870 */
FLASH_OB_WRPConfig(uint32_t WRPArea,uint32_t WRPStartOffset,uint32_t WRPEndOffset)871 static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRPEndOffset)
872 {
873 /* Check the parameters */
874 assert_param(IS_OB_WRPAREA(WRPArea));
875 assert_param(IS_FLASH_PAGE(WRPStartOffset));
876 assert_param(IS_FLASH_PAGE(WRPEndOffset));
877
878 /* Configure the write protected area */
879 if(WRPArea == OB_WRPAREA_BANK1_AREAA)
880 {
881 MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_PSTRT | FLASH_WRP1AR_WRP1A_PEND),
882 (WRPStartOffset | (WRPEndOffset << FLASH_WRP1AR_WRP1A_PEND_Pos)));
883 }
884 else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
885 {
886 MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_PSTRT | FLASH_WRP1BR_WRP1B_PEND),
887 (WRPStartOffset | (WRPEndOffset << FLASH_WRP1BR_WRP1B_PEND_Pos)));
888 }
889 else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
890 {
891 MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_PSTRT | FLASH_WRP2AR_WRP2A_PEND),
892 (WRPStartOffset | (WRPEndOffset << FLASH_WRP2AR_WRP2A_PEND_Pos)));
893 }
894 else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
895 {
896 MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_PSTRT | FLASH_WRP2BR_WRP2B_PEND),
897 (WRPStartOffset | (WRPEndOffset << FLASH_WRP2BR_WRP2B_PEND_Pos)));
898 }
899 else
900 {
901 /* Empty statement (to be compliant MISRA 15.7) */
902 }
903 }
904
905 /**
906 * @brief Set the read protection level.
907 *
908 * @note To configure the RDP level, the option lock bit OPTLOCK must be
909 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
910 * @note To validate the RDP level, the option bytes must be reloaded
911 * through the call of the HAL_FLASH_OB_Launch() function.
912 * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible
913 * to go back to other levels !!!
914 *
915 * @param RDPLevel specifies the read protection level.
916 * This parameter can be one of the following values:
917 * @arg OB_RDP_LEVEL_0: No protection
918 * @arg OB_RDP_LEVEL_0_5: No debug access to secure area
919 * @arg OB_RDP_LEVEL_1: Read protection of the memory
920 * @arg OB_RDP_LEVEL_2: Full chip protection
921 *
922 * @retval None
923 */
FLASH_OB_RDPConfig(uint32_t RDPLevel)924 static void FLASH_OB_RDPConfig(uint32_t RDPLevel)
925 {
926 /* Check the parameters */
927 assert_param(IS_OB_RDP_LEVEL(RDPLevel));
928
929 /* Configure the RDP level in the option bytes register */
930 MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);
931 }
932
933 /**
934 * @brief Program the FLASH User Option Byte.
935 *
936 * @note To configure the user option bytes, the option lock bit OPTLOCK must
937 * be cleared with the call of the HAL_FLASH_OB_Unlock() function.
938 * @note To validate the user option bytes, the option bytes must be reloaded
939 * through the call of the HAL_FLASH_OB_Launch() function.
940 *
941 * @param UserType The FLASH User Option Bytes to be modified
942 * This parameter can be a combination of @ref FLASH_OB_USER_Type
943 * @param UserConfig The FLASH User Option Bytes values.
944 * It can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
945 * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
946 * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
947 * @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
948 * @ref FLASH_OB_USER_WWDG_SW, @ref OB_USER_SWAP_BANK,
949 * @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_DBANK,
950 * @ref FLASH_OB_USER_SRAM2_PAR, @ref FLASH_OB_USER_SRAM2_RST,
951 * @ref OB_USER_nSWBOOT0, @ref OB_USER_nBOOT0, @ref FLASH_OB_USER_PA15_PUPEN
952 * and @ref OB_USER_TZEN
953 *
954 * @retval None
955 */
FLASH_OB_UserConfig(uint32_t UserType,uint32_t UserConfig)956 static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
957 {
958 uint32_t optr_reg_val = 0;
959 uint32_t optr_reg_mask = 0;
960
961 /* Check the parameters */
962 assert_param(IS_OB_USER_TYPE(UserType));
963
964 if((UserType & OB_USER_BOR_LEV) != 0U)
965 {
966 /* BOR level option byte should be modified */
967 assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));
968
969 /* Set value and mask for BOR level option byte */
970 optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);
971 optr_reg_mask |= FLASH_OPTR_BOR_LEV;
972 }
973
974 if((UserType & OB_USER_nRST_STOP) != 0U)
975 {
976 /* nRST_STOP option byte should be modified */
977 assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));
978
979 /* Set value and mask for nRST_STOP option byte */
980 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);
981 optr_reg_mask |= FLASH_OPTR_nRST_STOP;
982 }
983
984 if((UserType & OB_USER_nRST_STDBY) != 0U)
985 {
986 /* nRST_STDBY option byte should be modified */
987 assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));
988
989 /* Set value and mask for nRST_STDBY option byte */
990 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);
991 optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
992 }
993
994 if((UserType & OB_USER_nRST_SHDW) != 0U)
995 {
996 /* nRST_SHDW option byte should be modified */
997 assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));
998
999 /* Set value and mask for nRST_SHDW option byte */
1000 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);
1001 optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
1002 }
1003
1004 if((UserType & OB_USER_IWDG_SW) != 0U)
1005 {
1006 /* IWDG_SW option byte should be modified */
1007 assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));
1008
1009 /* Set value and mask for IWDG_SW option byte */
1010 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);
1011 optr_reg_mask |= FLASH_OPTR_IWDG_SW;
1012 }
1013
1014 if((UserType & OB_USER_IWDG_STOP) != 0U)
1015 {
1016 /* IWDG_STOP option byte should be modified */
1017 assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));
1018
1019 /* Set value and mask for IWDG_STOP option byte */
1020 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);
1021 optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
1022 }
1023
1024 if((UserType & OB_USER_IWDG_STDBY) != 0U)
1025 {
1026 /* IWDG_STDBY option byte should be modified */
1027 assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));
1028
1029 /* Set value and mask for IWDG_STDBY option byte */
1030 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);
1031 optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
1032 }
1033
1034 if((UserType & OB_USER_WWDG_SW) != 0U)
1035 {
1036 /* WWDG_SW option byte should be modified */
1037 assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));
1038
1039 /* Set value and mask for WWDG_SW option byte */
1040 optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);
1041 optr_reg_mask |= FLASH_OPTR_WWDG_SW;
1042 }
1043
1044 if((UserType & OB_USER_SWAP_BANK) != 0U)
1045 {
1046 /* SWAP_BANK option byte should be modified */
1047 assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTR_SWAP_BANK));
1048
1049 /* Set value and mask for SWAP_BANK option byte */
1050 optr_reg_val |= (UserConfig & FLASH_OPTR_SWAP_BANK);
1051 optr_reg_mask |= FLASH_OPTR_SWAP_BANK;
1052 }
1053
1054 if((UserType & OB_USER_DUALBANK) != 0U)
1055 {
1056 /* DUALBANK option byte should be modified */
1057 assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DB256K));
1058
1059 /* Set value and mask for DB256K option byte */
1060 optr_reg_val |= (UserConfig & FLASH_OPTR_DB256K);
1061 optr_reg_mask |= FLASH_OPTR_DB256K;
1062 }
1063
1064 if((UserType & OB_USER_SRAM2_PE) != 0U)
1065 {
1066 /* SRAM2_PAR option byte should be modified */
1067 assert_param(IS_OB_USER_SRAM2_PARITY(UserConfig & FLASH_OPTR_SRAM2_PE));
1068
1069 /* Set value and mask for SRAM2_PAR option byte */
1070 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_PE);
1071 optr_reg_mask |= FLASH_OPTR_SRAM2_PE;
1072 }
1073
1074 if((UserType & OB_USER_SRAM2_RST) != 0U)
1075 {
1076 /* SRAM2_RST option byte should be modified */
1077 assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST));
1078
1079 /* Set value and mask for SRAM2_RST option byte */
1080 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST);
1081 optr_reg_mask |= FLASH_OPTR_SRAM2_RST;
1082 }
1083
1084 if((UserType & OB_USER_nSWBOOT0) != 0U)
1085 {
1086 /* nSWBOOT0 option byte should be modified */
1087 assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0));
1088
1089 /* Set value and mask for nSWBOOT0 option byte */
1090 optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0);
1091 optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
1092 }
1093
1094 if((UserType & OB_USER_nBOOT0) != 0U)
1095 {
1096 /* nBOOT0 option byte should be modified */
1097 assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0));
1098
1099 /* Set value and mask for nBOOT0 option byte */
1100 optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0);
1101 optr_reg_mask |= FLASH_OPTR_nBOOT0;
1102 }
1103
1104 if((UserType & OB_USER_PA15_PUPEN) != 0U)
1105 {
1106 /* nBOOT0 option byte should be modified */
1107 assert_param(IS_OB_USER_PA15_PUPEN(UserConfig & FLASH_OPTR_PA15_PUPEN));
1108
1109 /* Set value and mask for nBOOT0 option byte */
1110 optr_reg_val |= (UserConfig & FLASH_OPTR_PA15_PUPEN);
1111 optr_reg_mask |= FLASH_OPTR_PA15_PUPEN;
1112 }
1113
1114 if((UserType & OB_USER_TZEN) != 0U)
1115 {
1116 /* TZEN option byte should be modified */
1117 assert_param(IS_OB_USER_TZEN(UserConfig & FLASH_OPTR_TZEN));
1118
1119 /* Set value and mask for TZEN option byte */
1120 optr_reg_val |= (UserConfig & FLASH_OPTR_TZEN);
1121 optr_reg_mask |= FLASH_OPTR_TZEN;
1122 }
1123
1124 /* Configure the option bytes register */
1125 MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);
1126 }
1127
1128 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1129 /**
1130 * @brief Configure the watermarked-based secure area.
1131 *
1132 * @param WMSecConfig specifies the area to be configured.
1133 * This parameter can be a combination of the following values:
1134 * @arg OB_WMSEC_AREA1 or @arg OB_WMSEC_AREA2: Select Flash Secure Area 1 or Area 2
1135 * @arg OB_WMSEC_SECURE_AREA_CONFIG: configure Flash Secure Area
1136 * @arg OB_WMSEC_HDP_AREA_CONFIG: configure Flash secure hide Area
1137 * @arg OB_WMSEC_HDP_AREA_ENABLE: enable secure hide Area in Secure Area
1138 * @arg OB_WMSEC_HDP_AREA_DISABLE: disable secure hide Area in Secure Area
1139 *
1140 * @param WMSecStartPage specifies the start page of the secure area
1141 * This parameter can be page number between 0 and (max number of pages in the bank - 1)
1142 *
1143 * @param WMSecEndPage specifies the end page of the secure area
1144 * This parameter can be page number between WMSecStartPage and (max number of pages in the bank - 1)
1145 *
1146 * @param WMHDPEndPage specifies the end page of the secure hide area
1147 * This parameter can be page number between WMSecStartPage and WMPCROPStartPage
1148 *
1149 * @retval None
1150 */
FLASH_OB_WMSECConfig(uint32_t WMSecConfig,uint32_t WMSecStartPage,uint32_t WMSecEndPage,uint32_t WMHDPEndPage)1151 static void FLASH_OB_WMSECConfig(uint32_t WMSecConfig, uint32_t WMSecStartPage, uint32_t WMSecEndPage, uint32_t WMHDPEndPage)
1152 {
1153 uint32_t tmp_secwm1 = 0U, tmp_secwm2 = 0U;
1154
1155 /* Check the parameters */
1156 assert_param(IS_OB_WMSEC_CONFIG(WMSecConfig));
1157 assert_param(IS_OB_WMSEC_AREA_EXCLUSIVE(WMSecConfig & 0x3U));
1158 assert_param(IS_FLASH_PAGE(WMSecStartPage));
1159 assert_param(IS_FLASH_PAGE(WMSecEndPage));
1160 assert_param(IS_FLASH_PAGE(WMHDPEndPage));
1161
1162 /* Read SECWM registers */
1163 if ((WMSecConfig & OB_WMSEC_AREA1) != 0U)
1164 {
1165 tmp_secwm1 = FLASH->SECWM1R1;
1166 tmp_secwm2 = FLASH->SECWM1R2;
1167 }
1168 else if ((WMSecConfig & OB_WMSEC_AREA2) != 0U)
1169 {
1170 tmp_secwm1 = FLASH->SECWM2R1;
1171 tmp_secwm2 = FLASH->SECWM2R2;
1172 }
1173 else
1174 {
1175 /* Nothing to do */
1176 }
1177
1178 /* Configure Secure Area */
1179 if ((WMSecConfig & OB_WMSEC_SECURE_AREA_CONFIG) != 0U)
1180 {
1181 MODIFY_REG(tmp_secwm1, (FLASH_SECWM1R1_SECWM1_PSTRT | FLASH_SECWM1R1_SECWM1_PEND),
1182 ((WMSecEndPage << FLASH_SECWM1R1_SECWM1_PEND_Pos) | WMSecStartPage));
1183 }
1184
1185 /* Configure Secure Hide Area */
1186 if ((WMSecConfig & OB_WMSEC_HDP_AREA_CONFIG) != 0U)
1187 {
1188 tmp_secwm2 &= (~(FLASH_SECWM1R2_HDP1_PEND));
1189 tmp_secwm2 |= (WMHDPEndPage << FLASH_SECWM1R2_HDP1_PEND_Pos);
1190 }
1191
1192 /* Enable Secure Hide Area */
1193 if ((WMSecConfig & OB_WMSEC_HDP_AREA_ENABLE) != 0U)
1194 {
1195 tmp_secwm2 |= FLASH_SECWM1R2_HDP1EN;
1196 }
1197
1198 /* Disable Secure Hide Area */
1199 if ((WMSecConfig & OB_WMSEC_HDP_AREA_DISABLE) != 0U)
1200 {
1201 tmp_secwm2 &= (~FLASH_SECWM1R2_HDP1EN);
1202 }
1203
1204 /* Write SECWM registers */
1205 if ((WMSecConfig & OB_WMSEC_AREA1) != 0U)
1206 {
1207 FLASH->SECWM1R1 = tmp_secwm1;
1208 FLASH->SECWM1R2 = tmp_secwm2;
1209 }
1210 else if ((WMSecConfig & OB_WMSEC_AREA2) != 0U)
1211 {
1212 FLASH->SECWM2R1 = tmp_secwm1;
1213 FLASH->SECWM2R2 = tmp_secwm2;
1214 }
1215 else
1216 {
1217 /* Nothing to do */
1218 }
1219 }
1220
1221 /**
1222 * @brief Configure the boot lock.
1223 *
1224 * @param BootLockConfig specifies the activation of the BOOT_LOCK.
1225 * This parameter can be one of the following values:
1226 * @arg OB_BOOT_LOCK_DISABLE: Boot Lock mode deactivated
1227 * @arg OB_BOOT_LOCK_ENABLE: Boot Lock mode activated
1228 *
1229 * @retval None
1230 */
FLASH_OB_BootLockConfig(uint32_t BootLockConfig)1231 static void FLASH_OB_BootLockConfig(uint32_t BootLockConfig)
1232 {
1233 /* Check the parameters */
1234 assert_param(IS_OB_BOOT_LOCK(BootLockConfig));
1235
1236 /* Configure the option bytes register */
1237 MODIFY_REG(FLASH->SECBOOTADD0R, FLASH_SECBOOTADD0R_BOOT_LOCK, BootLockConfig);
1238 }
1239 #endif
1240
1241 /**
1242 * @brief Configure the boot address.
1243 *
1244 * @param BootAddrConfig specifies the area to be configured.
1245 * This parameter can be one of the following values:
1246 * @arg OB_BOOTADDR_NS0: Non-secure boot address 0
1247 * @arg OB_BOOTADDR_NS1: Non-secure boot address 1
1248 * @arg OB_BOOTADDR_SEC0: Secure boot address 0
1249 *
1250 * @param BootAddr: specifies the address used for the boot
1251 * This parameter can be page number between 0 and 0xFFFFFF00
1252 *
1253 * @retval None
1254 */
FLASH_OB_BootAddrConfig(uint32_t BootAddrConfig,uint32_t BootAddr)1255 static void FLASH_OB_BootAddrConfig(uint32_t BootAddrConfig, uint32_t BootAddr)
1256 {
1257 /* Check the parameters */
1258 assert_param(IS_OB_BOOTADDR_CONFIG(BootAddrConfig));
1259
1260 if (BootAddrConfig == OB_BOOTADDR_NS0)
1261 {
1262 MODIFY_REG(FLASH->NSBOOTADD0R, FLASH_NSBOOTADD0R_NSBOOTADD0, BootAddr);
1263 }
1264 else if (BootAddrConfig == OB_BOOTADDR_NS1)
1265 {
1266 MODIFY_REG(FLASH->NSBOOTADD1R, FLASH_NSBOOTADD1R_NSBOOTADD1, BootAddr);
1267 }
1268 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1269 else if (BootAddrConfig == OB_BOOTADDR_SEC0)
1270 {
1271 MODIFY_REG(FLASH->SECBOOTADD0R, FLASH_SECBOOTADD0R_SECBOOTADD0, BootAddr);
1272 }
1273 #endif
1274 else
1275 {
1276 /* Empty statement (to be compliant MISRA 15.7) */
1277 }
1278 }
1279
1280 /**
1281 * @brief Return the FLASH Write Protection Option Bytes value.
1282 *
1283 * @param[in] WRPArea specifies the area to be returned.
1284 * This parameter can be one of the following values:
1285 * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
1286 * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
1287 * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A
1288 * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B
1289 *
1290 * @param[out] WRPStartOffset specifies the address where to copied the start page
1291 * of the write protected area
1292 *
1293 * @param[out] WRPEndOffset specifies the address where to copied the end page of
1294 * the write protected area
1295 *
1296 * @retval None
1297 */
FLASH_OB_GetWRP(uint32_t WRPArea,uint32_t * WRPStartOffset,uint32_t * WRPEndOffset)1298 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRPEndOffset)
1299 {
1300 /* Get the configuration of the write protected area */
1301 if(WRPArea == OB_WRPAREA_BANK1_AREAA)
1302 {
1303 *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_PSTRT);
1304 *WRPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_PEND) >> FLASH_WRP1AR_WRP1A_PEND_Pos);
1305 }
1306 else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
1307 {
1308 *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_PSTRT);
1309 *WRPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_PEND) >> FLASH_WRP1BR_WRP1B_PEND_Pos);
1310 }
1311 else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
1312 {
1313 *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_PSTRT);
1314 *WRPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_PEND) >> FLASH_WRP2AR_WRP2A_PEND_Pos);
1315 }
1316 else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
1317 {
1318 *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_PSTRT);
1319 *WRPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_PEND) >> FLASH_WRP2BR_WRP2B_PEND_Pos);
1320 }
1321 else
1322 {
1323 /* Empty statement (to be compliant MISRA 15.7) */
1324 }
1325 }
1326
1327 /**
1328 * @brief Return the FLASH Read Protection level.
1329 * @retval FLASH ReadOut Protection Status:
1330 * This return value can be one of the following values:
1331 * @arg OB_RDP_LEVEL_0: No protection
1332 * @arg OB_RDP_LEVEL_0_5: No debug access to secure area
1333 * @arg OB_RDP_LEVEL_1: Read protection of the memory
1334 * @arg OB_RDP_LEVEL_2: Full chip protection
1335 */
FLASH_OB_GetRDP(void)1336 static uint32_t FLASH_OB_GetRDP(void)
1337 {
1338 uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP);
1339
1340 if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_0_5) && (rdp_level != OB_RDP_LEVEL_2))
1341 {
1342 return (OB_RDP_LEVEL_1);
1343 }
1344 else
1345 {
1346 return (rdp_level);
1347 }
1348 }
1349
1350 /**
1351 * @brief Return the FLASH User Option Byte value.
1352 * @retval The FLASH User Option Bytes values,
1353 * it can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
1354 * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
1355 * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
1356 * @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
1357 * @ref FLASH_OB_USER_WWDG_SW, @ref OB_USER_SWAP_BANK,
1358 * @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_DBANK,
1359 * @ref FLASH_OB_USER_SRAM2_PAR, @ref FLASH_OB_USER_SRAM2_RST,
1360 * @ref OB_USER_nSWBOOT0, @ref OB_USER_nBOOT0, @ref FLASH_OB_USER_PA15_PUPEN
1361 * and @ref OB_USER_TZEN
1362 */
FLASH_OB_GetUser(void)1363 static uint32_t FLASH_OB_GetUser(void)
1364 {
1365 uint32_t user_config = READ_REG(FLASH->OPTR);
1366 CLEAR_BIT(user_config, FLASH_OPTR_RDP);
1367
1368 return user_config;
1369 }
1370
1371 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1372 /**
1373 * @brief Return the watermarked-based secure area.
1374 *
1375 * @param WMSecConfig [in/out] specifies the area to be returned.
1376 * This parameter can be one of the following values:
1377 * @arg OB_WMSEC_AREA1: Flash Secure Area 1
1378 * @arg OB_WMSEC_AREA2: Flash Secure Area 2
1379 * When return from the function, this parameter will have a combination of the following values:
1380 * @arg OB_WMSEC_AREA1 or @arg OB_WMSEC_AREA2: selected Flash Secure Area 1 or Area 2
1381 * @arg OB_WMSEC_HDP_AREA_ENABLE: Secure Hide Area in Secure Area enabled
1382 * @arg OB_WMSEC_HDP_AREA_DISABLE: Secure Hide Area in Secure Area disabled
1383 *
1384 * @param WMSecStartPage [out] specifies the address where to copied the start page of the secure area
1385 *
1386 * @param WMSecEndPage [out] specifies the address where to copied the end page of the secure area
1387 *
1388 * @param WMHDPEndPage [out] specifies the address where to copied the end page of the secure hide area
1389 *
1390 * @retval None
1391 */
FLASH_OB_GetWMSEC(uint32_t * WMSecConfig,uint32_t * WMSecStartPage,uint32_t * WMSecEndPage,uint32_t * WMHDPEndPage)1392 static void FLASH_OB_GetWMSEC(uint32_t * WMSecConfig, uint32_t * WMSecStartPage, uint32_t * WMSecEndPage, uint32_t * WMHDPEndPage)
1393 {
1394 uint32_t tmp_secwm1 = 0U, tmp_secwm2 = 0U;
1395
1396 /* Check the parameters */
1397 assert_param(IS_OB_WMSEC_CONFIG(*WMSecConfig));
1398 assert_param(IS_FLASH_BANK_EXCLUSIVE((*WMSecConfig) & 0x3U));
1399
1400 /* Read SECWM registers */
1401 if (((*WMSecConfig) & OB_WMSEC_AREA1) != 0U)
1402 {
1403 tmp_secwm1 = FLASH->SECWM1R1;
1404 tmp_secwm2 = FLASH->SECWM1R2;
1405 }
1406 else if (((*WMSecConfig) & OB_WMSEC_AREA2) != 0U)
1407 {
1408 tmp_secwm1 = FLASH->SECWM2R1;
1409 tmp_secwm2 = FLASH->SECWM2R2;
1410 }
1411 else
1412 {
1413 /* Nothing to do */
1414 }
1415
1416 /* Configuration of secure area */
1417 *WMSecStartPage = (tmp_secwm1 & FLASH_SECWM1R1_SECWM1_PSTRT);
1418 *WMSecEndPage = ((tmp_secwm1 & FLASH_SECWM1R1_SECWM1_PEND) >> FLASH_SECWM1R1_SECWM1_PEND_Pos);
1419
1420 /* Configuration of secure hide area */
1421 *WMHDPEndPage = ((tmp_secwm2 & FLASH_SECWM1R2_HDP1_PEND) >> FLASH_SECWM1R2_HDP1_PEND_Pos);
1422
1423 if ((tmp_secwm2 & FLASH_SECWM1R2_HDP1EN) == 0U)
1424 {
1425 *WMSecConfig = ((*WMSecConfig) | OB_WMSEC_HDP_AREA_DISABLE);
1426 }
1427 else
1428 {
1429 *WMSecConfig = ((*WMSecConfig) | OB_WMSEC_HDP_AREA_ENABLE);
1430 }
1431 }
1432
1433 /**
1434 * @brief Return the boot lock configuration.
1435 *
1436 * @retval Value of Boot Lock configuration.
1437 * It can be one of the following values:
1438 * @arg OB_BOOT_LOCK_DISABLE: Boot Lock mode deactivated
1439 * @arg OB_BOOT_LOCK_ENABLE: Boot Lock mode activated
1440 */
FLASH_OB_GetBootLock(void)1441 static uint32_t FLASH_OB_GetBootLock(void)
1442 {
1443 return (FLASH->SECBOOTADD0R & FLASH_SECBOOTADD0R_BOOT_LOCK);
1444 }
1445 #endif
1446
1447 /**
1448 * @brief Return the boot address.
1449 *
1450 * @param[in] BootAddrConfig specifies the area to be returned.
1451 * This parameter can be one of the following values:
1452 * @arg OB_BOOTADDR_NS0: Non-secure boot address 0
1453 * @arg OB_BOOTADDR_NS1: Non-secure boot address 1
1454 * @arg OB_BOOTADDR_SEC0: Secure boot address 0
1455 *
1456 * @param[out] BootAddr specifies the boot address value
1457 *
1458 * @retval None
1459 */
FLASH_OB_GetBootAddr(uint32_t BootAddrConfig,uint32_t * BootAddr)1460 static void FLASH_OB_GetBootAddr(uint32_t BootAddrConfig, uint32_t * BootAddr)
1461 {
1462 if (BootAddrConfig == OB_BOOTADDR_NS0)
1463 {
1464 *BootAddr = (FLASH->NSBOOTADD0R & FLASH_NSBOOTADD0R_NSBOOTADD0);
1465 }
1466 else if (BootAddrConfig == OB_BOOTADDR_NS1)
1467 {
1468 *BootAddr = (FLASH->NSBOOTADD1R & FLASH_NSBOOTADD1R_NSBOOTADD1);
1469 }
1470 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1471 else if (BootAddrConfig == OB_BOOTADDR_SEC0)
1472 {
1473 *BootAddr = (FLASH->SECBOOTADD0R & FLASH_SECBOOTADD0R_SECBOOTADD0);
1474 }
1475 #endif
1476 else
1477 {
1478 /* Empty statement (to be compliant MISRA 15.7) */
1479 }
1480 }
1481
1482 /**
1483 * @}
1484 */
1485
1486 /**
1487 * @}
1488 */
1489
1490 #endif /* HAL_FLASH_MODULE_ENABLED */
1491
1492 /**
1493 * @}
1494 */
1495
1496 /**
1497 * @}
1498 */
1499
1500
