1 /**
2 ******************************************************************************
3 * @file stm32l5xx_hal_adc_ex.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Converter (ADC)
7 * peripheral:
8 * + Peripheral Control functions
9 * Other functions (generic functions) are available in file
10 * "stm32l5xx_hal_adc.c".
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2019 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 [..]
25 (@) Sections "ADC peripheral features" and "How to use this driver" are
26 available in file of generic functions "stm32l5xx_hal_adc.c".
27 [..]
28 @endverbatim
29 ******************************************************************************
30 */
31
32 /* Includes ------------------------------------------------------------------*/
33 #include "stm32l5xx_hal.h"
34
35 /** @addtogroup STM32L5xx_HAL_Driver
36 * @{
37 */
38
39 /** @defgroup ADCEx ADCEx
40 * @brief ADC Extended HAL module driver
41 * @{
42 */
43
44 #ifdef HAL_ADC_MODULE_ENABLED
45
46 /* Private typedef -----------------------------------------------------------*/
47 /* Private define ------------------------------------------------------------*/
48
49 /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
50 * @{
51 */
52
53 #define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
54 ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
55 ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can
56 be updated anytime once the ADC is enabled */
57
58 /* Fixed timeout value for ADC calibration. */
59 /* Values defined to be higher than worst cases: maximum ratio between ADC */
60 /* and CPU clock frequencies. */
61 /* Example of profile low frequency : ADC frequency at 31.25kHz (ADC clock */
62 /* source PLL SAI 8MHz, ADC clock prescaler 256), CPU frequency 80MHz. */
63 /* Calibration time max = 116 / fADC (refer to datasheet) */
64 /* = 445 440 CPU cycles */
65 #define ADC_CALIBRATION_TIMEOUT (445440UL) /*!< ADC calibration time-out value (unit: CPU cycles) */
66
67 /**
68 * @}
69 */
70
71 /* Private macro -------------------------------------------------------------*/
72 /* Private variables ---------------------------------------------------------*/
73 /* Private function prototypes -----------------------------------------------*/
74 /* Exported functions --------------------------------------------------------*/
75
76 /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
77 * @{
78 */
79
80 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
81 * @brief Extended IO operation functions
82 *
83 @verbatim
84 ===============================================================================
85 ##### IO operation functions #####
86 ===============================================================================
87 [..] This section provides functions allowing to:
88
89 (+) Perform the ADC self-calibration for single or differential ending.
90 (+) Get calibration factors for single or differential ending.
91 (+) Set calibration factors for single or differential ending.
92
93 (+) Start conversion of ADC group injected.
94 (+) Stop conversion of ADC group injected.
95 (+) Poll for conversion complete on ADC group injected.
96 (+) Get result of ADC group injected channel conversion.
97 (+) Start conversion of ADC group injected and enable interruptions.
98 (+) Stop conversion of ADC group injected and disable interruptions.
99
100 (+) When multimode feature is available, start multimode and enable DMA transfer.
101 (+) Stop multimode and disable ADC DMA transfer.
102 (+) Get result of multimode conversion.
103
104 @endverbatim
105 * @{
106 */
107
108 /**
109 * @brief Perform an ADC automatic self-calibration
110 * Calibration prerequisite: ADC must be disabled (execute this
111 * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
112 * @param hadc ADC handle
113 * @param SingleDiff Selection of single-ended or differential input
114 * This parameter can be one of the following values:
115 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
116 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
117 * @retval HAL status
118 */
HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef * hadc,uint32_t SingleDiff)119 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
120 {
121 HAL_StatusTypeDef tmp_hal_status;
122 __IO uint32_t wait_loop_index = 0UL;
123
124 /* Check the parameters */
125 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
126 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
127
128 /* Process locked */
129 __HAL_LOCK(hadc);
130
131 /* Calibration prerequisite: ADC must be disabled. */
132
133 /* Disable the ADC (if not already disabled) */
134 tmp_hal_status = ADC_Disable(hadc);
135
136 /* Check if ADC is effectively disabled */
137 if (tmp_hal_status == HAL_OK)
138 {
139 /* Set ADC state */
140 ADC_STATE_CLR_SET(hadc->State,
141 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
142 HAL_ADC_STATE_BUSY_INTERNAL);
143
144 /* Start ADC calibration in mode single-ended or differential */
145 LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
146
147 /* Wait for calibration completion */
148 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
149 {
150 wait_loop_index++;
151 if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
152 {
153 /* Update ADC state machine to error */
154 ADC_STATE_CLR_SET(hadc->State,
155 HAL_ADC_STATE_BUSY_INTERNAL,
156 HAL_ADC_STATE_ERROR_INTERNAL);
157
158 /* Process unlocked */
159 __HAL_UNLOCK(hadc);
160
161 return HAL_ERROR;
162 }
163 }
164
165 /* Set ADC state */
166 ADC_STATE_CLR_SET(hadc->State,
167 HAL_ADC_STATE_BUSY_INTERNAL,
168 HAL_ADC_STATE_READY);
169 }
170 else
171 {
172 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
173
174 /* Note: No need to update variable "tmp_hal_status" here: already set */
175 /* to state "HAL_ERROR" by function disabling the ADC. */
176 }
177
178 /* Process unlocked */
179 __HAL_UNLOCK(hadc);
180
181 /* Return function status */
182 return tmp_hal_status;
183 }
184
185 /**
186 * @brief Get the calibration factor.
187 * @param hadc ADC handle.
188 * @param SingleDiff This parameter can be only:
189 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
190 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
191 * @retval Calibration value.
192 */
HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef * hadc,uint32_t SingleDiff)193 uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
194 {
195 /* Check the parameters */
196 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
197 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
198
199 /* Return the selected ADC calibration value */
200 return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff);
201 }
202
203 /**
204 * @brief Set the calibration factor to overwrite automatic conversion result.
205 * ADC must be enabled and no conversion is ongoing.
206 * @param hadc ADC handle
207 * @param SingleDiff This parameter can be only:
208 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
209 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
210 * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
211 * @retval HAL state
212 */
HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef * hadc,uint32_t SingleDiff,uint32_t CalibrationFactor)213 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
214 uint32_t CalibrationFactor)
215 {
216 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
217 uint32_t tmp_adc_is_conversion_on_going_regular;
218 uint32_t tmp_adc_is_conversion_on_going_injected;
219
220 /* Check the parameters */
221 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
222 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
223 assert_param(IS_ADC_CALFACT(CalibrationFactor));
224
225 /* Process locked */
226 __HAL_LOCK(hadc);
227
228 /* Verification of hardware constraints before modifying the calibration */
229 /* factors register: ADC must be enabled, no conversion on going. */
230 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
231 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
232
233 if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
234 && (tmp_adc_is_conversion_on_going_regular == 0UL)
235 && (tmp_adc_is_conversion_on_going_injected == 0UL)
236 )
237 {
238 /* Set the selected ADC calibration value */
239 LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor);
240 }
241 else
242 {
243 /* Update ADC state machine */
244 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
245 /* Update ADC error code */
246 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
247
248 /* Update ADC state machine to error */
249 tmp_hal_status = HAL_ERROR;
250 }
251
252 /* Process unlocked */
253 __HAL_UNLOCK(hadc);
254
255 /* Return function status */
256 return tmp_hal_status;
257 }
258
259 /**
260 * @brief Enable ADC, start conversion of injected group.
261 * @note Interruptions enabled in this function: None.
262 * @note Case of multimode enabled when multimode feature is available:
263 * HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
264 * then for ADC master.
265 * For ADC slave, ADC is enabled only (conversion is not started).
266 * For ADC master, ADC is enabled and multimode conversion is started.
267 * @param hadc ADC handle.
268 * @retval HAL status
269 */
HAL_ADCEx_InjectedStart(ADC_HandleTypeDef * hadc)270 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
271 {
272 HAL_StatusTypeDef tmp_hal_status;
273 uint32_t tmp_config_injected_queue;
274 #if defined(ADC_MULTIMODE_SUPPORT)
275 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
276 #endif /* ADC_MULTIMODE_SUPPORT */
277
278 /* Check the parameters */
279 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
280
281 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
282 {
283 return HAL_BUSY;
284 }
285 else
286 {
287 /* In case of software trigger detection enabled, JQDIS must be set
288 (which can be done only if ADSTART and JADSTART are both cleared).
289 If JQDIS is not set at that point, returns an error
290 - since software trigger detection is disabled. User needs to
291 resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
292 - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
293 the queue is empty */
294 tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
295
296 if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
297 && (tmp_config_injected_queue == 0UL)
298 )
299 {
300 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
301 return HAL_ERROR;
302 }
303
304 /* Process locked */
305 __HAL_LOCK(hadc);
306
307 /* Enable the ADC peripheral */
308 tmp_hal_status = ADC_Enable(hadc);
309
310 /* Start conversion if ADC is effectively enabled */
311 if (tmp_hal_status == HAL_OK)
312 {
313 /* Check if a regular conversion is ongoing */
314 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
315 {
316 /* Reset ADC error code field related to injected conversions only */
317 CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
318 }
319 else
320 {
321 /* Set ADC error code to none */
322 ADC_CLEAR_ERRORCODE(hadc);
323 }
324
325 /* Set ADC state */
326 /* - Clear state bitfield related to injected group conversion results */
327 /* - Set state bitfield related to injected operation */
328 ADC_STATE_CLR_SET(hadc->State,
329 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
330 HAL_ADC_STATE_INJ_BUSY);
331
332 #if defined(ADC_MULTIMODE_SUPPORT)
333 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
334 - if ADC instance is master or if multimode feature is not available
335 - if multimode setting is disabled (ADC instance slave in independent mode) */
336 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
337 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
338 )
339 {
340 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
341 }
342 #endif /* ADC_MULTIMODE_SUPPORT */
343
344 /* Clear ADC group injected group conversion flag */
345 /* (To ensure of no unknown state from potential previous ADC operations) */
346 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
347
348 /* Process unlocked */
349 /* Unlock before starting ADC conversions: in case of potential */
350 /* interruption, to let the process to ADC IRQ Handler. */
351 __HAL_UNLOCK(hadc);
352
353 /* Enable conversion of injected group, if automatic injected conversion */
354 /* is disabled. */
355 /* If software start has been selected, conversion starts immediately. */
356 /* If external trigger has been selected, conversion will start at next */
357 /* trigger event. */
358 /* Case of multimode enabled (when multimode feature is available): */
359 /* if ADC is slave, */
360 /* - ADC is enabled only (conversion is not started), */
361 /* - if multimode only concerns regular conversion, ADC is enabled */
362 /* and conversion is started. */
363 /* If ADC is master or independent, */
364 /* - ADC is enabled and conversion is started. */
365 #if defined(ADC_MULTIMODE_SUPPORT)
366 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
367 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
368 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
369 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
370 )
371 {
372 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
373 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
374 {
375 LL_ADC_INJ_StartConversion(hadc->Instance);
376 }
377 }
378 else
379 {
380 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
381 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
382 }
383 #else
384 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
385 {
386 /* Start ADC group injected conversion */
387 LL_ADC_INJ_StartConversion(hadc->Instance);
388 }
389 #endif /* ADC_MULTIMODE_SUPPORT */
390
391 }
392 else
393 {
394 /* Process unlocked */
395 __HAL_UNLOCK(hadc);
396 }
397
398 /* Return function status */
399 return tmp_hal_status;
400 }
401 }
402
403 /**
404 * @brief Stop conversion of injected channels. Disable ADC peripheral if
405 * no regular conversion is on going.
406 * @note If ADC must be disabled and if conversion is on going on
407 * regular group, function HAL_ADC_Stop must be used to stop both
408 * injected and regular groups, and disable the ADC.
409 * @note If injected group mode auto-injection is enabled,
410 * function HAL_ADC_Stop must be used.
411 * @note In case of multimode enabled (when multimode feature is available),
412 * HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
413 * For ADC master, conversion is stopped and ADC is disabled.
414 * For ADC slave, ADC is disabled only (conversion stop of ADC master
415 * has already stopped conversion of ADC slave).
416 * @param hadc ADC handle.
417 * @retval HAL status
418 */
HAL_ADCEx_InjectedStop(ADC_HandleTypeDef * hadc)419 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
420 {
421 HAL_StatusTypeDef tmp_hal_status;
422
423 /* Check the parameters */
424 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
425
426 /* Process locked */
427 __HAL_LOCK(hadc);
428
429 /* 1. Stop potential conversion on going on injected group only. */
430 tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
431
432 /* Disable ADC peripheral if injected conversions are effectively stopped */
433 /* and if no conversion on regular group is on-going */
434 if (tmp_hal_status == HAL_OK)
435 {
436 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
437 {
438 /* 2. Disable the ADC peripheral */
439 tmp_hal_status = ADC_Disable(hadc);
440
441 /* Check if ADC is effectively disabled */
442 if (tmp_hal_status == HAL_OK)
443 {
444 /* Set ADC state */
445 ADC_STATE_CLR_SET(hadc->State,
446 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
447 HAL_ADC_STATE_READY);
448 }
449 }
450 /* Conversion on injected group is stopped, but ADC not disabled since */
451 /* conversion on regular group is still running. */
452 else
453 {
454 /* Set ADC state */
455 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
456 }
457 }
458
459 /* Process unlocked */
460 __HAL_UNLOCK(hadc);
461
462 /* Return function status */
463 return tmp_hal_status;
464 }
465
466 /**
467 * @brief Wait for injected group conversion to be completed.
468 * @param hadc ADC handle
469 * @param Timeout Timeout value in millisecond.
470 * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is
471 * checked and cleared depending on AUTDLY bit status.
472 * @retval HAL status
473 */
HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)474 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
475 {
476 uint32_t tickstart;
477 uint32_t tmp_flag_end;
478 uint32_t tmp_adc_inj_is_trigger_source_sw_start;
479 uint32_t tmp_adc_reg_is_trigger_source_sw_start;
480 uint32_t tmp_cfgr;
481 #if defined(ADC_MULTIMODE_SUPPORT)
482 const ADC_TypeDef *tmpADC_Master;
483 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
484 #endif /* ADC_MULTIMODE_SUPPORT */
485
486 /* Check the parameters */
487 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
488
489 /* If end of sequence selected */
490 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
491 {
492 tmp_flag_end = ADC_FLAG_JEOS;
493 }
494 else /* end of conversion selected */
495 {
496 tmp_flag_end = ADC_FLAG_JEOC;
497 }
498
499 /* Get timeout */
500 tickstart = HAL_GetTick();
501
502 /* Wait until End of Conversion or Sequence flag is raised */
503 while ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
504 {
505 /* Check if timeout is disabled (set to infinite wait) */
506 if (Timeout != HAL_MAX_DELAY)
507 {
508 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
509 {
510 /* New check to avoid false timeout detection in case of preemption */
511 if ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
512 {
513 /* Update ADC state machine to timeout */
514 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
515
516 /* Process unlocked */
517 __HAL_UNLOCK(hadc);
518
519 return HAL_TIMEOUT;
520 }
521 }
522 }
523 }
524
525 /* Retrieve ADC configuration */
526 tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
527 tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
528 /* Get relevant register CFGR in ADC instance of ADC master or slave */
529 /* in function of multimode state (for devices with multimode */
530 /* available). */
531 #if defined(ADC_MULTIMODE_SUPPORT)
532 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
533 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
534 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
535 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
536 )
537 {
538 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
539 }
540 else
541 {
542 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
543 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
544 }
545 #else
546 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
547 #endif /* ADC_MULTIMODE_SUPPORT */
548
549 /* Update ADC state machine */
550 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
551
552 /* Determine whether any further conversion upcoming on group injected */
553 /* by external trigger or by automatic injected conversion */
554 /* from group regular. */
555 if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
556 ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
557 ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
558 (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
559 {
560 /* Check whether end of sequence is reached */
561 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
562 {
563 /* Particular case if injected contexts queue is enabled: */
564 /* when the last context has been fully processed, JSQR is reset */
565 /* by the hardware. Even if no injected conversion is planned to come */
566 /* (queue empty, triggers are ignored), it can start again */
567 /* immediately after setting a new context (JADSTART is still set). */
568 /* Therefore, state of HAL ADC injected group is kept to busy. */
569 if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
570 {
571 /* Set ADC state */
572 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
573
574 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
575 {
576 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
577 }
578 }
579 }
580 }
581
582 /* Clear polled flag */
583 if (tmp_flag_end == ADC_FLAG_JEOS)
584 {
585 /* Clear end of sequence JEOS flag of injected group if low power feature */
586 /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */
587 /* For injected groups, no new conversion will start before JEOS is */
588 /* cleared. */
589 if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
590 {
591 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
592 }
593 }
594 else
595 {
596 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
597 }
598
599 /* Return API HAL status */
600 return HAL_OK;
601 }
602
603 /**
604 * @brief Enable ADC, start conversion of injected group with interruption.
605 * @note Interruptions enabled in this function according to initialization
606 * setting : JEOC (end of conversion) or JEOS (end of sequence)
607 * @note Case of multimode enabled (when multimode feature is enabled):
608 * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
609 * then for ADC master.
610 * For ADC slave, ADC is enabled only (conversion is not started).
611 * For ADC master, ADC is enabled and multimode conversion is started.
612 * @param hadc ADC handle.
613 * @retval HAL status.
614 */
HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef * hadc)615 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
616 {
617 HAL_StatusTypeDef tmp_hal_status;
618 uint32_t tmp_config_injected_queue;
619 #if defined(ADC_MULTIMODE_SUPPORT)
620 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
621 #endif /* ADC_MULTIMODE_SUPPORT */
622
623 /* Check the parameters */
624 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
625
626 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
627 {
628 return HAL_BUSY;
629 }
630 else
631 {
632 /* In case of software trigger detection enabled, JQDIS must be set
633 (which can be done only if ADSTART and JADSTART are both cleared).
634 If JQDIS is not set at that point, returns an error
635 - since software trigger detection is disabled. User needs to
636 resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
637 - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
638 the queue is empty */
639 tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
640
641 if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
642 && (tmp_config_injected_queue == 0UL)
643 )
644 {
645 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
646 return HAL_ERROR;
647 }
648
649 /* Process locked */
650 __HAL_LOCK(hadc);
651
652 /* Enable the ADC peripheral */
653 tmp_hal_status = ADC_Enable(hadc);
654
655 /* Start conversion if ADC is effectively enabled */
656 if (tmp_hal_status == HAL_OK)
657 {
658 /* Check if a regular conversion is ongoing */
659 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
660 {
661 /* Reset ADC error code field related to injected conversions only */
662 CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
663 }
664 else
665 {
666 /* Set ADC error code to none */
667 ADC_CLEAR_ERRORCODE(hadc);
668 }
669
670 /* Set ADC state */
671 /* - Clear state bitfield related to injected group conversion results */
672 /* - Set state bitfield related to injected operation */
673 ADC_STATE_CLR_SET(hadc->State,
674 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
675 HAL_ADC_STATE_INJ_BUSY);
676
677 #if defined(ADC_MULTIMODE_SUPPORT)
678 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
679 - if ADC instance is master or if multimode feature is not available
680 - if multimode setting is disabled (ADC instance slave in independent mode) */
681 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
682 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
683 )
684 {
685 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
686 }
687 #endif /* ADC_MULTIMODE_SUPPORT */
688
689 /* Clear ADC group injected group conversion flag */
690 /* (To ensure of no unknown state from potential previous ADC operations) */
691 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
692
693 /* Process unlocked */
694 /* Unlock before starting ADC conversions: in case of potential */
695 /* interruption, to let the process to ADC IRQ Handler. */
696 __HAL_UNLOCK(hadc);
697
698 /* Enable ADC Injected context queue overflow interrupt if this feature */
699 /* is enabled. */
700 if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL)
701 {
702 __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
703 }
704
705 /* Enable ADC end of conversion interrupt */
706 switch (hadc->Init.EOCSelection)
707 {
708 case ADC_EOC_SEQ_CONV:
709 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
710 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
711 break;
712 /* case ADC_EOC_SINGLE_CONV */
713 default:
714 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
715 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
716 break;
717 }
718
719 /* Enable conversion of injected group, if automatic injected conversion */
720 /* is disabled. */
721 /* If software start has been selected, conversion starts immediately. */
722 /* If external trigger has been selected, conversion will start at next */
723 /* trigger event. */
724 /* Case of multimode enabled (when multimode feature is available): */
725 /* if ADC is slave, */
726 /* - ADC is enabled only (conversion is not started), */
727 /* - if multimode only concerns regular conversion, ADC is enabled */
728 /* and conversion is started. */
729 /* If ADC is master or independent, */
730 /* - ADC is enabled and conversion is started. */
731 #if defined(ADC_MULTIMODE_SUPPORT)
732 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
733 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
734 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
735 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
736 )
737 {
738 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
739 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
740 {
741 LL_ADC_INJ_StartConversion(hadc->Instance);
742 }
743 }
744 else
745 {
746 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
747 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
748 }
749 #else
750 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
751 {
752 /* Start ADC group injected conversion */
753 LL_ADC_INJ_StartConversion(hadc->Instance);
754 }
755 #endif /* ADC_MULTIMODE_SUPPORT */
756
757 }
758 else
759 {
760 /* Process unlocked */
761 __HAL_UNLOCK(hadc);
762 }
763
764 /* Return function status */
765 return tmp_hal_status;
766 }
767 }
768
769 /**
770 * @brief Stop conversion of injected channels, disable interruption of
771 * end-of-conversion. Disable ADC peripheral if no regular conversion
772 * is on going.
773 * @note If ADC must be disabled and if conversion is on going on
774 * regular group, function HAL_ADC_Stop must be used to stop both
775 * injected and regular groups, and disable the ADC.
776 * @note If injected group mode auto-injection is enabled,
777 * function HAL_ADC_Stop must be used.
778 * @note Case of multimode enabled (when multimode feature is available):
779 * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
780 * then for ADC slave.
781 * For ADC master, conversion is stopped and ADC is disabled.
782 * For ADC slave, ADC is disabled only (conversion stop of ADC master
783 * has already stopped conversion of ADC slave).
784 * @note In case of auto-injection mode, HAL_ADC_Stop() must be used.
785 * @param hadc ADC handle
786 * @retval HAL status
787 */
HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef * hadc)788 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
789 {
790 HAL_StatusTypeDef tmp_hal_status;
791
792 /* Check the parameters */
793 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
794
795 /* Process locked */
796 __HAL_LOCK(hadc);
797
798 /* 1. Stop potential conversion on going on injected group only. */
799 tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
800
801 /* Disable ADC peripheral if injected conversions are effectively stopped */
802 /* and if no conversion on the other group (regular group) is intended to */
803 /* continue. */
804 if (tmp_hal_status == HAL_OK)
805 {
806 /* Disable ADC end of conversion interrupt for injected channels */
807 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
808
809 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
810 {
811 /* 2. Disable the ADC peripheral */
812 tmp_hal_status = ADC_Disable(hadc);
813
814 /* Check if ADC is effectively disabled */
815 if (tmp_hal_status == HAL_OK)
816 {
817 /* Set ADC state */
818 ADC_STATE_CLR_SET(hadc->State,
819 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
820 HAL_ADC_STATE_READY);
821 }
822 }
823 /* Conversion on injected group is stopped, but ADC not disabled since */
824 /* conversion on regular group is still running. */
825 else
826 {
827 /* Set ADC state */
828 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
829 }
830 }
831
832 /* Process unlocked */
833 __HAL_UNLOCK(hadc);
834
835 /* Return function status */
836 return tmp_hal_status;
837 }
838
839 #if defined(ADC_MULTIMODE_SUPPORT)
840 /**
841 * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA.
842 * @note Multimode must have been previously configured using
843 * HAL_ADCEx_MultiModeConfigChannel() function.
844 * Interruptions enabled in this function:
845 * overrun, DMA half transfer, DMA transfer complete.
846 * Each of these interruptions has its dedicated callback function.
847 * @note State field of Slave ADC handle is not updated in this configuration:
848 * user should not rely on it for information related to Slave regular
849 * conversions.
850 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
851 * @param pData Destination Buffer address.
852 * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
853 * @retval HAL status
854 */
HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)855 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
856 {
857 HAL_StatusTypeDef tmp_hal_status;
858 ADC_HandleTypeDef tmp_hadc_slave;
859 ADC_Common_TypeDef *tmpADC_Common;
860
861 /* Check the parameters */
862 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
863 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
864 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
865 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
866
867 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
868 {
869 return HAL_BUSY;
870 }
871 else
872 {
873 /* Process locked */
874 __HAL_LOCK(hadc);
875
876 /* Temporary handle minimum initialization */
877 __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
878 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
879
880 /* Set a temporary handle of the ADC slave associated to the ADC master */
881 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
882
883 if (tmp_hadc_slave.Instance == NULL)
884 {
885 /* Set ADC state */
886 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
887
888 /* Process unlocked */
889 __HAL_UNLOCK(hadc);
890
891 return HAL_ERROR;
892 }
893
894 /* Enable the ADC peripherals: master and slave (in case if not already */
895 /* enabled previously) */
896 tmp_hal_status = ADC_Enable(hadc);
897 if (tmp_hal_status == HAL_OK)
898 {
899 tmp_hal_status = ADC_Enable(&tmp_hadc_slave);
900 }
901
902 /* Start multimode conversion of ADCs pair */
903 if (tmp_hal_status == HAL_OK)
904 {
905 /* Set ADC state */
906 ADC_STATE_CLR_SET(hadc->State,
907 (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP),
908 HAL_ADC_STATE_REG_BUSY);
909
910 /* Set ADC error code to none */
911 ADC_CLEAR_ERRORCODE(hadc);
912
913 /* Set the DMA transfer complete callback */
914 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
915
916 /* Set the DMA half transfer complete callback */
917 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
918
919 /* Set the DMA error callback */
920 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
921
922 /* Pointer to the common control register */
923 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
924
925 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
926 /* start (in case of SW start): */
927
928 /* Clear regular group conversion flag and overrun flag */
929 /* (To ensure of no unknown state from potential previous ADC operations) */
930 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
931
932 /* Process unlocked */
933 /* Unlock before starting ADC conversions: in case of potential */
934 /* interruption, to let the process to ADC IRQ Handler. */
935 __HAL_UNLOCK(hadc);
936
937 /* Enable ADC overrun interrupt */
938 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
939
940 /* Start the DMA channel */
941 tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
942
943 /* Enable conversion of regular group. */
944 /* If software start has been selected, conversion starts immediately. */
945 /* If external trigger has been selected, conversion will start at next */
946 /* trigger event. */
947 /* Start ADC group regular conversion */
948 LL_ADC_REG_StartConversion(hadc->Instance);
949 }
950 else
951 {
952 /* Process unlocked */
953 __HAL_UNLOCK(hadc);
954 }
955
956 /* Return function status */
957 return tmp_hal_status;
958 }
959 }
960
961 /**
962 * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
963 * @note Multimode is kept enabled after this function. MultiMode DMA bits
964 * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
965 * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
966 * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
967 * resort to HAL_ADCEx_DisableMultiMode() API.
968 * @note In case of DMA configured in circular mode, function
969 * HAL_ADC_Stop_DMA() must be called after this function with handle of
970 * ADC slave, to properly disable the DMA channel.
971 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
972 * @retval HAL status
973 */
HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef * hadc)974 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
975 {
976 HAL_StatusTypeDef tmp_hal_status;
977 uint32_t tickstart;
978 ADC_HandleTypeDef tmp_hadc_slave;
979 uint32_t tmp_hadc_slave_conversion_on_going;
980 HAL_StatusTypeDef tmp_hadc_slave_disable_status;
981
982 /* Check the parameters */
983 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
984
985 /* Process locked */
986 __HAL_LOCK(hadc);
987
988 /* 1. Stop potential multimode conversion on going, on regular and injected groups */
989 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
990
991 /* Disable ADC peripheral if conversions are effectively stopped */
992 if (tmp_hal_status == HAL_OK)
993 {
994 /* Temporary handle minimum initialization */
995 __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
996 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
997
998 /* Set a temporary handle of the ADC slave associated to the ADC master */
999 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
1000
1001 if (tmp_hadc_slave.Instance == NULL)
1002 {
1003 /* Update ADC state machine to error */
1004 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1005
1006 /* Process unlocked */
1007 __HAL_UNLOCK(hadc);
1008
1009 return HAL_ERROR;
1010 }
1011
1012 /* Procedure to disable the ADC peripheral: wait for conversions */
1013 /* effectively stopped (ADC master and ADC slave), then disable ADC */
1014
1015 /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
1016 tickstart = HAL_GetTick();
1017
1018 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1019 while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1020 || (tmp_hadc_slave_conversion_on_going == 1UL)
1021 )
1022 {
1023 if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
1024 {
1025 /* New check to avoid false timeout detection in case of preemption */
1026 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1027 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1028 || (tmp_hadc_slave_conversion_on_going == 1UL)
1029 )
1030 {
1031 /* Update ADC state machine to error */
1032 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1033
1034 /* Process unlocked */
1035 __HAL_UNLOCK(hadc);
1036
1037 return HAL_ERROR;
1038 }
1039 }
1040
1041 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1042 }
1043
1044 /* Disable the DMA channel (in case of DMA in circular mode or stop */
1045 /* while DMA transfer is on going) */
1046 /* Note: DMA channel of ADC slave should be stopped after this function */
1047 /* with HAL_ADC_Stop_DMA() API. */
1048 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1049
1050 /* Check if DMA channel effectively disabled */
1051 if (tmp_hal_status == HAL_ERROR)
1052 {
1053 /* Update ADC state machine to error */
1054 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1055 }
1056
1057 /* Disable ADC overrun interrupt */
1058 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1059
1060 /* 2. Disable the ADC peripherals: master and slave */
1061 /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
1062 /* memory a potential failing status. */
1063 if (tmp_hal_status == HAL_OK)
1064 {
1065 tmp_hadc_slave_disable_status = ADC_Disable(&tmp_hadc_slave);
1066 if ((ADC_Disable(hadc) == HAL_OK) &&
1067 (tmp_hadc_slave_disable_status == HAL_OK))
1068 {
1069 tmp_hal_status = HAL_OK;
1070 }
1071 }
1072 else
1073 {
1074 /* In case of error, attempt to disable ADC master and slave without status assert */
1075 (void) ADC_Disable(hadc);
1076 (void) ADC_Disable(&tmp_hadc_slave);
1077 }
1078
1079 /* Set ADC state (ADC master) */
1080 ADC_STATE_CLR_SET(hadc->State,
1081 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1082 HAL_ADC_STATE_READY);
1083 }
1084
1085 /* Process unlocked */
1086 __HAL_UNLOCK(hadc);
1087
1088 /* Return function status */
1089 return tmp_hal_status;
1090 }
1091
1092 /**
1093 * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration.
1094 * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
1095 * @retval The converted data values.
1096 */
HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef * hadc)1097 uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc)
1098 {
1099 const ADC_Common_TypeDef *tmpADC_Common;
1100
1101 /* Check the parameters */
1102 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1103
1104 /* Prevent unused argument(s) compilation warning if no assert_param check */
1105 /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */
1106 UNUSED(hadc);
1107
1108 /* Pointer to the common control register */
1109 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
1110
1111 /* Return the multi mode conversion value */
1112 return tmpADC_Common->CDR;
1113 }
1114 #endif /* ADC_MULTIMODE_SUPPORT */
1115
1116 /**
1117 * @brief Get ADC injected group conversion result.
1118 * @note Reading register JDRx automatically clears ADC flag JEOC
1119 * (ADC group injected end of unitary conversion).
1120 * @note This function does not clear ADC flag JEOS
1121 * (ADC group injected end of sequence conversion)
1122 * Occurrence of flag JEOS rising:
1123 * - If sequencer is composed of 1 rank, flag JEOS is equivalent
1124 * to flag JEOC.
1125 * - If sequencer is composed of several ranks, during the scan
1126 * sequence flag JEOC only is raised, at the end of the scan sequence
1127 * both flags JEOC and EOS are raised.
1128 * Flag JEOS must not be cleared by this function because
1129 * it would not be compliant with low power features
1130 * (feature low power auto-wait, not available on all STM32 series).
1131 * To clear this flag, either use function:
1132 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
1133 * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
1134 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
1135 * @param hadc ADC handle
1136 * @param InjectedRank the converted ADC injected rank.
1137 * This parameter can be one of the following values:
1138 * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
1139 * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
1140 * @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
1141 * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
1142 * @retval ADC group injected conversion data
1143 */
HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef * hadc,uint32_t InjectedRank)1144 uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
1145 {
1146 uint32_t tmp_jdr;
1147
1148 /* Check the parameters */
1149 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1150 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
1151
1152 /* Get ADC converted value */
1153 switch (InjectedRank)
1154 {
1155 case ADC_INJECTED_RANK_4:
1156 tmp_jdr = hadc->Instance->JDR4;
1157 break;
1158 case ADC_INJECTED_RANK_3:
1159 tmp_jdr = hadc->Instance->JDR3;
1160 break;
1161 case ADC_INJECTED_RANK_2:
1162 tmp_jdr = hadc->Instance->JDR2;
1163 break;
1164 case ADC_INJECTED_RANK_1:
1165 default:
1166 tmp_jdr = hadc->Instance->JDR1;
1167 break;
1168 }
1169
1170 /* Return ADC converted value */
1171 return tmp_jdr;
1172 }
1173
1174 /**
1175 * @brief Injected conversion complete callback in non-blocking mode.
1176 * @param hadc ADC handle
1177 * @retval None
1178 */
HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef * hadc)1179 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
1180 {
1181 /* Prevent unused argument(s) compilation warning */
1182 UNUSED(hadc);
1183
1184 /* NOTE : This function should not be modified. When the callback is needed,
1185 function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
1186 */
1187 }
1188
1189 /**
1190 * @brief Injected context queue overflow callback.
1191 * @note This callback is called if injected context queue is enabled
1192 (parameter "QueueInjectedContext" in injected channel configuration)
1193 and if a new injected context is set when queue is full (maximum 2
1194 contexts).
1195 * @param hadc ADC handle
1196 * @retval None
1197 */
HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef * hadc)1198 __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
1199 {
1200 /* Prevent unused argument(s) compilation warning */
1201 UNUSED(hadc);
1202
1203 /* NOTE : This function should not be modified. When the callback is needed,
1204 function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
1205 */
1206 }
1207
1208 /**
1209 * @brief Analog watchdog 2 callback in non-blocking mode.
1210 * @param hadc ADC handle
1211 * @retval None
1212 */
HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef * hadc)1213 __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
1214 {
1215 /* Prevent unused argument(s) compilation warning */
1216 UNUSED(hadc);
1217
1218 /* NOTE : This function should not be modified. When the callback is needed,
1219 function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
1220 */
1221 }
1222
1223 /**
1224 * @brief Analog watchdog 3 callback in non-blocking mode.
1225 * @param hadc ADC handle
1226 * @retval None
1227 */
HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef * hadc)1228 __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
1229 {
1230 /* Prevent unused argument(s) compilation warning */
1231 UNUSED(hadc);
1232
1233 /* NOTE : This function should not be modified. When the callback is needed,
1234 function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
1235 */
1236 }
1237
1238
1239 /**
1240 * @brief End Of Sampling callback in non-blocking mode.
1241 * @param hadc ADC handle
1242 * @retval None
1243 */
HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef * hadc)1244 __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
1245 {
1246 /* Prevent unused argument(s) compilation warning */
1247 UNUSED(hadc);
1248
1249 /* NOTE : This function should not be modified. When the callback is needed,
1250 function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
1251 */
1252 }
1253
1254 /**
1255 * @brief Stop ADC conversion of regular group (and injected channels in
1256 * case of auto_injection mode), disable ADC peripheral if no
1257 * conversion is on going on injected group.
1258 * @param hadc ADC handle
1259 * @retval HAL status.
1260 */
HAL_ADCEx_RegularStop(ADC_HandleTypeDef * hadc)1261 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc)
1262 {
1263 HAL_StatusTypeDef tmp_hal_status;
1264
1265 /* Check the parameters */
1266 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1267
1268 /* Process locked */
1269 __HAL_LOCK(hadc);
1270
1271 /* 1. Stop potential regular conversion on going */
1272 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1273
1274 /* Disable ADC peripheral if regular conversions are effectively stopped
1275 and if no injected conversions are on-going */
1276 if (tmp_hal_status == HAL_OK)
1277 {
1278 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1279 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1280
1281 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1282 {
1283 /* 2. Disable the ADC peripheral */
1284 tmp_hal_status = ADC_Disable(hadc);
1285
1286 /* Check if ADC is effectively disabled */
1287 if (tmp_hal_status == HAL_OK)
1288 {
1289 /* Set ADC state */
1290 ADC_STATE_CLR_SET(hadc->State,
1291 HAL_ADC_STATE_INJ_BUSY,
1292 HAL_ADC_STATE_READY);
1293 }
1294 }
1295 /* Conversion on injected group is stopped, but ADC not disabled since */
1296 /* conversion on regular group is still running. */
1297 else
1298 {
1299 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1300 }
1301 }
1302
1303 /* Process unlocked */
1304 __HAL_UNLOCK(hadc);
1305
1306 /* Return function status */
1307 return tmp_hal_status;
1308 }
1309
1310
1311 /**
1312 * @brief Stop ADC conversion of ADC groups regular and injected,
1313 * disable interrution of end-of-conversion,
1314 * disable ADC peripheral if no conversion is on going
1315 * on injected group.
1316 * @param hadc ADC handle
1317 * @retval HAL status.
1318 */
HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef * hadc)1319 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
1320 {
1321 HAL_StatusTypeDef tmp_hal_status;
1322
1323 /* Check the parameters */
1324 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1325
1326 /* Process locked */
1327 __HAL_LOCK(hadc);
1328
1329 /* 1. Stop potential regular conversion on going */
1330 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1331
1332 /* Disable ADC peripheral if conversions are effectively stopped
1333 and if no injected conversion is on-going */
1334 if (tmp_hal_status == HAL_OK)
1335 {
1336 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1337 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1338
1339 /* Disable all regular-related interrupts */
1340 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1341
1342 /* 2. Disable ADC peripheral if no injected conversions are on-going */
1343 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1344 {
1345 tmp_hal_status = ADC_Disable(hadc);
1346 /* if no issue reported */
1347 if (tmp_hal_status == HAL_OK)
1348 {
1349 /* Set ADC state */
1350 ADC_STATE_CLR_SET(hadc->State,
1351 HAL_ADC_STATE_INJ_BUSY,
1352 HAL_ADC_STATE_READY);
1353 }
1354 }
1355 else
1356 {
1357 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1358 }
1359 }
1360
1361 /* Process unlocked */
1362 __HAL_UNLOCK(hadc);
1363
1364 /* Return function status */
1365 return tmp_hal_status;
1366 }
1367
1368 /**
1369 * @brief Stop ADC conversion of regular group (and injected group in
1370 * case of auto_injection mode), disable ADC DMA transfer, disable
1371 * ADC peripheral if no conversion is on going
1372 * on injected group.
1373 * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
1374 * For multimode (when multimode feature is available),
1375 * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
1376 * @param hadc ADC handle
1377 * @retval HAL status.
1378 */
HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef * hadc)1379 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
1380 {
1381 HAL_StatusTypeDef tmp_hal_status;
1382
1383 /* Check the parameters */
1384 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1385
1386 /* Process locked */
1387 __HAL_LOCK(hadc);
1388
1389 /* 1. Stop potential regular conversion on going */
1390 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1391
1392 /* Disable ADC peripheral if conversions are effectively stopped
1393 and if no injected conversion is on-going */
1394 if (tmp_hal_status == HAL_OK)
1395 {
1396 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1397 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1398
1399 /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
1400 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
1401
1402 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
1403 /* while DMA transfer is on going) */
1404 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1405
1406 /* Check if DMA channel effectively disabled */
1407 if (tmp_hal_status != HAL_OK)
1408 {
1409 /* Update ADC state machine to error */
1410 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1411 }
1412
1413 /* Disable ADC overrun interrupt */
1414 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1415
1416 /* 2. Disable the ADC peripheral */
1417 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
1418 /* to keep in memory a potential failing status. */
1419 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1420 {
1421 if (tmp_hal_status == HAL_OK)
1422 {
1423 tmp_hal_status = ADC_Disable(hadc);
1424 }
1425 else
1426 {
1427 (void)ADC_Disable(hadc);
1428 }
1429
1430 /* Check if ADC is effectively disabled */
1431 if (tmp_hal_status == HAL_OK)
1432 {
1433 /* Set ADC state */
1434 ADC_STATE_CLR_SET(hadc->State,
1435 HAL_ADC_STATE_INJ_BUSY,
1436 HAL_ADC_STATE_READY);
1437 }
1438 }
1439 else
1440 {
1441 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1442 }
1443 }
1444
1445 /* Process unlocked */
1446 __HAL_UNLOCK(hadc);
1447
1448 /* Return function status */
1449 return tmp_hal_status;
1450 }
1451
1452 #if defined(ADC_MULTIMODE_SUPPORT)
1453 /**
1454 * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected
1455 * conversion is on-going.
1456 * @note Multimode is kept enabled after this function. Multimode DMA bits
1457 * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
1458 * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
1459 * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
1460 * resort to HAL_ADCEx_DisableMultiMode() API.
1461 * @note In case of DMA configured in circular mode, function
1462 * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
1463 * ADC slave, to properly disable the DMA channel.
1464 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
1465 * @retval HAL status
1466 */
HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef * hadc)1467 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
1468 {
1469 HAL_StatusTypeDef tmp_hal_status;
1470 uint32_t tickstart;
1471 ADC_HandleTypeDef tmp_hadc_slave;
1472 uint32_t tmp_hadc_slave_conversion_on_going;
1473
1474 /* Check the parameters */
1475 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1476
1477 /* Process locked */
1478 __HAL_LOCK(hadc);
1479
1480
1481 /* 1. Stop potential multimode conversion on going, on regular groups */
1482 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1483
1484 /* Disable ADC peripheral if conversions are effectively stopped */
1485 if (tmp_hal_status == HAL_OK)
1486 {
1487 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1488 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1489
1490 /* Temporary handle minimum initialization */
1491 __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
1492 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
1493
1494 /* Set a temporary handle of the ADC slave associated to the ADC master */
1495 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
1496
1497 if (tmp_hadc_slave.Instance == NULL)
1498 {
1499 /* Update ADC state machine to error */
1500 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1501
1502 /* Process unlocked */
1503 __HAL_UNLOCK(hadc);
1504
1505 return HAL_ERROR;
1506 }
1507
1508 /* Procedure to disable the ADC peripheral: wait for conversions */
1509 /* effectively stopped (ADC master and ADC slave), then disable ADC */
1510
1511 /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
1512 tickstart = HAL_GetTick();
1513
1514 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1515 while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1516 || (tmp_hadc_slave_conversion_on_going == 1UL)
1517 )
1518 {
1519 if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
1520 {
1521 /* New check to avoid false timeout detection in case of preemption */
1522 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1523 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1524 || (tmp_hadc_slave_conversion_on_going == 1UL)
1525 )
1526 {
1527 /* Update ADC state machine to error */
1528 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1529
1530 /* Process unlocked */
1531 __HAL_UNLOCK(hadc);
1532
1533 return HAL_ERROR;
1534 }
1535 }
1536
1537 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1538 }
1539
1540 /* Disable the DMA channel (in case of DMA in circular mode or stop */
1541 /* while DMA transfer is on going) */
1542 /* Note: DMA channel of ADC slave should be stopped after this function */
1543 /* with HAL_ADCEx_RegularStop_DMA() API. */
1544 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1545
1546 /* Check if DMA channel effectively disabled */
1547 if (tmp_hal_status != HAL_OK)
1548 {
1549 /* Update ADC state machine to error */
1550 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1551 }
1552
1553 /* Disable ADC overrun interrupt */
1554 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1555
1556 /* 2. Disable the ADC peripherals: master and slave if no injected */
1557 /* conversion is on-going. */
1558 /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
1559 /* memory a potential failing status. */
1560 if (tmp_hal_status == HAL_OK)
1561 {
1562 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1563 {
1564 tmp_hal_status = ADC_Disable(hadc);
1565 if (tmp_hal_status == HAL_OK)
1566 {
1567 if (LL_ADC_INJ_IsConversionOngoing((&tmp_hadc_slave)->Instance) == 0UL)
1568 {
1569 tmp_hal_status = ADC_Disable(&tmp_hadc_slave);
1570 }
1571 }
1572 }
1573
1574 if (tmp_hal_status == HAL_OK)
1575 {
1576 /* Both Master and Slave ADC's could be disabled. Update Master State */
1577 /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
1578 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
1579 }
1580 else
1581 {
1582 /* injected (Master or Slave) conversions are still on-going,
1583 no Master State change */
1584 }
1585 }
1586 }
1587
1588 /* Process unlocked */
1589 __HAL_UNLOCK(hadc);
1590
1591 /* Return function status */
1592 return tmp_hal_status;
1593 }
1594 #endif /* ADC_MULTIMODE_SUPPORT */
1595
1596 /**
1597 * @}
1598 */
1599
1600 /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
1601 * @brief ADC Extended Peripheral Control functions
1602 *
1603 @verbatim
1604 ===============================================================================
1605 ##### Peripheral Control functions #####
1606 ===============================================================================
1607 [..] This section provides functions allowing to:
1608 (+) Configure channels on injected group
1609 (+) Configure multimode when multimode feature is available
1610 (+) Enable or Disable Injected Queue
1611 (+) Disable ADC voltage regulator
1612 (+) Enter ADC deep-power-down mode
1613
1614 @endverbatim
1615 * @{
1616 */
1617
1618 /**
1619 * @brief Configure a channel to be assigned to ADC group injected.
1620 * @note Possibility to update parameters on the fly:
1621 * This function initializes injected group, following calls to this
1622 * function can be used to reconfigure some parameters of structure
1623 * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
1624 * The setting of these parameters is conditioned to ADC state:
1625 * Refer to comments of structure "ADC_InjectionConfTypeDef".
1626 * @note In case of usage of internal measurement channels:
1627 * Vbat/VrefInt/TempSensor.
1628 * These internal paths can be disabled using function
1629 * HAL_ADC_DeInit().
1630 * @note Caution: For Injected Context Queue use, a context must be fully
1631 * defined before start of injected conversion. All channels are configured
1632 * consecutively for the same ADC instance. Therefore, the number of calls to
1633 * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
1634 * InjectedNbrOfConversion for each context.
1635 * - Example 1: If 1 context is intended to be used (or if there is no use of the
1636 * Injected Queue Context feature) and if the context contains 3 injected ranks
1637 * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
1638 * called once for each channel (i.e. 3 times) before starting a conversion.
1639 * This function must not be called to configure a 4th injected channel:
1640 * it would start a new context into context queue.
1641 * - Example 2: If 2 contexts are intended to be used and each of them contains
1642 * 3 injected ranks (InjectedNbrOfConversion = 3),
1643 * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
1644 * for each context (3 channels x 2 contexts = 6 calls). Conversion can
1645 * start once the 1st context is set, that is after the first three
1646 * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
1647 * @param hadc ADC handle
1648 * @param pConfigInjected Structure of ADC injected group and ADC channel for
1649 * injected group.
1650 * @retval HAL status
1651 */
HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef * hadc,const ADC_InjectionConfTypeDef * pConfigInjected)1652 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
1653 const ADC_InjectionConfTypeDef *pConfigInjected)
1654 {
1655 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1656 uint32_t tmp_offset_shifted;
1657 uint32_t tmp_config_internal_channel;
1658 uint32_t tmp_adc_is_conversion_on_going_regular;
1659 uint32_t tmp_adc_is_conversion_on_going_injected;
1660 __IO uint32_t wait_loop_index = 0;
1661
1662 uint32_t tmp_jsqr_context_queue_being_built = 0U;
1663
1664 /* Check the parameters */
1665 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1666 assert_param(IS_ADC_SAMPLE_TIME(pConfigInjected->InjectedSamplingTime));
1667 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfigInjected->InjectedSingleDiff));
1668 assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->AutoInjectedConv));
1669 assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->QueueInjectedContext));
1670 assert_param(IS_ADC_EXTTRIGINJEC_EDGE(pConfigInjected->ExternalTrigInjecConvEdge));
1671 assert_param(IS_ADC_EXTTRIGINJEC(hadc, pConfigInjected->ExternalTrigInjecConv));
1672 assert_param(IS_ADC_OFFSET_NUMBER(pConfigInjected->InjectedOffsetNumber));
1673 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset));
1674 assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjecOversamplingMode));
1675
1676 if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
1677 {
1678 assert_param(IS_ADC_INJECTED_RANK(pConfigInjected->InjectedRank));
1679 assert_param(IS_ADC_INJECTED_NB_CONV(pConfigInjected->InjectedNbrOfConversion));
1680 assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedDiscontinuousConvMode));
1681 }
1682
1683
1684 /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
1685 ignored (considered as reset) */
1686 assert_param(!((pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
1687 && (pConfigInjected->InjecOversamplingMode == ENABLE)));
1688
1689 /* JDISCEN and JAUTO bits can't be set at the same time */
1690 assert_param(!((pConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
1691 && (pConfigInjected->AutoInjectedConv == ENABLE)));
1692
1693 /* DISCEN and JAUTO bits can't be set at the same time */
1694 assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (pConfigInjected->AutoInjectedConv == ENABLE)));
1695
1696 /* Verification of channel number */
1697 if (pConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
1698 {
1699 assert_param(IS_ADC_CHANNEL(hadc, pConfigInjected->InjectedChannel));
1700 }
1701 else
1702 {
1703 assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfigInjected->InjectedChannel));
1704 }
1705
1706 /* Process locked */
1707 __HAL_LOCK(hadc);
1708
1709 /* Configuration of injected group sequencer: */
1710 /* Hardware constraint: Must fully define injected context register JSQR */
1711 /* before make it entering into injected sequencer queue. */
1712 /* */
1713 /* - if scan mode is disabled: */
1714 /* * Injected channels sequence length is set to 0x00: 1 channel */
1715 /* converted (channel on injected rank 1) */
1716 /* Parameter "InjectedNbrOfConversion" is discarded. */
1717 /* * Injected context register JSQR setting is simple: register is fully */
1718 /* defined on one call of this function (for injected rank 1) and can */
1719 /* be entered into queue directly. */
1720 /* - if scan mode is enabled: */
1721 /* * Injected channels sequence length is set to parameter */
1722 /* "InjectedNbrOfConversion". */
1723 /* * Injected context register JSQR setting more complex: register is */
1724 /* fully defined over successive calls of this function, for each */
1725 /* injected channel rank. It is entered into queue only when all */
1726 /* injected ranks have been set. */
1727 /* Note: Scan mode is not present by hardware on this device, but used */
1728 /* by software for alignment over all STM32 devices. */
1729
1730 if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
1731 (pConfigInjected->InjectedNbrOfConversion == 1U))
1732 {
1733 /* Configuration of context register JSQR: */
1734 /* - number of ranks in injected group sequencer: fixed to 1st rank */
1735 /* (scan mode disabled, only rank 1 used) */
1736 /* - external trigger to start conversion */
1737 /* - external trigger polarity */
1738 /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
1739
1740 if (pConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
1741 {
1742 /* Enable external trigger if trigger selection is different of */
1743 /* software start. */
1744 /* Note: This configuration keeps the hardware feature of parameter */
1745 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
1746 /* software start. */
1747 if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
1748 {
1749 tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
1750 | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
1751 | pConfigInjected->ExternalTrigInjecConvEdge
1752 );
1753 }
1754 else
1755 {
1756 tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
1757 }
1758
1759 MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_jsqr_context_queue_being_built);
1760 /* For debug and informative reasons, hadc handle saves JSQR setting */
1761 hadc->InjectionConfig.ContextQueue = tmp_jsqr_context_queue_being_built;
1762
1763 }
1764 }
1765 else
1766 {
1767 /* Case of scan mode enabled, several channels to set into injected group */
1768 /* sequencer. */
1769 /* */
1770 /* Procedure to define injected context register JSQR over successive */
1771 /* calls of this function, for each injected channel rank: */
1772 /* 1. Start new context and set parameters related to all injected */
1773 /* channels: injected sequence length and trigger. */
1774
1775 /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
1776 /* call of the context under setting */
1777 if (hadc->InjectionConfig.ChannelCount == 0U)
1778 {
1779 /* Initialize number of channels that will be configured on the context */
1780 /* being built */
1781 hadc->InjectionConfig.ChannelCount = pConfigInjected->InjectedNbrOfConversion;
1782 /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
1783 call, this context will be written in JSQR register at the last call.
1784 At this point, the context is merely reset */
1785 hadc->InjectionConfig.ContextQueue = 0x00000000U;
1786
1787 /* Configuration of context register JSQR: */
1788 /* - number of ranks in injected group sequencer */
1789 /* - external trigger to start conversion */
1790 /* - external trigger polarity */
1791
1792 /* Enable external trigger if trigger selection is different of */
1793 /* software start. */
1794 /* Note: This configuration keeps the hardware feature of parameter */
1795 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
1796 /* software start. */
1797 if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
1798 {
1799 tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U)
1800 | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
1801 | pConfigInjected->ExternalTrigInjecConvEdge
1802 );
1803 }
1804 else
1805 {
1806 tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U));
1807 }
1808
1809 }
1810
1811 /* 2. Continue setting of context under definition with parameter */
1812 /* related to each channel: channel rank sequence */
1813 /* Clear the old JSQx bits for the selected rank */
1814 tmp_jsqr_context_queue_being_built &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, pConfigInjected->InjectedRank);
1815
1816 /* Set the JSQx bits for the selected rank */
1817 tmp_jsqr_context_queue_being_built |= ADC_JSQR_RK(pConfigInjected->InjectedChannel, pConfigInjected->InjectedRank);
1818
1819 /* Decrease channel count */
1820 hadc->InjectionConfig.ChannelCount--;
1821
1822 /* 3. tmp_jsqr_context_queue_being_built is fully built for this HAL_ADCEx_InjectedConfigChannel()
1823 call, aggregate the setting to those already built during the previous
1824 HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */
1825 hadc->InjectionConfig.ContextQueue |= tmp_jsqr_context_queue_being_built;
1826
1827 /* 4. End of context setting: if this is the last channel set, then write context
1828 into register JSQR and make it enter into queue */
1829 if (hadc->InjectionConfig.ChannelCount == 0U)
1830 {
1831 MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
1832 }
1833 }
1834
1835 /* Parameters update conditioned to ADC state: */
1836 /* Parameters that can be updated when ADC is disabled or enabled without */
1837 /* conversion on going on injected group: */
1838 /* - Injected context queue: Queue disable (active context is kept) or */
1839 /* enable (context decremented, up to 2 contexts queued) */
1840 /* - Injected discontinuous mode: can be enabled only if auto-injected */
1841 /* mode is disabled. */
1842 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1843 {
1844 /* If auto-injected mode is disabled: no constraint */
1845 if (pConfigInjected->AutoInjectedConv == DISABLE)
1846 {
1847 MODIFY_REG(hadc->Instance->CFGR,
1848 ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
1849 ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext) |
1850 ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode));
1851 }
1852 /* If auto-injected mode is enabled: Injected discontinuous setting is */
1853 /* discarded. */
1854 else
1855 {
1856 MODIFY_REG(hadc->Instance->CFGR,
1857 ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
1858 ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext));
1859 }
1860
1861 }
1862
1863 /* Parameters update conditioned to ADC state: */
1864 /* Parameters that can be updated when ADC is disabled or enabled without */
1865 /* conversion on going on regular and injected groups: */
1866 /* - Automatic injected conversion: can be enabled if injected group */
1867 /* external triggers are disabled. */
1868 /* - Channel sampling time */
1869 /* - Channel offset */
1870 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
1871 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
1872
1873 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
1874 && (tmp_adc_is_conversion_on_going_injected == 0UL)
1875 )
1876 {
1877 /* If injected group external triggers are disabled (set to injected */
1878 /* software start): no constraint */
1879 if ((pConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
1880 || (pConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
1881 {
1882 if (pConfigInjected->AutoInjectedConv == ENABLE)
1883 {
1884 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
1885 }
1886 else
1887 {
1888 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
1889 }
1890 }
1891 /* If Automatic injected conversion was intended to be set and could not */
1892 /* due to injected group external triggers enabled, error is reported. */
1893 else
1894 {
1895 if (pConfigInjected->AutoInjectedConv == ENABLE)
1896 {
1897 /* Update ADC state machine to error */
1898 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1899
1900 tmp_hal_status = HAL_ERROR;
1901 }
1902 else
1903 {
1904 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
1905 }
1906 }
1907
1908 if (pConfigInjected->InjecOversamplingMode == ENABLE)
1909 {
1910 assert_param(IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio));
1911 assert_param(IS_ADC_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift));
1912
1913 /* JOVSE must be reset in case of triggered regular mode */
1914 assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)
1915 == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
1916
1917 /* Configuration of Injected Oversampler: */
1918 /* - Oversampling Ratio */
1919 /* - Right bit shift */
1920
1921 /* Enable OverSampling mode */
1922 MODIFY_REG(hadc->Instance->CFGR2,
1923 ADC_CFGR2_JOVSE |
1924 ADC_CFGR2_OVSR |
1925 ADC_CFGR2_OVSS,
1926 ADC_CFGR2_JOVSE |
1927 pConfigInjected->InjecOversampling.Ratio |
1928 pConfigInjected->InjecOversampling.RightBitShift
1929 );
1930 }
1931 else
1932 {
1933 /* Disable Regular OverSampling */
1934 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
1935 }
1936
1937 /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
1938 if (pConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5)
1939 {
1940 /* Set sampling time of the selected ADC channel */
1941 LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
1942
1943 /* Set ADC sampling time common configuration */
1944 LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
1945 }
1946 else
1947 {
1948 /* Set sampling time of the selected ADC channel */
1949 LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel,
1950 pConfigInjected->InjectedSamplingTime);
1951
1952 /* Set ADC sampling time common configuration */
1953 LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
1954 }
1955
1956 /* Configure the offset: offset enable/disable, channel, offset value */
1957
1958 /* Shift the offset with respect to the selected ADC resolution. */
1959 /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
1960 tmp_offset_shifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, pConfigInjected->InjectedOffset);
1961
1962 if (pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
1963 {
1964 /* Set ADC selected offset number */
1965 LL_ADC_SetOffset(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedChannel,
1966 tmp_offset_shifted);
1967
1968 }
1969 else
1970 {
1971 /* Scan each offset register to check if the selected channel is targeted. */
1972 /* If this is the case, the corresponding offset number is disabled. */
1973 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
1974 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
1975 {
1976 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
1977 }
1978 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
1979 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
1980 {
1981 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
1982 }
1983 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
1984 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
1985 {
1986 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
1987 }
1988 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
1989 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
1990 {
1991 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
1992 }
1993 }
1994
1995 }
1996
1997 /* Parameters update conditioned to ADC state: */
1998 /* Parameters that can be updated only when ADC is disabled: */
1999 /* - Single or differential mode */
2000 /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
2001 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2002 {
2003 /* Set mode single-ended or differential input of the selected ADC channel */
2004 LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfigInjected->InjectedChannel, pConfigInjected->InjectedSingleDiff);
2005
2006 /* Configuration of differential mode */
2007 /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
2008 if (pConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
2009 {
2010 /* Set sampling time of the selected ADC channel */
2011 LL_ADC_SetChannelSamplingTime(hadc->Instance,
2012 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
2013 (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
2014 (uint32_t)pConfigInjected->InjectedChannel)
2015 + 1UL) & 0x1FUL)),
2016 pConfigInjected->InjectedSamplingTime);
2017 }
2018
2019 /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
2020 /* internal measurement paths enable: If internal channel selected, */
2021 /* enable dedicated internal buffers and path. */
2022 /* Note: these internal measurement paths can be disabled using */
2023 /* HAL_ADC_DeInit(). */
2024
2025 if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfigInjected->InjectedChannel))
2026 {
2027 /* Configuration of common ADC parameters (continuation) */
2028 /* Software is allowed to change common parameters only when all ADCs */
2029 /* of the common group are disabled. */
2030 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
2031 {
2032 tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2033
2034 /* If the requested internal measurement path has already been enabled, */
2035 /* bypass the configuration processing. */
2036 if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
2037 ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
2038 {
2039 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
2040 {
2041 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2042 LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
2043
2044 /* Delay for temperature sensor stabilization time */
2045 /* Wait loop initialization and execution */
2046 /* Note: Variable divided by 2 to compensate partially */
2047 /* CPU processing cycles, scaling in us split to not */
2048 /* exceed 32 bits register capacity and handle low frequency. */
2049 wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
2050 while(wait_loop_index != 0UL)
2051 {
2052 wait_loop_index--;
2053 }
2054 }
2055 }
2056 else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
2057 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
2058 {
2059 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
2060 {
2061 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2062 LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
2063 }
2064 }
2065 else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
2066 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
2067 {
2068 if (ADC_VREFINT_INSTANCE(hadc))
2069 {
2070 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2071 LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
2072 }
2073 }
2074 else
2075 {
2076 /* nothing to do */
2077 }
2078 }
2079 /* If the requested internal measurement path has already been enabled */
2080 /* and other ADC of the common group are enabled, internal */
2081 /* measurement paths cannot be enabled. */
2082 else
2083 {
2084 /* Update ADC state machine to error */
2085 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2086
2087 tmp_hal_status = HAL_ERROR;
2088 }
2089 }
2090
2091 }
2092
2093 /* Process unlocked */
2094 __HAL_UNLOCK(hadc);
2095
2096 /* Return function status */
2097 return tmp_hal_status;
2098 }
2099
2100 #if defined(ADC_MULTIMODE_SUPPORT)
2101 /**
2102 * @brief Enable ADC multimode and configure multimode parameters
2103 * @note Possibility to update parameters on the fly:
2104 * This function initializes multimode parameters, following
2105 * calls to this function can be used to reconfigure some parameters
2106 * of structure "ADC_MultiModeTypeDef" on the fly, without resetting
2107 * the ADCs.
2108 * The setting of these parameters is conditioned to ADC state.
2109 * For parameters constraints, see comments of structure
2110 * "ADC_MultiModeTypeDef".
2111 * @note To move back configuration from multimode to single mode, ADC must
2112 * be reset (using function HAL_ADC_Init() ).
2113 * @param hadc Master ADC handle
2114 * @param pMultimode Structure of ADC multimode configuration
2115 * @retval HAL status
2116 */
HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef * hadc,const ADC_MultiModeTypeDef * pMultimode)2117 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode)
2118 {
2119 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2120 ADC_Common_TypeDef *tmpADC_Common;
2121 ADC_HandleTypeDef tmp_hadc_slave;
2122 uint32_t tmp_hadc_slave_conversion_on_going;
2123
2124 /* Check the parameters */
2125 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
2126 assert_param(IS_ADC_MULTIMODE(pMultimode->Mode));
2127 if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
2128 {
2129 assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode));
2130 assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
2131 }
2132
2133 /* Process locked */
2134 __HAL_LOCK(hadc);
2135
2136 /* Temporary handle minimum initialization */
2137 __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
2138 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
2139
2140 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
2141
2142 if (tmp_hadc_slave.Instance == NULL)
2143 {
2144 /* Update ADC state machine to error */
2145 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2146
2147 /* Process unlocked */
2148 __HAL_UNLOCK(hadc);
2149
2150 return HAL_ERROR;
2151 }
2152
2153 /* Parameters update conditioned to ADC state: */
2154 /* Parameters that can be updated when ADC is disabled or enabled without */
2155 /* conversion on going on regular group: */
2156 /* - Multimode DMA configuration */
2157 /* - Multimode DMA mode */
2158 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
2159 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2160 && (tmp_hadc_slave_conversion_on_going == 0UL))
2161 {
2162 /* Pointer to the common control register */
2163 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
2164
2165 /* If multimode is selected, configure all multimode parameters. */
2166 /* Otherwise, reset multimode parameters (can be used in case of */
2167 /* transition from multimode to independent mode). */
2168 if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
2169 {
2170 MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
2171 pMultimode->DMAAccessMode |
2172 ADC_CCR_MULTI_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
2173
2174 /* Parameters that can be updated only when ADC is disabled: */
2175 /* - Multimode mode selection */
2176 /* - Multimode delay */
2177 /* Note: Delay range depends on selected resolution: */
2178 /* from 1 to 12 clock cycles for 12 bits */
2179 /* from 1 to 10 clock cycles for 10 bits, */
2180 /* from 1 to 8 clock cycles for 8 bits */
2181 /* from 1 to 6 clock cycles for 6 bits */
2182 /* If a higher delay is selected, it will be clipped to maximum delay */
2183 /* range */
2184 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
2185 {
2186 MODIFY_REG(tmpADC_Common->CCR,
2187 ADC_CCR_DUAL |
2188 ADC_CCR_DELAY,
2189 pMultimode->Mode |
2190 pMultimode->TwoSamplingDelay
2191 );
2192 }
2193 }
2194 else /* ADC_MODE_INDEPENDENT */
2195 {
2196 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
2197
2198 /* Parameters that can be updated only when ADC is disabled: */
2199 /* - Multimode mode selection */
2200 /* - Multimode delay */
2201 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
2202 {
2203 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
2204 }
2205 }
2206 }
2207 /* If one of the ADC sharing the same common group is enabled, no update */
2208 /* could be done on neither of the multimode structure parameters. */
2209 else
2210 {
2211 /* Update ADC state machine to error */
2212 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2213
2214 tmp_hal_status = HAL_ERROR;
2215 }
2216
2217 /* Process unlocked */
2218 __HAL_UNLOCK(hadc);
2219
2220 /* Return function status */
2221 return tmp_hal_status;
2222 }
2223 #endif /* ADC_MULTIMODE_SUPPORT */
2224
2225 /**
2226 * @brief Enable Injected Queue
2227 * @note This function resets CFGR register JQDIS bit in order to enable the
2228 * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
2229 * are both equal to 0 to ensure that no regular nor injected
2230 * conversion is ongoing.
2231 * @param hadc ADC handle
2232 * @retval HAL status
2233 */
HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef * hadc)2234 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc)
2235 {
2236 HAL_StatusTypeDef tmp_hal_status;
2237 uint32_t tmp_adc_is_conversion_on_going_regular;
2238 uint32_t tmp_adc_is_conversion_on_going_injected;
2239
2240 /* Check the parameters */
2241 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2242
2243 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2244 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2245
2246 /* Parameter can be set only if no conversion is on-going */
2247 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
2248 && (tmp_adc_is_conversion_on_going_injected == 0UL)
2249 )
2250 {
2251 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
2252
2253 /* Update state, clear previous result related to injected queue overflow */
2254 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
2255
2256 tmp_hal_status = HAL_OK;
2257 }
2258 else
2259 {
2260 tmp_hal_status = HAL_ERROR;
2261 }
2262
2263 return tmp_hal_status;
2264 }
2265
2266 /**
2267 * @brief Disable Injected Queue
2268 * @note This function sets CFGR register JQDIS bit in order to disable the
2269 * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
2270 * are both equal to 0 to ensure that no regular nor injected
2271 * conversion is ongoing.
2272 * @param hadc ADC handle
2273 * @retval HAL status
2274 */
HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef * hadc)2275 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc)
2276 {
2277 HAL_StatusTypeDef tmp_hal_status;
2278 uint32_t tmp_adc_is_conversion_on_going_regular;
2279 uint32_t tmp_adc_is_conversion_on_going_injected;
2280
2281 /* Check the parameters */
2282 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2283
2284 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2285 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2286
2287 /* Parameter can be set only if no conversion is on-going */
2288 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
2289 && (tmp_adc_is_conversion_on_going_injected == 0UL)
2290 )
2291 {
2292 LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE);
2293 tmp_hal_status = HAL_OK;
2294 }
2295 else
2296 {
2297 tmp_hal_status = HAL_ERROR;
2298 }
2299
2300 return tmp_hal_status;
2301 }
2302
2303 /**
2304 * @brief Disable ADC voltage regulator.
2305 * @note Disabling voltage regulator allows to save power. This operation can
2306 * be carried out only when ADC is disabled.
2307 * @note To enable again the voltage regulator, the user is expected to
2308 * resort to HAL_ADC_Init() API.
2309 * @param hadc ADC handle
2310 * @retval HAL status
2311 */
HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef * hadc)2312 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
2313 {
2314 HAL_StatusTypeDef tmp_hal_status;
2315
2316 /* Check the parameters */
2317 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2318
2319 /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
2320 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2321 {
2322 LL_ADC_DisableInternalRegulator(hadc->Instance);
2323 tmp_hal_status = HAL_OK;
2324 }
2325 else
2326 {
2327 tmp_hal_status = HAL_ERROR;
2328 }
2329
2330 return tmp_hal_status;
2331 }
2332
2333 /**
2334 * @brief Enter ADC deep-power-down mode
2335 * @note This mode is achieved in setting DEEPPWD bit and allows to save power
2336 * in reducing leakage currents. It is particularly interesting before
2337 * entering stop modes.
2338 * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the
2339 * ADC voltage regulator. This means that this API encompasses
2340 * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
2341 * calibration is lost.
2342 * @note To exit the ADC deep-power-down mode, the user is expected to
2343 * resort to HAL_ADC_Init() API as well as to relaunch a calibration
2344 * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
2345 * saved calibration factor.
2346 * @param hadc ADC handle
2347 * @retval HAL status
2348 */
HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef * hadc)2349 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
2350 {
2351 HAL_StatusTypeDef tmp_hal_status;
2352
2353 /* Check the parameters */
2354 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2355
2356 /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
2357 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2358 {
2359 LL_ADC_EnableDeepPowerDown(hadc->Instance);
2360 tmp_hal_status = HAL_OK;
2361 }
2362 else
2363 {
2364 tmp_hal_status = HAL_ERROR;
2365 }
2366
2367 return tmp_hal_status;
2368 }
2369
2370 /**
2371 * @}
2372 */
2373
2374 /**
2375 * @}
2376 */
2377
2378 #endif /* HAL_ADC_MODULE_ENABLED */
2379 /**
2380 * @}
2381 */
2382
2383 /**
2384 * @}
2385 */
2386
