1 /**
2 ******************************************************************************
3 * @file stm32l5xx_ll_ucpd.h
4 * @author MCD Application Team
5 * @brief Header file of UCPD LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L5xx_LL_UCPD_H
21 #define STM32L5xx_LL_UCPD_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l5xx.h"
29
30 /** @addtogroup STM32L5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (UCPD1)
35
36 /** @defgroup UCPD_LL UCPD
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43
44 /* Exported types ------------------------------------------------------------*/
45 #if defined(USE_FULL_LL_DRIVER)
46 /** @defgroup UCPD_LL_ES_INIT UCPD Exported Init structure
47 * @{
48 */
49
50 /**
51 * @brief UCPD Init structures definition
52 */
53 typedef struct
54 {
55 uint32_t psc_ucpdclk; /*!< Specify the prescaler for the UCPD clock.
56 This parameter can be a value of @ref UCPD_LL_EC_PSC.
57 This feature can be modified afterwards using function @ref LL_UCPD_SetPSCClk().
58 */
59
60 uint32_t transwin; /*!< Specify the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV)
61 to achieve a legal tTransitionWindow (set according to peripheral clock to define
62 an interval of between 12 and 20 us).
63 This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
64 This value can be modified afterwards using function @ref LL_UCPD_SetTransWin().
65 */
66
67 uint32_t IfrGap; /*!< Specify the definition of the clock divider (minus 1) in order to generate
68 tInterframeGap from the peripheral clock.
69 This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
70 This feature can be modified afterwards using function @ref LL_UCPD_SetIfrGap().
71 */
72
73 uint32_t HbitClockDiv; /*!< Specify the number of cycles (minus one) at UCPD peripheral for a half bit clock
74 e.g. program 3 for a bit clock that takes 8 cycles of the peripheral clock :
75 "UCPD1_CLK".
76 This parameter can be a value between Min_Data=0x0 and Max_Data=0x3F.
77 This feature can be modified using function @ref LL_UCPD_SetHbitClockDiv().
78 */
79
80 } LL_UCPD_InitTypeDef;
81
82 /**
83 * @}
84 */
85 #endif /* USE_FULL_LL_DRIVER */
86
87 /* Exported constants --------------------------------------------------------*/
88 /** @defgroup UCPD_LL_Exported_Constants UCPD Exported Constants
89 * @{
90 */
91
92 /** @defgroup UCPD_LL_EC_GET_FLAG Get Flags Defines
93 * @brief Flags defines which can be used with LL_ucpd_ReadReg function
94 * @{
95 */
96 #define LL_UCPD_SR_TXIS UCPD_SR_TXIS /*!< Transmit interrupt status */
97 #define LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC /*!< Transmit message discarded interrupt */
98 #define LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT /*!< Transmit message sent interrupt */
99 #define LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT /*!< Transmit message abort interrupt */
100 #define LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC /*!< HRST discarded interrupt */
101 #define LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT /*!< HRST sent interrupt */
102 #define LL_UCPD_SR_TXUND UCPD_SR_TXUND /*!< Tx data underrun condition interrupt */
103 #define LL_UCPD_SR_RXNE UCPD_SR_RXNE /*!< Receive data register not empty interrupt */
104 #define LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET /*!< Rx ordered set (4 K-codes) detected interrupt */
105 #define LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET /*!< Rx Hard Reset detect interrupt */
106 #define LL_UCPD_SR_RXOVR UCPD_SR_RXOVR /*!< Rx data overflow interrupt */
107 #define LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND /*!< Rx message received */
108 #define LL_UCPD_SR_RXERR UCPD_SR_RXERR /*!< Rx error */
109 #define LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1 /*!< Type C voltage level event on CC1 */
110 #define LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2 /*!< Type C voltage level event on CC2 */
111 #define LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1 /*!<Status of DC level on CC1 pin */
112 #define LL_UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2 /*!<Status of DC level on CC2 pin */
113 #define LL_UCPD_SR_FRSEVT UCPD_SR_FRSEVT /*!<Fast Role Swap detection event */
114
115 /**
116 * @}
117 */
118
119 /** @defgroup UCPD_LL_EC_IT IT Defines
120 * @brief IT defines which can be used with LL_UCPD_ReadReg and LL_UCPD_WriteReg functions
121 * @{
122 */
123 #define LL_UCPD_IMR_TXIS UCPD_IMR_TXISIE /*!< Enable transmit interrupt status */
124 #define LL_UCPD_IMR_TXMSGDISC UCPD_IMR_TXMSGDISCIE /*!< Enable transmit message discarded interrupt */
125 #define LL_UCPD_IMR_TXMSGSENT UCPD_IMR_TXMSGSENTIE /*!< Enable transmit message sent interrupt */
126 #define LL_UCPD_IMR_TXMSGABT UCPD_IMR_TXMSGABTIE /*!< Enable transmit message abort interrupt */
127 #define LL_UCPD_IMR_HRSTDISC UCPD_IMR_HRSTDISCIE /*!< Enable HRST discarded interrupt */
128 #define LL_UCPD_IMR_HRSTSENT UCPD_IMR_HRSTSENTIE /*!< Enable HRST sent interrupt */
129 #define LL_UCPD_IMR_TXUND UCPD_IMR_TXUNDIE /*!< Enable tx data underrun condition interrupt */
130 #define LL_UCPD_IMR_RXNE UCPD_IMR_RXNEIE /*!< Enable Receive data register not empty interrupt */
131 #define LL_UCPD_IMR_RXORDDET UCPD_IMR_RXORDDETIE /*!< Enable Rx ordered set (4 K-codes) detected interrupt */
132 #define LL_UCPD_IMR_RXHRSTDET UCPD_IMR_RXHRSTDETIE /*!< Enable Rx Hard Reset detect interrupt */
133 #define LL_UCPD_IMR_RXOVR UCPD_IMR_RXOVRIE /*!< Enable Rx data overflow interrupt */
134 #define LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGENDIE /*!< Enable Rx message received */
135 #define LL_UCPD_IMR_TYPECEVT1 UCPD_IMR_TYPECEVT1IE /*!< Enable Type C voltage level event on CC1 */
136 #define LL_UCPD_IMR_TYPECEVT2 UCPD_IMR_TYPECEVT2IE /*!< Enable Type C voltage level event on CC2 */
137 #define LL_UCPD_IMR_FRSEVT UCPD_IMR_FRSEVTIE /*!< Enable fast Role Swap detection event */
138
139 /**
140 * @}
141 */
142
143 /** @defgroup UCPD_LL_EC_ORDERSET Ordered sets value
144 * @brief definition of the usual Ordered sets
145 * @{
146 */
147 #define LL_UCPD_SYNC1 0x18u /*!< K-code for Startsynch #1 */
148 #define LL_UCPD_SYNC2 0x11u /*!< K-code for Startsynch #2 */
149 #define LL_UCPD_SYNC3 0x06u /*!< K-code for Startsynch #3 */
150 #define LL_UCPD_RST1 0x07u /*!< K-code for Hard Reset #1 */
151 #define LL_UCPD_RST2 0x19u /*!< K-code for Hard Reset #2 */
152 #define LL_UCPD_EOP 0x0Du /*!< K-code for EOP End of Packet */
153
154 #define LL_UCPD_ORDERED_SET_SOP (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC2<<15u)) /*!< SOP Ordered set coding */
155 #define LL_UCPD_ORDERED_SET_SOP1 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP' Ordered set coding */
156 #define LL_UCPD_ORDERED_SET_SOP2 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC3<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP'' Ordered set coding */
157 #define LL_UCPD_ORDERED_SET_HARD_RESET (LL_UCPD_RST1 | (LL_UCPD_RST1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_RST2<<15u )) /*!< Hard Reset Ordered set coding */
158 #define LL_UCPD_ORDERED_SET_CABLE_RESET (LL_UCPD_RST1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< Cable Reset Ordered set coding */
159 #define LL_UCPD_ORDERED_SET_SOP1_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_RST2<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP' Debug Ordered set coding */
160 #define LL_UCPD_ORDERED_SET_SOP2_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC2<<15u)) /*!< SOP'' Debug Ordered set coding */
161 /**
162 * @}
163 */
164
165 /** @defgroup UCPD_LL_EC_MODE Role Mode
166 * @{
167 */
168 #define LL_UCPD_ROLE_SNK UCPD_CR_ANAMODE /*!< Mode SNK Rd */
169 #define LL_UCPD_ROLE_SRC 0x0U /*!< Mode SRC Rp */
170 /**
171 * @}
172 */
173
174 /** @defgroup UCPD_LL_EC_RESISTOR Resistor value
175 * @{
176 */
177 #define LL_UCPD_RESISTOR_DEFAULT UCPD_CR_ANASUBMODE_0 /*!< Rp default */
178 #define LL_UCPD_RESISTOR_1_5A UCPD_CR_ANASUBMODE_1 /*!< Rp 1.5 A */
179 #define LL_UCPD_RESISTOR_3_0A UCPD_CR_ANASUBMODE /*!< Rp 3.0 A */
180 #define LL_UCPD_RESISTOR_NONE 0x0U /*!< No resistor */
181 /**
182 * @}
183 */
184
185 /** @defgroup UCPD_LL_EC_CFG1_ORDERSET ordered set configuration
186 * @{
187 */
188 #define LL_UCPD_ORDERSET_SOP UCPD_CFG1_RXORDSETEN_0 /*!< SOP Ordered set detection enabled */
189 #define LL_UCPD_ORDERSET_SOP1 UCPD_CFG1_RXORDSETEN_1 /*!< SOP' Ordered set detection enabled */
190 #define LL_UCPD_ORDERSET_SOP2 UCPD_CFG1_RXORDSETEN_2 /*!< SOP'' Ordered set detection enabled */
191 #define LL_UCPD_ORDERSET_HARDRST UCPD_CFG1_RXORDSETEN_3 /*!< Hard Reset Ordered set detection enabled */
192 #define LL_UCPD_ORDERSET_CABLERST UCPD_CFG1_RXORDSETEN_4 /*!< Cable Reset Ordered set detection enabled */
193 #define LL_UCPD_ORDERSET_SOP1_DEBUG UCPD_CFG1_RXORDSETEN_5 /*!< SOP' Debug Ordered set detection enabled */
194 #define LL_UCPD_ORDERSET_SOP2_DEBUG UCPD_CFG1_RXORDSETEN_6 /*!< SOP'' Debug Ordered set detection enabled */
195 #define LL_UCPD_ORDERSET_SOP_EXT1 UCPD_CFG1_RXORDSETEN_7 /*!< SOP extension#1 Ordered set detection enabled */
196 #define LL_UCPD_ORDERSET_SOP_EXT2 UCPD_CFG1_RXORDSETEN_8 /*!< SOP extension#2 Ordered set detection enabled */
197 /**
198 * @}
199 */
200
201 /** @defgroup UCPD_LL_EC_CCxEVT CCx event
202 * @{
203 */
204 #define LL_UCPD_SNK_CC1_VOPEN 0x00u /*!< CC1 Sink Open state */
205 #define LL_UCPD_SNK_CC1_VRP UCPD_SR_TYPEC_VSTATE_CC1_0 /*!< CC1 Sink vRP default state */
206 #define LL_UCPD_SNK_CC1_VRP15A UCPD_SR_TYPEC_VSTATE_CC1_1 /*!< CC1 Sink vRP 1.5A state */
207 #define LL_UCPD_SNK_CC1_VRP30A (UCPD_SR_TYPEC_VSTATE_CC1_0 | UCPD_SR_TYPEC_VSTATE_CC1_1) /*!< CC1 Sink vRP 3.0A state */
208
209 #define LL_UCPD_SNK_CC2_VOPEN 0x00u /*!< CC2 Sink Open state */
210 #define LL_UCPD_SNK_CC2_VRP UCPD_SR_TYPEC_VSTATE_CC2_0 /*!< CC2 Sink vRP default state */
211 #define LL_UCPD_SNK_CC2_VRP15A UCPD_SR_TYPEC_VSTATE_CC2_1 /*!< CC2 Sink vRP 1.5A state */
212 #define LL_UCPD_SNK_CC2_VRP30A (UCPD_SR_TYPEC_VSTATE_CC2_0 | UCPD_SR_TYPEC_VSTATE_CC2_1) /*!< CC2 Sink vRP 3.0A state */
213
214 #define LL_UCPD_SRC_CC1_VRA 0x0U /*!< CC1 Source vRA state */
215 #define LL_UCPD_SRC_CC1_VRD UCPD_SR_TYPEC_VSTATE_CC1_0 /*!< CC1 Source vRD state */
216 #define LL_UCPD_SRC_CC1_OPEN UCPD_SR_TYPEC_VSTATE_CC1_1 /*!< CC1 Source Open state */
217
218 #define LL_UCPD_SRC_CC2_VRA 0x0U /*!< CC2 Source vRA state */
219 #define LL_UCPD_SRC_CC2_VRD UCPD_SR_TYPEC_VSTATE_CC2_0 /*!< CC2 Source vRD state */
220 #define LL_UCPD_SRC_CC2_OPEN UCPD_SR_TYPEC_VSTATE_CC2_1 /*!< CC2 Source Open state */
221 /**
222 * @}
223 */
224
225 /** @defgroup UCPD_LL_EC_PSC prescaler for UCPDCLK
226 * @{
227 */
228 #define LL_UCPD_PSC_DIV1 0x0u /*!< Bypass pre-scaling / divide by 1 */
229 #define LL_UCPD_PSC_DIV2 UCPD_CFG1_PSC_UCPDCLK_0 /*!< Pre-scale clock by dividing by 2 */
230 #define LL_UCPD_PSC_DIV4 UCPD_CFG1_PSC_UCPDCLK_1 /*!< Pre-scale clock by dividing by 4 */
231 #define LL_UCPD_PSC_DIV8 (UCPD_CFG1_PSC_UCPDCLK_1 | UCPD_CFG1_PSC_UCPDCLK_0) /*!< Pre-scale clock by dividing by 8 */
232 #define LL_UCPD_PSC_DIV16 UCPD_CFG1_PSC_UCPDCLK_2 /*!< Pre-scale clock by dividing by 16 */
233 /**
234 * @}
235 */
236
237 /** @defgroup UCPD_LL_EC_CCENABLE CC pin enable
238 * @{
239 */
240 #define LL_UCPD_CCENABLE_NONE 0x0U /*!< Neither PHY is activated (e.g. disabled state of source) */
241 #define LL_UCPD_CCENABLE_CC1 UCPD_CR_CCENABLE_0 /*!< Controls apply to only CC1 */
242 #define LL_UCPD_CCENABLE_CC2 UCPD_CR_CCENABLE_1 /*!< Controls apply to only CC1 */
243 #define LL_UCPD_CCENABLE_CC1CC2 (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1) /*!< Controls apply to both CC1 and CC2 (normal usage for sink/source) */
244 /**
245 * @}
246 */
247
248 /** @defgroup UCPD_LL_EC_CCPIN CC pin selection
249 * @{
250 */
251 #define LL_UCPD_CCPIN_CC1 0x0U /*!< Use CC1 IO for power delivery communication */
252 #define LL_UCPD_CCPIN_CC2 UCPD_CR_PHYCCSEL /*!< Use CC2 IO for power delivery communication */
253 /**
254 * @}
255 */
256
257 /** @defgroup UCPD_LL_EC_RXMODE Receiver mode
258 * @{
259 */
260 #define LL_UCPD_RXMODE_NORMAL 0x0U /*!< Normal receive mode */
261 #define LL_UCPD_RXMODE_BIST_TEST_DATA UCPD_CR_RXMODE /*!< BIST receive mode (BIST Test Data Mode) */
262 /**
263 * @}
264 */
265
266 /** @defgroup UCPD_LL_EC_TXMODE Type of Tx packet
267 * @{
268 */
269 #define LL_UCPD_TXMODE_NORMAL 0x0U /*!< Initiate the transfer of a Tx message */
270 #define LL_UCPD_TXMODE_CABLE_RESET UCPD_CR_TXMODE_0 /*!< Trigger a the transfer of a Cable Reset sequence */
271 #define LL_UCPD_TXMODE_BIST_CARRIER2 UCPD_CR_TXMODE_1 /*!< Trigger a BIST test sequence send (BIST Carrier Mode 2) */
272 /**
273 * @}
274 */
275
276 /** @defgroup UCPD_LL_EC_RXORDSET Rx ordered set code detected
277 * @{
278 */
279 #define LL_UCPD_RXORDSET_SOP 0x0U /*!< SOP code detected in receiver */
280 #define LL_UCPD_RXORDSET_SOP1 UCPD_RX_ORDSET_RXORDSET_0 /*!< SOP' code detected in receiver */
281 #define LL_UCPD_RXORDSET_SOP2 UCPD_RX_ORDSET_RXORDSET_1 /*!< SOP'' code detected in receiver */
282 #define LL_UCPD_RXORDSET_SOP1_DEBUG (UCPD_RX_ORDSET_RXORDSET_0 | UCPD_RX_ORDSET_RXORDSET_1) /*!< SOP' Debug code detected in receiver */
283 #define LL_UCPD_RXORDSET_SOP2_DEBUG UCPD_RX_ORDSET_RXORDSET_2 /*!< SOP'' Debug code detected in receiver */
284 #define LL_UCPD_RXORDSET_CABLE_RESET (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_0) /*!< Cable Reset code detected in receiver */
285 #define LL_UCPD_RXORDSET_SOPEXT1 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1) /*!< SOP extension#1 code detected in receiver */
286 #define LL_UCPD_RXORDSET_SOPEXT2 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1 | UCPD_RX_ORDSET_RXORDSET_0) /*!< SOP extension#2 code detected in receiver */
287 /**
288 * @}
289 */
290
291 /**
292 * @}
293 */
294
295 /* Exported macro ------------------------------------------------------------*/
296 /** @defgroup UCPD_LL_Exported_Macros UCPD Exported Macros
297 * @{
298 */
299
300 /** @defgroup UCPD_LL_EM_WRITE_READ Common Write and read registers Macros
301 * @{
302 */
303
304 /**
305 * @brief Write a value in UCPD register
306 * @param __INSTANCE__ UCPD Instance
307 * @param __REG__ Register to be written
308 * @param __VALUE__ Value to be written in the register
309 * @retval None
310 */
311 #define LL_UCPD_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
312
313 /**
314 * @brief Read a value in UCPD register
315 * @param __INSTANCE__ UCPD Instance
316 * @param __REG__ Register to be read
317 * @retval Register value
318 */
319 #define LL_UCPD_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
320 /**
321 * @}
322 */
323
324 /**
325 * @}
326 */
327
328 /* Exported functions --------------------------------------------------------*/
329 /** @defgroup UCPD_LL_Exported_Functions UCPD Exported Functions
330 * @{
331 */
332
333 /** @defgroup UCPD_LL_EF_Configuration Configuration
334 * @{
335 */
336
337 /** @defgroup UCPD_LL_EF_CFG1 CFG1 register
338 * @{
339 */
340 /**
341 * @brief Enable UCPD peripheral
342 * @rmtoll CFG1 UCPDEN LL_UCPD_Enable
343 * @param UCPDx UCPD Instance
344 * @retval None
345 */
LL_UCPD_Enable(UCPD_TypeDef * UCPDx)346 __STATIC_INLINE void LL_UCPD_Enable(UCPD_TypeDef *UCPDx)
347 {
348 SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN);
349 }
350
351 /**
352 * @brief Disable UCPD peripheral
353 * @note When disabling the UCPD, follow the procedure described in the Reference Manual.
354 * @rmtoll CFG1 UCPDEN LL_UCPD_Disable
355 * @param UCPDx UCPD Instance
356 * @retval None
357 */
LL_UCPD_Disable(UCPD_TypeDef * UCPDx)358 __STATIC_INLINE void LL_UCPD_Disable(UCPD_TypeDef *UCPDx)
359 {
360 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN);
361 }
362
363 /**
364 * @brief Check if UCPD peripheral is enabled
365 * @rmtoll CFG1 UCPDEN LL_UCPD_IsEnabled
366 * @param UCPDx UCPD Instance
367 * @retval State of bit (1 or 0).
368 */
LL_UCPD_IsEnabled(UCPD_TypeDef const * const UCPDx)369 __STATIC_INLINE uint32_t LL_UCPD_IsEnabled(UCPD_TypeDef const *const UCPDx)
370 {
371 return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL);
372 }
373
374 /**
375 * @brief Set the receiver ordered set detection enable
376 * @rmtoll CFG1 RXORDSETEN LL_UCPD_SetRxOrderSet
377 * @param UCPDx UCPD Instance
378 * @param OrderSet This parameter can be combination of the following values:
379 * @arg @ref LL_UCPD_ORDERSET_SOP
380 * @arg @ref LL_UCPD_ORDERSET_SOP1
381 * @arg @ref LL_UCPD_ORDERSET_SOP2
382 * @arg @ref LL_UCPD_ORDERSET_HARDRST
383 * @arg @ref LL_UCPD_ORDERSET_CABLERST
384 * @arg @ref LL_UCPD_ORDERSET_SOP1_DEBUG
385 * @arg @ref LL_UCPD_ORDERSET_SOP2_DEBUG
386 * @arg @ref LL_UCPD_ORDERSET_SOP_EXT1
387 * @arg @ref LL_UCPD_ORDERSET_SOP_EXT2
388 * @retval None
389 */
LL_UCPD_SetRxOrderSet(UCPD_TypeDef * UCPDx,uint32_t OrderSet)390 __STATIC_INLINE void LL_UCPD_SetRxOrderSet(UCPD_TypeDef *UCPDx, uint32_t OrderSet)
391 {
392 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_RXORDSETEN, OrderSet);
393 }
394
395 /**
396 * @brief Set the prescaler for ucpd clock
397 * @rmtoll CFG1 UCPDCLK LL_UCPD_SetPSCClk
398 * @param UCPDx UCPD Instance
399 * @param Psc This parameter can be one of the following values:
400 * @arg @ref LL_UCPD_PSC_DIV1
401 * @arg @ref LL_UCPD_PSC_DIV2
402 * @arg @ref LL_UCPD_PSC_DIV4
403 * @arg @ref LL_UCPD_PSC_DIV8
404 * @arg @ref LL_UCPD_PSC_DIV16
405 * @retval None
406 */
LL_UCPD_SetPSCClk(UCPD_TypeDef * UCPDx,uint32_t Psc)407 __STATIC_INLINE void LL_UCPD_SetPSCClk(UCPD_TypeDef *UCPDx, uint32_t Psc)
408 {
409 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK, Psc);
410 }
411
412 /**
413 * @brief Set the number of cycles (minus 1) of the half bit clock
414 * @rmtoll CFG1 TRANSWIN LL_UCPD_SetTransWin
415 * @param UCPDx UCPD Instance
416 * @param TransWin a value between Min_Data=0x1 and Max_Data=0x1F
417 * @retval None
418 */
LL_UCPD_SetTransWin(UCPD_TypeDef * UCPDx,uint32_t TransWin)419 __STATIC_INLINE void LL_UCPD_SetTransWin(UCPD_TypeDef *UCPDx, uint32_t TransWin)
420 {
421 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_TRANSWIN, TransWin << UCPD_CFG1_TRANSWIN_Pos);
422 }
423
424 /**
425 * @brief Set the clock divider value to generate an interframe gap
426 * @rmtoll CFG1 IFRGAP LL_UCPD_SetIfrGap
427 * @param UCPDx UCPD Instance
428 * @param IfrGap a value between Min_Data=0x1 and Max_Data=0x1F
429 * @retval None
430 */
LL_UCPD_SetIfrGap(UCPD_TypeDef * UCPDx,uint32_t IfrGap)431 __STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap)
432 {
433 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos);
434 }
435
436 /**
437 * @brief Set the clock divider value to generate an interframe gap
438 * @rmtoll CFG1 HBITCLKDIV LL_UCPD_SetHbitClockDiv
439 * @param UCPDx UCPD Instance
440 * @param HbitClock a value between Min_Data=0x0 and Max_Data=0x3F
441 * @retval None
442 */
LL_UCPD_SetHbitClockDiv(UCPD_TypeDef * UCPDx,uint32_t HbitClock)443 __STATIC_INLINE void LL_UCPD_SetHbitClockDiv(UCPD_TypeDef *UCPDx, uint32_t HbitClock)
444 {
445 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_HBITCLKDIV, HbitClock << UCPD_CFG1_HBITCLKDIV_Pos);
446 }
447
448 /**
449 * @}
450 */
451
452 /** @defgroup UCPD_LL_EF_CFG2 CFG2 register
453 * @{
454 */
455
456 /**
457 * @brief Enable the wakeup mode
458 * @rmtoll CFG2 WUPEN LL_UCPD_WakeUpEnable
459 * @param UCPDx UCPD Instance
460 * @retval None
461 */
LL_UCPD_WakeUpEnable(UCPD_TypeDef * UCPDx)462 __STATIC_INLINE void LL_UCPD_WakeUpEnable(UCPD_TypeDef *UCPDx)
463 {
464 SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN);
465 }
466
467 /**
468 * @brief Disable the wakeup mode
469 * @rmtoll CFG2 WUPEN LL_UCPD_WakeUpDisable
470 * @param UCPDx UCPD Instance
471 * @retval None
472 */
LL_UCPD_WakeUpDisable(UCPD_TypeDef * UCPDx)473 __STATIC_INLINE void LL_UCPD_WakeUpDisable(UCPD_TypeDef *UCPDx)
474 {
475 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN);
476 }
477
478 /**
479 * @brief Force clock enable
480 * @rmtoll CFG2 FORCECLK LL_UCPD_ForceClockEnable
481 * @param UCPDx UCPD Instance
482 * @retval None
483 */
LL_UCPD_ForceClockEnable(UCPD_TypeDef * UCPDx)484 __STATIC_INLINE void LL_UCPD_ForceClockEnable(UCPD_TypeDef *UCPDx)
485 {
486 SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK);
487 }
488
489 /**
490 * @brief Force clock disable
491 * @rmtoll CFG2 FORCECLK LL_UCPD_ForceClockDisable
492 * @param UCPDx UCPD Instance
493 * @retval None
494 */
LL_UCPD_ForceClockDisable(UCPD_TypeDef * UCPDx)495 __STATIC_INLINE void LL_UCPD_ForceClockDisable(UCPD_TypeDef *UCPDx)
496 {
497 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK);
498 }
499
500 /**
501 * @brief RxFilter enable
502 * @rmtoll CFG2 RXFILTDIS LL_UCPD_RxFilterEnable
503 * @param UCPDx UCPD Instance
504 * @retval None
505 */
LL_UCPD_RxFilterEnable(UCPD_TypeDef * UCPDx)506 __STATIC_INLINE void LL_UCPD_RxFilterEnable(UCPD_TypeDef *UCPDx)
507 {
508 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS);
509 }
510
511 /**
512 * @brief RxFilter disable
513 * @rmtoll CFG2 RXFILTDIS LL_UCPD_RxFilterDisable
514 * @param UCPDx UCPD Instance
515 * @retval None
516 */
LL_UCPD_RxFilterDisable(UCPD_TypeDef * UCPDx)517 __STATIC_INLINE void LL_UCPD_RxFilterDisable(UCPD_TypeDef *UCPDx)
518 {
519 SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS);
520 }
521
522 /**
523 * @}
524 */
525
526 /**
527 * @}
528 */
529
530 /** @defgroup UCPD_LL_EF_CR CR register
531 * @{
532 */
533 /**
534 * @brief Type C detector for CC2 enable
535 * @rmtoll CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Enable
536 * @param UCPDx UCPD Instance
537 * @retval None
538 */
LL_UCPD_TypeCDetectionCC2Enable(UCPD_TypeDef * UCPDx)539 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Enable(UCPD_TypeDef *UCPDx)
540 {
541 CLEAR_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS);
542 }
543
544 /**
545 * @brief Type C detector for CC2 disable
546 * @rmtoll CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Disable
547 * @param UCPDx UCPD Instance
548 * @retval None
549 */
LL_UCPD_TypeCDetectionCC2Disable(UCPD_TypeDef * UCPDx)550 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Disable(UCPD_TypeDef *UCPDx)
551 {
552 SET_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS);
553 }
554
555 /**
556 * @brief Type C detector for CC1 enable
557 * @rmtoll CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Enable
558 * @param UCPDx UCPD Instance
559 * @retval None
560 */
LL_UCPD_TypeCDetectionCC1Enable(UCPD_TypeDef * UCPDx)561 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Enable(UCPD_TypeDef *UCPDx)
562 {
563 CLEAR_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS);
564 }
565
566 /**
567 * @brief Type C detector for CC1 disable
568 * @rmtoll CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Disable
569 * @param UCPDx UCPD Instance
570 * @retval None
571 */
LL_UCPD_TypeCDetectionCC1Disable(UCPD_TypeDef * UCPDx)572 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Disable(UCPD_TypeDef *UCPDx)
573 {
574 SET_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS);
575 }
576
577 /**
578 * @brief Source Vconn discharge enable
579 * @rmtoll CR RDCH LL_UCPD_VconnDischargeEnable
580 * @param UCPDx UCPD Instance
581 * @retval None
582 */
LL_UCPD_VconnDischargeEnable(UCPD_TypeDef * UCPDx)583 __STATIC_INLINE void LL_UCPD_VconnDischargeEnable(UCPD_TypeDef *UCPDx)
584 {
585 SET_BIT(UCPDx->CR, UCPD_CR_RDCH);
586 }
587
588 /**
589 * @brief Source Vconn discharge disable
590 * @rmtoll CR RDCH LL_UCPD_VconnDischargeDisable
591 * @param UCPDx UCPD Instance
592 * @retval None
593 */
LL_UCPD_VconnDischargeDisable(UCPD_TypeDef * UCPDx)594 __STATIC_INLINE void LL_UCPD_VconnDischargeDisable(UCPD_TypeDef *UCPDx)
595 {
596 CLEAR_BIT(UCPDx->CR, UCPD_CR_RDCH);
597 }
598
599 /**
600 * @brief Signal Fast Role Swap request
601 * @rmtoll CR FRSTX LL_UCPD_VconnDischargeDisable
602 * @param UCPDx UCPD Instance
603 * @retval None
604 */
LL_UCPD_SignalFRSTX(UCPD_TypeDef * UCPDx)605 __STATIC_INLINE void LL_UCPD_SignalFRSTX(UCPD_TypeDef *UCPDx)
606 {
607 SET_BIT(UCPDx->CR, UCPD_CR_FRSTX);
608 }
609
610 /**
611 * @brief Fast Role swap RX detection enable
612 * @rmtoll CR FRSRXEN LL_UCPD_FRSDetectionEnable
613 * @param UCPDx UCPD Instance
614 * @retval None
615 */
LL_UCPD_FRSDetectionEnable(UCPD_TypeDef * UCPDx)616 __STATIC_INLINE void LL_UCPD_FRSDetectionEnable(UCPD_TypeDef *UCPDx)
617 {
618 SET_BIT(UCPDx->CR, UCPD_CR_FRSRXEN);
619 }
620
621 /**
622 * @brief Fast Role swap RX detection disable
623 * @rmtoll CR FRSRXEN LL_UCPD_FRSDetectionDisable
624 * @param UCPDx UCPD Instance
625 * @retval None
626 */
LL_UCPD_FRSDetectionDisable(UCPD_TypeDef * UCPDx)627 __STATIC_INLINE void LL_UCPD_FRSDetectionDisable(UCPD_TypeDef *UCPDx)
628 {
629 CLEAR_BIT(UCPDx->CR, UCPD_CR_FRSRXEN);
630 }
631
632 /**
633 * @brief Set cc enable
634 * @rmtoll CR CC1VCONNEN LL_UCPD_SetccEnable
635 * @param UCPDx UCPD Instance
636 * @param CCEnable This parameter can be one of the following values:
637 * @arg @ref LL_UCPD_CCENABLE_NONE
638 * @arg @ref LL_UCPD_CCENABLE_CC1
639 * @arg @ref LL_UCPD_CCENABLE_CC2
640 * @arg @ref LL_UCPD_CCENABLE_CC1CC2
641 * @retval None
642 */
LL_UCPD_SetccEnable(UCPD_TypeDef * UCPDx,uint32_t CCEnable)643 __STATIC_INLINE void LL_UCPD_SetccEnable(UCPD_TypeDef *UCPDx, uint32_t CCEnable)
644 {
645 MODIFY_REG(UCPDx->CR, UCPD_CR_CCENABLE, CCEnable);
646 }
647
648 /**
649 * @brief Set UCPD SNK role
650 * @rmtoll CR ANAMODE LL_UCPD_SetSNKRole
651 * @param UCPDx UCPD Instance
652 * @retval None
653 */
LL_UCPD_SetSNKRole(UCPD_TypeDef * UCPDx)654 __STATIC_INLINE void LL_UCPD_SetSNKRole(UCPD_TypeDef *UCPDx)
655 {
656 SET_BIT(UCPDx->CR, UCPD_CR_ANAMODE);
657 }
658
659 /**
660 * @brief Set UCPD SRC role
661 * @rmtoll CR ANAMODE LL_UCPD_SetSRCRole
662 * @param UCPDx UCPD Instance
663 * @retval None
664 */
LL_UCPD_SetSRCRole(UCPD_TypeDef * UCPDx)665 __STATIC_INLINE void LL_UCPD_SetSRCRole(UCPD_TypeDef *UCPDx)
666 {
667 CLEAR_BIT(UCPDx->CR, UCPD_CR_ANAMODE);
668 }
669
670 /**
671 * @brief Get UCPD Role
672 * @rmtoll CR ANAMODE LL_UCPD_GetRole
673 * @param UCPDx UCPD Instance
674 * @retval Returned value can be one of the following values:
675 * @arg @ref LL_UCPD_ROLE_SNK
676 * @arg @ref LL_UCPD_ROLE_SRC
677 */
LL_UCPD_GetRole(UCPD_TypeDef const * const UCPDx)678 __STATIC_INLINE uint32_t LL_UCPD_GetRole(UCPD_TypeDef const *const UCPDx)
679 {
680 return (uint32_t)(READ_BIT(UCPDx->CR, UCPD_CR_ANAMODE));
681 }
682
683 /**
684 * @brief Set Rp resistor
685 * @rmtoll CR ANASUBMODE LL_UCPD_SetRpResistor
686 * @param UCPDx UCPD Instance
687 * @param Resistor This parameter can be one of the following values:
688 * @arg @ref LL_UCPD_RESISTOR_DEFAULT
689 * @arg @ref LL_UCPD_RESISTOR_1_5A
690 * @arg @ref LL_UCPD_RESISTOR_3_0A
691 * @arg @ref LL_UCPD_RESISTOR_NONE
692 * @retval None
693 */
LL_UCPD_SetRpResistor(UCPD_TypeDef * UCPDx,uint32_t Resistor)694 __STATIC_INLINE void LL_UCPD_SetRpResistor(UCPD_TypeDef *UCPDx, uint32_t Resistor)
695 {
696 MODIFY_REG(UCPDx->CR, UCPD_CR_ANASUBMODE, Resistor);
697 }
698
699 /**
700 * @brief Set CC pin
701 * @rmtoll CR PHYCCSEL LL_UCPD_SetCCPin
702 * @param UCPDx UCPD Instance
703 * @param CCPin This parameter can be one of the following values:
704 * @arg @ref LL_UCPD_CCPIN_CC1
705 * @arg @ref LL_UCPD_CCPIN_CC2
706 * @retval None
707 */
LL_UCPD_SetCCPin(UCPD_TypeDef * UCPDx,uint32_t CCPin)708 __STATIC_INLINE void LL_UCPD_SetCCPin(UCPD_TypeDef *UCPDx, uint32_t CCPin)
709 {
710 MODIFY_REG(UCPDx->CR, UCPD_CR_PHYCCSEL, CCPin);
711 }
712
713 /**
714 * @brief Rx enable
715 * @rmtoll CR PHYRXEN LL_UCPD_RxEnable
716 * @param UCPDx UCPD Instance
717 * @retval None
718 */
LL_UCPD_RxEnable(UCPD_TypeDef * UCPDx)719 __STATIC_INLINE void LL_UCPD_RxEnable(UCPD_TypeDef *UCPDx)
720 {
721 SET_BIT(UCPDx->CR, UCPD_CR_PHYRXEN);
722 }
723
724 /**
725 * @brief Rx disable
726 * @rmtoll CR PHYRXEN LL_UCPD_RxDisable
727 * @param UCPDx UCPD Instance
728 * @retval None
729 */
LL_UCPD_RxDisable(UCPD_TypeDef * UCPDx)730 __STATIC_INLINE void LL_UCPD_RxDisable(UCPD_TypeDef *UCPDx)
731 {
732 CLEAR_BIT(UCPDx->CR, UCPD_CR_PHYRXEN);
733 }
734
735 /**
736 * @brief Set Rx mode
737 * @rmtoll CR RXMODE LL_UCPD_SetRxMode
738 * @param UCPDx UCPD Instance
739 * @param RxMode This parameter can be one of the following values:
740 * @arg @ref LL_UCPD_RXMODE_NORMAL
741 * @arg @ref LL_UCPD_RXMODE_BIST_TEST_DATA
742 * @retval None
743 */
LL_UCPD_SetRxMode(UCPD_TypeDef * UCPDx,uint32_t RxMode)744 __STATIC_INLINE void LL_UCPD_SetRxMode(UCPD_TypeDef *UCPDx, uint32_t RxMode)
745 {
746 MODIFY_REG(UCPDx->CR, UCPD_CR_RXMODE, RxMode);
747 }
748
749 /**
750 * @brief Send Hard Reset
751 * @rmtoll CR TXHRST LL_UCPD_SendHardReset
752 * @param UCPDx UCPD Instance
753 * @retval None
754 */
LL_UCPD_SendHardReset(UCPD_TypeDef * UCPDx)755 __STATIC_INLINE void LL_UCPD_SendHardReset(UCPD_TypeDef *UCPDx)
756 {
757 SET_BIT(UCPDx->CR, UCPD_CR_TXHRST);
758 }
759
760 /**
761 * @brief Send message
762 * @rmtoll CR TXSEND LL_UCPD_SendMessage
763 * @param UCPDx UCPD Instance
764 * @retval None
765 */
LL_UCPD_SendMessage(UCPD_TypeDef * UCPDx)766 __STATIC_INLINE void LL_UCPD_SendMessage(UCPD_TypeDef *UCPDx)
767 {
768 SET_BIT(UCPDx->CR, UCPD_CR_TXSEND);
769 }
770
771 /**
772 * @brief Set Tx mode
773 * @rmtoll CR TXMODE LL_UCPD_SetTxMode
774 * @param UCPDx UCPD Instance
775 * @param TxMode This parameter can be one of the following values:
776 * @arg @ref LL_UCPD_TXMODE_NORMAL
777 * @arg @ref LL_UCPD_TXMODE_CABLE_RESET
778 * @arg @ref LL_UCPD_TXMODE_BIST_CARRIER2
779 * @retval None
780 */
LL_UCPD_SetTxMode(UCPD_TypeDef * UCPDx,uint32_t TxMode)781 __STATIC_INLINE void LL_UCPD_SetTxMode(UCPD_TypeDef *UCPDx, uint32_t TxMode)
782 {
783 MODIFY_REG(UCPDx->CR, UCPD_CR_TXMODE, TxMode);
784 }
785
786 /**
787 * @}
788 */
789
790 /** @defgroup UCPD_LL_EF_IT_Management Interrupt Management
791 * @{
792 */
793
794 /**
795 * @brief Enable FRS interrupt
796 * @rmtoll IMR FRSEVTIE LL_UCPD_EnableIT_FRS
797 * @param UCPDx UCPD Instance
798 * @retval None
799 */
LL_UCPD_EnableIT_FRS(UCPD_TypeDef * UCPDx)800 __STATIC_INLINE void LL_UCPD_EnableIT_FRS(UCPD_TypeDef *UCPDx)
801 {
802 SET_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE);
803 }
804
805 /**
806 * @brief Enable type c event on CC2
807 * @rmtoll IMR TYPECEVT2IE LL_UCPD_EnableIT_TypeCEventCC2
808 * @param UCPDx UCPD Instance
809 * @retval None
810 */
LL_UCPD_EnableIT_TypeCEventCC2(UCPD_TypeDef * UCPDx)811 __STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx)
812 {
813 SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE);
814 }
815
816 /**
817 * @brief Enable type c event on CC1
818 * @rmtoll IMR TYPECEVT1IE LL_UCPD_EnableIT_TypeCEventCC1
819 * @param UCPDx UCPD Instance
820 * @retval None
821 */
LL_UCPD_EnableIT_TypeCEventCC1(UCPD_TypeDef * UCPDx)822 __STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx)
823 {
824 SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE);
825 }
826
827 /**
828 * @brief Enable Rx message end interrupt
829 * @rmtoll IMR RXMSGENDIE LL_UCPD_EnableIT_RxMsgEnd
830 * @param UCPDx UCPD Instance
831 * @retval None
832 */
LL_UCPD_EnableIT_RxMsgEnd(UCPD_TypeDef * UCPDx)833 __STATIC_INLINE void LL_UCPD_EnableIT_RxMsgEnd(UCPD_TypeDef *UCPDx)
834 {
835 SET_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE);
836 }
837
838 /**
839 * @brief Enable Rx overrun interrupt
840 * @rmtoll IMR RXOVRIE LL_UCPD_EnableIT_RxOvr
841 * @param UCPDx UCPD Instance
842 * @retval None
843 */
LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef * UCPDx)844 __STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx)
845 {
846 SET_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE);
847 }
848
849 /**
850 * @brief Enable Rx hard resrt interrupt
851 * @rmtoll IMR RXHRSTDETIE LL_UCPD_EnableIT_RxHRST
852 * @param UCPDx UCPD Instance
853 * @retval None
854 */
LL_UCPD_EnableIT_RxHRST(UCPD_TypeDef * UCPDx)855 __STATIC_INLINE void LL_UCPD_EnableIT_RxHRST(UCPD_TypeDef *UCPDx)
856 {
857 SET_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE);
858 }
859
860 /**
861 * @brief Enable Rx orderset interrupt
862 * @rmtoll IMR RXORDDETIE LL_UCPD_EnableIT_RxOrderSet
863 * @param UCPDx UCPD Instance
864 * @retval None
865 */
LL_UCPD_EnableIT_RxOrderSet(UCPD_TypeDef * UCPDx)866 __STATIC_INLINE void LL_UCPD_EnableIT_RxOrderSet(UCPD_TypeDef *UCPDx)
867 {
868 SET_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE);
869 }
870
871 /**
872 * @brief Enable Rx non empty interrupt
873 * @rmtoll IMR RXNEIE LL_UCPD_EnableIT_RxNE
874 * @param UCPDx UCPD Instance
875 * @retval None
876 */
LL_UCPD_EnableIT_RxNE(UCPD_TypeDef * UCPDx)877 __STATIC_INLINE void LL_UCPD_EnableIT_RxNE(UCPD_TypeDef *UCPDx)
878 {
879 SET_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE);
880 }
881
882 /**
883 * @brief Enable TX underrun interrupt
884 * @rmtoll IMR TXUNDIE LL_UCPD_EnableIT_TxUND
885 * @param UCPDx UCPD Instance
886 * @retval None
887 */
LL_UCPD_EnableIT_TxUND(UCPD_TypeDef * UCPDx)888 __STATIC_INLINE void LL_UCPD_EnableIT_TxUND(UCPD_TypeDef *UCPDx)
889 {
890 SET_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE);
891 }
892
893 /**
894 * @brief Enable hard reset sent interrupt
895 * @rmtoll IMR HRSTSENTIE LL_UCPD_EnableIT_TxHRSTSENT
896 * @param UCPDx UCPD Instance
897 * @retval None
898 */
LL_UCPD_EnableIT_TxHRSTSENT(UCPD_TypeDef * UCPDx)899 __STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx)
900 {
901 SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE);
902 }
903
904 /**
905 * @brief Enable hard reset discard interrupt
906 * @rmtoll IMR HRSTDISCIE LL_UCPD_EnableIT_TxHRSTDISC
907 * @param UCPDx UCPD Instance
908 * @retval None
909 */
LL_UCPD_EnableIT_TxHRSTDISC(UCPD_TypeDef * UCPDx)910 __STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx)
911 {
912 SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE);
913 }
914
915 /**
916 * @brief Enable Tx message abort interrupt
917 * @rmtoll IMR TXMSGABTIE LL_UCPD_EnableIT_TxMSGABT
918 * @param UCPDx UCPD Instance
919 * @retval None
920 */
LL_UCPD_EnableIT_TxMSGABT(UCPD_TypeDef * UCPDx)921 __STATIC_INLINE void LL_UCPD_EnableIT_TxMSGABT(UCPD_TypeDef *UCPDx)
922 {
923 SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE);
924 }
925
926 /**
927 * @brief Enable Tx message sent interrupt
928 * @rmtoll IMR TXMSGSENTIE LL_UCPD_EnableIT_TxMSGSENT
929 * @param UCPDx UCPD Instance
930 * @retval None
931 */
LL_UCPD_EnableIT_TxMSGSENT(UCPD_TypeDef * UCPDx)932 __STATIC_INLINE void LL_UCPD_EnableIT_TxMSGSENT(UCPD_TypeDef *UCPDx)
933 {
934 SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE);
935 }
936
937 /**
938 * @brief Enable Tx message discarded interrupt
939 * @rmtoll IMR TXMSGDISCIE LL_UCPD_EnableIT_TxMSGDISC
940 * @param UCPDx UCPD Instance
941 * @retval None
942 */
LL_UCPD_EnableIT_TxMSGDISC(UCPD_TypeDef * UCPDx)943 __STATIC_INLINE void LL_UCPD_EnableIT_TxMSGDISC(UCPD_TypeDef *UCPDx)
944 {
945 SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE);
946 }
947
948 /**
949 * @brief Enable Tx data receive interrupt
950 * @rmtoll IMR TXISIE LL_UCPD_EnableIT_TxIS
951 * @param UCPDx UCPD Instance
952 * @retval None
953 */
LL_UCPD_EnableIT_TxIS(UCPD_TypeDef * UCPDx)954 __STATIC_INLINE void LL_UCPD_EnableIT_TxIS(UCPD_TypeDef *UCPDx)
955 {
956 SET_BIT(UCPDx->IMR, UCPD_IMR_TXISIE);
957 }
958
959 /**
960 * @brief Disable FRS interrupt
961 * @rmtoll IMR FRSEVTIE LL_UCPD_DisableIT_FRS
962 * @param UCPDx UCPD Instance
963 * @retval None
964 */
LL_UCPD_DisableIT_FRS(UCPD_TypeDef * UCPDx)965 __STATIC_INLINE void LL_UCPD_DisableIT_FRS(UCPD_TypeDef *UCPDx)
966 {
967 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE);
968 }
969
970 /**
971 * @brief Disable type c event on CC2
972 * @rmtoll IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2
973 * @param UCPDx UCPD Instance
974 * @retval None
975 */
LL_UCPD_DisableIT_TypeCEventCC2(UCPD_TypeDef * UCPDx)976 __STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx)
977 {
978 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE);
979 }
980
981 /**
982 * @brief Disable type c event on CC1
983 * @rmtoll IMR TYPECEVT1IE LL_UCPD_DisableIT_TypeCEventCC1
984 * @param UCPDx UCPD Instance
985 * @retval None
986 */
LL_UCPD_DisableIT_TypeCEventCC1(UCPD_TypeDef * UCPDx)987 __STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx)
988 {
989 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE);
990 }
991
992 /**
993 * @brief Disable Rx message end interrupt
994 * @rmtoll IMR RXMSGENDIE LL_UCPD_DisableIT_RxMsgEnd
995 * @param UCPDx UCPD Instance
996 * @retval None
997 */
LL_UCPD_DisableIT_RxMsgEnd(UCPD_TypeDef * UCPDx)998 __STATIC_INLINE void LL_UCPD_DisableIT_RxMsgEnd(UCPD_TypeDef *UCPDx)
999 {
1000 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE);
1001 }
1002
1003 /**
1004 * @brief Disable Rx overrun interrupt
1005 * @rmtoll IMR RXOVRIE LL_UCPD_DisableIT_RxOvr
1006 * @param UCPDx UCPD Instance
1007 * @retval None
1008 */
LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef * UCPDx)1009 __STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx)
1010 {
1011 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE);
1012 }
1013
1014 /**
1015 * @brief Disable Rx hard resrt interrupt
1016 * @rmtoll IMR RXHRSTDETIE LL_UCPD_DisableIT_RxHRST
1017 * @param UCPDx UCPD Instance
1018 * @retval None
1019 */
LL_UCPD_DisableIT_RxHRST(UCPD_TypeDef * UCPDx)1020 __STATIC_INLINE void LL_UCPD_DisableIT_RxHRST(UCPD_TypeDef *UCPDx)
1021 {
1022 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE);
1023 }
1024
1025 /**
1026 * @brief Disable Rx orderset interrupt
1027 * @rmtoll IMR RXORDDETIE LL_UCPD_DisableIT_RxOrderSet
1028 * @param UCPDx UCPD Instance
1029 * @retval None
1030 */
LL_UCPD_DisableIT_RxOrderSet(UCPD_TypeDef * UCPDx)1031 __STATIC_INLINE void LL_UCPD_DisableIT_RxOrderSet(UCPD_TypeDef *UCPDx)
1032 {
1033 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE);
1034 }
1035
1036 /**
1037 * @brief Disable Rx non empty interrupt
1038 * @rmtoll IMR RXNEIE LL_UCPD_DisableIT_RxNE
1039 * @param UCPDx UCPD Instance
1040 * @retval None
1041 */
LL_UCPD_DisableIT_RxNE(UCPD_TypeDef * UCPDx)1042 __STATIC_INLINE void LL_UCPD_DisableIT_RxNE(UCPD_TypeDef *UCPDx)
1043 {
1044 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE);
1045 }
1046
1047 /**
1048 * @brief Disable TX underrun interrupt
1049 * @rmtoll IMR TXUNDIE LL_UCPD_DisableIT_TxUND
1050 * @param UCPDx UCPD Instance
1051 * @retval None
1052 */
LL_UCPD_DisableIT_TxUND(UCPD_TypeDef * UCPDx)1053 __STATIC_INLINE void LL_UCPD_DisableIT_TxUND(UCPD_TypeDef *UCPDx)
1054 {
1055 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE);
1056 }
1057
1058 /**
1059 * @brief Disable hard reset sent interrupt
1060 * @rmtoll IMR HRSTSENTIE LL_UCPD_DisableIT_TxHRSTSENT
1061 * @param UCPDx UCPD Instance
1062 * @retval None
1063 */
LL_UCPD_DisableIT_TxHRSTSENT(UCPD_TypeDef * UCPDx)1064 __STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx)
1065 {
1066 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE);
1067 }
1068
1069 /**
1070 * @brief Disable hard reset discard interrupt
1071 * @rmtoll IMR HRSTDISCIE LL_UCPD_DisableIT_TxHRSTDISC
1072 * @param UCPDx UCPD Instance
1073 * @retval None
1074 */
LL_UCPD_DisableIT_TxHRSTDISC(UCPD_TypeDef * UCPDx)1075 __STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx)
1076 {
1077 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE);
1078 }
1079
1080 /**
1081 * @brief Disable Tx message abort interrupt
1082 * @rmtoll IMR TXMSGABTIE LL_UCPD_DisableIT_TxMSGABT
1083 * @param UCPDx UCPD Instance
1084 * @retval None
1085 */
LL_UCPD_DisableIT_TxMSGABT(UCPD_TypeDef * UCPDx)1086 __STATIC_INLINE void LL_UCPD_DisableIT_TxMSGABT(UCPD_TypeDef *UCPDx)
1087 {
1088 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE);
1089 }
1090
1091 /**
1092 * @brief Disable Tx message sent interrupt
1093 * @rmtoll IMR TXMSGSENTIE LL_UCPD_DisableIT_TxMSGSENT
1094 * @param UCPDx UCPD Instance
1095 * @retval None
1096 */
LL_UCPD_DisableIT_TxMSGSENT(UCPD_TypeDef * UCPDx)1097 __STATIC_INLINE void LL_UCPD_DisableIT_TxMSGSENT(UCPD_TypeDef *UCPDx)
1098 {
1099 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE);
1100 }
1101
1102 /**
1103 * @brief Disable Tx message discarded interrupt
1104 * @rmtoll IMR TXMSGDISCIE LL_UCPD_DisableIT_TxMSGDISC
1105 * @param UCPDx UCPD Instance
1106 * @retval None
1107 */
LL_UCPD_DisableIT_TxMSGDISC(UCPD_TypeDef * UCPDx)1108 __STATIC_INLINE void LL_UCPD_DisableIT_TxMSGDISC(UCPD_TypeDef *UCPDx)
1109 {
1110 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE);
1111 }
1112
1113 /**
1114 * @brief Disable Tx data receive interrupt
1115 * @rmtoll IMR TXISIE LL_UCPD_DisableIT_TxIS
1116 * @param UCPDx UCPD Instance
1117 * @retval None
1118 */
LL_UCPD_DisableIT_TxIS(UCPD_TypeDef * UCPDx)1119 __STATIC_INLINE void LL_UCPD_DisableIT_TxIS(UCPD_TypeDef *UCPDx)
1120 {
1121 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXISIE);
1122 }
1123
1124 /**
1125 * @brief Check if FRS interrupt enabled
1126 * @rmtoll IMR FRSEVTIE LL_UCPD_DisableIT_FRS
1127 * @param UCPDx UCPD Instance
1128 * @retval State of bit (1 or 0).
1129 */
LL_UCPD_IsEnableIT_FRS(UCPD_TypeDef const * const UCPDx)1130 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_FRS(UCPD_TypeDef const *const UCPDx)
1131 {
1132 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE) == UCPD_IMR_FRSEVTIE) ? 1UL : 0UL);
1133 }
1134
1135 /**
1136 * @brief Check if type c event on CC2 enabled
1137 * @rmtoll IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2
1138 * @param UCPDx UCPD Instance
1139 * @retval State of bit (1 or 0).
1140 */
LL_UCPD_IsEnableIT_TypeCEventCC2(UCPD_TypeDef const * const UCPDx)1141 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC2(UCPD_TypeDef const *const UCPDx)
1142 {
1143 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE) == UCPD_IMR_TYPECEVT2IE) ? 1UL : 0UL);
1144 }
1145
1146 /**
1147 * @brief Check if type c event on CC1 enabled
1148 * @rmtoll IMR2 TYPECEVT1IE LL_UCPD_IsEnableIT_TypeCEventCC1
1149 * @param UCPDx UCPD Instance
1150 * @retval State of bit (1 or 0).
1151 */
LL_UCPD_IsEnableIT_TypeCEventCC1(UCPD_TypeDef const * const UCPDx)1152 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC1(UCPD_TypeDef const *const UCPDx)
1153 {
1154 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE) == UCPD_IMR_TYPECEVT1IE) ? 1UL : 0UL);
1155 }
1156
1157 /**
1158 * @brief Check if Rx message end interrupt enabled
1159 * @rmtoll IMR RXMSGENDIE LL_UCPD_IsEnableIT_RxMsgEnd
1160 * @param UCPDx UCPD Instance
1161 * @retval State of bit (1 or 0).
1162 */
LL_UCPD_IsEnableIT_RxMsgEnd(UCPD_TypeDef const * const UCPDx)1163 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxMsgEnd(UCPD_TypeDef const *const UCPDx)
1164 {
1165 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE) == UCPD_IMR_RXMSGENDIE) ? 1UL : 0UL);
1166 }
1167
1168 /**
1169 * @brief Check if Rx overrun interrupt enabled
1170 * @rmtoll IMR RXOVRIE LL_UCPD_IsEnableIT_RxOvr
1171 * @param UCPDx UCPD Instance
1172 * @retval State of bit (1 or 0).
1173 */
LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const * const UCPDx)1174 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPDx)
1175 {
1176 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE) == UCPD_IMR_RXOVRIE) ? 1UL : 0UL);
1177 }
1178
1179 /**
1180 * @brief Check if Rx hard resrt interrupt enabled
1181 * @rmtoll IMR RXHRSTDETIE LL_UCPD_IsEnableIT_RxHRST
1182 * @param UCPDx UCPD Instance
1183 * @retval State of bit (1 or 0).
1184 */
LL_UCPD_IsEnableIT_RxHRST(UCPD_TypeDef const * const UCPDx)1185 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxHRST(UCPD_TypeDef const *const UCPDx)
1186 {
1187 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE) == UCPD_IMR_RXHRSTDETIE) ? 1UL : 0UL);
1188 }
1189
1190 /**
1191 * @brief Check if Rx orderset interrupt enabled
1192 * @rmtoll IMR RXORDDETIE LL_UCPD_IsEnableIT_RxOrderSet
1193 * @param UCPDx UCPD Instance
1194 * @retval State of bit (1 or 0).
1195 */
LL_UCPD_IsEnableIT_RxOrderSet(UCPD_TypeDef const * const UCPDx)1196 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOrderSet(UCPD_TypeDef const *const UCPDx)
1197 {
1198 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE) == UCPD_IMR_RXORDDETIE) ? 1UL : 0UL);
1199 }
1200
1201 /**
1202 * @brief Check if Rx non empty interrupt enabled
1203 * @rmtoll IMR RXNEIE LL_UCPD_IsEnableIT_RxNE
1204 * @param UCPDx UCPD Instance
1205 * @retval State of bit (1 or 0).
1206 */
LL_UCPD_IsEnableIT_RxNE(UCPD_TypeDef const * const UCPDx)1207 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxNE(UCPD_TypeDef const *const UCPDx)
1208 {
1209 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE) == UCPD_IMR_RXNEIE) ? 1UL : 0UL);
1210 }
1211
1212 /**
1213 * @brief Check if TX underrun interrupt enabled
1214 * @rmtoll IMR TXUNDIE LL_UCPD_IsEnableIT_TxUND
1215 * @param UCPDx UCPD Instance
1216 * @retval State of bit (1 or 0).
1217 */
LL_UCPD_IsEnableIT_TxUND(UCPD_TypeDef const * const UCPDx)1218 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxUND(UCPD_TypeDef const *const UCPDx)
1219 {
1220 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE) == UCPD_IMR_TXUNDIE) ? 1UL : 0UL);
1221 }
1222
1223 /**
1224 * @brief Check if hard reset sent interrupt enabled
1225 * @rmtoll IMR HRSTSENTIE LL_UCPD_IsEnableIT_TxHRSTSENT
1226 * @param UCPDx UCPD Instance
1227 * @retval State of bit (1 or 0).
1228 */
LL_UCPD_IsEnableIT_TxHRSTSENT(UCPD_TypeDef const * const UCPDx)1229 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTSENT(UCPD_TypeDef const *const UCPDx)
1230 {
1231 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE) == UCPD_IMR_HRSTSENTIE) ? 1UL : 0UL);
1232 }
1233
1234 /**
1235 * @brief Check if hard reset discard interrupt enabled
1236 * @rmtoll IMR HRSTDISCIE LL_UCPD_IsEnableIT_TxHRSTDISC
1237 * @param UCPDx UCPD Instance
1238 * @retval State of bit (1 or 0).
1239 */
LL_UCPD_IsEnableIT_TxHRSTDISC(UCPD_TypeDef const * const UCPDx)1240 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTDISC(UCPD_TypeDef const *const UCPDx)
1241 {
1242 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE) == UCPD_IMR_HRSTDISCIE) ? 1UL : 0UL);
1243 }
1244
1245 /**
1246 * @brief Check if Tx message abort interrupt enabled
1247 * @rmtoll IMR TXMSGABTIE LL_UCPD_IsEnableIT_TxMSGABT
1248 * @param UCPDx UCPD Instance
1249 * @retval State of bit (1 or 0).
1250 */
LL_UCPD_IsEnableIT_TxMSGABT(UCPD_TypeDef const * const UCPDx)1251 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGABT(UCPD_TypeDef const *const UCPDx)
1252 {
1253 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE) == UCPD_IMR_TXMSGABTIE) ? 1UL : 0UL);
1254 }
1255
1256 /**
1257 * @brief Check if Tx message sent interrupt enabled
1258 * @rmtoll IMR TXMSGSENTIE LL_UCPD_IsEnableIT_TxMSGSENT
1259 * @param UCPDx UCPD Instance
1260 * @retval State of bit (1 or 0).
1261 */
LL_UCPD_IsEnableIT_TxMSGSENT(UCPD_TypeDef const * const UCPDx)1262 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGSENT(UCPD_TypeDef const *const UCPDx)
1263 {
1264 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE) == UCPD_IMR_TXMSGSENTIE) ? 1UL : 0UL);
1265 }
1266
1267 /**
1268 * @brief Check if Tx message discarded interrupt enabled
1269 * @rmtoll IMR TXMSGDISCIE LL_UCPD_IsEnableIT_TxMSGDISC
1270 * @param UCPDx UCPD Instance
1271 * @retval State of bit (1 or 0).
1272 */
LL_UCPD_IsEnableIT_TxMSGDISC(UCPD_TypeDef const * const UCPDx)1273 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGDISC(UCPD_TypeDef const *const UCPDx)
1274 {
1275 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE) == UCPD_IMR_TXMSGDISCIE) ? 1UL : 0UL);
1276 }
1277
1278 /**
1279 * @brief Check if Tx data receive interrupt enabled
1280 * @rmtoll IMR TXISIE LL_UCPD_IsEnableIT_TxIS
1281 * @param UCPDx UCPD Instance
1282 * @retval State of bit (1 or 0).
1283 */
LL_UCPD_IsEnableIT_TxIS(UCPD_TypeDef const * const UCPDx)1284 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxIS(UCPD_TypeDef const *const UCPDx)
1285 {
1286 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXISIE) == UCPD_IMR_TXISIE) ? 1UL : 0UL);
1287 }
1288
1289 /**
1290 * @}
1291 */
1292
1293 /** @defgroup UCPD_LL_EF_IT_Clear Interrupt Clear
1294 * @{
1295 */
1296
1297 /**
1298 * @brief Clear FRS interrupt
1299 * @rmtoll ICR FRSEVTIE LL_UCPD_ClearFlag_FRS
1300 * @param UCPDx UCPD Instance
1301 * @retval None
1302 */
LL_UCPD_ClearFlag_FRS(UCPD_TypeDef * UCPDx)1303 __STATIC_INLINE void LL_UCPD_ClearFlag_FRS(UCPD_TypeDef *UCPDx)
1304 {
1305 SET_BIT(UCPDx->ICR, UCPD_ICR_FRSEVTCF);
1306 }
1307
1308 /**
1309 * @brief Clear type c event on CC2
1310 * @rmtoll IIMR TYPECEVT2IE LL_UCPD_ClearFlag_TypeCEventCC2
1311 * @param UCPDx UCPD Instance
1312 * @retval None
1313 */
LL_UCPD_ClearFlag_TypeCEventCC2(UCPD_TypeDef * UCPDx)1314 __STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC2(UCPD_TypeDef *UCPDx)
1315 {
1316 SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT2CF);
1317 }
1318
1319 /**
1320 * @brief Clear type c event on CC1
1321 * @rmtoll IIMR TYPECEVT1IE LL_UCPD_ClearFlag_TypeCEventCC1
1322 * @param UCPDx UCPD Instance
1323 * @retval None
1324 */
LL_UCPD_ClearFlag_TypeCEventCC1(UCPD_TypeDef * UCPDx)1325 __STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC1(UCPD_TypeDef *UCPDx)
1326 {
1327 SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT1CF);
1328 }
1329
1330 /**
1331 * @brief Clear Rx message end interrupt
1332 * @rmtoll ICR RXMSGENDIE LL_UCPD_ClearFlag_RxMsgEnd
1333 * @param UCPDx UCPD Instance
1334 * @retval None
1335 */
LL_UCPD_ClearFlag_RxMsgEnd(UCPD_TypeDef * UCPDx)1336 __STATIC_INLINE void LL_UCPD_ClearFlag_RxMsgEnd(UCPD_TypeDef *UCPDx)
1337 {
1338 SET_BIT(UCPDx->ICR, UCPD_ICR_RXMSGENDCF);
1339 }
1340
1341 /**
1342 * @brief Clear Rx overrun interrupt
1343 * @rmtoll ICR RXOVRIE LL_UCPD_ClearFlag_RxOvr
1344 * @param UCPDx UCPD Instance
1345 * @retval None
1346 */
LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef * UCPDx)1347 __STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx)
1348 {
1349 SET_BIT(UCPDx->ICR, UCPD_ICR_RXOVRCF);
1350 }
1351
1352 /**
1353 * @brief Clear Rx hard resrt interrupt
1354 * @rmtoll ICR RXHRSTDETIE LL_UCPD_ClearFlag_RxHRST
1355 * @param UCPDx UCPD Instance
1356 * @retval None
1357 */
LL_UCPD_ClearFlag_RxHRST(UCPD_TypeDef * UCPDx)1358 __STATIC_INLINE void LL_UCPD_ClearFlag_RxHRST(UCPD_TypeDef *UCPDx)
1359 {
1360 SET_BIT(UCPDx->ICR, UCPD_ICR_RXHRSTDETCF);
1361 }
1362
1363 /**
1364 * @brief Clear Rx orderset interrupt
1365 * @rmtoll ICR RXORDDETIE LL_UCPD_ClearFlag_RxOrderSet
1366 * @param UCPDx UCPD Instance
1367 * @retval None
1368 */
LL_UCPD_ClearFlag_RxOrderSet(UCPD_TypeDef * UCPDx)1369 __STATIC_INLINE void LL_UCPD_ClearFlag_RxOrderSet(UCPD_TypeDef *UCPDx)
1370 {
1371 SET_BIT(UCPDx->ICR, UCPD_ICR_RXORDDETCF);
1372 }
1373
1374 /**
1375 * @brief Clear TX underrun interrupt
1376 * @rmtoll ICR TXUNDIE LL_UCPD_ClearFlag_TxUND
1377 * @param UCPDx UCPD Instance
1378 * @retval None
1379 */
LL_UCPD_ClearFlag_TxUND(UCPD_TypeDef * UCPDx)1380 __STATIC_INLINE void LL_UCPD_ClearFlag_TxUND(UCPD_TypeDef *UCPDx)
1381 {
1382 SET_BIT(UCPDx->ICR, UCPD_ICR_TXUNDCF);
1383 }
1384
1385 /**
1386 * @brief Clear hard reset sent interrupt
1387 * @rmtoll ICR HRSTSENTIE LL_UCPD_ClearFlag_TxHRSTSENT
1388 * @param UCPDx UCPD Instance
1389 * @retval None
1390 */
LL_UCPD_ClearFlag_TxHRSTSENT(UCPD_TypeDef * UCPDx)1391 __STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTSENT(UCPD_TypeDef *UCPDx)
1392 {
1393 SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTSENTCF);
1394 }
1395
1396 /**
1397 * @brief Clear hard reset discard interrupt
1398 * @rmtoll ICR HRSTDISCIE LL_UCPD_ClearFlag_TxHRSTDISC
1399 * @param UCPDx UCPD Instance
1400 * @retval None
1401 */
LL_UCPD_ClearFlag_TxHRSTDISC(UCPD_TypeDef * UCPDx)1402 __STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTDISC(UCPD_TypeDef *UCPDx)
1403 {
1404 SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTDISCCF);
1405 }
1406
1407 /**
1408 * @brief Clear Tx message abort interrupt
1409 * @rmtoll ICR TXMSGABTIE LL_UCPD_ClearFlag_TxMSGABT
1410 * @param UCPDx UCPD Instance
1411 * @retval None
1412 */
LL_UCPD_ClearFlag_TxMSGABT(UCPD_TypeDef * UCPDx)1413 __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGABT(UCPD_TypeDef *UCPDx)
1414 {
1415 SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGABTCF);
1416 }
1417
1418 /**
1419 * @brief Clear Tx message sent interrupt
1420 * @rmtoll ICR TXMSGSENTIE LL_UCPD_ClearFlag_TxMSGSENT
1421 * @param UCPDx UCPD Instance
1422 * @retval None
1423 */
LL_UCPD_ClearFlag_TxMSGSENT(UCPD_TypeDef * UCPDx)1424 __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGSENT(UCPD_TypeDef *UCPDx)
1425 {
1426 SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGSENTCF);
1427 }
1428
1429 /**
1430 * @brief Clear Tx message discarded interrupt
1431 * @rmtoll ICR TXMSGDISCIE LL_UCPD_ClearFlag_TxMSGDISC
1432 * @param UCPDx UCPD Instance
1433 * @retval None
1434 */
LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef * UCPDx)1435 __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx)
1436 {
1437 SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGDISCCF);
1438 }
1439
1440 /**
1441 * @}
1442 */
1443
1444 /** @defgroup UCPD_LL_EF_FLAG_Management FLAG Management
1445 * @{
1446 */
1447
1448 /**
1449 * @brief Check if FRS interrupt
1450 * @rmtoll SR FRSEVT LL_UCPD_IsActiveFlag_FRS
1451 * @param UCPDx UCPD Instance
1452 * @retval None
1453 */
LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const * const UCPDx)1454 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPDx)
1455 {
1456 return ((READ_BIT(UCPDx->SR, UCPD_SR_FRSEVT) == UCPD_SR_FRSEVT) ? 1UL : 0UL);
1457 }
1458
1459 /**
1460 * @brief Check if type c event on CC2
1461 * @rmtoll SR TYPECEVT2 LL_UCPD_IsActiveFlag_TypeCEventCC2
1462 * @param UCPDx UCPD Instance
1463 * @retval None
1464 */
LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const * const UCPDx)1465 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx)
1466 {
1467 return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT2) == UCPD_SR_TYPECEVT2) ? 1UL : 0UL);
1468 }
1469
1470 /**
1471 * @brief Check if type c event on CC1
1472 * @rmtoll SR TYPECEVT1 LL_UCPD_IsActiveFlag_TypeCEventCC1
1473 * @param UCPDx UCPD Instance
1474 * @retval None
1475 */
LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const * const UCPDx)1476 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx)
1477 {
1478 return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT1) == UCPD_SR_TYPECEVT1) ? 1UL : 0UL);
1479 }
1480
1481 /**
1482 * @brief Check if Rx message end interrupt
1483 * @rmtoll SR RXMSGEND LL_UCPD_IsActiveFlag_RxMsgEnd
1484 * @param UCPDx UCPD Instance
1485 * @retval None
1486 */
LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const * const UCPDx)1487 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx)
1488 {
1489 return ((READ_BIT(UCPDx->SR, UCPD_SR_RXMSGEND) == UCPD_SR_RXMSGEND) ? 1UL : 0UL);
1490 }
1491
1492 /**
1493 * @brief Check if Rx overrun interrupt
1494 * @rmtoll SR RXOVR LL_UCPD_IsActiveFlag_RxOvr
1495 * @param UCPDx UCPD Instance
1496 * @retval None
1497 */
LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const * const UCPDx)1498 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx)
1499 {
1500 return ((READ_BIT(UCPDx->SR, UCPD_SR_RXOVR) == UCPD_SR_RXOVR) ? 1UL : 0UL);
1501 }
1502
1503 /**
1504 * @brief Check if Rx hard resrt interrupt
1505 * @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST
1506 * @param UCPDx UCPD Instance
1507 * @retval None
1508 */
LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const * const UCPDx)1509 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx)
1510 {
1511 return ((READ_BIT(UCPDx->SR, UCPD_SR_RXHRSTDET) == UCPD_SR_RXHRSTDET) ? 1UL : 0UL);
1512 }
1513
1514 /**
1515 * @brief Check if Rx orderset interrupt
1516 * @rmtoll SR RXORDDET LL_UCPD_IsActiveFlag_RxOrderSet
1517 * @param UCPDx UCPD Instance
1518 * @retval State of bit (1 or 0).
1519 */
LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const * const UCPDx)1520 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *const UCPDx)
1521 {
1522 return ((READ_BIT(UCPDx->SR, UCPD_SR_RXORDDET) == UCPD_SR_RXORDDET) ? 1UL : 0UL);
1523 }
1524
1525 /**
1526 * @brief Check if Rx non empty interrupt
1527 * @rmtoll SR RXNE LL_UCPD_IsActiveFlag_RxNE
1528 * @param UCPDx UCPD Instance
1529 * @retval State of bit (1 or 0).
1530 */
LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const * const UCPDx)1531 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCPDx)
1532 {
1533 return ((READ_BIT(UCPDx->SR, UCPD_SR_RXNE) == UCPD_SR_RXNE) ? 1UL : 0UL);
1534 }
1535
1536 /**
1537 * @brief Check if TX underrun interrupt
1538 * @rmtoll SR TXUND LL_UCPD_IsActiveFlag_TxUND
1539 * @param UCPDx UCPD Instance
1540 * @retval State of bit (1 or 0).
1541 */
LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const * const UCPDx)1542 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UCPDx)
1543 {
1544 return ((READ_BIT(UCPDx->SR, UCPD_SR_TXUND) == UCPD_SR_TXUND) ? 1UL : 0UL);
1545 }
1546
1547 /**
1548 * @brief Check if hard reset sent interrupt
1549 * @rmtoll SR HRSTSENT LL_UCPD_IsActiveFlag_TxHRSTSENT
1550 * @param UCPDx UCPD Instance
1551 * @retval State of bit (1 or 0).
1552 */
LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const * const UCPDx)1553 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *const UCPDx)
1554 {
1555 return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTSENT) == UCPD_SR_HRSTSENT) ? 1UL : 0UL);
1556 }
1557
1558 /**
1559 * @brief Check if hard reset discard interrupt
1560 * @rmtoll SR HRSTDISC LL_UCPD_IsActiveFlag_TxHRSTDISC
1561 * @param UCPDx UCPD Instance
1562 * @retval State of bit (1 or 0).
1563 */
LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const * const UCPDx)1564 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *const UCPDx)
1565 {
1566 return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTDISC) == UCPD_SR_HRSTDISC) ? 1UL : 0UL);
1567 }
1568
1569 /**
1570 * @brief Check if Tx message abort interrupt
1571 * @rmtoll SR TXMSGABT LL_UCPD_IsActiveFlag_TxMSGABT
1572 * @param UCPDx UCPD Instance
1573 * @retval State of bit (1 or 0).
1574 */
LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const * const UCPDx)1575 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const UCPDx)
1576 {
1577 return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGABT) == UCPD_SR_TXMSGABT) ? 1UL : 0UL);
1578 }
1579
1580 /**
1581 * @brief Check if Tx message sent interrupt
1582 * @rmtoll SR TXMSGSENT LL_UCPD_IsActiveFlag_TxMSGSENT
1583 * @param UCPDx UCPD Instance
1584 * @retval State of bit (1 or 0).
1585 */
LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const * const UCPDx)1586 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *const UCPDx)
1587 {
1588 return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGSENT) == UCPD_SR_TXMSGSENT) ? 1UL : 0UL);
1589 }
1590
1591 /**
1592 * @brief Check if Tx message discarded interrupt
1593 * @rmtoll SR TXMSGDISC LL_UCPD_IsActiveFlag_TxMSGDISC
1594 * @param UCPDx UCPD Instance
1595 * @retval State of bit (1 or 0).
1596 */
LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const * const UCPDx)1597 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *const UCPDx)
1598 {
1599 return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGDISC) == UCPD_SR_TXMSGDISC) ? 1UL : 0UL);
1600 }
1601
1602 /**
1603 * @brief Check if Tx data receive interrupt
1604 * @rmtoll SR TXIS LL_UCPD_IsActiveFlag_TxIS
1605 * @param UCPDx UCPD Instance
1606 * @retval State of bit (1 or 0).
1607 */
LL_UCPD_IsActiveFlag_TxIS(UCPD_TypeDef const * const UCPDx)1608 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxIS(UCPD_TypeDef const *const UCPDx)
1609 {
1610 return ((READ_BIT(UCPDx->SR, UCPD_SR_TXIS) == UCPD_SR_TXIS) ? 1UL : 0UL);
1611 }
1612
1613 /**
1614 * @brief return the vstate value for CC2
1615 * @rmtoll SR TXIS LL_UCPD_GetTypeCVstateCC2
1616 * @param UCPDx UCPD Instance
1617 * @retval val
1618 */
LL_UCPD_GetTypeCVstateCC2(UCPD_TypeDef const * const UCPDx)1619 __STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC2(UCPD_TypeDef const *const UCPDx)
1620 {
1621 return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC2;
1622 }
1623
1624 /**
1625 * @brief return the vstate value for CC1
1626 * @rmtoll SR TXIS LL_UCPD_GetTypeCVstateCC1
1627 * @param UCPDx UCPD Instance
1628 * @retval val
1629 */
LL_UCPD_GetTypeCVstateCC1(UCPD_TypeDef const * const UCPDx)1630 __STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC1(UCPD_TypeDef const *const UCPDx)
1631 {
1632 return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC1;
1633 }
1634
1635 /**
1636 * @}
1637 */
1638
1639
1640 /** @defgroup UCPD_LL_EF_DMA_Management DMA Management
1641 * @{
1642 */
1643
1644 /**
1645 * @brief Rx DMA Enable
1646 * @rmtoll CFG1 RXDMAEN LL_UCPD_RxDMAEnable
1647 * @param UCPDx UCPD Instance
1648 * @retval None
1649 */
LL_UCPD_RxDMAEnable(UCPD_TypeDef * UCPDx)1650 __STATIC_INLINE void LL_UCPD_RxDMAEnable(UCPD_TypeDef *UCPDx)
1651 {
1652 SET_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN);
1653 }
1654
1655 /**
1656 * @brief Rx DMA Disable
1657 * @rmtoll CFG1 RXDMAEN LL_UCPD_RxDMADisable
1658 * @param UCPDx UCPD Instance
1659 * @retval None
1660 */
LL_UCPD_RxDMADisable(UCPD_TypeDef * UCPDx)1661 __STATIC_INLINE void LL_UCPD_RxDMADisable(UCPD_TypeDef *UCPDx)
1662 {
1663 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN);
1664 }
1665
1666 /**
1667 * @brief Tx DMA Enable
1668 * @rmtoll CFG1 TXDMAEN LL_UCPD_TxDMAEnable
1669 * @param UCPDx UCPD Instance
1670 * @retval None
1671 */
LL_UCPD_TxDMAEnable(UCPD_TypeDef * UCPDx)1672 __STATIC_INLINE void LL_UCPD_TxDMAEnable(UCPD_TypeDef *UCPDx)
1673 {
1674 SET_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN);
1675 }
1676
1677 /**
1678 * @brief Tx DMA Disable
1679 * @rmtoll CFG1 TXDMAEN LL_UCPD_TxDMADisable
1680 * @param UCPDx UCPD Instance
1681 * @retval None
1682 */
LL_UCPD_TxDMADisable(UCPD_TypeDef * UCPDx)1683 __STATIC_INLINE void LL_UCPD_TxDMADisable(UCPD_TypeDef *UCPDx)
1684 {
1685 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN);
1686 }
1687
1688 /**
1689 * @brief Check if DMA Tx is enabled
1690 * @rmtoll CR2 TXDMAEN LL_UCPD_IsEnabledTxDMA
1691 * @param UCPDx UCPD Instance
1692 * @retval State of bit (1 or 0).
1693 */
LL_UCPD_IsEnabledTxDMA(UCPD_TypeDef const * const UCPDx)1694 __STATIC_INLINE uint32_t LL_UCPD_IsEnabledTxDMA(UCPD_TypeDef const *const UCPDx)
1695 {
1696 return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN) == (UCPD_CFG1_TXDMAEN)) ? 1UL : 0UL);
1697 }
1698
1699 /**
1700 * @brief Check if DMA Rx is enabled
1701 * @rmtoll CR2 RXDMAEN LL_UCPD_IsEnabledRxDMA
1702 * @param UCPDx UCPD Instance
1703 * @retval State of bit (1 or 0).
1704 */
LL_UCPD_IsEnabledRxDMA(UCPD_TypeDef const * const UCPDx)1705 __STATIC_INLINE uint32_t LL_UCPD_IsEnabledRxDMA(UCPD_TypeDef const *const UCPDx)
1706 {
1707 return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN) == (UCPD_CFG1_RXDMAEN)) ? 1UL : 0UL);
1708 }
1709
1710 /**
1711 * @}
1712 */
1713
1714 /** @defgroup UCPD_LL_EF_DATA_Management DATA Management
1715 * @{
1716 */
1717
1718 /**
1719 * @brief write the orderset for Tx message
1720 * @rmtoll TX_ORDSET TXORDSET LL_UCPD_WriteTxOrderSet
1721 * @param UCPDx UCPD Instance
1722 * @param TxOrderSet one of the following value
1723 * @arg @ref LL_UCPD_ORDERED_SET_SOP
1724 * @arg @ref LL_UCPD_ORDERED_SET_SOP1
1725 * @arg @ref LL_UCPD_ORDERED_SET_SOP2
1726 * @arg @ref LL_UCPD_ORDERED_SET_HARD_RESET
1727 * @arg @ref LL_UCPD_ORDERED_SET_CABLE_RESET
1728 * @arg @ref LL_UCPD_ORDERED_SET_SOP1_DEBUG
1729 * @arg @ref LL_UCPD_ORDERED_SET_SOP2_DEBUG
1730 * @retval None
1731 */
LL_UCPD_WriteTxOrderSet(UCPD_TypeDef * UCPDx,uint32_t TxOrderSet)1732 __STATIC_INLINE void LL_UCPD_WriteTxOrderSet(UCPD_TypeDef *UCPDx, uint32_t TxOrderSet)
1733 {
1734 WRITE_REG(UCPDx->TX_ORDSET, TxOrderSet);
1735 }
1736
1737 /**
1738 * @brief write the Tx paysize
1739 * @rmtoll TX_PAYSZ TXPAYSZ LL_UCPD_WriteTxPaySize
1740 * @param UCPDx UCPD Instance
1741 * @param TxPaySize
1742 * @retval None.
1743 */
LL_UCPD_WriteTxPaySize(UCPD_TypeDef * UCPDx,uint32_t TxPaySize)1744 __STATIC_INLINE void LL_UCPD_WriteTxPaySize(UCPD_TypeDef *UCPDx, uint32_t TxPaySize)
1745 {
1746 WRITE_REG(UCPDx->TX_PAYSZ, TxPaySize);
1747 }
1748
1749 /**
1750 * @brief Write data
1751 * @rmtoll TXDR DR LL_UCPD_WriteData
1752 * @param UCPDx UCPD Instance
1753 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1754 * @retval None.
1755 */
LL_UCPD_WriteData(UCPD_TypeDef * UCPDx,uint8_t Data)1756 __STATIC_INLINE void LL_UCPD_WriteData(UCPD_TypeDef *UCPDx, uint8_t Data)
1757 {
1758 WRITE_REG(UCPDx->TXDR, Data);
1759 }
1760
1761 /**
1762 * @brief read RX the orderset
1763 * @rmtoll RX_ORDSET RXORDSET LL_UCPD_ReadRxOrderSet
1764 * @param UCPDx UCPD Instance
1765 * @retval RxOrderSet one of the following value
1766 * @arg @ref LL_UCPD_RXORDSET_SOP
1767 * @arg @ref LL_UCPD_RXORDSET_SOP1
1768 * @arg @ref LL_UCPD_RXORDSET_SOP2
1769 * @arg @ref LL_UCPD_RXORDSET_SOP1_DEBUG
1770 * @arg @ref LL_UCPD_RXORDSET_SOP2_DEBUG
1771 * @arg @ref LL_UCPD_RXORDSET_CABLE_RESET
1772 * @arg @ref LL_UCPD_RXORDSET_SOPEXT1
1773 * @arg @ref LL_UCPD_RXORDSET_SOPEXT2
1774 */
LL_UCPD_ReadRxOrderSet(UCPD_TypeDef const * const UCPDx)1775 __STATIC_INLINE uint32_t LL_UCPD_ReadRxOrderSet(UCPD_TypeDef const *const UCPDx)
1776 {
1777 return READ_BIT(UCPDx->RX_ORDSET, UCPD_RX_ORDSET_RXORDSET);
1778 }
1779
1780 /**
1781 * @brief Read the Rx paysize
1782 * @rmtoll RX_PAYSZ RXPAYSZ LL_UCPD_ReadRxPaySize
1783 * @param UCPDx UCPD Instance
1784 * @retval RXPaysize.
1785 */
LL_UCPD_ReadRxPaySize(UCPD_TypeDef const * const UCPDx)1786 __STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const *const UCPDx)
1787 {
1788 return READ_BIT(UCPDx->RX_PAYSZ, UCPD_RX_PAYSZ_RXPAYSZ);
1789 }
1790
1791 /**
1792 * @brief Read data
1793 * @rmtoll RXDR RXDATA LL_UCPD_ReadData
1794 * @param UCPDx UCPD Instance
1795 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
1796 */
LL_UCPD_ReadData(UCPD_TypeDef const * const UCPDx)1797 __STATIC_INLINE uint32_t LL_UCPD_ReadData(UCPD_TypeDef const *const UCPDx)
1798 {
1799 return READ_REG(UCPDx->RXDR);
1800 }
1801
1802 /**
1803 * @brief Set Rx OrderSet Ext1
1804 * @rmtoll RX_ORDEXT1 RXSOPX1 LL_UCPD_SetRxOrdExt1
1805 * @param UCPDx UCPD Instance
1806 * @param SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF
1807 * @retval None
1808 */
LL_UCPD_SetRxOrdExt1(UCPD_TypeDef * UCPDx,uint32_t SOPExt)1809 __STATIC_INLINE void LL_UCPD_SetRxOrdExt1(UCPD_TypeDef *UCPDx, uint32_t SOPExt)
1810 {
1811 WRITE_REG(UCPDx->RX_ORDEXT1, SOPExt);
1812 }
1813
1814 /**
1815 * @brief Set Rx OrderSet Ext2
1816 * @rmtoll RX_ORDEXT2 RXSOPX2 LL_UCPD_SetRxOrdExt2
1817 * @param UCPDx UCPD Instance
1818 * @param SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF
1819 * @retval None
1820 */
LL_UCPD_SetRxOrdExt2(UCPD_TypeDef * UCPDx,uint32_t SOPExt)1821 __STATIC_INLINE void LL_UCPD_SetRxOrdExt2(UCPD_TypeDef *UCPDx, uint32_t SOPExt)
1822 {
1823 WRITE_REG(UCPDx->RX_ORDEXT2, SOPExt);
1824 }
1825
1826 /**
1827 * @}
1828 */
1829
1830 #if defined(USE_FULL_LL_DRIVER)
1831 /** @defgroup UCPD_LL_EF_Init Initialization and de-initialization functions
1832 * @{
1833 */
1834
1835 ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx);
1836 ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct);
1837 void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct);
1838
1839 /**
1840 * @}
1841 */
1842 #endif /* USE_FULL_LL_DRIVER */
1843
1844 /**
1845 * @}
1846 */
1847
1848 #endif /* defined (UCPD1) */
1849
1850 /**
1851 * @}
1852 */
1853
1854 /**
1855 * @}
1856 */
1857
1858 #ifdef __cplusplus
1859 }
1860 #endif
1861
1862 #endif /* STM32L5xx_LL_UCPD_H */
1863
1864
