1 /**
2 ******************************************************************************
3 * @file stm32l5xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 *
7 ******************************************************************************
8 * @attention
9 *
10 * Copyright (c) 2019 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file
14 * in the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 @verbatim
19 ==============================================================================
20 ##### How to use this driver #####
21 ==============================================================================
22 [..]
23 The LL SYSTEM driver contains a set of generic APIs that can be
24 used by user:
25 (+) Some of the FLASH features need to be handled in the SYSTEM file.
26 (+) Access to DBGCMU registers
27 (+) Access to SYSCFG registers
28 (+) Access to VREFBUF registers
29
30 @endverbatim
31 ******************************************************************************
32 */
33
34 /* Define to prevent recursive inclusion -------------------------------------*/
35 #ifndef STM32L5xx_LL_SYSTEM_H
36 #define STM32L5xx_LL_SYSTEM_H
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 /* Includes ------------------------------------------------------------------*/
43 #include "stm32l5xx.h"
44
45 /** @addtogroup STM32L5xx_LL_Driver
46 * @{
47 */
48
49 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
50
51 /** @defgroup SYSTEM_LL SYSTEM
52 * @{
53 */
54
55 /* Private types -------------------------------------------------------------*/
56 /* Private variables ---------------------------------------------------------*/
57
58 /* Private constants ---------------------------------------------------------*/
59 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
60 * @{
61 */
62 /**
63 * @brief VREFBUF VREF_SC0 & VREF_SC1 calibration values
64 */
65 #define VREFBUF_SC0_CAL_ADDR ((uint8_t*) (0x0BFA0579UL)) /*!< Address of VREFBUF trimming value for VRS=0,
66 VREF_SC0 in STM32L5 datasheet */
67 #define VREFBUF_SC1_CAL_ADDR ((uint8_t*) (0x0BFA0530UL)) /*!< Address of VREFBUF trimming value for VRS=1,
68 VREF_SC1 in STM32L5 datasheet */
69
70 /**
71 * @brief Power-down in Run mode Flash key
72 */
73 #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */
74 #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1
75 to unlock the RUN_PD bit in FLASH_ACR */
76
77 /**
78 * @}
79 */
80
81 /* Private macros ------------------------------------------------------------*/
82
83 /* Exported types ------------------------------------------------------------*/
84 /* Exported constants --------------------------------------------------------*/
85 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
86 * @{
87 */
88
89 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
90 * @{
91 */
92 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
93 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
94 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
95 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
96 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
97 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
98 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
99 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
100 /**
101 * @}
102 */
103
104 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
105 * @{
106 */
107 #define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
108 with Break Input of TIM1/8/15/16/17 */
109 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
110 with TIM1/8/15/16/17 Break Input
111 and also the PVDE and PLS bits of the Power Control Interface */
112 #define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal
113 with Break Input of TIM1/8/15/16/17 */
114 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4
115 with Break Input of TIM1/15/16/17 */
116 /**
117 * @}
118 */
119
120 /** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRP
121 * @{
122 */
123 #define LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_P0WP /*!< SRAM2 Write protection page 0 */
124 #define LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_P1WP /*!< SRAM2 Write protection page 1 */
125 #define LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_P2WP /*!< SRAM2 Write protection page 2 */
126 #define LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_P3WP /*!< SRAM2 Write protection page 3 */
127 #define LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_P4WP /*!< SRAM2 Write protection page 4 */
128 #define LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_P5WP /*!< SRAM2 Write protection page 5 */
129 #define LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_P6WP /*!< SRAM2 Write protection page 6 */
130 #define LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_P7WP /*!< SRAM2 Write protection page 7 */
131 #define LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_P8WP /*!< SRAM2 Write protection page 8 */
132 #define LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_P9WP /*!< SRAM2 Write protection page 9 */
133 #define LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_P10WP /*!< SRAM2 Write protection page 10 */
134 #define LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_P11WP /*!< SRAM2 Write protection page 11 */
135 #define LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_P12WP /*!< SRAM2 Write protection page 12 */
136 #define LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_P13WP /*!< SRAM2 Write protection page 13 */
137 #define LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_P14WP /*!< SRAM2 Write protection page 14 */
138 #define LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_P15WP /*!< SRAM2 Write protection page 15 */
139 #define LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_P16WP /*!< SRAM2 Write protection page 16 */
140 #define LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_P17WP /*!< SRAM2 Write protection page 17 */
141 #define LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_P18WP /*!< SRAM2 Write protection page 18 */
142 #define LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_P19WP /*!< SRAM2 Write protection page 19 */
143 #define LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_P20WP /*!< SRAM2 Write protection page 20 */
144 #define LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_P21WP /*!< SRAM2 Write protection page 21 */
145 #define LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_P22WP /*!< SRAM2 Write protection page 22 */
146 #define LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_P23WP /*!< SRAM2 Write protection page 23 */
147 #define LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_P24WP /*!< SRAM2 Write protection page 24 */
148 #define LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_P25WP /*!< SRAM2 Write protection page 25 */
149 #define LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_P26WP /*!< SRAM2 Write protection page 26 */
150 #define LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_P27WP /*!< SRAM2 Write protection page 27 */
151 #define LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_P28WP /*!< SRAM2 Write protection page 28 */
152 #define LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_P29WP /*!< SRAM2 Write protection page 29 */
153 #define LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_P30WP /*!< SRAM2 Write protection page 30 */
154 #define LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_P31WP /*!< SRAM2 Write protection page 31 */
155 #define LL_SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_P32WP /*!< SRAM2 Write protection page 32 */
156 #define LL_SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_P33WP /*!< SRAM2 Write protection page 33 */
157 #define LL_SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_P34WP /*!< SRAM2 Write protection page 34 */
158 #define LL_SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_P35WP /*!< SRAM2 Write protection page 35 */
159 #define LL_SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_P36WP /*!< SRAM2 Write protection page 36 */
160 #define LL_SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_P37WP /*!< SRAM2 Write protection page 37 */
161 #define LL_SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_P38WP /*!< SRAM2 Write protection page 38 */
162 #define LL_SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_P39WP /*!< SRAM2 Write protection page 39 */
163 #define LL_SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_P40WP /*!< SRAM2 Write protection page 40 */
164 #define LL_SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_P41WP /*!< SRAM2 Write protection page 41 */
165 #define LL_SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_P42WP /*!< SRAM2 Write protection page 42 */
166 #define LL_SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_P43WP /*!< SRAM2 Write protection page 43 */
167 #define LL_SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_P44WP /*!< SRAM2 Write protection page 44 */
168 #define LL_SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_P45WP /*!< SRAM2 Write protection page 45 */
169 #define LL_SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_P46WP /*!< SRAM2 Write protection page 46 */
170 #define LL_SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_P47WP /*!< SRAM2 Write protection page 47 */
171 #define LL_SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_P48WP /*!< SRAM2 Write protection page 48 */
172 #define LL_SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_P49WP /*!< SRAM2 Write protection page 49 */
173 #define LL_SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_P50WP /*!< SRAM2 Write protection page 50 */
174 #define LL_SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_P51WP /*!< SRAM2 Write protection page 51 */
175 #define LL_SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_P52WP /*!< SRAM2 Write protection page 52 */
176 #define LL_SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_P53WP /*!< SRAM2 Write protection page 53 */
177 #define LL_SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_P54WP /*!< SRAM2 Write protection page 54 */
178 #define LL_SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_P55WP /*!< SRAM2 Write protection page 55 */
179 #define LL_SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_P56WP /*!< SRAM2 Write protection page 56 */
180 #define LL_SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_P57WP /*!< SRAM2 Write protection page 57 */
181 #define LL_SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_P58WP /*!< SRAM2 Write protection page 58 */
182 #define LL_SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_P59WP /*!< SRAM2 Write protection page 59 */
183 #define LL_SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_P60WP /*!< SRAM2 Write protection page 60 */
184 #define LL_SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_P61WP /*!< SRAM2 Write protection page 61 */
185 #define LL_SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_P62WP /*!< SRAM2 Write protection page 62 */
186 #define LL_SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_P63WP /*!< SRAM2 Write protection page 63 */
187 /**
188 * @}
189 */
190
191 /** @defgroup SYSTEM_LL_EC_SECURE_ATTRIBUTES Secure attributes
192 * @note Only available when system implements security (TZEN=1)
193 * @{
194 */
195 #define LL_SYSCFG_CLOCK_SEC SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock configuration secure-only access */
196 #define LL_SYSCFG_CLOCK_NSEC 0U /*!< SYSCFG clock configuration secure/non-secure access */
197 #define LL_SYSCFG_CLASSB_SEC SYSCFG_SECCFGR_CLASSBSEC /*!< Class B configuration secure-only access */
198 #define LL_SYSCFG_CLASSB_NSEC 0U /*!< Class B configuration secure/non-secure access */
199 #define LL_SYSCFG_SRAM2_SEC SYSCFG_SECCFGR_SRAM2SEC /*!< SRAM2 configuration secure-only access */
200 #define LL_SYSCFG_SRAM2_NSEC 0U /*!< SRAM2 configuration secure/non-secure access */
201 #define LL_SYSCFG_FPU_SEC SYSCFG_SECCFGR_FPUSEC /*!< FPU configuration secure-only access */
202 #define LL_SYSCFG_FPU_NSEC 0U /*!< FPU configuration secure/non-secure access */
203 /**
204 * @}
205 */
206
207 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
208 * @{
209 */
210 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
211 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
212 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
213 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
214 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
215 /**
216 * @}
217 */
218
219 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP DBGMCU APB1 GRP1 STOP
220 * @{
221 */
222 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/
223 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/
224 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/
225 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/
226 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/
227 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/
228 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted*/
229 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/
230 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/
231 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/
232 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/
233 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen*/
234 #define LL_DBGMCU_APB1_GRP1_FDCAN1_STOP DBGMCU_APB1FZR1_DBG_FDCAN1_STOP /*!< The FDCAN1 receive registers are frozen*/
235 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
236 /**
237 * @}
238 */
239
240 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP DBGMCU APB1 GRP2 STOP
241 * @{
242 */
243 #define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/
244 #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
245 #define LL_DBGMCU_APB1_GRP2_LPTIM3_STOP DBGMCU_APB1FZR2_DBG_LPTIM3_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
246 /**
247 * @}
248 */
249
250 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP DBGMCU APB2 GRP1 STOP
251 * @{
252 */
253 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/
254 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/
255 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/
256 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/
257 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/
258 /**
259 * @}
260 */
261
262 #if defined(VREFBUF)
263 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
264 * @{
265 */
266 #define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
267 #define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */
268 /**
269 * @}
270 */
271 #endif /* VREFBUF */
272
273 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
274 * @{
275 */
276 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH zero wait state */
277 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH one wait state */
278 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH two wait states */
279 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH three wait states */
280 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH four wait states */
281 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait states */
282 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
283 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */
284 #define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */
285 #define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */
286 #define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */
287 #define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
288 #define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
289 #define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
290 #define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
291 #define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
292 /**
293 * @}
294 */
295
296 /**
297 * @}
298 */
299
300 /* Exported macro ------------------------------------------------------------*/
301
302 /* Exported functions --------------------------------------------------------*/
303 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
304 * @{
305 */
306
307 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
308 * @{
309 */
310
311 /**
312 * @brief Enable I/O analog switches supplied by VDD.
313 * @rmtoll SYSCFG_CFGR1 ANASWVDD LL_SYSCFG_EnableAnalogSwitchVdd
314 * @retval None
315 */
LL_SYSCFG_EnableAnalogSwitchVdd(void)316 __STATIC_INLINE void LL_SYSCFG_EnableAnalogSwitchVdd(void)
317 {
318 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
319 }
320
321 /**
322 * @brief Disable I/O analog switches supplied by VDD.
323 * @note I/O analog switches are supplied by VDDA or booster
324 * when booster in on.
325 * Dedicated voltage booster (supplied by VDD) is the recommended
326 * configuration with low VDDA voltage operation.
327 * @rmtoll SYSCFG_CFGR1 ANASWVDD LL_SYSCFG_DisableAnalogSwitchVdd
328 * @retval None
329 */
LL_SYSCFG_DisableAnalogSwitchVdd(void)330 __STATIC_INLINE void LL_SYSCFG_DisableAnalogSwitchVdd(void)
331 {
332 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
333 }
334
335 /**
336 * @brief Enable I/O analog switch voltage booster.
337 * @note When voltage booster is enabled, I/O analog switches are supplied
338 * by a dedicated voltage booster, from VDD power domain. This is
339 * the recommended configuration with low VDDA voltage operation.
340 * @note The I/O analog switch voltage booster is relevant for peripherals
341 * using I/O in analog input: ADC, COMP, OPAMP.
342 * However, COMP and OPAMP inputs have a high impedance and
343 * voltage booster do not impact performance significantly.
344 * Therefore, the voltage booster is mainly intended for
345 * usage with ADC.
346 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
347 * @retval None
348 */
LL_SYSCFG_EnableAnalogBooster(void)349 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
350 {
351 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
352 }
353
354 /**
355 * @brief Disable I/O analog switch voltage booster.
356 * @note When voltage booster is enabled, I/O analog switches are supplied
357 * by a dedicated voltage booster, from VDD power domain. This is
358 * the recommended configuration with low VDDA voltage operation.
359 * @note The I/O analog switch voltage booster is relevant for peripherals
360 * using I/O in analog input: ADC, COMP, OPAMP.
361 * However, COMP and OPAMP inputs have a high impedance and
362 * voltage booster do not impact performance significantly.
363 * Therefore, the voltage booster is mainly intended for
364 * usage with ADC.
365 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
366 * @retval None
367 */
LL_SYSCFG_DisableAnalogBooster(void)368 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
369 {
370 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
371 }
372
373 /**
374 * @brief Enable the I2C fast mode plus driving capability.
375 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
376 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
377 * @param ConfigFastModePlus This parameter can be a combination of the following values:
378 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
379 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
380 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
381 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
382 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
383 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2
384 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
385 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
386 * @retval None
387 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)388 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
389 {
390 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
391 }
392
393 /**
394 * @brief Disable the I2C fast mode plus driving capability.
395 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
396 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
397 * @param ConfigFastModePlus This parameter can be a combination of the following values:
398 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
399 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
400 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
401 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
402 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
403 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2
404 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
405 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
406 * @retval None
407 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)408 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
409 {
410 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
411 }
412
413 /**
414 * @brief Enable Floating Point Unit Invalid operation Interrupt
415 * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
416 * @retval None
417 */
LL_SYSCFG_EnableIT_FPU_IOC(void)418 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
419 {
420 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0);
421 }
422
423 /**
424 * @brief Enable Floating Point Unit Divide-by-zero Interrupt
425 * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
426 * @retval None
427 */
LL_SYSCFG_EnableIT_FPU_DZC(void)428 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
429 {
430 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1);
431 }
432
433 /**
434 * @brief Enable Floating Point Unit Underflow Interrupt
435 * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
436 * @retval None
437 */
LL_SYSCFG_EnableIT_FPU_UFC(void)438 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
439 {
440 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2);
441 }
442
443 /**
444 * @brief Enable Floating Point Unit Overflow Interrupt
445 * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
446 * @retval None
447 */
LL_SYSCFG_EnableIT_FPU_OFC(void)448 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
449 {
450 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3);
451 }
452
453 /**
454 * @brief Enable Floating Point Unit Input denormal Interrupt
455 * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
456 * @retval None
457 */
LL_SYSCFG_EnableIT_FPU_IDC(void)458 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
459 {
460 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4);
461 }
462
463 /**
464 * @brief Enable Floating Point Unit Inexact Interrupt
465 * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
466 * @retval None
467 */
LL_SYSCFG_EnableIT_FPU_IXC(void)468 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
469 {
470 SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5);
471 }
472
473 /**
474 * @brief Disable Floating Point Unit Invalid operation Interrupt
475 * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
476 * @retval None
477 */
LL_SYSCFG_DisableIT_FPU_IOC(void)478 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
479 {
480 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0);
481 }
482
483 /**
484 * @brief Disable Floating Point Unit Divide-by-zero Interrupt
485 * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
486 * @retval None
487 */
LL_SYSCFG_DisableIT_FPU_DZC(void)488 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
489 {
490 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1);
491 }
492
493 /**
494 * @brief Disable Floating Point Unit Underflow Interrupt
495 * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
496 * @retval None
497 */
LL_SYSCFG_DisableIT_FPU_UFC(void)498 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
499 {
500 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2);
501 }
502
503 /**
504 * @brief Disable Floating Point Unit Overflow Interrupt
505 * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
506 * @retval None
507 */
LL_SYSCFG_DisableIT_FPU_OFC(void)508 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
509 {
510 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3);
511 }
512
513 /**
514 * @brief Disable Floating Point Unit Input denormal Interrupt
515 * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
516 * @retval None
517 */
LL_SYSCFG_DisableIT_FPU_IDC(void)518 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
519 {
520 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4);
521 }
522
523 /**
524 * @brief Disable Floating Point Unit Inexact Interrupt
525 * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
526 * @retval None
527 */
LL_SYSCFG_DisableIT_FPU_IXC(void)528 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
529 {
530 CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5);
531 }
532
533 /**
534 * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
535 * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
536 * @retval State of bit (1 or 0).
537 */
LL_SYSCFG_IsEnabledIT_FPU_IOC(void)538 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
539 {
540 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0) == SYSCFG_FPUIMR_FPU_IE_0) ? 1UL : 0UL);
541 }
542
543 /**
544 * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
545 * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
546 * @retval State of bit (1 or 0).
547 */
LL_SYSCFG_IsEnabledIT_FPU_DZC(void)548 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
549 {
550 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1) == SYSCFG_FPUIMR_FPU_IE_1) ? 1UL : 0UL);
551 }
552
553 /**
554 * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
555 * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
556 * @retval State of bit (1 or 0).
557 */
LL_SYSCFG_IsEnabledIT_FPU_UFC(void)558 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
559 {
560 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2) == SYSCFG_FPUIMR_FPU_IE_2) ? 1UL : 0UL);
561 }
562
563 /**
564 * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
565 * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
566 * @retval State of bit (1 or 0).
567 */
LL_SYSCFG_IsEnabledIT_FPU_OFC(void)568 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
569 {
570 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3) == SYSCFG_FPUIMR_FPU_IE_3) ? 1UL : 0UL);
571 }
572
573 /**
574 * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
575 * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
576 * @retval State of bit (1 or 0).
577 */
LL_SYSCFG_IsEnabledIT_FPU_IDC(void)578 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
579 {
580 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4) == SYSCFG_FPUIMR_FPU_IE_4) ? 1UL : 0UL);
581 }
582
583 /**
584 * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
585 * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
586 * @retval State of bit (1 or 0).
587 */
LL_SYSCFG_IsEnabledIT_FPU_IXC(void)588 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
589 {
590 return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5) == SYSCFG_FPUIMR_FPU_IE_5) ? 1UL : 0UL);
591 }
592
593 /**
594 * @brief Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is
595 * automatically cleared at the end of the SRAM2 erase operation.)
596 * @note This bit is write-protected: setting this bit is possible only after the
597 * correct key sequence is written in the SYSCFG_SKR register as described in
598 * the Reference Manual.
599 * @rmtoll SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase
600 * @retval None
601 */
LL_SYSCFG_EnableSRAM2Erase(void)602 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void)
603 {
604 /* Starts a hardware SRAM2 erase operation*/
605 SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER);
606 }
607
608 /**
609 * @brief Check if SRAM2 erase operation is on going
610 * @rmtoll SYSCFG_SCSR SRAM2BSY LL_SYSCFG_IsSRAM2EraseOngoing
611 * @retval State of bit (1 or 0).
612 */
LL_SYSCFG_IsSRAM2EraseOngoing(void)613 __STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void)
614 {
615 return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == SYSCFG_SCSR_SRAM2BSY) ? 1UL : 0UL);
616 }
617
618 /**
619 * @brief Set connections to TIM1/8/15/16/17 Break inputs
620 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
621 * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
622 * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
623 * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
624 * @param Break This parameter can be a combination of the following values:
625 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
626 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
627 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
628 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
629 * @retval None
630 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)631 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
632 {
633 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
634 }
635
636 /**
637 * @brief Get connections to TIM1/8/15/16/17 Break inputs
638 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
639 * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
640 * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
641 * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
642 * @retval Returned value can be can be a combination of the following values:
643 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
644 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
645 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
646 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
647 */
LL_SYSCFG_GetTIMBreakInputs(void)648 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
649 {
650 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
651 }
652
653 /**
654 * @brief Check if SRAM2 parity error detected
655 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
656 * @retval State of bit (1 or 0).
657 */
LL_SYSCFG_IsActiveFlag_SP(void)658 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
659 {
660 return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == SYSCFG_CFGR2_SPF) ? 1UL : 0UL);
661 }
662
663 /**
664 * @brief Clear SRAM2 parity error flag
665 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
666 * @retval None
667 */
LL_SYSCFG_ClearFlag_SP(void)668 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
669 {
670 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
671 }
672
673 /**
674 * @brief Enable SRAM2 page write protection
675 * @note Write protection is cleared only by a system reset
676 * @rmtoll SYSCFG_SWPR PxWP LL_SYSCFG_EnableSRAM2PageWRP_0_31
677 * @param SRAM2WRP This parameter can be a combination of the following values:
678 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0
679 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1
680 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2
681 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3
682 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4
683 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5
684 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6
685 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7
686 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8
687 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9
688 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10
689 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11
690 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12
691 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13
692 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14
693 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15
694 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16
695 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17
696 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18
697 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19
698 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20
699 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21
700 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22
701 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23
702 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24
703 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25
704 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26
705 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27
706 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28
707 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29
708 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30
709 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31
710 * @retval None
711 */
LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)712 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)
713 {
714 SET_BIT(SYSCFG->SWPR, SRAM2WRP);
715 }
716
717 /**
718 * @brief Enable SRAM2 page write protection for Pages in range 32 to 63
719 * @note Write protection is cleared only by a system reset
720 * @rmtoll SYSCFG_SWPR2 PxWP LL_SYSCFG_EnableSRAM2PageWRP_32_63
721 * @param SRAM2WRP This parameter can be a combination of the following values:
722 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE32
723 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE33
724 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE34
725 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE35
726 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE36
727 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE37
728 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE38
729 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE39
730 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE40
731 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE41
732 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE42
733 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE43
734 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE44
735 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE45
736 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE46
737 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE47
738 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE48
739 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE49
740 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE50
741 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE51
742 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE52
743 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE53
744 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE54
745 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE55
746 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE56
747 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE57
748 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE58
749 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE59
750 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE60
751 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE61
752 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE62
753 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE63
754 * @retval None
755 */
LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)756 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)
757 {
758 SET_BIT(SYSCFG->SWPR2, SRAM2WRP);
759 }
760
761 /**
762 * @brief SRAM2 page write protection lock prior to erase
763 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP
764 * @retval None
765 */
LL_SYSCFG_LockSRAM2WRP(void)766 __STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void)
767 {
768 /* Writing a wrong key reactivates the write protection */
769 WRITE_REG(SYSCFG->SKR, 0x00);
770 }
771
772 /**
773 * @brief SRAM2 page write protection unlock prior to erase
774 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP
775 * @retval None
776 */
LL_SYSCFG_UnlockSRAM2WRP(void)777 __STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void)
778 {
779 /* unlock the write protection of the SRAM2ER bit */
780 WRITE_REG(SYSCFG->SKR, 0xCA);
781 WRITE_REG(SYSCFG->SKR, 0x53);
782 }
783
784 /** @defgroup SYSTEM_LL_EF_SYSCFG_Secure_Management Secure Management
785 * @{
786 */
787
788 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
789
790 /**
791 * @brief Configure Secure mode
792 * @note Only available from secure state when system implements security (TZEN=1)
793 * @rmtoll SYSCFG_SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n
794 * SYSCFG_SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n
795 * SYSCFG_SECCFGR SRAM2SEC LL_SYSCFG_ConfigSecure\n
796 * SYSCFG_SECCFGR FPUSEC LL_SYSCFG_ConfigSecure
797 * @param Configuration This parameter shall be the full combination
798 * of the following values:
799 * @arg @ref LL_SYSCFG_CLOCK_SEC or @arg @ref LL_SYSCFG_CLOCK_NSEC
800 * @arg @ref LL_SYSCFG_CLASSB_SEC or @arg @ref LL_SYSCFG_CLASSB_NSEC
801 * @arg @ref LL_SYSCFG_SRAM2_SEC or @arg @ref LL_SYSCFG_SRAM2_NSEC
802 * @arg @ref LL_SYSCFG_FPU_SEC or @arg @ref LL_SYSCFG_FPU_NSEC
803 * @retval None
804 */
LL_SYSCFG_ConfigSecure(uint32_t Configuration)805 __STATIC_INLINE void LL_SYSCFG_ConfigSecure(uint32_t Configuration)
806 {
807 WRITE_REG(SYSCFG->SECCFGR, Configuration);
808 }
809
810 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
811
812 /**
813 * @brief Get Secure mode configuration
814 * @note Only available when system implements security (TZEN=1)
815 * @rmtoll SYSCFG_SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n
816 * SYSCFG_SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n
817 * SYSCFG_SECCFGR SRAM2SEC LL_SYSCFG_ConfigSecure\n
818 * SYSCFG_SECCFGR FPUSEC LL_SYSCFG_ConfigSecure
819 * @retval Returned value is the combination of the following values:
820 * @arg @ref LL_SYSCFG_CLOCK_SEC or @arg @ref LL_SYSCFG_CLOCK_NSEC
821 * @arg @ref LL_SYSCFG_CLASSB_SEC or @arg @ref LL_SYSCFG_CLASSB_NSEC
822 * @arg @ref LL_SYSCFG_SRAM2_SEC or @arg @ref LL_SYSCFG_SRAM2_NSEC
823 * @arg @ref LL_SYSCFG_FPU_SEC or @arg @ref LL_SYSCFG_FPU_NSEC
824 */
LL_SYSCFG_GetConfigSecure(void)825 __STATIC_INLINE uint32_t LL_SYSCFG_GetConfigSecure(void)
826 {
827 return (uint32_t)(READ_BIT(SYSCFG->SECCFGR, 0xFU));
828 }
829
830 /**
831 * @}
832 */
833
834 /**
835 * @}
836 */
837
838
839 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
840 * @{
841 */
842
843 /**
844 * @brief Return the device identifier
845 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
846 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
847 */
LL_DBGMCU_GetDeviceID(void)848 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
849 {
850 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
851 }
852
853 /**
854 * @brief Return the device revision identifier
855 * @note This field indicates the revision of the device.
856 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
857 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
858 */
LL_DBGMCU_GetRevisionID(void)859 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
860 {
861 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
862 }
863
864 /**
865 * @brief Enable the Debug Module during STOP mode
866 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
867 * @retval None
868 */
LL_DBGMCU_EnableDBGStopMode(void)869 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
870 {
871 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
872 }
873
874 /**
875 * @brief Disable the Debug Module during STOP mode
876 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
877 * @retval None
878 */
LL_DBGMCU_DisableDBGStopMode(void)879 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
880 {
881 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
882 }
883
884 /**
885 * @brief Enable the Debug Module during STANDBY mode
886 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
887 * @retval None
888 */
LL_DBGMCU_EnableDBGStandbyMode(void)889 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
890 {
891 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
892 }
893
894 /**
895 * @brief Disable the Debug Module during STANDBY mode
896 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
897 * @retval None
898 */
LL_DBGMCU_DisableDBGStandbyMode(void)899 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
900 {
901 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
902 }
903
904 /**
905 * @brief Enable the clock for Trace port
906 * @rmtoll DBGMCU_CR TRACE_EN LL_DBGMCU_EnableTraceClock
907 * @retval None
908 */
LL_DBGMCU_EnableTraceClock(void)909 __STATIC_INLINE void LL_DBGMCU_EnableTraceClock(void)
910 {
911 SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_EN);
912 }
913
914 /**
915 * @brief Disable the clock for Trace port
916 * @rmtoll DBGMCU_CR TRACE_EN LL_DBGMCU_DisableTraceClock
917 * @retval None
918 */
LL_DBGMCU_DisableTraceClock(void)919 __STATIC_INLINE void LL_DBGMCU_DisableTraceClock(void)
920 {
921 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_EN);
922 }
923
924 /**
925 * @brief Indicate if the clock for Trace port is enabled
926 * @rmtoll DBGMCU_CR TRACE_EN LL_DBGMCU_IsEnabledTraceClock
927 * @retval State of bit (1 or 0).
928 */
LL_DBGMCU_IsEnabledTraceClock(void)929 __STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTraceClock(void)
930 {
931 return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_EN) == (DBGMCU_CR_TRACE_EN)) ? 1UL : 0UL);
932 }
933
934 /**
935 * @brief Set Trace pin assignment control
936 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
937 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
938 * @param PinAssignment This parameter can be one of the following values:
939 * @arg @ref LL_DBGMCU_TRACE_NONE
940 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
941 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
942 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
943 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
944 * @retval None
945 */
LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)946 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
947 {
948 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
949 }
950
951 /**
952 * @brief Get Trace pin assignment control
953 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
954 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
955 * @retval Returned value can be one of the following values:
956 * @arg @ref LL_DBGMCU_TRACE_NONE
957 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
958 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
959 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
960 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
961 */
LL_DBGMCU_GetTracePinAssignment(void)962 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
963 {
964 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
965 }
966
967 /**
968 * @brief Freeze APB1 peripherals (group1 peripherals)
969 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
970 * @param Periphs This parameter can be a combination of the following values:
971 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
972 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
973 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
974 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
975 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
976 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
977 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
978 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
979 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
980 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
981 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
982 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
983 * @arg @ref LL_DBGMCU_APB1_GRP1_FDCAN1_STOP
984 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
985 * @retval None
986 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)987 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
988 {
989 SET_BIT(DBGMCU->APB1FZR1, Periphs);
990 }
991
992 /**
993 * @brief Freeze APB1 peripherals (group2 peripherals)
994 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
995 * @param Periphs This parameter can be a combination of the following values:
996 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP
997 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
998 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM3_STOP
999 * @retval None
1000 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1001 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1002 {
1003 SET_BIT(DBGMCU->APB1FZR2, Periphs);
1004 }
1005
1006 /**
1007 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1008 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1009 * @param Periphs This parameter can be a combination of the following values:
1010 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1011 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1012 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1013 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1014 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1015 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1016 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1017 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1018 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1019 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1020 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1021 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1022 * @arg @ref LL_DBGMCU_APB1_GRP1_FDCAN1_STOP
1023 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1024 * @retval None
1025 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1026 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1027 {
1028 CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
1029 }
1030
1031 /**
1032 * @brief Unfreeze APB1 peripherals (group2 peripherals)
1033 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
1034 * @param Periphs This parameter can be a combination of the following values:
1035 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP
1036 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1037 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM3_STOP
1038 * @retval None
1039 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1040 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1041 {
1042 CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
1043 }
1044
1045 /**
1046 * @brief Freeze APB2 peripherals
1047 * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1048 * @param Periphs This parameter can be a combination of the following values:
1049 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1050 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
1051 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1052 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1053 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1054 * @retval None
1055 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1056 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1057 {
1058 SET_BIT(DBGMCU->APB2FZR, Periphs);
1059 }
1060
1061 /**
1062 * @brief Unfreeze APB2 peripherals
1063 * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1064 * @param Periphs This parameter can be a combination of the following values:
1065 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1066 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
1067 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1068 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1069 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1070 * @retval None
1071 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1072 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1073 {
1074 CLEAR_BIT(DBGMCU->APB2FZR, Periphs);
1075 }
1076
1077 /**
1078 * @}
1079 */
1080
1081 #if defined(VREFBUF)
1082 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
1083 * @{
1084 */
1085
1086 /**
1087 * @brief Enable Internal voltage reference
1088 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
1089 * @retval None
1090 */
LL_VREFBUF_Enable(void)1091 __STATIC_INLINE void LL_VREFBUF_Enable(void)
1092 {
1093 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1094 }
1095
1096 /**
1097 * @brief Disable Internal voltage reference
1098 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
1099 * @retval None
1100 */
LL_VREFBUF_Disable(void)1101 __STATIC_INLINE void LL_VREFBUF_Disable(void)
1102 {
1103 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1104 }
1105
1106 /**
1107 * @brief Enable high impedance (VREF+pin is high impedance)
1108 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
1109 * @retval None
1110 */
LL_VREFBUF_EnableHIZ(void)1111 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
1112 {
1113 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1114 }
1115
1116 /**
1117 * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
1118 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
1119 * @retval None
1120 */
LL_VREFBUF_DisableHIZ(void)1121 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
1122 {
1123 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1124 }
1125
1126 /**
1127 * @brief Set the Voltage reference scale
1128 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
1129 * @param Scale This parameter can be one of the following values:
1130 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1131 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1132 * @retval None
1133 */
LL_VREFBUF_SetVoltageScaling(uint32_t Scale)1134 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
1135 {
1136 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
1137 }
1138
1139 /**
1140 * @brief Get the Voltage reference scale
1141 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
1142 * @retval Returned value can be one of the following values:
1143 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1144 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1145 */
LL_VREFBUF_GetVoltageScaling(void)1146 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
1147 {
1148 return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
1149 }
1150
1151 /**
1152 * @brief Get the VREFBUF trimming value for VRS=0 (VREF_SC0)
1153 * @retval Between 0 and 0x3F
1154 */
LL_VREFBUF_SC0_GetCalibration(void)1155 __STATIC_INLINE uint32_t LL_VREFBUF_SC0_GetCalibration(void)
1156 {
1157 return (uint32_t)(*VREFBUF_SC0_CAL_ADDR);
1158 }
1159
1160 /**
1161 * @brief Get the VREFBUF trimming value for VRS=1 (VREF_SC1)
1162 * @retval Between 0 and 0x3F
1163 */
LL_VREFBUF_SC1_GetCalibration(void)1164 __STATIC_INLINE uint32_t LL_VREFBUF_SC1_GetCalibration(void)
1165 {
1166 return (uint32_t)(*VREFBUF_SC1_CAL_ADDR);
1167 }
1168
1169 /**
1170 * @brief Check if Voltage reference buffer is ready
1171 * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
1172 * @retval State of bit (1 or 0).
1173 */
LL_VREFBUF_IsVREFReady(void)1174 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
1175 {
1176 return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == VREFBUF_CSR_VRR) ? 1UL : 0UL);
1177 }
1178
1179 /**
1180 * @brief Get the trimming code for VREFBUF calibration
1181 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
1182 * @retval Between 0 and 0x3F
1183 */
LL_VREFBUF_GetTrimming(void)1184 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
1185 {
1186 return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
1187 }
1188
1189 /**
1190 * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
1191 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
1192 * @param Value Between 0 and 0x3F
1193 * @retval None
1194 */
LL_VREFBUF_SetTrimming(uint32_t Value)1195 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
1196 {
1197 WRITE_REG(VREFBUF->CCR, Value);
1198 }
1199
1200 /**
1201 * @}
1202 */
1203 #endif /* VREFBUF */
1204
1205 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1206 * @{
1207 */
1208
1209 /**
1210 * @brief Set FLASH Latency
1211 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1212 * @param Latency This parameter can be one of the following values:
1213 * @arg @ref LL_FLASH_LATENCY_0
1214 * @arg @ref LL_FLASH_LATENCY_1
1215 * @arg @ref LL_FLASH_LATENCY_2
1216 * @arg @ref LL_FLASH_LATENCY_3
1217 * @arg @ref LL_FLASH_LATENCY_4
1218 * @arg @ref LL_FLASH_LATENCY_5
1219 * @arg @ref LL_FLASH_LATENCY_6
1220 * @arg @ref LL_FLASH_LATENCY_7
1221 * @arg @ref LL_FLASH_LATENCY_8
1222 * @arg @ref LL_FLASH_LATENCY_9
1223 * @arg @ref LL_FLASH_LATENCY_10
1224 * @arg @ref LL_FLASH_LATENCY_11
1225 * @arg @ref LL_FLASH_LATENCY_12
1226 * @arg @ref LL_FLASH_LATENCY_13
1227 * @arg @ref LL_FLASH_LATENCY_14
1228 * @arg @ref LL_FLASH_LATENCY_15
1229 * @retval None
1230 */
LL_FLASH_SetLatency(uint32_t Latency)1231 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1232 {
1233 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1234 }
1235
1236 /**
1237 * @brief Get FLASH Latency
1238 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1239 * @retval Returned value can be one of the following values:
1240 * @arg @ref LL_FLASH_LATENCY_0
1241 * @arg @ref LL_FLASH_LATENCY_1
1242 * @arg @ref LL_FLASH_LATENCY_2
1243 * @arg @ref LL_FLASH_LATENCY_3
1244 * @arg @ref LL_FLASH_LATENCY_4
1245 * @arg @ref LL_FLASH_LATENCY_5
1246 * @arg @ref LL_FLASH_LATENCY_6
1247 * @arg @ref LL_FLASH_LATENCY_7
1248 * @arg @ref LL_FLASH_LATENCY_8
1249 * @arg @ref LL_FLASH_LATENCY_9
1250 * @arg @ref LL_FLASH_LATENCY_10
1251 * @arg @ref LL_FLASH_LATENCY_11
1252 * @arg @ref LL_FLASH_LATENCY_12
1253 * @arg @ref LL_FLASH_LATENCY_13
1254 * @arg @ref LL_FLASH_LATENCY_14
1255 * @arg @ref LL_FLASH_LATENCY_15
1256 */
LL_FLASH_GetLatency(void)1257 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1258 {
1259 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1260 }
1261
1262 /**
1263 * @brief Enable Flash Power-down mode during run mode or Low-power run mode
1264 * @note Flash memory can be put in power-down mode only when the code is executed
1265 * from RAM
1266 * @note Flash must not be accessed when power down is enabled
1267 * @note Flash must not be put in power-down while a program or an erase operation
1268 * is on-going
1269 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
1270 * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n
1271 * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown
1272 * @retval None
1273 */
LL_FLASH_EnableRunPowerDown(void)1274 __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
1275 {
1276 /* Following values must be written consecutively to unlock the RUN_PD bit in
1277 FLASH_ACR */
1278 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
1279 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
1280 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
1281 }
1282
1283 /**
1284 * @brief Disable Flash Power-down mode during run mode or Low-power run mode
1285 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n
1286 * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n
1287 * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown
1288 * @retval None
1289 */
LL_FLASH_DisableRunPowerDown(void)1290 __STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
1291 {
1292 /* Following values must be written consecutively to unlock the RUN_PD bit in
1293 FLASH_ACR */
1294 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
1295 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
1296 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
1297 }
1298
1299 /**
1300 * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
1301 * @note Flash must not be put in power-down while a program or an erase operation
1302 * is on-going
1303 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
1304 * @retval None
1305 */
LL_FLASH_EnableSleepPowerDown(void)1306 __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
1307 {
1308 SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1309 }
1310
1311 /**
1312 * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
1313 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
1314 * @retval None
1315 */
LL_FLASH_DisableSleepPowerDown(void)1316 __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
1317 {
1318 CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1319 }
1320
1321 /**
1322 * @}
1323 */
1324
1325 /**
1326 * @}
1327 */
1328
1329 /**
1330 * @}
1331 */
1332
1333 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
1334
1335 /**
1336 * @}
1337 */
1338
1339 #ifdef __cplusplus
1340 }
1341 #endif
1342
1343 #endif /* STM32L5xx_LL_SYSTEM_H */
1344
1345
