1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_ll_fmc.h 4 * @author MCD Application Team 5 * @brief Header file of FMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L5xx_LL_FMC_H 21 #define STM32L5xx_LL_FMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l5xx_hal_def.h" 29 30 /** @addtogroup STM32L5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FMC_LL 35 * @{ 36 */ 37 38 /** @addtogroup FMC_LL_Private_Macros 39 * @{ 40 */ 41 42 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ 43 ((__BANK__) == FMC_NORSRAM_BANK2) || \ 44 ((__BANK__) == FMC_NORSRAM_BANK3) || \ 45 ((__BANK__) == FMC_NORSRAM_BANK4)) 46 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ 47 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) 48 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ 49 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ 50 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) 51 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 52 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 53 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) 54 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ 55 ((__SIZE__) == FMC_PAGE_SIZE_128) || \ 56 ((__SIZE__) == FMC_PAGE_SIZE_256) || \ 57 ((__SIZE__) == FMC_PAGE_SIZE_512) || \ 58 ((__SIZE__) == FMC_PAGE_SIZE_1024)) 59 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ 60 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) 61 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ 62 ((__MODE__) == FMC_ACCESS_MODE_B) || \ 63 ((__MODE__) == FMC_ACCESS_MODE_C) || \ 64 ((__MODE__) == FMC_ACCESS_MODE_D)) 65 #define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \ 66 ((__NBL__) == FMC_NBL_SETUPTIME_1) || \ 67 ((__NBL__) == FMC_NBL_SETUPTIME_2) || \ 68 ((__NBL__) == FMC_NBL_SETUPTIME_3)) 69 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ 70 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) 71 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ 72 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) 73 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ 74 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) 75 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ 76 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) 77 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ 78 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) 79 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ 80 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) 81 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 82 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) 83 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) 84 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ 85 ((__BURST__) == FMC_WRITE_BURST_ENABLE)) 86 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 87 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 88 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) 89 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) 90 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) 91 #define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) 92 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) 93 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) 94 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) 95 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) 96 #define IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(__TIME__) (((__TIME__) >= 1U) && ((__TIME__) <= 65535U)) 97 98 99 #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) 100 #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ 101 ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) 102 #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ 103 ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) 104 #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ 105 ((__STATE__) == FMC_NAND_ECC_ENABLE)) 106 107 #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ 108 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ 109 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 110 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 111 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 112 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 113 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) 114 #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) 115 #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) 116 #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) 117 #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) 118 #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) 119 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) 120 121 122 /** 123 * @} 124 */ 125 126 /* Exported typedef ----------------------------------------------------------*/ 127 128 /** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types 129 * @{ 130 */ 131 132 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef 133 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef 134 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef 135 136 #define FMC_NORSRAM_DEVICE FMC_Bank1_R 137 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R 138 #define FMC_NAND_DEVICE FMC_Bank3_R 139 140 /** 141 * @brief FMC NORSRAM Configuration Structure definition 142 */ 143 typedef struct 144 { 145 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 146 This parameter can be a value of @ref FMC_NORSRAM_Bank */ 147 148 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 149 multiplexed on the data bus or not. 150 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ 151 152 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 153 the corresponding memory device. 154 This parameter can be a value of @ref FMC_Memory_Type */ 155 156 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 157 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ 158 159 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 160 valid only with synchronous burst Flash memories. 161 This parameter can be a value of @ref FMC_Burst_Access_Mode */ 162 163 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 164 the Flash memory in burst mode. 165 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ 166 167 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 168 clock cycle before the wait state or during the wait state, 169 valid only when accessing memories in burst mode. 170 This parameter can be a value of @ref FMC_Wait_Timing */ 171 172 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. 173 This parameter can be a value of @ref FMC_Write_Operation */ 174 175 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 176 signal, valid for Flash memory access in burst mode. 177 This parameter can be a value of @ref FMC_Wait_Signal */ 178 179 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 180 This parameter can be a value of @ref FMC_Extended_Mode */ 181 182 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 183 valid only with asynchronous Flash memories. 184 This parameter can be a value of @ref FMC_AsynchronousWait */ 185 186 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 187 This parameter can be a value of @ref FMC_Write_Burst */ 188 189 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. 190 This parameter is only enabled through the FMC_BCR1 register, 191 and don't care through FMC_BCR2..4 registers. 192 This parameter can be a value of @ref FMC_Continous_Clock */ 193 194 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. 195 This parameter is only enabled through the FMC_BCR1 register, 196 and don't care through FMC_BCR2..4 registers. 197 This parameter can be a value of @ref FMC_Write_FIFO */ 198 199 uint32_t PageSize; /*!< Specifies the memory page size. 200 This parameter can be a value of @ref FMC_Page_Size */ 201 202 uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number 203 This parameter can be a value of @ref FMC_Byte_Lane */ 204 205 FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this 206 NSBank for PSRAM refresh. 207 This parameter can be set to ENABLE or DISABLE */ 208 209 uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for 210 synchronous accesses and in HCLK cycles for asynchronous accesses, 211 valid only if MaxChipSelectPulse is ENABLE. 212 This parameter can be a value between Min_Data = 1 and Max_Data = 65535. 213 @note: This parameter is common to all NSBank. */ 214 } FMC_NORSRAM_InitTypeDef; 215 216 /** 217 * @brief FMC NORSRAM Timing parameters structure definition 218 */ 219 typedef struct 220 { 221 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 222 the duration of the address setup time. 223 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 224 @note This parameter is not used with synchronous NOR Flash memories. */ 225 226 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 227 the duration of the address hold time. 228 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 229 @note This parameter is not used with synchronous NOR Flash memories. */ 230 231 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 232 the duration of the data setup time. 233 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 234 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 235 NOR Flash memories. */ 236 237 uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure 238 the duration of the data hold time. 239 This parameter can be a value between Min_Data = 0 and Max_Data = 3. 240 @note This parameter is used for used in asynchronous accesses. */ 241 242 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 243 the duration of the bus turnaround. 244 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 245 @note This parameter is only used for multiplexed NOR Flash memories. */ 246 247 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 248 HCLK cycles. This parameter can be a value between Min_Data = 2 and 249 Max_Data = 16. 250 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 251 accesses. */ 252 253 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 254 to the memory before getting the first data. 255 The parameter value depends on the memory type as shown below: 256 - It must be set to 0 in case of a CRAM 257 - It is don't care in asynchronous NOR, SRAM or ROM accesses 258 - It may assume a value between Min_Data = 2 and Max_Data = 17 259 in NOR Flash memories with synchronous burst mode enable */ 260 261 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 262 This parameter can be a value of @ref FMC_Access_Mode */ 263 } FMC_NORSRAM_TimingTypeDef; 264 265 /** 266 * @brief FMC NAND Configuration Structure definition 267 */ 268 typedef struct 269 { 270 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. 271 This parameter can be a value of @ref FMC_NAND_Bank */ 272 273 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. 274 This parameter can be any value of @ref FMC_Wait_feature */ 275 276 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 277 This parameter can be any value of @ref FMC_NAND_Data_Width */ 278 279 uint32_t EccComputation; /*!< Enables or disables the ECC computation. 280 This parameter can be any value of @ref FMC_ECC */ 281 282 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. 283 This parameter can be any value of @ref FMC_ECC_Page_Size */ 284 285 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 286 delay between CLE low and RE low. 287 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 288 289 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 290 delay between ALE low and RE low. 291 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 292 } FMC_NAND_InitTypeDef; 293 294 /** 295 * @brief FMC NAND Timing parameters structure definition 296 */ 297 typedef struct 298 { 299 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before 300 the command assertion for NAND-Flash read or write access 301 to common/Attribute or I/O memory space (depending on 302 the memory space timing to be configured). 303 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ 304 305 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 306 command for NAND-Flash read or write access to 307 common/Attribute or I/O memory space (depending on the 308 memory space timing to be configured). 309 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 310 311 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 312 (and data for write access) after the command de-assertion 313 for NAND-Flash read or write access to common/Attribute 314 or I/O memory space (depending on the memory space timing 315 to be configured). 316 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 317 318 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 319 data bus is kept in HiZ after the start of a NAND-Flash 320 write access to common/Attribute or I/O memory space (depending 321 on the memory space timing to be configured). 322 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 323 } FMC_NAND_PCC_TimingTypeDef; 324 325 326 /** 327 * @} 328 */ 329 330 /* Exported constants --------------------------------------------------------*/ 331 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants 332 * @{ 333 */ 334 335 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller 336 * @{ 337 */ 338 339 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank 340 * @{ 341 */ 342 #define FMC_NORSRAM_BANK1 (0x00000000U) 343 #define FMC_NORSRAM_BANK2 (0x00000002U) 344 #define FMC_NORSRAM_BANK3 (0x00000004U) 345 #define FMC_NORSRAM_BANK4 (0x00000006U) 346 /** 347 * @} 348 */ 349 350 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing 351 * @{ 352 */ 353 #define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) 354 #define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) 355 /** 356 * @} 357 */ 358 359 /** @defgroup FMC_Memory_Type FMC Memory Type 360 * @{ 361 */ 362 #define FMC_MEMORY_TYPE_SRAM (0x00000000U) 363 #define FMC_MEMORY_TYPE_PSRAM (0x00000004U) 364 #define FMC_MEMORY_TYPE_NOR (0x00000008U) 365 /** 366 * @} 367 */ 368 369 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width 370 * @{ 371 */ 372 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) 373 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) 374 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) 375 /** 376 * @} 377 */ 378 379 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access 380 * @{ 381 */ 382 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) 383 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) 384 /** 385 * @} 386 */ 387 388 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode 389 * @{ 390 */ 391 #define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) 392 #define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) 393 /** 394 * @} 395 */ 396 397 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity 398 * @{ 399 */ 400 #define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) 401 #define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) 402 /** 403 * @} 404 */ 405 406 /** @defgroup FMC_Wait_Timing FMC Wait Timing 407 * @{ 408 */ 409 #define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) 410 #define FMC_WAIT_TIMING_DURING_WS (0x00000800U) 411 /** 412 * @} 413 */ 414 415 /** @defgroup FMC_Write_Operation FMC Write Operation 416 * @{ 417 */ 418 #define FMC_WRITE_OPERATION_DISABLE (0x00000000U) 419 #define FMC_WRITE_OPERATION_ENABLE (0x00001000U) 420 /** 421 * @} 422 */ 423 424 /** @defgroup FMC_Wait_Signal FMC Wait Signal 425 * @{ 426 */ 427 #define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) 428 #define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) 429 /** 430 * @} 431 */ 432 433 /** @defgroup FMC_Extended_Mode FMC Extended Mode 434 * @{ 435 */ 436 #define FMC_EXTENDED_MODE_DISABLE (0x00000000U) 437 #define FMC_EXTENDED_MODE_ENABLE (0x00004000U) 438 /** 439 * @} 440 */ 441 442 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait 443 * @{ 444 */ 445 #define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) 446 #define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) 447 /** 448 * @} 449 */ 450 451 /** @defgroup FMC_Page_Size FMC Page Size 452 * @{ 453 */ 454 #define FMC_PAGE_SIZE_NONE (0x00000000U) 455 #define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0 456 #define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1 457 #define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\ 458 | FMC_BCRx_CPSIZE_1) 459 #define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2 460 /** 461 * @} 462 */ 463 464 /** @defgroup FMC_Write_Burst FMC Write Burst 465 * @{ 466 */ 467 #define FMC_WRITE_BURST_DISABLE (0x00000000U) 468 #define FMC_WRITE_BURST_ENABLE (0x00080000U) 469 /** 470 * @} 471 */ 472 473 /** @defgroup FMC_Continous_Clock FMC Continuous Clock 474 * @{ 475 */ 476 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) 477 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) 478 /** 479 * @} 480 */ 481 482 #if defined(FMC_BCR1_WFDIS) 483 /** @defgroup FMC_Write_FIFO FMC Write FIFO 484 * @{ 485 */ 486 #define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS 487 #define FMC_WRITE_FIFO_ENABLE (0x00000000U) 488 #endif /* FMC_BCR1_WFDIS */ 489 /** 490 * @} 491 */ 492 493 /** @defgroup FMC_Access_Mode FMC Access Mode 494 * @{ 495 */ 496 #define FMC_ACCESS_MODE_A (0x00000000U) 497 #define FMC_ACCESS_MODE_B (0x10000000U) 498 #define FMC_ACCESS_MODE_C (0x20000000U) 499 #define FMC_ACCESS_MODE_D (0x30000000U) 500 /** 501 * @} 502 */ 503 504 /** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup 505 * @{ 506 */ 507 #define FMC_NBL_SETUPTIME_0 (0x00000000U) 508 #define FMC_NBL_SETUPTIME_1 (0x00400000U) 509 #define FMC_NBL_SETUPTIME_2 (0x00800000U) 510 #define FMC_NBL_SETUPTIME_3 (0x00C00000U) 511 /** 512 * @} 513 */ 514 515 /** 516 * @} 517 */ 518 519 520 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller 521 * @{ 522 */ 523 /** @defgroup FMC_NAND_Bank FMC NAND Bank 524 * @{ 525 */ 526 #define FMC_NAND_BANK3 (0x00000100U) 527 /** 528 * @} 529 */ 530 531 /** @defgroup FMC_Wait_feature FMC Wait feature 532 * @{ 533 */ 534 #define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U) 535 #define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U) 536 /** 537 * @} 538 */ 539 540 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type 541 * @{ 542 */ 543 #define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) 544 /** 545 * @} 546 */ 547 548 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width 549 * @{ 550 */ 551 #define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U) 552 #define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U) 553 /** 554 * @} 555 */ 556 557 /** @defgroup FMC_ECC FMC ECC 558 * @{ 559 */ 560 #define FMC_NAND_ECC_DISABLE (0x00000000U) 561 #define FMC_NAND_ECC_ENABLE (0x00000040U) 562 /** 563 * @} 564 */ 565 566 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size 567 * @{ 568 */ 569 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) 570 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) 571 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) 572 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) 573 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) 574 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) 575 /** 576 * @} 577 */ 578 579 /** 580 * @} 581 */ 582 583 584 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition 585 * @{ 586 */ 587 #define FMC_IT_RISING_EDGE (0x00000008U) 588 #define FMC_IT_LEVEL (0x00000010U) 589 #define FMC_IT_FALLING_EDGE (0x00000020U) 590 /** 591 * @} 592 */ 593 594 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition 595 * @{ 596 */ 597 #define FMC_FLAG_RISING_EDGE (0x00000001U) 598 #define FMC_FLAG_LEVEL (0x00000002U) 599 #define FMC_FLAG_FALLING_EDGE (0x00000004U) 600 #define FMC_FLAG_FEMPT (0x00000040U) 601 /** 602 * @} 603 */ 604 605 /** 606 * @} 607 */ 608 609 /** 610 * @} 611 */ 612 613 /* Private macro -------------------------------------------------------------*/ 614 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros 615 * @{ 616 */ 617 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros 618 * @brief macros to handle NOR device enable/disable and read/write operations 619 * @{ 620 */ 621 622 /** 623 * @brief Enable the NORSRAM device access. 624 * @param __INSTANCE__ FMC_NORSRAM Instance 625 * @param __BANK__ FMC_NORSRAM Bank 626 * @retval None 627 */ 628 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 629 |= FMC_BCRx_MBKEN) 630 631 /** 632 * @brief Disable the NORSRAM device access. 633 * @param __INSTANCE__ FMC_NORSRAM Instance 634 * @param __BANK__ FMC_NORSRAM Bank 635 * @retval None 636 */ 637 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 638 &= ~FMC_BCRx_MBKEN) 639 640 /** 641 * @} 642 */ 643 644 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros 645 * @brief macros to handle NAND device enable/disable 646 * @{ 647 */ 648 649 /** 650 * @brief Enable the NAND device access. 651 * @param __INSTANCE__ FMC_NAND Instance 652 * @retval None 653 */ 654 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) 655 656 /** 657 * @brief Disable the NAND device access. 658 * @param __INSTANCE__ FMC_NAND Instance 659 * @param __BANK__ FMC_NAND Bank 660 * @retval None 661 */ 662 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) 663 664 /** 665 * @} 666 */ 667 668 /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt 669 * @brief macros to handle NAND interrupts 670 * @{ 671 */ 672 673 /** 674 * @brief Enable the NAND device interrupt. 675 * @param __INSTANCE__ FMC_NAND instance 676 * @param __INTERRUPT__ FMC_NAND interrupt 677 * This parameter can be any combination of the following values: 678 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 679 * @arg FMC_IT_LEVEL: Interrupt level. 680 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 681 * @retval None 682 */ 683 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) 684 685 /** 686 * @brief Disable the NAND device interrupt. 687 * @param __INSTANCE__ FMC_NAND Instance 688 * @param __INTERRUPT__ FMC_NAND interrupt 689 * This parameter can be any combination of the following values: 690 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 691 * @arg FMC_IT_LEVEL: Interrupt level. 692 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 693 * @retval None 694 */ 695 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) 696 697 /** 698 * @brief Get flag status of the NAND device. 699 * @param __INSTANCE__ FMC_NAND Instance 700 * @param __BANK__ FMC_NAND Bank 701 * @param __FLAG__ FMC_NAND flag 702 * This parameter can be any combination of the following values: 703 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 704 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 705 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 706 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 707 * @retval The state of FLAG (SET or RESET). 708 */ 709 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) 710 711 /** 712 * @brief Clear flag status of the NAND device. 713 * @param __INSTANCE__ FMC_NAND Instance 714 * @param __FLAG__ FMC_NAND flag 715 * This parameter can be any combination of the following values: 716 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 717 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 718 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 719 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 720 * @retval None 721 */ 722 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) 723 724 /** 725 * @} 726 */ 727 728 729 /** 730 * @} 731 */ 732 733 /** 734 * @} 735 */ 736 737 /* Private functions ---------------------------------------------------------*/ 738 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions 739 * @{ 740 */ 741 742 /** @defgroup FMC_LL_NORSRAM NOR SRAM 743 * @{ 744 */ 745 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 746 * @{ 747 */ 748 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, 749 FMC_NORSRAM_InitTypeDef *Init); 750 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, 751 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 752 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, 753 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, 754 uint32_t ExtendedMode); 755 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, 756 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 757 /** 758 * @} 759 */ 760 761 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 762 * @{ 763 */ 764 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 765 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 766 /** 767 * @} 768 */ 769 /** 770 * @} 771 */ 772 773 /** @defgroup FMC_LL_NAND NAND 774 * @{ 775 */ 776 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 777 * @{ 778 */ 779 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); 780 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, 781 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 782 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, 783 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 784 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); 785 /** 786 * @} 787 */ 788 789 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions 790 * @{ 791 */ 792 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); 793 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); 794 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, 795 uint32_t Timeout); 796 /** 797 * @} 798 */ 799 /** 800 * @} 801 */ 802 803 804 805 /** 806 * @} 807 */ 808 809 /** 810 * @} 811 */ 812 813 /** 814 * @} 815 */ 816 817 #ifdef __cplusplus 818 } 819 #endif 820 821 #endif /* STM32L5xx_LL_FMC_H */ 822
