1 /**
2 ******************************************************************************
3 * @file stm32l5xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L5xx_LL_DMA_H
21 #define STM32L5xx_LL_DMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l5xx.h"
29 #include "stm32l5xx_ll_dmamux.h"
30
31 /** @addtogroup STM32L5xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMA1) || defined (DMA2)
36
37 /** @defgroup DMA_LL DMA
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
44 * @{
45 */
46 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
47 static const uint8_t CHANNEL_OFFSET_TAB[] =
48 {
49 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
55 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE),
56 (uint8_t)(DMA1_Channel8_BASE - DMA1_BASE)
57 };
58 /**
59 * @}
60 */
61
62 /* Private constants ---------------------------------------------------------*/
63 /* Private macros ------------------------------------------------------------*/
64 /* Exported types ------------------------------------------------------------*/
65 #if defined(USE_FULL_LL_DRIVER)
66 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
67 * @{
68 */
69 typedef struct
70 {
71 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
72 or as Source base address in case of memory to memory transfer direction.
73
74 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
75
76 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
77 or as Destination base address in case of memory to memory transfer direction.
78
79 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
80
81 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
82 from memory to memory or from peripheral to memory.
83 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
84
85 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
86
87 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
88 This parameter can be a value of @ref DMA_LL_EC_MODE
89 @note: The circular buffer mode cannot be used if the memory to memory
90 data transfer direction is configured on the selected Channel
91
92 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
93
94 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
95 is incremented or not.
96 This parameter can be a value of @ref DMA_LL_EC_PERIPH
97
98 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
99
100 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
101 is incremented or not.
102 This parameter can be a value of @ref DMA_LL_EC_MEMORY
103
104 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
105
106 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
107 in case of memory to memory transfer direction.
108 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
109
110 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
111
112 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
113 in case of memory to memory transfer direction.
114 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
115
116 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
117
118 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
119 The data unit is equal to the source buffer configuration set in PeripheralSize
120 or MemorySize parameters depending in the transfer direction.
121 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
122
123 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
124
125 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
126 This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
127
128 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
129
130 uint32_t Priority; /*!< Specifies the channel priority level.
131 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
132
133 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
134
135 uint32_t DoubleBufferMode; /*!< Specifies the double buffer mode.
136 This parameter can be a value of @ref DMA_LL_EC_DOUBLEBUFFER_MODE
137 This feature can be modified afterwards using unitary function @ref LL_DMA_EnableDoubleBufferMode() & LL_DMA_DisableDoubleBufferMode(). */
138
139 uint32_t TargetMemInDoubleBufferMode;
140 /*!< Specifies the target memory in double buffer mode.
141 This parameter can be a value of @ref DMA_LL_EC_CURRENTTARGETMEM
142 This feature can be modified afterwards using unitary function @ref LL_DMA_SetCurrentTargetMem(). */
143
144 } LL_DMA_InitTypeDef;
145 /**
146 * @}
147 */
148 #endif /*USE_FULL_LL_DRIVER*/
149
150 /* Exported constants --------------------------------------------------------*/
151 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
152 * @{
153 */
154 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
155 * @brief Flags defines which can be used with LL_DMA_WriteReg function
156 * @{
157 */
158 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
159 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
160 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
161 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
162 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
163 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
164 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
165 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
166 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
167 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
168 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
169 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
170 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
171 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
172 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
173 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
174 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
175 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
176 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
177 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
178 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
179 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
180 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
181 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
182 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
183 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
184 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
185 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
186 #define LL_DMA_IFCR_CGIF8 DMA_IFCR_CGIF8 /*!< Channel 8 global flag */
187 #define LL_DMA_IFCR_CTCIF8 DMA_IFCR_CTCIF8 /*!< Channel 8 transfer complete flag */
188 #define LL_DMA_IFCR_CHTIF8 DMA_IFCR_CHTIF8 /*!< Channel 8 half transfer flag */
189 #define LL_DMA_IFCR_CTEIF8 DMA_IFCR_CTEIF8 /*!< Channel 8 transfer error flag */
190 /**
191 * @}
192 */
193
194 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
195 * @brief Flags defines which can be used with LL_DMA_ReadReg function
196 * @{
197 */
198 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
199 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
200 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
201 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
202 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
203 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
204 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
205 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
206 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
207 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
208 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
209 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
210 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
211 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
212 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
213 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
214 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
215 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
216 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
217 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
218 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
219 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
220 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
221 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
222 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
223 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
224 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
225 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
226 #define LL_DMA_ISR_GIF8 DMA_ISR_GIF8 /*!< Channel 8 global flag */
227 #define LL_DMA_ISR_TCIF8 DMA_ISR_TCIF8 /*!< Channel 8 transfer complete flag */
228 #define LL_DMA_ISR_HTIF8 DMA_ISR_HTIF8 /*!< Channel 8 half transfer flag */
229 #define LL_DMA_ISR_TEIF8 DMA_ISR_TEIF8 /*!< Channel 8 transfer error flag */
230 /**
231 * @}
232 */
233
234 /** @defgroup DMA_LL_EC_IT IT Defines
235 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
236 * @{
237 */
238 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
239 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
240 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
241 /**
242 * @}
243 */
244
245 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
246 * @{
247 */
248 #define LL_DMA_CHANNEL_1 0x00000000U /*!< DMA Channel 1 */
249 #define LL_DMA_CHANNEL_2 0x00000001U /*!< DMA Channel 2 */
250 #define LL_DMA_CHANNEL_3 0x00000002U /*!< DMA Channel 3 */
251 #define LL_DMA_CHANNEL_4 0x00000003U /*!< DMA Channel 4 */
252 #define LL_DMA_CHANNEL_5 0x00000004U /*!< DMA Channel 5 */
253 #define LL_DMA_CHANNEL_6 0x00000005U /*!< DMA Channel 6 */
254 #define LL_DMA_CHANNEL_7 0x00000006U /*!< DMA Channel 7 */
255 #define LL_DMA_CHANNEL_8 0x00000007U /*!< DMA Channel 8 */
256 #if defined(USE_FULL_LL_DRIVER)
257 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
258 #endif /*USE_FULL_LL_DRIVER*/
259 /**
260 * @}
261 */
262
263 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
264 * @{
265 */
266 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
267 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
268 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
269 /**
270 * @}
271 */
272
273 /** @defgroup DMA_LL_EC_MODE Transfer mode
274 * @{
275 */
276 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
277 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
278 /**
279 * @}
280 */
281
282 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
283 * @{
284 */
285 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
286 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
287 /**
288 * @}
289 */
290
291 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
292 * @{
293 */
294 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
295 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
296 /**
297 * @}
298 */
299
300 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
301 * @{
302 */
303 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
304 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
305 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
306 /**
307 * @}
308 */
309
310 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
311 * @{
312 */
313 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
314 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
315 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
316 /**
317 * @}
318 */
319
320 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
321 * @{
322 */
323 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
324 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
325 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
326 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
327 /**
328 * @}
329 */
330
331 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE
332 * @{
333 */
334 #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
335 #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_CCR_DBM /*!< Enable double buffering mode */
336 /**
337 * @}
338 */
339
340 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENT TARGET MEMORY
341 * @{
342 */
343 #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
344 #define LL_DMA_CURRENTTARGETMEM1 DMA_CCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
345 /**
346 * @}
347 */
348
349 /** @defgroup DMA_LL_CHANNEL_SEC_MODE CHANNEL SECURITY MODE
350 * @{
351 */
352 #define LL_DMA_CHANNEL_NSEC 0x00000000U /*!< Disable secure DMA channel */
353 #define LL_DMA_CHANNEL_SEC DMA_CCR_SECM /*!< Enable secure DMA channel */
354 /**
355 * @}
356 */
357
358 /** @defgroup DMA_LL_SOURCE_TRANSFER_SEC_MODE TRANSFER SECURITY SOURCE MODE
359 * @{
360 */
361 #define LL_DMA_CHANNEL_SRC_NSEC 0x00000000U /*!< Disable secure DMA transfer from the source */
362 #define LL_DMA_CHANNEL_SRC_SEC DMA_CCR_SSEC /*!< Enable secure DMA transfer from the source */
363 /**
364 * @}
365 */
366
367 /** @defgroup DMA_LL_DEST_TRANSFER_SEC_MODE TRANSFER SECURITY DESTINATION MODE
368 * @{
369 */
370 #define LL_DMA_CHANNEL_DEST_NSEC 0x00000000U /*!< Disable secure DMA transfer to the destination */
371 #define LL_DMA_CHANNEL_DEST_SEC DMA_CCR_DSEC /*!< Enable secure DMA transfer to the destination */
372 /**
373 * @}
374 */
375
376 /** @defgroup DMA_LL_SEC_PRIVILEGE_MODE PRIVILEGE MODE
377 * @{
378 */
379 #define LL_DMA_CHANNEL_NPRIV 0x00000000U /*!< Disable privilege transfer to the destination */
380 #define LL_DMA_CHANNEL_PRIV DMA_CCR_PRIV /*!< Enable privilege transfer to the destination */
381 /**
382 * @}
383 */
384
385 /**
386 * @}
387 */
388
389 /* Exported macro ------------------------------------------------------------*/
390 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
391 * @{
392 */
393
394 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
395 * @{
396 */
397 /**
398 * @brief Write a value in DMA register
399 * @param __INSTANCE__ DMA Instance
400 * @param __REG__ Register to be written
401 * @param __VALUE__ Value to be written in the register
402 * @retval None
403 */
404 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
405
406 /**
407 * @brief Read a value in DMA register
408 * @param __INSTANCE__ DMA Instance
409 * @param __REG__ Register to be read
410 * @retval Register value
411 */
412 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
413 /**
414 * @}
415 */
416
417 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
418 * @{
419 */
420 /**
421 * @brief Convert DMAx_Channely into DMAx
422 * @param __CHANNEL_INSTANCE__ DMAx_Channely
423 * @retval DMAx
424 */
425 #if defined(DMA2)
426 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
427 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel8)) ? DMA2 : DMA1)
428 #else
429 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
430 #endif
431
432 /**
433 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
434 * @param __CHANNEL_INSTANCE__ DMAx_Channely
435 * @retval LL_DMA_CHANNEL_y
436 */
437 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
438 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
439 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
440 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
441 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
442 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
443 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
444 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
445 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
446 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
447 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
448 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
449 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
450 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \
451 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel7)) ? LL_DMA_CHANNEL_7 : \
452 LL_DMA_CHANNEL_8)
453
454 /**
455 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
456 * @param __DMA_INSTANCE__ DMAx
457 * @param __CHANNEL__ LL_DMA_CHANNEL_y
458 * @retval DMAx_Channely
459 */
460 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
461 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
462 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
463 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
464 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
465 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
466 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
467 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
468 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
469 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
470 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
471 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
472 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
473 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
474 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA2_Channel7 : \
475 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) ? DMA1_Channel8 : \
476 DMA2_Channel8)
477
478 /**
479 * @}
480 */
481
482 /**
483 * @}
484 */
485
486 /* Exported functions --------------------------------------------------------*/
487 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
488 * @{
489 */
490
491 /** @defgroup DMA_LL_EF_Configuration Configuration
492 * @{
493 */
494 /**
495 * @brief Enable DMA channel.
496 * @rmtoll CCR EN LL_DMA_EnableChannel
497 * @param DMAx DMAx Instance
498 * @param Channel This parameter can be one of the following values:
499 * @arg @ref LL_DMA_CHANNEL_1
500 * @arg @ref LL_DMA_CHANNEL_2
501 * @arg @ref LL_DMA_CHANNEL_3
502 * @arg @ref LL_DMA_CHANNEL_4
503 * @arg @ref LL_DMA_CHANNEL_5
504 * @arg @ref LL_DMA_CHANNEL_6
505 * @arg @ref LL_DMA_CHANNEL_7
506 * @arg @ref LL_DMA_CHANNEL_8
507 * @retval None
508 */
LL_DMA_EnableChannel(DMA_TypeDef * DMAx,uint32_t Channel)509 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
510 {
511 uint32_t dma_base_addr = (uint32_t)DMAx;
512 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
513 }
514
515 /**
516 * @brief Disable DMA channel.
517 * @rmtoll CCR EN LL_DMA_DisableChannel
518 * @param DMAx DMAx Instance
519 * @param Channel This parameter can be one of the following values:
520 * @arg @ref LL_DMA_CHANNEL_1
521 * @arg @ref LL_DMA_CHANNEL_2
522 * @arg @ref LL_DMA_CHANNEL_3
523 * @arg @ref LL_DMA_CHANNEL_4
524 * @arg @ref LL_DMA_CHANNEL_5
525 * @arg @ref LL_DMA_CHANNEL_6
526 * @arg @ref LL_DMA_CHANNEL_7
527 * @arg @ref LL_DMA_CHANNEL_8
528 * @retval None
529 */
LL_DMA_DisableChannel(DMA_TypeDef * DMAx,uint32_t Channel)530 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
531 {
532 uint32_t dma_base_addr = (uint32_t)DMAx;
533 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
534 }
535
536 /**
537 * @brief Check if DMA channel is enabled or disabled.
538 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
539 * @param DMAx DMAx Instance
540 * @param Channel This parameter can be one of the following values:
541 * @arg @ref LL_DMA_CHANNEL_1
542 * @arg @ref LL_DMA_CHANNEL_2
543 * @arg @ref LL_DMA_CHANNEL_3
544 * @arg @ref LL_DMA_CHANNEL_4
545 * @arg @ref LL_DMA_CHANNEL_5
546 * @arg @ref LL_DMA_CHANNEL_6
547 * @arg @ref LL_DMA_CHANNEL_7
548 * @arg @ref LL_DMA_CHANNEL_8
549 * @retval State of bit (1 or 0).
550 */
LL_DMA_IsEnabledChannel(DMA_TypeDef * DMAx,uint32_t Channel)551 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
552 {
553 uint32_t dma_base_addr = (uint32_t)DMAx;
554 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
555 DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
556 }
557
558 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
559
560 /**
561 * @brief Configure all secure parameters link to DMA transfer.
562 * @rmtoll CCR SECM LL_DMA_ConfigChannelSecure\n
563 * CCR SSEC LL_DMA_ConfigChannelSecure\n
564 * CCR DSEC LL_DMA_ConfigChannelSecure\n
565 * @param DMAx DMAx Instance
566 * @param Channel This parameter can be one of the following values:
567 * @arg @ref LL_DMA_CHANNEL_1
568 * @arg @ref LL_DMA_CHANNEL_2
569 * @arg @ref LL_DMA_CHANNEL_3
570 * @arg @ref LL_DMA_CHANNEL_4
571 * @arg @ref LL_DMA_CHANNEL_5
572 * @arg @ref LL_DMA_CHANNEL_6
573 * @arg @ref LL_DMA_CHANNEL_7
574 * @arg @ref LL_DMA_CHANNEL_8
575 * @param Configuration This parameter must be a combination of all the following values:
576 * @arg @ref LL_DMA_CHANNEL_SEC or @ref LL_DMA_CHANNEL_NSEC
577 * @arg @ref LL_DMA_CHANNEL_SRC_SEC or @ref LL_DMA_CHANNEL_SRC_NSEC
578 * @arg @ref LL_DMA_CHANNEL_DEST_SEC or LL_DMA_CHANNEL_DEST_NSEC
579 * @retval None
580 */
LL_DMA_ConfigChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)581 __STATIC_INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
582 {
583 uint32_t dma_base_addr = (uint32_t)DMAx;
584 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + (uint32_t)(CHANNEL_OFFSET_TAB[Channel & 0x07U])))->CCR,
585 DMA_CCR_SECM | DMA_CCR_SSEC | DMA_CCR_DSEC,
586 Configuration);
587 }
588
589 /**
590 * @brief Configure all secure parameters link to DMA transfer.
591 * @rmtoll CCR SECM LL_DMA_GetConfigChannelSecure\n
592 * CCR SSEC LL_DMA_GetConfigChannelSecure\n
593 * CCR DSEC LL_DMA_GetConfigChannelSecure\n
594 * @param DMAx DMAx Instance
595 * @param Channel This parameter can be one of the following values:
596 * @arg @ref LL_DMA_CHANNEL_1
597 * @arg @ref LL_DMA_CHANNEL_2
598 * @arg @ref LL_DMA_CHANNEL_3
599 * @arg @ref LL_DMA_CHANNEL_4
600 * @arg @ref LL_DMA_CHANNEL_5
601 * @arg @ref LL_DMA_CHANNEL_6
602 * @arg @ref LL_DMA_CHANNEL_7
603 * @arg @ref LL_DMA_CHANNEL_8
604 * @retval Configuration This parameter must be a combination of all the following values:
605 * @arg @ref LL_DMA_CHANNEL_SEC or @ref LL_DMA_CHANNEL_NSEC
606 * @arg @ref LL_DMA_CHANNEL_SRC_SEC or @ref LL_DMA_CHANNEL_SRC_NSEC
607 * @arg @ref LL_DMA_CHANNEL_DEST_SEC or LL_DMA_CHANNEL_DEST_NSEC
608 */
LL_DMA_GetConfigChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)609 __STATIC_INLINE uint32_t LL_DMA_GetConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
610 {
611 uint32_t dma_base_addr = (uint32_t)DMAx;
612 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
613 DMA_CCR_SECM | DMA_CCR_SSEC | DMA_CCR_DSEC));
614 }
615
616 #endif /* __ARM_FEATURE_CMSE */
617
618 /**
619 * @brief Configure all parameters link to DMA transfer.
620 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
621 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
622 * CCR CIRC LL_DMA_ConfigTransfer\n
623 * CCR PINC LL_DMA_ConfigTransfer\n
624 * CCR MINC LL_DMA_ConfigTransfer\n
625 * CCR PSIZE LL_DMA_ConfigTransfer\n
626 * CCR MSIZE LL_DMA_ConfigTransfer\n
627 * CCR PL LL_DMA_ConfigTransfer
628 * @param DMAx DMAx Instance
629 * @param Channel This parameter can be one of the following values:
630 * @arg @ref LL_DMA_CHANNEL_1
631 * @arg @ref LL_DMA_CHANNEL_2
632 * @arg @ref LL_DMA_CHANNEL_3
633 * @arg @ref LL_DMA_CHANNEL_4
634 * @arg @ref LL_DMA_CHANNEL_5
635 * @arg @ref LL_DMA_CHANNEL_6
636 * @arg @ref LL_DMA_CHANNEL_7
637 * @arg @ref LL_DMA_CHANNEL_8
638 * @param Configuration This parameter must be a combination of all the following values:
639 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
640 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
641 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
642 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
643 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
644 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
645 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
646 * @arg @ref LL_DMA_DOUBLEBUFFER_MODE_DISABLE OR LL_DMA_DOUBLEBUFFER_MODE_ENABLE
647 * @arg @ref LL_DMA_CURRENTTARGETMEM0 or LL_DMA_CURRENTTARGETMEM1
648 * @retval None
649 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)650 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
651 {
652 uint32_t dma_base_addr = (uint32_t)DMAx;
653 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
654 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL | DMA_CCR_DBM | DMA_CCR_CT,
655 Configuration);
656 }
657
658 /**
659 * @brief Set Data transfer direction (read from peripheral or from memory).
660 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
661 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
662 * @param DMAx DMAx Instance
663 * @param Channel This parameter can be one of the following values:
664 * @arg @ref LL_DMA_CHANNEL_1
665 * @arg @ref LL_DMA_CHANNEL_2
666 * @arg @ref LL_DMA_CHANNEL_3
667 * @arg @ref LL_DMA_CHANNEL_4
668 * @arg @ref LL_DMA_CHANNEL_5
669 * @arg @ref LL_DMA_CHANNEL_6
670 * @arg @ref LL_DMA_CHANNEL_7
671 * @arg @ref LL_DMA_CHANNEL_8
672 * @param Direction This parameter can be one of the following values:
673 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
674 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
675 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
676 * @retval None
677 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)678 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
679 {
680 uint32_t dma_base_addr = (uint32_t)DMAx;
681 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
682 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
683 }
684
685 /**
686 * @brief Get Data transfer direction (read from peripheral or from memory).
687 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
688 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
689 * @param DMAx DMAx Instance
690 * @param Channel This parameter can be one of the following values:
691 * @arg @ref LL_DMA_CHANNEL_1
692 * @arg @ref LL_DMA_CHANNEL_2
693 * @arg @ref LL_DMA_CHANNEL_3
694 * @arg @ref LL_DMA_CHANNEL_4
695 * @arg @ref LL_DMA_CHANNEL_5
696 * @arg @ref LL_DMA_CHANNEL_6
697 * @arg @ref LL_DMA_CHANNEL_7
698 * @arg @ref LL_DMA_CHANNEL_8
699 * @retval Returned value can be one of the following values:
700 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
701 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
702 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
703 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel)704 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
705 {
706 uint32_t dma_base_addr = (uint32_t)DMAx;
707 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
708 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
709 }
710
711 /**
712 * @brief Set DMA mode circular or normal.
713 * @note The circular buffer mode cannot be used if the memory-to-memory
714 * data transfer is configured on the selected Channel.
715 * @rmtoll CCR CIRC LL_DMA_SetMode
716 * @param DMAx DMAx Instance
717 * @param Channel This parameter can be one of the following values:
718 * @arg @ref LL_DMA_CHANNEL_1
719 * @arg @ref LL_DMA_CHANNEL_2
720 * @arg @ref LL_DMA_CHANNEL_3
721 * @arg @ref LL_DMA_CHANNEL_4
722 * @arg @ref LL_DMA_CHANNEL_5
723 * @arg @ref LL_DMA_CHANNEL_6
724 * @arg @ref LL_DMA_CHANNEL_7
725 * @arg @ref LL_DMA_CHANNEL_8
726 * @param Mode This parameter can be one of the following values:
727 * @arg @ref LL_DMA_MODE_NORMAL
728 * @arg @ref LL_DMA_MODE_CIRCULAR
729 * @retval None
730 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)731 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
732 {
733 uint32_t dma_base_addr = (uint32_t)DMAx;
734 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CIRC,
735 Mode);
736 }
737
738 /**
739 * @brief Get DMA mode circular or normal.
740 * @rmtoll CCR CIRC LL_DMA_GetMode
741 * @param DMAx DMAx Instance
742 * @param Channel This parameter can be one of the following values:
743 * @arg @ref LL_DMA_CHANNEL_1
744 * @arg @ref LL_DMA_CHANNEL_2
745 * @arg @ref LL_DMA_CHANNEL_3
746 * @arg @ref LL_DMA_CHANNEL_4
747 * @arg @ref LL_DMA_CHANNEL_5
748 * @arg @ref LL_DMA_CHANNEL_6
749 * @arg @ref LL_DMA_CHANNEL_7
750 * @arg @ref LL_DMA_CHANNEL_8
751 * @retval Returned value can be one of the following values:
752 * @arg @ref LL_DMA_MODE_NORMAL
753 * @arg @ref LL_DMA_MODE_CIRCULAR
754 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Channel)755 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
756 {
757 uint32_t dma_base_addr = (uint32_t)DMAx;
758 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
759 DMA_CCR_CIRC));
760 }
761
762 /**
763 * @brief Set Peripheral increment mode.
764 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
765 * @param DMAx DMAx Instance
766 * @param Channel This parameter can be one of the following values:
767 * @arg @ref LL_DMA_CHANNEL_1
768 * @arg @ref LL_DMA_CHANNEL_2
769 * @arg @ref LL_DMA_CHANNEL_3
770 * @arg @ref LL_DMA_CHANNEL_4
771 * @arg @ref LL_DMA_CHANNEL_5
772 * @arg @ref LL_DMA_CHANNEL_6
773 * @arg @ref LL_DMA_CHANNEL_7
774 * @arg @ref LL_DMA_CHANNEL_8
775 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
776 * @arg @ref LL_DMA_PERIPH_INCREMENT
777 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
778 * @retval None
779 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcIncMode)780 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
781 {
782 uint32_t dma_base_addr = (uint32_t)DMAx;
783 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC,
784 PeriphOrM2MSrcIncMode);
785 }
786
787 /**
788 * @brief Get Peripheral increment mode.
789 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
790 * @param DMAx DMAx Instance
791 * @param Channel This parameter can be one of the following values:
792 * @arg @ref LL_DMA_CHANNEL_1
793 * @arg @ref LL_DMA_CHANNEL_2
794 * @arg @ref LL_DMA_CHANNEL_3
795 * @arg @ref LL_DMA_CHANNEL_4
796 * @arg @ref LL_DMA_CHANNEL_5
797 * @arg @ref LL_DMA_CHANNEL_6
798 * @arg @ref LL_DMA_CHANNEL_7
799 * @arg @ref LL_DMA_CHANNEL_8
800 * @retval Returned value can be one of the following values:
801 * @arg @ref LL_DMA_PERIPH_INCREMENT
802 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
803 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel)804 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
805 {
806 uint32_t dma_base_addr = (uint32_t)DMAx;
807 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
808 DMA_CCR_PINC));
809 }
810
811 /**
812 * @brief Set Memory increment mode.
813 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
814 * @param DMAx DMAx Instance
815 * @param Channel This parameter can be one of the following values:
816 * @arg @ref LL_DMA_CHANNEL_1
817 * @arg @ref LL_DMA_CHANNEL_2
818 * @arg @ref LL_DMA_CHANNEL_3
819 * @arg @ref LL_DMA_CHANNEL_4
820 * @arg @ref LL_DMA_CHANNEL_5
821 * @arg @ref LL_DMA_CHANNEL_6
822 * @arg @ref LL_DMA_CHANNEL_7
823 * @arg @ref LL_DMA_CHANNEL_8
824 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
825 * @arg @ref LL_DMA_MEMORY_INCREMENT
826 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
827 * @retval None
828 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstIncMode)829 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
830 {
831 uint32_t dma_base_addr = (uint32_t)DMAx;
832 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MINC,
833 MemoryOrM2MDstIncMode);
834 }
835
836 /**
837 * @brief Get Memory increment mode.
838 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
839 * @param DMAx DMAx Instance
840 * @param Channel This parameter can be one of the following values:
841 * @arg @ref LL_DMA_CHANNEL_1
842 * @arg @ref LL_DMA_CHANNEL_2
843 * @arg @ref LL_DMA_CHANNEL_3
844 * @arg @ref LL_DMA_CHANNEL_4
845 * @arg @ref LL_DMA_CHANNEL_5
846 * @arg @ref LL_DMA_CHANNEL_6
847 * @arg @ref LL_DMA_CHANNEL_7
848 * @arg @ref LL_DMA_CHANNEL_8
849 * @retval Returned value can be one of the following values:
850 * @arg @ref LL_DMA_MEMORY_INCREMENT
851 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
852 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel)853 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
854 {
855 uint32_t dma_base_addr = (uint32_t)DMAx;
856 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
857 DMA_CCR_MINC));
858 }
859
860 /**
861 * @brief Set Peripheral size.
862 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
863 * @param DMAx DMAx Instance
864 * @param Channel This parameter can be one of the following values:
865 * @arg @ref LL_DMA_CHANNEL_1
866 * @arg @ref LL_DMA_CHANNEL_2
867 * @arg @ref LL_DMA_CHANNEL_3
868 * @arg @ref LL_DMA_CHANNEL_4
869 * @arg @ref LL_DMA_CHANNEL_5
870 * @arg @ref LL_DMA_CHANNEL_6
871 * @arg @ref LL_DMA_CHANNEL_7
872 * @arg @ref LL_DMA_CHANNEL_8
873 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
874 * @arg @ref LL_DMA_PDATAALIGN_BYTE
875 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
876 * @arg @ref LL_DMA_PDATAALIGN_WORD
877 * @retval None
878 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcDataSize)879 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
880 {
881 uint32_t dma_base_addr = (uint32_t)DMAx;
882 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE,
883 PeriphOrM2MSrcDataSize);
884 }
885
886 /**
887 * @brief Get Peripheral size.
888 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
889 * @param DMAx DMAx Instance
890 * @param Channel This parameter can be one of the following values:
891 * @arg @ref LL_DMA_CHANNEL_1
892 * @arg @ref LL_DMA_CHANNEL_2
893 * @arg @ref LL_DMA_CHANNEL_3
894 * @arg @ref LL_DMA_CHANNEL_4
895 * @arg @ref LL_DMA_CHANNEL_5
896 * @arg @ref LL_DMA_CHANNEL_6
897 * @arg @ref LL_DMA_CHANNEL_7
898 * @arg @ref LL_DMA_CHANNEL_8
899 * @retval Returned value can be one of the following values:
900 * @arg @ref LL_DMA_PDATAALIGN_BYTE
901 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
902 * @arg @ref LL_DMA_PDATAALIGN_WORD
903 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel)904 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
905 {
906 uint32_t dma_base_addr = (uint32_t)DMAx;
907 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
908 DMA_CCR_PSIZE));
909 }
910
911 /**
912 * @brief Set Memory size.
913 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
914 * @param DMAx DMAx Instance
915 * @param Channel This parameter can be one of the following values:
916 * @arg @ref LL_DMA_CHANNEL_1
917 * @arg @ref LL_DMA_CHANNEL_2
918 * @arg @ref LL_DMA_CHANNEL_3
919 * @arg @ref LL_DMA_CHANNEL_4
920 * @arg @ref LL_DMA_CHANNEL_5
921 * @arg @ref LL_DMA_CHANNEL_6
922 * @arg @ref LL_DMA_CHANNEL_7
923 * @arg @ref LL_DMA_CHANNEL_8
924 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
925 * @arg @ref LL_DMA_MDATAALIGN_BYTE
926 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
927 * @arg @ref LL_DMA_MDATAALIGN_WORD
928 * @retval None
929 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstDataSize)930 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
931 {
932 uint32_t dma_base_addr = (uint32_t)DMAx;
933 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MSIZE,
934 MemoryOrM2MDstDataSize);
935 }
936
937 /**
938 * @brief Get Memory size.
939 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
940 * @param DMAx DMAx Instance
941 * @param Channel This parameter can be one of the following values:
942 * @arg @ref LL_DMA_CHANNEL_1
943 * @arg @ref LL_DMA_CHANNEL_2
944 * @arg @ref LL_DMA_CHANNEL_3
945 * @arg @ref LL_DMA_CHANNEL_4
946 * @arg @ref LL_DMA_CHANNEL_5
947 * @arg @ref LL_DMA_CHANNEL_6
948 * @arg @ref LL_DMA_CHANNEL_7
949 * @arg @ref LL_DMA_CHANNEL_8
950 * @retval Returned value can be one of the following values:
951 * @arg @ref LL_DMA_MDATAALIGN_BYTE
952 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
953 * @arg @ref LL_DMA_MDATAALIGN_WORD
954 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel)955 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
956 {
957 uint32_t dma_base_addr = (uint32_t)DMAx;
958 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
959 DMA_CCR_MSIZE));
960 }
961
962 /**
963 * @brief Set Channel priority level.
964 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
965 * @param DMAx DMAx Instance
966 * @param Channel This parameter can be one of the following values:
967 * @arg @ref LL_DMA_CHANNEL_1
968 * @arg @ref LL_DMA_CHANNEL_2
969 * @arg @ref LL_DMA_CHANNEL_3
970 * @arg @ref LL_DMA_CHANNEL_4
971 * @arg @ref LL_DMA_CHANNEL_5
972 * @arg @ref LL_DMA_CHANNEL_6
973 * @arg @ref LL_DMA_CHANNEL_7
974 * @arg @ref LL_DMA_CHANNEL_8
975 * @param Priority This parameter can be one of the following values:
976 * @arg @ref LL_DMA_PRIORITY_LOW
977 * @arg @ref LL_DMA_PRIORITY_MEDIUM
978 * @arg @ref LL_DMA_PRIORITY_HIGH
979 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
980 * @retval None
981 */
LL_DMA_SetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)982 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
983 {
984 uint32_t dma_base_addr = (uint32_t)DMAx;
985 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PL,
986 Priority);
987 }
988
989 /**
990 * @brief Get Channel priority level.
991 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
992 * @param DMAx DMAx Instance
993 * @param Channel This parameter can be one of the following values:
994 * @arg @ref LL_DMA_CHANNEL_1
995 * @arg @ref LL_DMA_CHANNEL_2
996 * @arg @ref LL_DMA_CHANNEL_3
997 * @arg @ref LL_DMA_CHANNEL_4
998 * @arg @ref LL_DMA_CHANNEL_5
999 * @arg @ref LL_DMA_CHANNEL_6
1000 * @arg @ref LL_DMA_CHANNEL_7
1001 * @arg @ref LL_DMA_CHANNEL_8
1002 * @retval Returned value can be one of the following values:
1003 * @arg @ref LL_DMA_PRIORITY_LOW
1004 * @arg @ref LL_DMA_PRIORITY_MEDIUM
1005 * @arg @ref LL_DMA_PRIORITY_HIGH
1006 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
1007 */
LL_DMA_GetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel)1008 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
1009 {
1010 uint32_t dma_base_addr = (uint32_t)DMAx;
1011 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
1012 DMA_CCR_PL));
1013 }
1014
1015 /**
1016 * @brief Enable the double buffer mode.
1017 * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
1018 * @param DMAx DMAx Instance
1019 * @param Channel This parameter can be one of the following values:
1020 * @arg @ref LL_DMA_CHANNEL_1
1021 * @arg @ref LL_DMA_CHANNEL_2
1022 * @arg @ref LL_DMA_CHANNEL_3
1023 * @arg @ref LL_DMA_CHANNEL_4
1024 * @arg @ref LL_DMA_CHANNEL_5
1025 * @arg @ref LL_DMA_CHANNEL_6
1026 * @arg @ref LL_DMA_CHANNEL_7
1027 * @arg @ref LL_DMA_CHANNEL_8
1028 * @retval None
1029 */
LL_DMA_EnableDoubleBufferMode(DMA_TypeDef * DMAx,uint32_t Channel)1030 __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Channel)
1031 {
1032 uint32_t dma_base_addr = (uint32_t)DMAx;
1033 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DBM);
1034 }
1035
1036 /**
1037 * @brief Disable the double buffer mode.
1038 * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
1039 * @param DMAx DMAx Instance
1040 * @param Channel This parameter can be one of the following values:
1041 * @arg @ref LL_DMA_CHANNEL_1
1042 * @arg @ref LL_DMA_CHANNEL_2
1043 * @arg @ref LL_DMA_CHANNEL_3
1044 * @arg @ref LL_DMA_CHANNEL_4
1045 * @arg @ref LL_DMA_CHANNEL_5
1046 * @arg @ref LL_DMA_CHANNEL_6
1047 * @arg @ref LL_DMA_CHANNEL_7
1048 * @arg @ref LL_DMA_CHANNEL_8
1049 * @retval None
1050 */
LL_DMA_DisableDoubleBufferMode(DMA_TypeDef * DMAx,uint32_t Channel)1051 __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Channel)
1052 {
1053 uint32_t dma_base_addr = (uint32_t)DMAx;
1054 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DBM);
1055 }
1056
1057 /**
1058 * @brief Check if double buffer mode is enabled or not.
1059 * @rmtoll CCR DBM LL_DMA_IsEnabledDoubleBufferMode\n
1060 * @param DMAx DMAx Instance
1061 * @param Channel This parameter can be one of the following values:
1062 * @arg @ref LL_DMA_CHANNEL_1
1063 * @arg @ref LL_DMA_CHANNEL_2
1064 * @arg @ref LL_DMA_CHANNEL_3
1065 * @arg @ref LL_DMA_CHANNEL_4
1066 * @arg @ref LL_DMA_CHANNEL_5
1067 * @arg @ref LL_DMA_CHANNEL_6
1068 * @arg @ref LL_DMA_CHANNEL_7
1069 * @arg @ref LL_DMA_CHANNEL_8
1070 * @retval State of bit (1 or 0).
1071 */
LL_DMA_IsEnabledDoubleBufferMode(DMA_TypeDef * DMAx,uint32_t Channel)1072 __STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode (DMA_TypeDef *DMAx, uint32_t Channel)
1073 {
1074 uint32_t dma_base_addr = (uint32_t)DMAx;
1075 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
1076 DMA_CCR_DBM) == (DMA_CCR_DBM)) ? 1UL : 0UL);
1077 }
1078
1079 /**
1080 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1081 * @rmtoll CR CT LL_DMA_SetCurrentTargetMem
1082 * @param DMAx DMAx Instance
1083 * @param Channel This parameter can be one of the following values:
1084 * @arg @ref LL_DMA_CHANNEL_1
1085 * @arg @ref LL_DMA_CHANNEL_2
1086 * @arg @ref LL_DMA_CHANNEL_3
1087 * @arg @ref LL_DMA_CHANNEL_4
1088 * @arg @ref LL_DMA_CHANNEL_5
1089 * @arg @ref LL_DMA_CHANNEL_6
1090 * @arg @ref LL_DMA_CHANNEL_7
1091 * @arg @ref LL_DMA_CHANNEL_8
1092 * @param CurrentMemory This parameter can be one of the following values:
1093 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1094 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1095 * @retval None
1096 */
LL_DMA_SetCurrentTargetMem(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t CurrentMemory)1097 __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t CurrentMemory)
1098 {
1099 uint32_t dma_base_addr = (uint32_t)DMAx;
1100 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CT, CurrentMemory);
1101 }
1102
1103 /**
1104 * @brief Get Current target (only in double buffer mode)
1105 * @rmtoll CR CT LL_DMA_GetCurrentTargetMem
1106 * @param DMAx DMAx Instance
1107 * @param Channel This parameter can be one of the following values:
1108 * @arg @ref LL_DMA_CHANNEL_1
1109 * @arg @ref LL_DMA_CHANNEL_2
1110 * @arg @ref LL_DMA_CHANNEL_3
1111 * @arg @ref LL_DMA_CHANNEL_4
1112 * @arg @ref LL_DMA_CHANNEL_5
1113 * @arg @ref LL_DMA_CHANNEL_6
1114 * @arg @ref LL_DMA_CHANNEL_7
1115 * @arg @ref LL_DMA_CHANNEL_8
1116 * @retval Returned value can be one of the following values:
1117 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1118 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1119 */
LL_DMA_GetCurrentTargetMem(DMA_TypeDef * DMAx,uint32_t Channel)1120 __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Channel)
1121 {
1122 uint32_t dma_base_addr = (uint32_t)DMAx;
1123 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
1124 DMA_CCR_CT));
1125 }
1126
1127 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1128 /**
1129 * @brief Enable the DMA Channel secure attribute.
1130 * @rmtoll CCR SECM LL_DMA_EnableChannelSecure\n
1131 * @param DMAx DMAx Instance
1132 * @param Channel This parameter can be one of the following values:
1133 * @arg @ref LL_DMA_CHANNEL_1
1134 * @arg @ref LL_DMA_CHANNEL_2
1135 * @arg @ref LL_DMA_CHANNEL_3
1136 * @arg @ref LL_DMA_CHANNEL_4
1137 * @arg @ref LL_DMA_CHANNEL_5
1138 * @arg @ref LL_DMA_CHANNEL_6
1139 * @arg @ref LL_DMA_CHANNEL_7
1140 * @arg @ref LL_DMA_CHANNEL_8
1141 * @retval None
1142 */
LL_DMA_EnableChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)1143 __STATIC_INLINE void LL_DMA_EnableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
1144 {
1145 uint32_t dma_base_addr = (uint32_t)DMAx;
1146 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SECM);
1147 }
1148
1149 /**
1150 * @brief Disable the DMA channel secure attribute.
1151 * @rmtoll CCR SECM LL_DMA_DisableChannelSecure\n
1152 * @param DMAx DMAx Instance
1153 * @param Channel This parameter can be one of the following values:
1154 * @arg @ref LL_DMA_CHANNEL_1
1155 * @arg @ref LL_DMA_CHANNEL_2
1156 * @arg @ref LL_DMA_CHANNEL_3
1157 * @arg @ref LL_DMA_CHANNEL_4
1158 * @arg @ref LL_DMA_CHANNEL_5
1159 * @arg @ref LL_DMA_CHANNEL_6
1160 * @arg @ref LL_DMA_CHANNEL_7
1161 * @arg @ref LL_DMA_CHANNEL_8
1162 * @retval None
1163 */
LL_DMA_DisableChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)1164 __STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
1165 {
1166 uint32_t dma_base_addr = (uint32_t)DMAx;
1167 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SECM);
1168 }
1169
1170 /**
1171 * @brief Check if DMA channel is secure or not.
1172 * @rmtoll CCR SECM LL_DMA_IsEnabledChannelSecure\n
1173 * @param DMAx DMAx Instance
1174 * @param Channel This parameter can be one of the following values:
1175 * @arg @ref LL_DMA_CHANNEL_1
1176 * @arg @ref LL_DMA_CHANNEL_2
1177 * @arg @ref LL_DMA_CHANNEL_3
1178 * @arg @ref LL_DMA_CHANNEL_4
1179 * @arg @ref LL_DMA_CHANNEL_5
1180 * @arg @ref LL_DMA_CHANNEL_6
1181 * @arg @ref LL_DMA_CHANNEL_7
1182 * @arg @ref LL_DMA_CHANNEL_8
1183 * @retval State of bit (1 or 0).
1184 */
LL_DMA_IsEnabledChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)1185 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
1186 {
1187 uint32_t dma_base_addr = (uint32_t)DMAx;
1188 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
1189 DMA_CCR_SECM) == (DMA_CCR_SECM)) ? 1UL : 0UL);
1190 }
1191
1192 /**
1193 * @brief Enable the secure attribute on DMA channel source.
1194 * @rmtoll CCR SSEC LL_DMA_EnableChannelSrcSecure\n
1195 * @param DMAx DMAx Instance
1196 * @param Channel This parameter can be one of the following values:
1197 * @arg @ref LL_DMA_CHANNEL_1
1198 * @arg @ref LL_DMA_CHANNEL_2
1199 * @arg @ref LL_DMA_CHANNEL_3
1200 * @arg @ref LL_DMA_CHANNEL_4
1201 * @arg @ref LL_DMA_CHANNEL_5
1202 * @arg @ref LL_DMA_CHANNEL_6
1203 * @arg @ref LL_DMA_CHANNEL_7
1204 * @arg @ref LL_DMA_CHANNEL_8
1205 * @retval None
1206 */
LL_DMA_EnableChannelSrcSecure(DMA_TypeDef * DMAx,uint32_t Channel)1207 __STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t Channel)
1208 {
1209 uint32_t dma_base_addr = (uint32_t)DMAx;
1210 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SSEC);
1211 }
1212
1213 /**
1214 * @brief Disable the secure attribute on DMA channel source.
1215 * @rmtoll CCR SSEC LL_DMA_DisableChannelSrcSecure\n
1216 * @param DMAx DMAx Instance
1217 * @param Channel This parameter can be one of the following values:
1218 * @arg @ref LL_DMA_CHANNEL_1
1219 * @arg @ref LL_DMA_CHANNEL_2
1220 * @arg @ref LL_DMA_CHANNEL_3
1221 * @arg @ref LL_DMA_CHANNEL_4
1222 * @arg @ref LL_DMA_CHANNEL_5
1223 * @arg @ref LL_DMA_CHANNEL_6
1224 * @arg @ref LL_DMA_CHANNEL_7
1225 * @arg @ref LL_DMA_CHANNEL_8
1226 * @retval None
1227 */
LL_DMA_DisableChannelSrcSecure(DMA_TypeDef * DMAx,uint32_t Channel)1228 __STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t Channel)
1229 {
1230 uint32_t dma_base_addr = (uint32_t)DMAx;
1231 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SSEC);
1232 }
1233
1234 /**
1235 * @brief Check if DMA channel source attribute is secure or not.
1236 * @rmtoll CCR SSEC LL_DMA_IsEnabledChannelSrcSecure\n
1237 * @param DMAx DMAx Instance
1238 * @param Channel This parameter can be one of the following values:
1239 * @arg @ref LL_DMA_CHANNEL_1
1240 * @arg @ref LL_DMA_CHANNEL_2
1241 * @arg @ref LL_DMA_CHANNEL_3
1242 * @arg @ref LL_DMA_CHANNEL_4
1243 * @arg @ref LL_DMA_CHANNEL_5
1244 * @arg @ref LL_DMA_CHANNEL_6
1245 * @arg @ref LL_DMA_CHANNEL_7
1246 * @arg @ref LL_DMA_CHANNEL_8
1247 * @retval State of bit (1 or 0).
1248 */
LL_DMA_IsEnabledChannelSrcSecure(DMA_TypeDef * DMAx,uint32_t Channel)1249 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t Channel)
1250 {
1251 uint32_t dma_base_addr = (uint32_t)DMAx;
1252 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
1253 DMA_CCR_SSEC) == (DMA_CCR_SSEC)) ? 1UL : 0UL);
1254 }
1255
1256 /**
1257 * @brief Enable the secure attribute on DMA channel destination
1258 * @rmtoll CCR DSEC LL_DMA_EnableChannelDestSecure\n
1259 * @param DMAx DMAx Instance
1260 * @param Channel This parameter can be one of the following values:
1261 * @arg @ref LL_DMA_CHANNEL_1
1262 * @arg @ref LL_DMA_CHANNEL_2
1263 * @arg @ref LL_DMA_CHANNEL_3
1264 * @arg @ref LL_DMA_CHANNEL_4
1265 * @arg @ref LL_DMA_CHANNEL_5
1266 * @arg @ref LL_DMA_CHANNEL_6
1267 * @arg @ref LL_DMA_CHANNEL_7
1268 * @arg @ref LL_DMA_CHANNEL_8
1269 * @retval None
1270 */
LL_DMA_EnableChannelDestSecure(DMA_TypeDef * DMAx,uint32_t Channel)1271 __STATIC_INLINE void LL_DMA_EnableChannelDestSecure(DMA_TypeDef *DMAx, uint32_t Channel)
1272 {
1273 uint32_t dma_base_addr = (uint32_t)DMAx;
1274 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DSEC);
1275 }
1276
1277 /**
1278 * @brief Disable the secure attribute on DMA channel destination.
1279 * @rmtoll CCR DSEC LL_DMA_DisableChannelDestSecure\n
1280 * @param DMAx DMAx Instance
1281 * @param Channel This parameter can be one of the following values:
1282 * @arg @ref LL_DMA_CHANNEL_1
1283 * @arg @ref LL_DMA_CHANNEL_2
1284 * @arg @ref LL_DMA_CHANNEL_3
1285 * @arg @ref LL_DMA_CHANNEL_4
1286 * @arg @ref LL_DMA_CHANNEL_5
1287 * @arg @ref LL_DMA_CHANNEL_6
1288 * @arg @ref LL_DMA_CHANNEL_7
1289 * @arg @ref LL_DMA_CHANNEL_8
1290 * @retval None
1291 */
LL_DMA_DisableChannelDestSecure(DMA_TypeDef * DMAx,uint32_t Channel)1292 __STATIC_INLINE void LL_DMA_DisableChannelDestSecure(DMA_TypeDef *DMAx, uint32_t Channel)
1293 {
1294 uint32_t dma_base_addr = (uint32_t)DMAx;
1295 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DSEC);
1296 }
1297
1298 /**
1299 * @brief Check if DMA channel destination attribute is secure or not.
1300 * @rmtoll CCR DSEC LL_DMA_IsEnabledChannelDestSecure\n
1301 * @param DMAx DMAx Instance
1302 * @param Channel This parameter can be one of the following values:
1303 * @arg @ref LL_DMA_CHANNEL_1
1304 * @arg @ref LL_DMA_CHANNEL_2
1305 * @arg @ref LL_DMA_CHANNEL_3
1306 * @arg @ref LL_DMA_CHANNEL_4
1307 * @arg @ref LL_DMA_CHANNEL_5
1308 * @arg @ref LL_DMA_CHANNEL_6
1309 * @arg @ref LL_DMA_CHANNEL_7
1310 * @arg @ref LL_DMA_CHANNEL_8
1311 * @retval State of bit (1 or 0).
1312 */
LL_DMA_IsEnabledChannelDestSecure(DMA_TypeDef * DMAx,uint32_t Channel)1313 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(DMA_TypeDef *DMAx, uint32_t Channel)
1314 {
1315 uint32_t dma_base_addr = (uint32_t)DMAx;
1316 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
1317 DMA_CCR_DSEC) == (DMA_CCR_DSEC)) ? 1UL : 0UL);
1318 }
1319
1320 #endif /* __ARM_FEATURE_CMSE */
1321
1322 /**
1323 * @brief Enable the privilege attribute on DMA channel.
1324 * @rmtoll CCR PRIV LL_DMA_EnableChannelPrivilege\n
1325 * @param DMAx DMAx Instance
1326 * @param Channel This parameter can be one of the following values:
1327 * @arg @ref LL_DMA_CHANNEL_1
1328 * @arg @ref LL_DMA_CHANNEL_2
1329 * @arg @ref LL_DMA_CHANNEL_3
1330 * @arg @ref LL_DMA_CHANNEL_4
1331 * @arg @ref LL_DMA_CHANNEL_5
1332 * @arg @ref LL_DMA_CHANNEL_6
1333 * @arg @ref LL_DMA_CHANNEL_7
1334 * @arg @ref LL_DMA_CHANNEL_8
1335 * @retval None
1336 */
LL_DMA_EnableChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)1337 __STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
1338 {
1339 uint32_t dma_base_addr = (uint32_t)DMAx;
1340 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIV);
1341 }
1342
1343 /**
1344 * @brief Disable the privilege attribute on DMA channel.
1345 * @rmtoll CCR PRIV LL_DMA_DisableChannelPrivilege\n
1346 * @param DMAx DMAx Instance
1347 * @param Channel This parameter can be one of the following values:
1348 * @arg @ref LL_DMA_CHANNEL_1
1349 * @arg @ref LL_DMA_CHANNEL_2
1350 * @arg @ref LL_DMA_CHANNEL_3
1351 * @arg @ref LL_DMA_CHANNEL_4
1352 * @arg @ref LL_DMA_CHANNEL_5
1353 * @arg @ref LL_DMA_CHANNEL_6
1354 * @arg @ref LL_DMA_CHANNEL_7
1355 * @arg @ref LL_DMA_CHANNEL_8
1356 * @retval None
1357 */
LL_DMA_DisableChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)1358 __STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
1359 {
1360 uint32_t dma_base_addr = (uint32_t)DMAx;
1361 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIV);
1362 }
1363
1364 /**
1365 * @brief Check if DMA channel attribute is privilege or not.
1366 * @rmtoll CCR PRIV LL_DMA_IsEnabledChannelPrivilege\n
1367 * @param DMAx DMAx Instance
1368 * @param Channel This parameter can be one of the following values:
1369 * @arg @ref LL_DMA_CHANNEL_1
1370 * @arg @ref LL_DMA_CHANNEL_2
1371 * @arg @ref LL_DMA_CHANNEL_3
1372 * @arg @ref LL_DMA_CHANNEL_4
1373 * @arg @ref LL_DMA_CHANNEL_5
1374 * @arg @ref LL_DMA_CHANNEL_6
1375 * @arg @ref LL_DMA_CHANNEL_7
1376 * @arg @ref LL_DMA_CHANNEL_8
1377 * @retval State of bit (1 or 0).
1378 */
LL_DMA_IsEnabledChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)1379 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
1380 {
1381 uint32_t dma_base_addr = (uint32_t)DMAx;
1382 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
1383 DMA_CCR_PRIV) == (DMA_CCR_PRIV)) ? 1UL : 0UL);
1384 }
1385
1386 /**
1387 * @brief Set Number of data to transfer.
1388 * @note This action has no effect if
1389 * channel is enabled.
1390 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
1391 * @param DMAx DMAx Instance
1392 * @param Channel This parameter can be one of the following values:
1393 * @arg @ref LL_DMA_CHANNEL_1
1394 * @arg @ref LL_DMA_CHANNEL_2
1395 * @arg @ref LL_DMA_CHANNEL_3
1396 * @arg @ref LL_DMA_CHANNEL_4
1397 * @arg @ref LL_DMA_CHANNEL_5
1398 * @arg @ref LL_DMA_CHANNEL_6
1399 * @arg @ref LL_DMA_CHANNEL_7
1400 * @arg @ref LL_DMA_CHANNEL_8
1401 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
1402 * @retval None
1403 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t NbData)1404 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
1405 {
1406 uint32_t dma_base_addr = (uint32_t)DMAx;
1407 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
1408 DMA_CNDTR_NDT, NbData);
1409 }
1410
1411 /**
1412 * @brief Get Number of data to transfer.
1413 * @note Once the channel is enabled, the return value indicate the
1414 * remaining bytes to be transmitted.
1415 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
1416 * @param DMAx DMAx Instance
1417 * @param Channel This parameter can be one of the following values:
1418 * @arg @ref LL_DMA_CHANNEL_1
1419 * @arg @ref LL_DMA_CHANNEL_2
1420 * @arg @ref LL_DMA_CHANNEL_3
1421 * @arg @ref LL_DMA_CHANNEL_4
1422 * @arg @ref LL_DMA_CHANNEL_5
1423 * @arg @ref LL_DMA_CHANNEL_6
1424 * @arg @ref LL_DMA_CHANNEL_7
1425 * @arg @ref LL_DMA_CHANNEL_8
1426 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1427 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Channel)1428 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
1429 {
1430 uint32_t dma_base_addr = (uint32_t)DMAx;
1431 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
1432 DMA_CNDTR_NDT));
1433 }
1434
1435 /**
1436 * @brief Configure the Source and Destination addresses.
1437 * @note This API must not be called when the DMA channel is enabled.
1438 * @note Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
1439 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
1440 * CM0AR MA LL_DMA_ConfigAddresses
1441 * @param DMAx DMAx Instance
1442 * @param Channel This parameter can be one of the following values:
1443 * @arg @ref LL_DMA_CHANNEL_1
1444 * @arg @ref LL_DMA_CHANNEL_2
1445 * @arg @ref LL_DMA_CHANNEL_3
1446 * @arg @ref LL_DMA_CHANNEL_4
1447 * @arg @ref LL_DMA_CHANNEL_5
1448 * @arg @ref LL_DMA_CHANNEL_6
1449 * @arg @ref LL_DMA_CHANNEL_7
1450 * @arg @ref LL_DMA_CHANNEL_8
1451 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1452 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1453 * @param Direction This parameter can be one of the following values:
1454 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1455 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1456 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1457 * @retval None
1458 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)1459 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
1460 uint32_t DstAddress, uint32_t Direction)
1461 {
1462 uint32_t dma_base_addr = (uint32_t)DMAx;
1463 /* Direction Memory to Periph */
1464 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1465 {
1466 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CM0AR, SrcAddress);
1467 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, DstAddress);
1468 }
1469 /* Direction Periph to Memory and Memory to Memory */
1470 else
1471 {
1472 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, SrcAddress);
1473 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CM0AR, DstAddress);
1474 }
1475 }
1476
1477 /**
1478 * @brief Set the Memory address.
1479 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1480 * @note This API must not be called when the DMA channel is enabled.
1481 * @rmtoll CM0AR MA LL_DMA_SetMemoryAddress
1482 * @param DMAx DMAx Instance
1483 * @param Channel This parameter can be one of the following values:
1484 * @arg @ref LL_DMA_CHANNEL_1
1485 * @arg @ref LL_DMA_CHANNEL_2
1486 * @arg @ref LL_DMA_CHANNEL_3
1487 * @arg @ref LL_DMA_CHANNEL_4
1488 * @arg @ref LL_DMA_CHANNEL_5
1489 * @arg @ref LL_DMA_CHANNEL_6
1490 * @arg @ref LL_DMA_CHANNEL_7
1491 * @arg @ref LL_DMA_CHANNEL_8
1492 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1493 * @retval None
1494 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1495 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1496 {
1497 uint32_t dma_base_addr = (uint32_t)DMAx;
1498 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress);
1499 }
1500
1501 /**
1502 * @brief Set the Peripheral address.
1503 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1504 * @note This API must not be called when the DMA channel is enabled.
1505 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
1506 * @param DMAx DMAx Instance
1507 * @param Channel This parameter can be one of the following values:
1508 * @arg @ref LL_DMA_CHANNEL_1
1509 * @arg @ref LL_DMA_CHANNEL_2
1510 * @arg @ref LL_DMA_CHANNEL_3
1511 * @arg @ref LL_DMA_CHANNEL_4
1512 * @arg @ref LL_DMA_CHANNEL_5
1513 * @arg @ref LL_DMA_CHANNEL_6
1514 * @arg @ref LL_DMA_CHANNEL_7
1515 * @arg @ref LL_DMA_CHANNEL_8
1516 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1517 * @retval None
1518 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphAddress)1519 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
1520 {
1521 uint32_t dma_base_addr = (uint32_t)DMAx;
1522 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, PeriphAddress);
1523 }
1524
1525 /**
1526 * @brief Get Memory address.
1527 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1528 * @rmtoll CM0AR MA LL_DMA_GetMemoryAddress
1529 * @param DMAx DMAx Instance
1530 * @param Channel This parameter can be one of the following values:
1531 * @arg @ref LL_DMA_CHANNEL_1
1532 * @arg @ref LL_DMA_CHANNEL_2
1533 * @arg @ref LL_DMA_CHANNEL_3
1534 * @arg @ref LL_DMA_CHANNEL_4
1535 * @arg @ref LL_DMA_CHANNEL_5
1536 * @arg @ref LL_DMA_CHANNEL_6
1537 * @arg @ref LL_DMA_CHANNEL_7
1538 * @arg @ref LL_DMA_CHANNEL_8
1539 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1540 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel)1541 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1542 {
1543 uint32_t dma_base_addr = (uint32_t)DMAx;
1544 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CM0AR));
1545 }
1546
1547 /**
1548 * @brief Get Peripheral address.
1549 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1550 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1551 * @param DMAx DMAx Instance
1552 * @param Channel This parameter can be one of the following values:
1553 * @arg @ref LL_DMA_CHANNEL_1
1554 * @arg @ref LL_DMA_CHANNEL_2
1555 * @arg @ref LL_DMA_CHANNEL_3
1556 * @arg @ref LL_DMA_CHANNEL_4
1557 * @arg @ref LL_DMA_CHANNEL_5
1558 * @arg @ref LL_DMA_CHANNEL_6
1559 * @arg @ref LL_DMA_CHANNEL_7
1560 * @arg @ref LL_DMA_CHANNEL_8
1561 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1562 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel)1563 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1564 {
1565 uint32_t dma_base_addr = (uint32_t)DMAx;
1566 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
1567 }
1568
1569 /**
1570 * @brief Set the Memory to Memory Source address.
1571 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1572 * @note This API must not be called when the DMA channel is enabled.
1573 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1574 * @param DMAx DMAx Instance
1575 * @param Channel This parameter can be one of the following values:
1576 * @arg @ref LL_DMA_CHANNEL_1
1577 * @arg @ref LL_DMA_CHANNEL_2
1578 * @arg @ref LL_DMA_CHANNEL_3
1579 * @arg @ref LL_DMA_CHANNEL_4
1580 * @arg @ref LL_DMA_CHANNEL_5
1581 * @arg @ref LL_DMA_CHANNEL_6
1582 * @arg @ref LL_DMA_CHANNEL_7
1583 * @arg @ref LL_DMA_CHANNEL_8
1584 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1585 * @retval None
1586 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1587 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1588 {
1589 uint32_t dma_base_addr = (uint32_t)DMAx;
1590 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, MemoryAddress);
1591 }
1592
1593 /**
1594 * @brief Set the Memory to Memory Destination address.
1595 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1596 * @note This API must not be called when the DMA channel is enabled.
1597 * @rmtoll CM0AR MA LL_DMA_SetM2MDstAddress
1598 * @param DMAx DMAx Instance
1599 * @param Channel This parameter can be one of the following values:
1600 * @arg @ref LL_DMA_CHANNEL_1
1601 * @arg @ref LL_DMA_CHANNEL_2
1602 * @arg @ref LL_DMA_CHANNEL_3
1603 * @arg @ref LL_DMA_CHANNEL_4
1604 * @arg @ref LL_DMA_CHANNEL_5
1605 * @arg @ref LL_DMA_CHANNEL_6
1606 * @arg @ref LL_DMA_CHANNEL_7
1607 * @arg @ref LL_DMA_CHANNEL_8
1608 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1609 * @retval None
1610 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1611 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1612 {
1613 uint32_t dma_base_addr = (uint32_t)DMAx;
1614 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress);
1615 }
1616
1617 /**
1618 * @brief Get the Memory to Memory Source address.
1619 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1620 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1621 * @param DMAx DMAx Instance
1622 * @param Channel This parameter can be one of the following values:
1623 * @arg @ref LL_DMA_CHANNEL_1
1624 * @arg @ref LL_DMA_CHANNEL_2
1625 * @arg @ref LL_DMA_CHANNEL_3
1626 * @arg @ref LL_DMA_CHANNEL_4
1627 * @arg @ref LL_DMA_CHANNEL_5
1628 * @arg @ref LL_DMA_CHANNEL_6
1629 * @arg @ref LL_DMA_CHANNEL_7
1630 * @arg @ref LL_DMA_CHANNEL_8
1631 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1632 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel)1633 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1634 {
1635 uint32_t dma_base_addr = (uint32_t)DMAx;
1636 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
1637 }
1638
1639 /**
1640 * @brief Get the Memory to Memory Destination address.
1641 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1642 * @rmtoll CM0AR MA LL_DMA_GetM2MDstAddress
1643 * @param DMAx DMAx Instance
1644 * @param Channel This parameter can be one of the following values:
1645 * @arg @ref LL_DMA_CHANNEL_1
1646 * @arg @ref LL_DMA_CHANNEL_2
1647 * @arg @ref LL_DMA_CHANNEL_3
1648 * @arg @ref LL_DMA_CHANNEL_4
1649 * @arg @ref LL_DMA_CHANNEL_5
1650 * @arg @ref LL_DMA_CHANNEL_6
1651 * @arg @ref LL_DMA_CHANNEL_7
1652 * @arg @ref LL_DMA_CHANNEL_8
1653 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1654 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel)1655 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1656 {
1657 uint32_t dma_base_addr = (uint32_t)DMAx;
1658 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CM0AR));
1659 }
1660
1661 /**
1662 * @brief Set DMA request for DMA Channels on DMAMUX Channel x.
1663 * @note DMAMUX channel 0 to 7 are mapped to DMA1 channel 1 to 8.
1664 * DMAMUX channel 8 to 15 are mapped to DMA2 channel 1 to 8.
1665 * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
1666 * @param DMAx DMAx Instance
1667 * @param Channel This parameter can be one of the following values:
1668 * @arg @ref LL_DMA_CHANNEL_1
1669 * @arg @ref LL_DMA_CHANNEL_2
1670 * @arg @ref LL_DMA_CHANNEL_3
1671 * @arg @ref LL_DMA_CHANNEL_4
1672 * @arg @ref LL_DMA_CHANNEL_5
1673 * @arg @ref LL_DMA_CHANNEL_6
1674 * @arg @ref LL_DMA_CHANNEL_7
1675 * @arg @ref LL_DMA_CHANNEL_8
1676 * @param Request This parameter can be one of the following values:
1677 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1678 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1679 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1680 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1681 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1682 * @arg @ref LL_DMAMUX_REQ_ADC1
1683 * @arg @ref LL_DMAMUX_REQ_ADC2
1684 * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
1685 * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
1686 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
1687 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
1688 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1689 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1690 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1691 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1692 * @arg @ref LL_DMAMUX_REQ_SPI3_RX
1693 * @arg @ref LL_DMAMUX_REQ_SPI3_TX
1694 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1695 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1696 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
1697 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
1698 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
1699 * @arg @ref LL_DMAMUX_REQ_I2C3_TX
1700 * @arg @ref LL_DMAMUX_REQ_I2C4_RX
1701 * @arg @ref LL_DMAMUX_REQ_I2C4_TX
1702 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1703 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1704 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1705 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1706 * @arg @ref LL_DMAMUX_REQ_USART3_RX
1707 * @arg @ref LL_DMAMUX_REQ_USART3_TX
1708 * @arg @ref LL_DMAMUX_REQ_UART4_RX
1709 * @arg @ref LL_DMAMUX_REQ_UART4_TX
1710 * @arg @ref LL_DMAMUX_REQ_UART5_RX
1711 * @arg @ref LL_DMAMUX_REQ_UART5_TX
1712 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1713 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1714 * @arg @ref LL_DMAMUX_REQ_SAI1_A
1715 * @arg @ref LL_DMAMUX_REQ_SAI1_B
1716 * @arg @ref LL_DMAMUX_REQ_SAI2_A
1717 * @arg @ref LL_DMAMUX_REQ_SAI2_B
1718 * @arg @ref LL_DMAMUX_REQ_OSPI1
1719 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1720 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1721 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1722 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1723 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1724 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
1725 * @arg @ref LL_DMAMUX_REQ_TIM1_COM
1726 * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
1727 * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
1728 * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
1729 * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
1730 * @arg @ref LL_DMAMUX_REQ_TIM8_UP
1731 * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
1732 * @arg @ref LL_DMAMUX_REQ_TIM8_COM
1733 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1734 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1735 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1736 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1737 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1738 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
1739 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
1740 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
1741 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
1742 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
1743 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
1744 * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
1745 * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
1746 * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
1747 * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
1748 * @arg @ref LL_DMAMUX_REQ_TIM4_UP
1749 * @arg @ref LL_DMAMUX_REQ_TIM5_CH1
1750 * @arg @ref LL_DMAMUX_REQ_TIM5_CH2
1751 * @arg @ref LL_DMAMUX_REQ_TIM5_CH3
1752 * @arg @ref LL_DMAMUX_REQ_TIM5_CH4
1753 * @arg @ref LL_DMAMUX_REQ_TIM5_UP
1754 * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG
1755 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
1756 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
1757 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
1758 * @arg @ref LL_DMAMUX_REQ_TIM15_COM
1759 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1760 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1761 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1762 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1763 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0
1764 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1
1765 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2
1766 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3
1767 * @arg @ref LL_DMAMUX_REQ_AES_IN
1768 * @arg @ref LL_DMAMUX_REQ_AES_OUT
1769 * @arg @ref LL_DMAMUX_REQ_HASH_IN
1770 * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
1771 * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
1772 * @retval None
1773 */
LL_DMA_SetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Request)1774 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
1775 {
1776 uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U);
1777 MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
1778 }
1779
1780 /**
1781 * @brief Get DMA request for DMA Channels on DMAMUX Channel x.
1782 * @note DMAMUX channel 0 to 7 are mapped to DMA1 channel 1 to 8.
1783 * DMAMUX channel 8 to 15 are mapped to DMA2 channel 1 to 8.
1784 * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
1785 * @param DMAx DMAx Instance
1786 * @param Channel This parameter can be one of the following values:
1787 * @arg @ref LL_DMA_CHANNEL_1
1788 * @arg @ref LL_DMA_CHANNEL_2
1789 * @arg @ref LL_DMA_CHANNEL_3
1790 * @arg @ref LL_DMA_CHANNEL_4
1791 * @arg @ref LL_DMA_CHANNEL_5
1792 * @arg @ref LL_DMA_CHANNEL_6
1793 * @arg @ref LL_DMA_CHANNEL_7
1794 * @arg @ref LL_DMA_CHANNEL_8
1795 * @retval Returned value can be one of the following values:
1796 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1797 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1798 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1799 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1800 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1801 * @arg @ref LL_DMAMUX_REQ_ADC1
1802 * @arg @ref LL_DMAMUX_REQ_ADC2
1803 * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
1804 * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
1805 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
1806 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
1807 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1808 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1809 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1810 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1811 * @arg @ref LL_DMAMUX_REQ_SPI3_RX
1812 * @arg @ref LL_DMAMUX_REQ_SPI3_TX
1813 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1814 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1815 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
1816 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
1817 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
1818 * @arg @ref LL_DMAMUX_REQ_I2C3_TX
1819 * @arg @ref LL_DMAMUX_REQ_I2C4_RX
1820 * @arg @ref LL_DMAMUX_REQ_I2C4_TX
1821 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1822 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1823 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1824 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1825 * @arg @ref LL_DMAMUX_REQ_USART3_RX
1826 * @arg @ref LL_DMAMUX_REQ_USART3_TX
1827 * @arg @ref LL_DMAMUX_REQ_UART4_RX
1828 * @arg @ref LL_DMAMUX_REQ_UART4_TX
1829 * @arg @ref LL_DMAMUX_REQ_UART5_RX
1830 * @arg @ref LL_DMAMUX_REQ_UART5_TX
1831 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1832 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1833 * @arg @ref LL_DMAMUX_REQ_SAI1_A
1834 * @arg @ref LL_DMAMUX_REQ_SAI1_B
1835 * @arg @ref LL_DMAMUX_REQ_SAI2_A
1836 * @arg @ref LL_DMAMUX_REQ_SAI2_B
1837 * @arg @ref LL_DMAMUX_REQ_OSPI1
1838 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1839 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1840 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1841 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1842 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1843 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
1844 * @arg @ref LL_DMAMUX_REQ_TIM1_COM
1845 * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
1846 * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
1847 * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
1848 * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
1849 * @arg @ref LL_DMAMUX_REQ_TIM8_UP
1850 * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
1851 * @arg @ref LL_DMAMUX_REQ_TIM8_COM
1852 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1853 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1854 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1855 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1856 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1857 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
1858 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
1859 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
1860 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
1861 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
1862 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
1863 * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
1864 * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
1865 * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
1866 * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
1867 * @arg @ref LL_DMAMUX_REQ_TIM4_UP
1868 * @arg @ref LL_DMAMUX_REQ_TIM5_CH1
1869 * @arg @ref LL_DMAMUX_REQ_TIM5_CH2
1870 * @arg @ref LL_DMAMUX_REQ_TIM5_CH3
1871 * @arg @ref LL_DMAMUX_REQ_TIM5_CH4
1872 * @arg @ref LL_DMAMUX_REQ_TIM5_UP
1873 * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG
1874 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
1875 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
1876 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
1877 * @arg @ref LL_DMAMUX_REQ_TIM15_COM
1878 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1879 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1880 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1881 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1882 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0
1883 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1
1884 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2
1885 * @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3
1886 * @arg @ref LL_DMAMUX_REQ_AES_IN
1887 * @arg @ref LL_DMAMUX_REQ_AES_OUT
1888 * @arg @ref LL_DMAMUX_REQ_HASH_IN
1889 * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
1890 * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
1891 */
LL_DMA_GetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel)1892 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
1893 {
1894 uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U);
1895 return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID));
1896 }
1897
1898 /**
1899 * @brief Set Memory 1 address (used in case of Double buffer mode).
1900 * @rmtoll CM1AR M1A LL_DMA_SetMemory1Address
1901 * @param DMAx DMAx Instance
1902 * @param Channel This parameter can be one of the following values:
1903 * @arg @ref LL_DMA_CHANNEL_1
1904 * @arg @ref LL_DMA_CHANNEL_2
1905 * @arg @ref LL_DMA_CHANNEL_3
1906 * @arg @ref LL_DMA_CHANNEL_4
1907 * @arg @ref LL_DMA_CHANNEL_5
1908 * @arg @ref LL_DMA_CHANNEL_6
1909 * @arg @ref LL_DMA_CHANNEL_7
1910 * @arg @ref LL_DMA_CHANNEL_8
1911 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1912 * @retval None
1913 */
LL_DMA_SetMemory1Address(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1914 __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1915 {
1916 uint32_t dma_base_addr = (uint32_t)DMAx;
1917 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CM1AR, MemoryAddress);
1918 }
1919
1920 /**
1921 * @brief Get Memory 1 address (used in case of Double buffer mode).
1922 * @rmtoll CM1AR MA LL_DMA_GetMemory1Address
1923 * @param DMAx DMAx Instance
1924 * @param Channel This parameter can be one of the following values:
1925 * @arg @ref LL_DMA_CHANNEL_1
1926 * @arg @ref LL_DMA_CHANNEL_2
1927 * @arg @ref LL_DMA_CHANNEL_3
1928 * @arg @ref LL_DMA_CHANNEL_4
1929 * @arg @ref LL_DMA_CHANNEL_5
1930 * @arg @ref LL_DMA_CHANNEL_6
1931 * @arg @ref LL_DMA_CHANNEL_7
1932 * @arg @ref LL_DMA_CHANNEL_8
1933 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1934 */
LL_DMA_GetMemory1Address(DMA_TypeDef * DMAx,uint32_t Channel)1935 __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Channel)
1936 {
1937 uint32_t dma_base_addr = (uint32_t)DMAx;
1938 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CM1AR));
1939 }
1940
1941 /**
1942 * @}
1943 */
1944
1945 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1946 * @{
1947 */
1948
1949 /**
1950 * @brief Get Channel 1 global interrupt flag.
1951 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1952 * @param DMAx DMAx Instance
1953 * @retval State of bit (1 or 0).
1954 */
LL_DMA_IsActiveFlag_GI1(DMA_TypeDef * DMAx)1955 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1956 {
1957 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
1958 }
1959
1960 /**
1961 * @brief Get Channel 2 global interrupt flag.
1962 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1963 * @param DMAx DMAx Instance
1964 * @retval State of bit (1 or 0).
1965 */
LL_DMA_IsActiveFlag_GI2(DMA_TypeDef * DMAx)1966 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1967 {
1968 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
1969 }
1970
1971 /**
1972 * @brief Get Channel 3 global interrupt flag.
1973 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1974 * @param DMAx DMAx Instance
1975 * @retval State of bit (1 or 0).
1976 */
LL_DMA_IsActiveFlag_GI3(DMA_TypeDef * DMAx)1977 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1978 {
1979 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
1980 }
1981
1982 /**
1983 * @brief Get Channel 4 global interrupt flag.
1984 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1985 * @param DMAx DMAx Instance
1986 * @retval State of bit (1 or 0).
1987 */
LL_DMA_IsActiveFlag_GI4(DMA_TypeDef * DMAx)1988 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1989 {
1990 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
1991 }
1992
1993 /**
1994 * @brief Get Channel 5 global interrupt flag.
1995 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1996 * @param DMAx DMAx Instance
1997 * @retval State of bit (1 or 0).
1998 */
LL_DMA_IsActiveFlag_GI5(DMA_TypeDef * DMAx)1999 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
2000 {
2001 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
2002 }
2003
2004 /**
2005 * @brief Get Channel 6 global interrupt flag.
2006 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
2007 * @param DMAx DMAx Instance
2008 * @retval State of bit (1 or 0).
2009 */
LL_DMA_IsActiveFlag_GI6(DMA_TypeDef * DMAx)2010 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
2011 {
2012 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
2013 }
2014
2015 /**
2016 * @brief Get Channel 7 global interrupt flag.
2017 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
2018 * @param DMAx DMAx Instance
2019 * @retval State of bit (1 or 0).
2020 */
LL_DMA_IsActiveFlag_GI7(DMA_TypeDef * DMAx)2021 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
2022 {
2023 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
2024 }
2025
2026 /**
2027 * @brief Get Channel 8 global interrupt flag.
2028 * @rmtoll ISR GIF8 LL_DMA_IsActiveFlag_GI8
2029 * @param DMAx DMAx Instance
2030 * @retval State of bit (1 or 0).
2031 */
LL_DMA_IsActiveFlag_GI8(DMA_TypeDef * DMAx)2032 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx)
2033 {
2034 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF8) == (DMA_ISR_GIF8))? 1UL : 0UL);
2035 }
2036
2037 /**
2038 * @brief Get Channel 1 transfer complete flag.
2039 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
2040 * @param DMAx DMAx Instance
2041 * @retval State of bit (1 or 0).
2042 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)2043 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
2044 {
2045 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
2046 }
2047
2048 /**
2049 * @brief Get Channel 2 transfer complete flag.
2050 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
2051 * @param DMAx DMAx Instance
2052 * @retval State of bit (1 or 0).
2053 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)2054 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
2055 {
2056 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
2057 }
2058
2059 /**
2060 * @brief Get Channel 3 transfer complete flag.
2061 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
2062 * @param DMAx DMAx Instance
2063 * @retval State of bit (1 or 0).
2064 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)2065 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
2066 {
2067 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
2068 }
2069
2070 /**
2071 * @brief Get Channel 4 transfer complete flag.
2072 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
2073 * @param DMAx DMAx Instance
2074 * @retval State of bit (1 or 0).
2075 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)2076 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
2077 {
2078 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
2079 }
2080
2081 /**
2082 * @brief Get Channel 5 transfer complete flag.
2083 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
2084 * @param DMAx DMAx Instance
2085 * @retval State of bit (1 or 0).
2086 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)2087 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
2088 {
2089 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
2090 }
2091
2092 /**
2093 * @brief Get Channel 6 transfer complete flag.
2094 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
2095 * @param DMAx DMAx Instance
2096 * @retval State of bit (1 or 0).
2097 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)2098 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
2099 {
2100 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
2101 }
2102
2103 /**
2104 * @brief Get Channel 7 transfer complete flag.
2105 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
2106 * @param DMAx DMAx Instance
2107 * @retval State of bit (1 or 0).
2108 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)2109 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
2110 {
2111 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
2112 }
2113
2114 /**
2115 * @brief Get Channel 8 transfer complete flag.
2116 * @rmtoll ISR TCIF8 LL_DMA_IsActiveFlag_TC8
2117 * @param DMAx DMAx Instance
2118 * @retval State of bit (1 or 0).
2119 */
LL_DMA_IsActiveFlag_TC8(DMA_TypeDef * DMAx)2120 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx)
2121 {
2122 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF8) == (DMA_ISR_TCIF8)) ? 1UL : 0UL);
2123 }
2124
2125 /**
2126 * @brief Get Channel 1 half transfer flag.
2127 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
2128 * @param DMAx DMAx Instance
2129 * @retval State of bit (1 or 0).
2130 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)2131 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
2132 {
2133 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
2134 }
2135
2136 /**
2137 * @brief Get Channel 2 half transfer flag.
2138 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
2139 * @param DMAx DMAx Instance
2140 * @retval State of bit (1 or 0).
2141 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)2142 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
2143 {
2144 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
2145 }
2146
2147 /**
2148 * @brief Get Channel 3 half transfer flag.
2149 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
2150 * @param DMAx DMAx Instance
2151 * @retval State of bit (1 or 0).
2152 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)2153 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
2154 {
2155 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
2156 }
2157
2158 /**
2159 * @brief Get Channel 4 half transfer flag.
2160 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
2161 * @param DMAx DMAx Instance
2162 * @retval State of bit (1 or 0).
2163 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)2164 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
2165 {
2166 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
2167 }
2168
2169 /**
2170 * @brief Get Channel 5 half transfer flag.
2171 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
2172 * @param DMAx DMAx Instance
2173 * @retval State of bit (1 or 0).
2174 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)2175 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
2176 {
2177 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
2178 }
2179
2180 /**
2181 * @brief Get Channel 6 half transfer flag.
2182 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
2183 * @param DMAx DMAx Instance
2184 * @retval State of bit (1 or 0).
2185 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)2186 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
2187 {
2188 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
2189 }
2190
2191 /**
2192 * @brief Get Channel 7 half transfer flag.
2193 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
2194 * @param DMAx DMAx Instance
2195 * @retval State of bit (1 or 0).
2196 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)2197 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
2198 {
2199 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
2200 }
2201
2202 /**
2203 * @brief Get Channel 8 half transfer flag.
2204 * @rmtoll ISR HTIF8 LL_DMA_IsActiveFlag_HT8
2205 * @param DMAx DMAx Instance
2206 * @retval State of bit (1 or 0).
2207 */
LL_DMA_IsActiveFlag_HT8(DMA_TypeDef * DMAx)2208 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx)
2209 {
2210 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF8) == (DMA_ISR_HTIF8)) ? 1UL : 0UL);
2211 }
2212
2213 /**
2214 * @brief Get Channel 1 transfer error flag.
2215 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
2216 * @param DMAx DMAx Instance
2217 * @retval State of bit (1 or 0).
2218 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)2219 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
2220 {
2221 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
2222 }
2223
2224 /**
2225 * @brief Get Channel 2 transfer error flag.
2226 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
2227 * @param DMAx DMAx Instance
2228 * @retval State of bit (1 or 0).
2229 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)2230 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
2231 {
2232 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
2233 }
2234
2235 /**
2236 * @brief Get Channel 3 transfer error flag.
2237 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
2238 * @param DMAx DMAx Instance
2239 * @retval State of bit (1 or 0).
2240 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)2241 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
2242 {
2243 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
2244 }
2245
2246 /**
2247 * @brief Get Channel 4 transfer error flag.
2248 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
2249 * @param DMAx DMAx Instance
2250 * @retval State of bit (1 or 0).
2251 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)2252 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
2253 {
2254 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
2255 }
2256
2257 /**
2258 * @brief Get Channel 5 transfer error flag.
2259 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
2260 * @param DMAx DMAx Instance
2261 * @retval State of bit (1 or 0).
2262 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)2263 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
2264 {
2265 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
2266 }
2267
2268 /**
2269 * @brief Get Channel 6 transfer error flag.
2270 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
2271 * @param DMAx DMAx Instance
2272 * @retval State of bit (1 or 0).
2273 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)2274 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
2275 {
2276 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
2277 }
2278
2279 /**
2280 * @brief Get Channel 7 transfer error flag.
2281 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
2282 * @param DMAx DMAx Instance
2283 * @retval State of bit (1 or 0).
2284 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)2285 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
2286 {
2287 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
2288 }
2289
2290 /**
2291 * @brief Get Channel 8 transfer error flag.
2292 * @rmtoll ISR TEIF8 LL_DMA_IsActiveFlag_TE8
2293 * @param DMAx DMAx Instance
2294 * @retval State of bit (1 or 0).
2295 */
LL_DMA_IsActiveFlag_TE8(DMA_TypeDef * DMAx)2296 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx)
2297 {
2298 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF8) == (DMA_ISR_TEIF8)) ? 1UL : 0UL);
2299 }
2300
2301 /**
2302 * @brief Clear Channel 1 global interrupt flag.
2303 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
2304 * @param DMAx DMAx Instance
2305 * @retval None
2306 */
LL_DMA_ClearFlag_GI1(DMA_TypeDef * DMAx)2307 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
2308 {
2309 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
2310 }
2311
2312 /**
2313 * @brief Clear Channel 2 global interrupt flag.
2314 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
2315 * @param DMAx DMAx Instance
2316 * @retval None
2317 */
LL_DMA_ClearFlag_GI2(DMA_TypeDef * DMAx)2318 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
2319 {
2320 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
2321 }
2322
2323 /**
2324 * @brief Clear Channel 3 global interrupt flag.
2325 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
2326 * @param DMAx DMAx Instance
2327 * @retval None
2328 */
LL_DMA_ClearFlag_GI3(DMA_TypeDef * DMAx)2329 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
2330 {
2331 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
2332 }
2333
2334 /**
2335 * @brief Clear Channel 4 global interrupt flag.
2336 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
2337 * @param DMAx DMAx Instance
2338 * @retval None
2339 */
LL_DMA_ClearFlag_GI4(DMA_TypeDef * DMAx)2340 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
2341 {
2342 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
2343 }
2344
2345 /**
2346 * @brief Clear Channel 5 global interrupt flag.
2347 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
2348 * @param DMAx DMAx Instance
2349 * @retval None
2350 */
LL_DMA_ClearFlag_GI5(DMA_TypeDef * DMAx)2351 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
2352 {
2353 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
2354 }
2355
2356 /**
2357 * @brief Clear Channel 6 global interrupt flag.
2358 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
2359 * @param DMAx DMAx Instance
2360 * @retval None
2361 */
LL_DMA_ClearFlag_GI6(DMA_TypeDef * DMAx)2362 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
2363 {
2364 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
2365 }
2366
2367 /**
2368 * @brief Clear Channel 7 global interrupt flag.
2369 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
2370 * @param DMAx DMAx Instance
2371 * @retval None
2372 */
LL_DMA_ClearFlag_GI7(DMA_TypeDef * DMAx)2373 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
2374 {
2375 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
2376 }
2377
2378 /**
2379 * @brief Clear Channel 8 global interrupt flag.
2380 * @rmtoll IFCR CGIF8 LL_DMA_ClearFlag_GI8
2381 * @param DMAx DMAx Instance
2382 * @retval None
2383 */
LL_DMA_ClearFlag_GI8(DMA_TypeDef * DMAx)2384 __STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx)
2385 {
2386 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF8);
2387 }
2388
2389 /**
2390 * @brief Clear Channel 1 transfer complete flag.
2391 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
2392 * @param DMAx DMAx Instance
2393 * @retval None
2394 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)2395 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
2396 {
2397 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
2398 }
2399
2400 /**
2401 * @brief Clear Channel 2 transfer complete flag.
2402 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
2403 * @param DMAx DMAx Instance
2404 * @retval None
2405 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)2406 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
2407 {
2408 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
2409 }
2410
2411 /**
2412 * @brief Clear Channel 3 transfer complete flag.
2413 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
2414 * @param DMAx DMAx Instance
2415 * @retval None
2416 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)2417 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
2418 {
2419 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
2420 }
2421
2422 /**
2423 * @brief Clear Channel 4 transfer complete flag.
2424 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
2425 * @param DMAx DMAx Instance
2426 * @retval None
2427 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)2428 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
2429 {
2430 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
2431 }
2432
2433 /**
2434 * @brief Clear Channel 5 transfer complete flag.
2435 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
2436 * @param DMAx DMAx Instance
2437 * @retval None
2438 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)2439 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
2440 {
2441 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
2442 }
2443
2444 /**
2445 * @brief Clear Channel 6 transfer complete flag.
2446 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
2447 * @param DMAx DMAx Instance
2448 * @retval None
2449 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)2450 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
2451 {
2452 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
2453 }
2454
2455 /**
2456 * @brief Clear Channel 7 transfer complete flag.
2457 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
2458 * @param DMAx DMAx Instance
2459 * @retval None
2460 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)2461 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
2462 {
2463 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
2464 }
2465
2466 /**
2467 * @brief Clear Channel 8 transfer complete flag.
2468 * @rmtoll IFCR CTCIF8 LL_DMA_ClearFlag_TC8
2469 * @param DMAx DMAx Instance
2470 * @retval None
2471 */
LL_DMA_ClearFlag_TC8(DMA_TypeDef * DMAx)2472 __STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx)
2473 {
2474 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF8);
2475 }
2476
2477 /**
2478 * @brief Clear Channel 1 half transfer flag.
2479 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
2480 * @param DMAx DMAx Instance
2481 * @retval None
2482 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)2483 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
2484 {
2485 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
2486 }
2487
2488 /**
2489 * @brief Clear Channel 2 half transfer flag.
2490 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
2491 * @param DMAx DMAx Instance
2492 * @retval None
2493 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)2494 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
2495 {
2496 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
2497 }
2498
2499 /**
2500 * @brief Clear Channel 3 half transfer flag.
2501 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
2502 * @param DMAx DMAx Instance
2503 * @retval None
2504 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)2505 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
2506 {
2507 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
2508 }
2509
2510 /**
2511 * @brief Clear Channel 4 half transfer flag.
2512 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
2513 * @param DMAx DMAx Instance
2514 * @retval None
2515 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)2516 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
2517 {
2518 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
2519 }
2520
2521 /**
2522 * @brief Clear Channel 5 half transfer flag.
2523 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
2524 * @param DMAx DMAx Instance
2525 * @retval None
2526 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)2527 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
2528 {
2529 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
2530 }
2531
2532 /**
2533 * @brief Clear Channel 6 half transfer flag.
2534 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
2535 * @param DMAx DMAx Instance
2536 * @retval None
2537 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)2538 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
2539 {
2540 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
2541 }
2542
2543 /**
2544 * @brief Clear Channel 7 half transfer flag.
2545 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
2546 * @param DMAx DMAx Instance
2547 * @retval None
2548 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)2549 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
2550 {
2551 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
2552 }
2553
2554 /**
2555 * @brief Clear Channel 8 half transfer flag.
2556 * @rmtoll IFCR CHTIF8 LL_DMA_ClearFlag_HT8
2557 * @param DMAx DMAx Instance
2558 * @retval None
2559 */
LL_DMA_ClearFlag_HT8(DMA_TypeDef * DMAx)2560 __STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx)
2561 {
2562 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF8);
2563 }
2564
2565 /**
2566 * @brief Clear Channel 1 transfer error flag.
2567 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
2568 * @param DMAx DMAx Instance
2569 * @retval None
2570 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)2571 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
2572 {
2573 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
2574 }
2575
2576 /**
2577 * @brief Clear Channel 2 transfer error flag.
2578 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
2579 * @param DMAx DMAx Instance
2580 * @retval None
2581 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)2582 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
2583 {
2584 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
2585 }
2586
2587 /**
2588 * @brief Clear Channel 3 transfer error flag.
2589 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
2590 * @param DMAx DMAx Instance
2591 * @retval None
2592 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)2593 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
2594 {
2595 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
2596 }
2597
2598 /**
2599 * @brief Clear Channel 4 transfer error flag.
2600 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
2601 * @param DMAx DMAx Instance
2602 * @retval None
2603 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)2604 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
2605 {
2606 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
2607 }
2608
2609 /**
2610 * @brief Clear Channel 5 transfer error flag.
2611 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
2612 * @param DMAx DMAx Instance
2613 * @retval None
2614 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)2615 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
2616 {
2617 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
2618 }
2619
2620 /**
2621 * @brief Clear Channel 6 transfer error flag.
2622 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
2623 * @param DMAx DMAx Instance
2624 * @retval None
2625 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)2626 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
2627 {
2628 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
2629 }
2630
2631 /**
2632 * @brief Clear Channel 7 transfer error flag.
2633 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
2634 * @param DMAx DMAx Instance
2635 * @retval None
2636 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)2637 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2638 {
2639 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
2640 }
2641
2642 /**
2643 * @brief Clear Channel 8 transfer error flag.
2644 * @rmtoll IFCR CTEIF8 LL_DMA_ClearFlag_TE8
2645 * @param DMAx DMAx Instance
2646 * @retval None
2647 */
LL_DMA_ClearFlag_TE8(DMA_TypeDef * DMAx)2648 __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx)
2649 {
2650 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF8);
2651 }
2652
2653 /**
2654 * @}
2655 */
2656
2657 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2658 * @{
2659 */
2660 /**
2661 * @brief Enable Transfer complete interrupt.
2662 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
2663 * @param DMAx DMAx Instance
2664 * @param Channel This parameter can be one of the following values:
2665 * @arg @ref LL_DMA_CHANNEL_1
2666 * @arg @ref LL_DMA_CHANNEL_2
2667 * @arg @ref LL_DMA_CHANNEL_3
2668 * @arg @ref LL_DMA_CHANNEL_4
2669 * @arg @ref LL_DMA_CHANNEL_5
2670 * @arg @ref LL_DMA_CHANNEL_6
2671 * @arg @ref LL_DMA_CHANNEL_7
2672 * @arg @ref LL_DMA_CHANNEL_8
2673 * @retval None
2674 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2675 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2676 {
2677 uint32_t dma_base_addr = (uint32_t)DMAx;
2678 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
2679 }
2680
2681 /**
2682 * @brief Enable Half transfer interrupt.
2683 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
2684 * @param DMAx DMAx Instance
2685 * @param Channel This parameter can be one of the following values:
2686 * @arg @ref LL_DMA_CHANNEL_1
2687 * @arg @ref LL_DMA_CHANNEL_2
2688 * @arg @ref LL_DMA_CHANNEL_3
2689 * @arg @ref LL_DMA_CHANNEL_4
2690 * @arg @ref LL_DMA_CHANNEL_5
2691 * @arg @ref LL_DMA_CHANNEL_6
2692 * @arg @ref LL_DMA_CHANNEL_7
2693 * @arg @ref LL_DMA_CHANNEL_8
2694 * @retval None
2695 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2696 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2697 {
2698 uint32_t dma_base_addr = (uint32_t)DMAx;
2699 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
2700 }
2701
2702 /**
2703 * @brief Enable Transfer error interrupt.
2704 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
2705 * @param DMAx DMAx Instance
2706 * @param Channel This parameter can be one of the following values:
2707 * @arg @ref LL_DMA_CHANNEL_1
2708 * @arg @ref LL_DMA_CHANNEL_2
2709 * @arg @ref LL_DMA_CHANNEL_3
2710 * @arg @ref LL_DMA_CHANNEL_4
2711 * @arg @ref LL_DMA_CHANNEL_5
2712 * @arg @ref LL_DMA_CHANNEL_6
2713 * @arg @ref LL_DMA_CHANNEL_7
2714 * @arg @ref LL_DMA_CHANNEL_8
2715 * @retval None
2716 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2717 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2718 {
2719 uint32_t dma_base_addr = (uint32_t)DMAx;
2720 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
2721 }
2722
2723 /**
2724 * @brief Disable Transfer complete interrupt.
2725 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
2726 * @param DMAx DMAx Instance
2727 * @param Channel This parameter can be one of the following values:
2728 * @arg @ref LL_DMA_CHANNEL_1
2729 * @arg @ref LL_DMA_CHANNEL_2
2730 * @arg @ref LL_DMA_CHANNEL_3
2731 * @arg @ref LL_DMA_CHANNEL_4
2732 * @arg @ref LL_DMA_CHANNEL_5
2733 * @arg @ref LL_DMA_CHANNEL_6
2734 * @arg @ref LL_DMA_CHANNEL_7
2735 * @arg @ref LL_DMA_CHANNEL_8
2736 * @retval None
2737 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2738 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2739 {
2740 uint32_t dma_base_addr = (uint32_t)DMAx;
2741 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
2742 }
2743
2744 /**
2745 * @brief Disable Half transfer interrupt.
2746 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
2747 * @param DMAx DMAx Instance
2748 * @param Channel This parameter can be one of the following values:
2749 * @arg @ref LL_DMA_CHANNEL_1
2750 * @arg @ref LL_DMA_CHANNEL_2
2751 * @arg @ref LL_DMA_CHANNEL_3
2752 * @arg @ref LL_DMA_CHANNEL_4
2753 * @arg @ref LL_DMA_CHANNEL_5
2754 * @arg @ref LL_DMA_CHANNEL_6
2755 * @arg @ref LL_DMA_CHANNEL_7
2756 * @arg @ref LL_DMA_CHANNEL_8
2757 * @retval None
2758 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2759 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2760 {
2761 uint32_t dma_base_addr = (uint32_t)DMAx;
2762 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
2763 }
2764
2765 /**
2766 * @brief Disable Transfer error interrupt.
2767 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
2768 * @param DMAx DMAx Instance
2769 * @param Channel This parameter can be one of the following values:
2770 * @arg @ref LL_DMA_CHANNEL_1
2771 * @arg @ref LL_DMA_CHANNEL_2
2772 * @arg @ref LL_DMA_CHANNEL_3
2773 * @arg @ref LL_DMA_CHANNEL_4
2774 * @arg @ref LL_DMA_CHANNEL_5
2775 * @arg @ref LL_DMA_CHANNEL_6
2776 * @arg @ref LL_DMA_CHANNEL_7
2777 * @arg @ref LL_DMA_CHANNEL_8
2778 * @retval None
2779 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2780 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2781 {
2782 uint32_t dma_base_addr = (uint32_t)DMAx;
2783 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
2784 }
2785
2786 /**
2787 * @brief Check if Transfer complete Interrupt is enabled.
2788 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
2789 * @param DMAx DMAx Instance
2790 * @param Channel This parameter can be one of the following values:
2791 * @arg @ref LL_DMA_CHANNEL_1
2792 * @arg @ref LL_DMA_CHANNEL_2
2793 * @arg @ref LL_DMA_CHANNEL_3
2794 * @arg @ref LL_DMA_CHANNEL_4
2795 * @arg @ref LL_DMA_CHANNEL_5
2796 * @arg @ref LL_DMA_CHANNEL_6
2797 * @arg @ref LL_DMA_CHANNEL_7
2798 * @arg @ref LL_DMA_CHANNEL_8
2799 * @retval State of bit (1 or 0).
2800 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2801 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2802 {
2803 uint32_t dma_base_addr = (uint32_t)DMAx;
2804 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
2805 DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
2806 }
2807
2808 /**
2809 * @brief Check if Half transfer Interrupt is enabled.
2810 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
2811 * @param DMAx DMAx Instance
2812 * @param Channel This parameter can be one of the following values:
2813 * @arg @ref LL_DMA_CHANNEL_1
2814 * @arg @ref LL_DMA_CHANNEL_2
2815 * @arg @ref LL_DMA_CHANNEL_3
2816 * @arg @ref LL_DMA_CHANNEL_4
2817 * @arg @ref LL_DMA_CHANNEL_5
2818 * @arg @ref LL_DMA_CHANNEL_6
2819 * @arg @ref LL_DMA_CHANNEL_7
2820 * @arg @ref LL_DMA_CHANNEL_8
2821 * @retval State of bit (1 or 0).
2822 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2823 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2824 {
2825 uint32_t dma_base_addr = (uint32_t)DMAx;
2826 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
2827 DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
2828 }
2829
2830 /**
2831 * @brief Check if Transfer error Interrupt is enabled.
2832 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
2833 * @param DMAx DMAx Instance
2834 * @param Channel This parameter can be one of the following values:
2835 * @arg @ref LL_DMA_CHANNEL_1
2836 * @arg @ref LL_DMA_CHANNEL_2
2837 * @arg @ref LL_DMA_CHANNEL_3
2838 * @arg @ref LL_DMA_CHANNEL_4
2839 * @arg @ref LL_DMA_CHANNEL_5
2840 * @arg @ref LL_DMA_CHANNEL_6
2841 * @arg @ref LL_DMA_CHANNEL_7
2842 * @arg @ref LL_DMA_CHANNEL_8
2843 * @retval State of bit (1 or 0).
2844 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2845 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2846 {
2847 uint32_t dma_base_addr = (uint32_t)DMAx;
2848 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
2849 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
2850 }
2851
2852 /**
2853 * @}
2854 */
2855
2856 #if defined(USE_FULL_LL_DRIVER)
2857 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2858 * @{
2859 */
2860 ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
2861 ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
2862 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2863
2864 /**
2865 * @}
2866 */
2867 #endif /* USE_FULL_LL_DRIVER */
2868
2869 /**
2870 * @}
2871 */
2872
2873 /**
2874 * @}
2875 */
2876
2877 #endif /* DMA1 || DMA2 */
2878
2879 /**
2880 * @}
2881 */
2882
2883 #ifdef __cplusplus
2884 }
2885 #endif
2886
2887 #endif /* STM32L5xx_LL_DMA_H */
2888
2889
