1 /**
2 ******************************************************************************
3 * @file stm32l5xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L5xx_LL_DAC_H
21 #define STM32L5xx_LL_DAC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l5xx.h"
29
30 /** @addtogroup STM32L5xx_LL_Driver
31 * @{
32 */
33
34 #if defined(DAC1)
35
36 /** @defgroup DAC_LL DAC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
45 * @{
46 */
47
48 /* Internal masks for DAC channels definition */
49 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
50 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
51 /* - channel bits position into register SWTRIG */
52 /* - channel register offset of data holding register DHRx */
53 /* - channel register offset of data output register DORx */
54 /* - channel register offset of sample-and-hold sample time register SHSRx */
55 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
56 CR, MCR, CCR, SHHR, SHRR of channel 1 */
57 #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
58 CR, MCR, CCR, SHHR, SHRR of channel 2 */
59 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
60
61 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
62 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
63 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
64
65 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
66 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
67 DHR12Rx channel 1 (shifted left of 20 bits) */
68 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
69 DHR12Rx channel 1 (shifted left of 24 bits) */
70
71 #define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus
72 DHR12Rx channel 1 (shifted left of 28 bits) */
73 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
74 DHR12Rx channel 1 (shifted left of 20 bits) */
75 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
76 DHR12Rx channel 1 (shifted left of 24 bits) */
77
78 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
79 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
80 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
81 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
82 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
83
84 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
85
86 #define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus
87 DORx channel 2 (shifted left of 5 bits) */
88 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
89
90 #define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
91 #define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus
92 SHSRx channel 2 (shifted left of 6 bits) */
93 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
94
95
96 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
97 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
98 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
99 to position 0 */
100 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
101 to position 0 */
102
103 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx
104 channel 1 or 2 versus DHR12Rx channel 1
105 (shifted left of 28 bits) */
106 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
107 channel 1 or 2 versus DHR12Rx channel 1
108 (shifted left of 20 bits) */
109 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
110 channel 1 or 2 versus DHR12Rx channel 1
111 (shifted left of 24 bits) */
112 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx
113 channel 1 or 2 versus DORx channel 1
114 (shifted left of 5 bits) */
115 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx
116 channel 1 or 2 versus SHSRx channel 1
117 (shifted left of 6 bits) */
118
119 /* DAC registers bits positions */
120 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
121 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
122 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
123
124 /* Miscellaneous data */
125 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
126 bits (voltage range determined by analog voltage
127 references Vref+ and Vref-, refer to reference manual) */
128
129 /**
130 * @}
131 */
132
133
134 /* Private macros ------------------------------------------------------------*/
135 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
136 * @{
137 */
138
139 /**
140 * @brief Driver macro reserved for internal use: set a pointer to
141 * a register from a register basis from which an offset
142 * is applied.
143 * @param __REG__ Register basis from which the offset is applied.
144 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
145 * @retval Pointer to register address
146 */
147 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
148 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
149
150 /**
151 * @}
152 */
153
154
155 /* Exported types ------------------------------------------------------------*/
156 #if defined(USE_FULL_LL_DRIVER)
157 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
158 * @{
159 */
160
161 /**
162 * @brief Structure definition of some features of DAC instance.
163 */
164 typedef struct
165 {
166 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
167 internal (SW start) or from external peripheral
168 (timer event, external interrupt line).
169 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
170
171 This feature can be modified afterwards using unitary
172 function @ref LL_DAC_SetTriggerSource(). */
173
174 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
175 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
176
177 This feature can be modified afterwards using unitary
178 function @ref LL_DAC_SetWaveAutoGeneration(). */
179
180 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
181 If waveform automatic generation mode is set to noise, this parameter
182 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
183 If waveform automatic generation mode is set to triangle,
184 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
185 @note If waveform automatic generation mode is disabled,
186 this parameter is discarded.
187
188 This feature can be modified afterwards using unitary
189 function @ref LL_DAC_SetWaveNoiseLFSR(),
190 @ref LL_DAC_SetWaveTriangleAmplitude()
191 depending on the wave automatic generation selected. */
192
193 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
194 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
195
196 This feature can be modified afterwards using unitary
197 function @ref LL_DAC_SetOutputBuffer(). */
198
199 uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
200 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
201
202 This feature can be modified afterwards using unitary
203 function @ref LL_DAC_SetOutputConnection(). */
204
205 uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC
206 channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
207
208 This feature can be modified afterwards using unitary
209 function @ref LL_DAC_SetOutputMode(). */
210 } LL_DAC_InitTypeDef;
211
212 /**
213 * @}
214 */
215 #endif /* USE_FULL_LL_DRIVER */
216
217 /* Exported constants --------------------------------------------------------*/
218 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
219 * @{
220 */
221
222 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
223 * @brief Flags defines which can be used with LL_DAC_ReadReg function
224 * @{
225 */
226 /* DAC channel 1 flags */
227 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
228 #define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
229 #define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */
230
231 /* DAC channel 2 flags */
232 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
233 #define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
234 #define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */
235
236 /**
237 * @}
238 */
239
240 /** @defgroup DAC_LL_EC_IT DAC interruptions
241 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
242 * @{
243 */
244 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
245
246 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
247
248 /**
249 * @}
250 */
251
252 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
253 * @{
254 */
255 #define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
256 #define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
257 /**
258 * @}
259 */
260
261 /** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode
262 * @brief High frequency interface mode defines that can be used
263 * with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode
264 * @{
265 */
266 #define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */
267 #define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_CR_HFSEL) /*!< High frequency interface mode compatible to AHB>80MHz enabled */
268 /**
269 * @}
270 */
271
272 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
273 * @{
274 */
275 #define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL /*!< DAC channel in mode normal operation */
276 #define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */
277 /**
278 * @}
279 */
280
281 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
282 * @{
283 */
284 #define LL_DAC_TRIG_SOFTWARE 0x00000000UL /*!< DAC channel conversion trigger internal (SW start) */
285 #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM1 TRGO. */
286 #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
287 #define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
288 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
289 #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
290 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
291 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
292 #define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
293 #define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */
294 #define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM2 TRGO. */
295 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
296 /**
297 * @}
298 */
299
300 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
301 * @{
302 */
303 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
304 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
305 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
306 /**
307 * @}
308 */
309
310 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
311 * @{
312 */
313 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
314 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
315 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
316 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
317 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
318 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
319 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
320 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
321 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
322 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
323 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
324 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
325 /**
326 * @}
327 */
328
329 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
330 * @{
331 */
332 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
333 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
334 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
335 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
336 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
337 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
338 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
339 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
340 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
341 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
342 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
343 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
344 /**
345 * @}
346 */
347
348 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
349 * @{
350 */
351 #define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL /*!< The selected DAC channel output is on mode normal. */
352 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
353 /**
354 * @}
355 */
356
357 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
358 * @{
359 */
360 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
361 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
362 /**
363 * @}
364 */
365
366 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
367 * @{
368 */
369 #define LL_DAC_OUTPUT_CONNECT_EXTERNAL (1UL << 0) /*!< The selected DAC channel output is connected to external pin */
370 #define LL_DAC_OUTPUT_CONNECT_INTERNAL (1UL << 1) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
371 #define LL_DAC_OUTPUT_CONNECT_BOTH (1UL << 2) /*!< The selected DAC channel output is connected to extrenan and to on-chip peripherals via internal paths. */
372
373 #define LL_DAC_OUTPUT_CONNECT_GPIO LL_DAC_OUTPUT_CONNECT_EXTERNAL /*!< kept for legacy purpose */
374 /**
375 * @}
376 */
377
378 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
379 * @{
380 */
381 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
382 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
383 /**
384 * @}
385 */
386
387 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
388 * @{
389 */
390 /* List of DAC registers intended to be used (most commonly) with */
391 /* DMA transfer. */
392 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
393 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
394 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
395 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
396 /**
397 * @}
398 */
399
400 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
401 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
402 * not timeout values.
403 * For details on delays values, refer to descriptions in source code
404 * above each literal definition.
405 * @{
406 */
407
408 /* Delay for DAC channel voltage settling time from DAC channel startup */
409 /* (transition from disable to enable). */
410 /* Note: DAC channel startup time depends on board application environment: */
411 /* impedance connected to DAC channel output. */
412 /* The delay below is specified under conditions: */
413 /* - voltage maximum transition (lowest to highest value) */
414 /* - until voltage reaches final value +-1LSB */
415 /* - DAC channel output buffer enabled */
416 /* - load impedance of 5kOhm (min), 50pF (max) */
417 /* Literal set to maximum value (refer to device datasheet, */
418 /* parameter "tWAKEUP"). */
419 /* Unit: us */
420 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
421
422 /* Delay for DAC channel voltage settling time. */
423 /* Note: DAC channel startup time depends on board application environment: */
424 /* impedance connected to DAC channel output. */
425 /* The delay below is specified under conditions: */
426 /* - voltage maximum transition (lowest to highest value) */
427 /* - until voltage reaches final value +-1LSB */
428 /* - DAC channel output buffer enabled */
429 /* - load impedance of 5kOhm min, 50pF max */
430 /* Literal set to maximum value (refer to device datasheet, */
431 /* parameter "tSETTLING"). */
432 /* Unit: us */
433 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL /*!< Delay for DAC channel voltage settling time */
434
435 /**
436 * @}
437 */
438
439 /**
440 * @}
441 */
442
443 /* Exported macro ------------------------------------------------------------*/
444 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
445 * @{
446 */
447
448 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
449 * @{
450 */
451
452 /**
453 * @brief Write a value in DAC register
454 * @param __INSTANCE__ DAC Instance
455 * @param __REG__ Register to be written
456 * @param __VALUE__ Value to be written in the register
457 * @retval None
458 */
459 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
460
461 /**
462 * @brief Read a value in DAC register
463 * @param __INSTANCE__ DAC Instance
464 * @param __REG__ Register to be read
465 * @retval Register value
466 */
467 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
468
469 /**
470 * @}
471 */
472
473 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
474 * @{
475 */
476
477 /**
478 * @brief Helper macro to get DAC channel number in decimal format
479 * from literals LL_DAC_CHANNEL_x.
480 * Example:
481 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
482 * will return decimal number "1".
483 * @note The input can be a value from functions where a channel
484 * number is returned.
485 * @param __CHANNEL__ This parameter can be one of the following values:
486 * @arg @ref LL_DAC_CHANNEL_1
487 * @arg @ref LL_DAC_CHANNEL_2
488 * @retval 1...2
489 */
490 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
491 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
492
493 /**
494 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
495 * from number in decimal format.
496 * Example:
497 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
498 * will return a data equivalent to "LL_DAC_CHANNEL_1".
499 * @note If the input parameter does not correspond to a DAC channel,
500 * this macro returns value '0'.
501 * @param __DECIMAL_NB__ 1...2
502 * @retval Returned value can be one of the following values:
503 * @arg @ref LL_DAC_CHANNEL_1
504 * @arg @ref LL_DAC_CHANNEL_2
505 */
506 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
507 (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
508
509 /**
510 * @brief Helper macro to define the DAC conversion data full-scale digital
511 * value corresponding to the selected DAC resolution.
512 * @note DAC conversion data full-scale corresponds to voltage range
513 * determined by analog voltage references Vref+ and Vref-
514 * (refer to reference manual).
515 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
516 * @arg @ref LL_DAC_RESOLUTION_12B
517 * @arg @ref LL_DAC_RESOLUTION_8B
518 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
519 */
520 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
521 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
522
523 /**
524 * @brief Helper macro to calculate the DAC conversion data (unit: digital
525 * value) corresponding to a voltage (unit: mVolt).
526 * @note This helper macro is intended to provide input data in voltage
527 * rather than digital value,
528 * to be used with LL DAC functions such as
529 * @ref LL_DAC_ConvertData12RightAligned().
530 * @note Analog reference voltage (Vref+) must be either known from
531 * user board environment or can be calculated using ADC measurement
532 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
533 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
534 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
535 * (unit: mVolt).
536 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
537 * @arg @ref LL_DAC_RESOLUTION_12B
538 * @arg @ref LL_DAC_RESOLUTION_8B
539 * @retval DAC conversion data (unit: digital value)
540 */
541 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
542 __DAC_VOLTAGE__,\
543 __DAC_RESOLUTION__) \
544 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
545 / (__VREFANALOG_VOLTAGE__) \
546 )
547
548 /**
549 * @}
550 */
551
552 /**
553 * @}
554 */
555
556
557 /* Exported functions --------------------------------------------------------*/
558 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
559 * @{
560 */
561 /** @defgroup DAC_LL_EF_Channel_Configuration Configuration of DAC instance
562 * @{
563 */
564 /**
565 * @brief Set the high frequency interface mode for the selected DAC instance
566 * @rmtoll CR HFSEL LL_DAC_SetHighFrequencyMode
567 * @param DACx DAC instance
568 * @param HighFreqMode This parameter can be one of the following values:
569 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
570 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
571 * @retval None
572 */
LL_DAC_SetHighFrequencyMode(DAC_TypeDef * DACx,uint32_t HighFreqMode)573 __STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t HighFreqMode)
574 {
575 MODIFY_REG(DACx->CR, DAC_CR_HFSEL, HighFreqMode);
576 }
577
578 /**
579 * @brief Get the high frequency interface mode for the selected DAC instance
580 * @rmtoll CR HFSEL LL_DAC_GetHighFrequencyMode
581 * @param DACx DAC instance
582 * @retval Returned value can be one of the following values:
583 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
584 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
585 */
LL_DAC_GetHighFrequencyMode(DAC_TypeDef * DACx)586 __STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(DAC_TypeDef *DACx)
587 {
588 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_HFSEL));
589 }
590 /**
591 * @}
592 */
593
594 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
595 * @{
596 */
597
598 /**
599 * @brief Set the operating mode for the selected DAC channel:
600 * calibration or normal operating mode.
601 * @rmtoll CR CEN1 LL_DAC_SetMode\n
602 * CR CEN2 LL_DAC_SetMode
603 * @param DACx DAC instance
604 * @param DAC_Channel This parameter can be one of the following values:
605 * @arg @ref LL_DAC_CHANNEL_1
606 * @arg @ref LL_DAC_CHANNEL_2
607 * @param ChannelMode This parameter can be one of the following values:
608 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
609 * @arg @ref LL_DAC_MODE_CALIBRATION
610 * @retval None
611 */
LL_DAC_SetMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t ChannelMode)612 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
613 {
614 MODIFY_REG(DACx->CR,
615 DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
616 ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
617 }
618
619 /**
620 * @brief Get the operating mode for the selected DAC channel:
621 * calibration or normal operating mode.
622 * @rmtoll CR CEN1 LL_DAC_GetMode\n
623 * CR CEN2 LL_DAC_GetMode
624 * @param DACx DAC instance
625 * @param DAC_Channel This parameter can be one of the following values:
626 * @arg @ref LL_DAC_CHANNEL_1
627 * @arg @ref LL_DAC_CHANNEL_2
628 * @retval Returned value can be one of the following values:
629 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
630 * @arg @ref LL_DAC_MODE_CALIBRATION
631 */
LL_DAC_GetMode(DAC_TypeDef * DACx,uint32_t DAC_Channel)632 __STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
633 {
634 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
635 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
636 );
637 }
638
639 /**
640 * @brief Set the offset trimming value for the selected DAC channel.
641 * Trimming has an impact when output buffer is enabled
642 * and is intended to replace factory calibration default values.
643 * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n
644 * CCR OTRIM2 LL_DAC_SetTrimmingValue
645 * @param DACx DAC instance
646 * @param DAC_Channel This parameter can be one of the following values:
647 * @arg @ref LL_DAC_CHANNEL_1
648 * @arg @ref LL_DAC_CHANNEL_2
649 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
650 * @retval None
651 */
LL_DAC_SetTrimmingValue(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TrimmingValue)652 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
653 {
654 MODIFY_REG(DACx->CCR,
655 DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
656 TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
657 }
658
659 /**
660 * @brief Get the offset trimming value for the selected DAC channel.
661 * Trimming has an impact when output buffer is enabled
662 * and is intended to replace factory calibration default values.
663 * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n
664 * CCR OTRIM2 LL_DAC_GetTrimmingValue
665 * @param DACx DAC instance
666 * @param DAC_Channel This parameter can be one of the following values:
667 * @arg @ref LL_DAC_CHANNEL_1
668 * @arg @ref LL_DAC_CHANNEL_2
669 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
670 */
LL_DAC_GetTrimmingValue(DAC_TypeDef * DACx,uint32_t DAC_Channel)671 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
672 {
673 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
674 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
675 );
676 }
677
678 /**
679 * @brief Set the conversion trigger source for the selected DAC channel.
680 * @note For conversion trigger source to be effective, DAC trigger
681 * must be enabled using function @ref LL_DAC_EnableTrigger().
682 * @note To set conversion trigger source, DAC channel must be disabled.
683 * Otherwise, the setting is discarded.
684 * @note Availability of parameters of trigger sources from timer
685 * depends on timers availability on the selected device.
686 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
687 * CR TSEL2 LL_DAC_SetTriggerSource
688 * @param DACx DAC instance
689 * @param DAC_Channel This parameter can be one of the following values:
690 * @arg @ref LL_DAC_CHANNEL_1
691 * @arg @ref LL_DAC_CHANNEL_2
692 * @param TriggerSource This parameter can be one of the following values:
693 * @arg @ref LL_DAC_TRIG_SOFTWARE
694 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
695 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
696 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
697 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
698 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
699 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
700 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
701 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
702 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
703 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
704 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
705 * @retval None
706 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)707 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
708 {
709 MODIFY_REG(DACx->CR,
710 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
711 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
712 }
713
714 /**
715 * @brief Get the conversion trigger source for the selected DAC channel.
716 * @note For conversion trigger source to be effective, DAC trigger
717 * must be enabled using function @ref LL_DAC_EnableTrigger().
718 * @note Availability of parameters of trigger sources from timer
719 * depends on timers availability on the selected device.
720 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
721 * CR TSEL2 LL_DAC_GetTriggerSource
722 * @param DACx DAC instance
723 * @param DAC_Channel This parameter can be one of the following values:
724 * @arg @ref LL_DAC_CHANNEL_1
725 * @arg @ref LL_DAC_CHANNEL_2
726 * @retval Returned value can be one of the following values:
727 * @arg @ref LL_DAC_TRIG_SOFTWARE
728 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
729 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
730 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
731 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
732 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
733 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
734 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
735 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
736 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
737 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
738 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
739 */
LL_DAC_GetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel)740 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
741 {
742 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
743 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
744 );
745 }
746
747 /**
748 * @brief Set the waveform automatic generation mode
749 * for the selected DAC channel.
750 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
751 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
752 * @param DACx DAC instance
753 * @param DAC_Channel This parameter can be one of the following values:
754 * @arg @ref LL_DAC_CHANNEL_1
755 * @arg @ref LL_DAC_CHANNEL_2
756 * @param WaveAutoGeneration This parameter can be one of the following values:
757 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
758 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
759 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
760 * @retval None
761 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)762 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
763 {
764 MODIFY_REG(DACx->CR,
765 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
766 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
767 }
768
769 /**
770 * @brief Get the waveform automatic generation mode
771 * for the selected DAC channel.
772 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
773 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
774 * @param DACx DAC instance
775 * @param DAC_Channel This parameter can be one of the following values:
776 * @arg @ref LL_DAC_CHANNEL_1
777 * @arg @ref LL_DAC_CHANNEL_2
778 * @retval Returned value can be one of the following values:
779 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
780 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
781 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
782 */
LL_DAC_GetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel)783 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
784 {
785 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
786 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
787 );
788 }
789
790 /**
791 * @brief Set the noise waveform generation for the selected DAC channel:
792 * Noise mode and parameters LFSR (linear feedback shift register).
793 * @note For wave generation to be effective, DAC channel
794 * wave generation mode must be enabled using
795 * function @ref LL_DAC_SetWaveAutoGeneration().
796 * @note This setting can be set when the selected DAC channel is disabled
797 * (otherwise, the setting operation is ignored).
798 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
799 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
800 * @param DACx DAC instance
801 * @param DAC_Channel This parameter can be one of the following values:
802 * @arg @ref LL_DAC_CHANNEL_1
803 * @arg @ref LL_DAC_CHANNEL_2
804 * @param NoiseLFSRMask This parameter can be one of the following values:
805 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
806 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
807 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
808 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
809 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
810 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
811 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
812 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
813 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
814 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
815 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
816 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
817 * @retval None
818 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)819 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
820 {
821 MODIFY_REG(DACx->CR,
822 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
823 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
824 }
825
826 /**
827 * @brief Get the noise waveform generation for the selected DAC channel:
828 * Noise mode and parameters LFSR (linear feedback shift register).
829 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
830 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
831 * @param DACx DAC instance
832 * @param DAC_Channel This parameter can be one of the following values:
833 * @arg @ref LL_DAC_CHANNEL_1
834 * @arg @ref LL_DAC_CHANNEL_2
835 * @retval Returned value can be one of the following values:
836 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
837 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
838 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
839 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
840 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
841 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
842 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
843 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
844 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
845 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
846 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
847 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
848 */
LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel)849 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
850 {
851 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
852 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
853 );
854 }
855
856 /**
857 * @brief Set the triangle waveform generation for the selected DAC channel:
858 * triangle mode and amplitude.
859 * @note For wave generation to be effective, DAC channel
860 * wave generation mode must be enabled using
861 * function @ref LL_DAC_SetWaveAutoGeneration().
862 * @note This setting can be set when the selected DAC channel is disabled
863 * (otherwise, the setting operation is ignored).
864 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
865 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
866 * @param DACx DAC instance
867 * @param DAC_Channel This parameter can be one of the following values:
868 * @arg @ref LL_DAC_CHANNEL_1
869 * @arg @ref LL_DAC_CHANNEL_2
870 * @param TriangleAmplitude This parameter can be one of the following values:
871 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
872 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
873 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
874 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
875 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
876 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
877 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
878 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
879 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
880 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
881 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
882 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
883 * @retval None
884 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)885 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
886 uint32_t TriangleAmplitude)
887 {
888 MODIFY_REG(DACx->CR,
889 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
890 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
891 }
892
893 /**
894 * @brief Get the triangle waveform generation for the selected DAC channel:
895 * triangle mode and amplitude.
896 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
897 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
898 * @param DACx DAC instance
899 * @param DAC_Channel This parameter can be one of the following values:
900 * @arg @ref LL_DAC_CHANNEL_1
901 * @arg @ref LL_DAC_CHANNEL_2
902 * @retval Returned value can be one of the following values:
903 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
904 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
905 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
906 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
907 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
908 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
909 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
910 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
911 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
912 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
913 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
914 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
915 */
LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel)916 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
917 {
918 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
919 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
920 );
921 }
922
923 /**
924 * @brief Set the output for the selected DAC channel.
925 * @note This function set several features:
926 * - mode normal or sample-and-hold
927 * - buffer
928 * - connection to GPIO or internal path.
929 * These features can also be set individually using
930 * dedicated functions:
931 * - @ref LL_DAC_SetOutputBuffer()
932 * - @ref LL_DAC_SetOutputMode()
933 * - @ref LL_DAC_SetOutputConnection()
934 * @note On this STM32 series, output connection depends on output mode
935 * (normal or sample and hold) and output buffer state.
936 * - if output connection is set to internal path and output buffer
937 * is enabled (whatever output mode):
938 * output connection is also connected to GPIO pin
939 * (both connections to GPIO pin and internal path).
940 * - if output connection is set to GPIO pin, output buffer
941 * is disabled, output mode set to sample and hold:
942 * output connection is also connected to internal path
943 * (both connections to GPIO pin and internal path).
944 * @note Mode sample-and-hold requires an external capacitor
945 * to be connected between DAC channel output and ground.
946 * Capacitor value depends on load on DAC channel output and
947 * sample-and-hold timings configured.
948 * As indication, capacitor typical value is 100nF
949 * (refer to device datasheet, parameter "CSH").
950 * @rmtoll CR MODE1 LL_DAC_ConfigOutput\n
951 * CR MODE2 LL_DAC_ConfigOutput
952 * @param DACx DAC instance
953 * @param DAC_Channel This parameter can be one of the following values:
954 * @arg @ref LL_DAC_CHANNEL_1
955 * @arg @ref LL_DAC_CHANNEL_2
956 * @param OutputMode This parameter can be one of the following values:
957 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
958 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
959 * @param OutputBuffer This parameter can be one of the following values:
960 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
961 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
962 * @param OutputConnection This parameter can be one of the following values:
963 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
964 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
965 * @retval None
966 */
LL_DAC_ConfigOutput(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode,uint32_t OutputBuffer,uint32_t OutputConnection)967 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
968 uint32_t OutputBuffer, uint32_t OutputConnection)
969 {
970 MODIFY_REG(DACx->MCR,
971 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
972 (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
973 }
974
975 /**
976 * @brief Set the output mode normal or sample-and-hold
977 * for the selected DAC channel.
978 * @note Mode sample-and-hold requires an external capacitor
979 * to be connected between DAC channel output and ground.
980 * Capacitor value depends on load on DAC channel output and
981 * sample-and-hold timings configured.
982 * As indication, capacitor typical value is 100nF
983 * (refer to device datasheet, parameter "CSH").
984 * @rmtoll CR MODE1 LL_DAC_SetOutputMode\n
985 * CR MODE2 LL_DAC_SetOutputMode
986 * @param DACx DAC instance
987 * @param DAC_Channel This parameter can be one of the following values:
988 * @arg @ref LL_DAC_CHANNEL_1
989 * @arg @ref LL_DAC_CHANNEL_2
990 * @param OutputMode This parameter can be one of the following values:
991 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
992 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
993 * @retval None
994 */
LL_DAC_SetOutputMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode)995 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
996 {
997 MODIFY_REG(DACx->MCR,
998 (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
999 OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1000 }
1001
1002 /**
1003 * @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
1004 * @rmtoll CR MODE1 LL_DAC_GetOutputMode\n
1005 * CR MODE2 LL_DAC_GetOutputMode
1006 * @param DACx DAC instance
1007 * @param DAC_Channel This parameter can be one of the following values:
1008 * @arg @ref LL_DAC_CHANNEL_1
1009 * @arg @ref LL_DAC_CHANNEL_2
1010 * @retval Returned value can be one of the following values:
1011 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1012 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1013 */
LL_DAC_GetOutputMode(DAC_TypeDef * DACx,uint32_t DAC_Channel)1014 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1015 {
1016 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1017 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1018 );
1019 }
1020
1021 /**
1022 * @brief Set the output buffer for the selected DAC channel.
1023 * @note On this STM32 series, when buffer is enabled, its offset can be
1024 * trimmed: factory calibration default values can be
1025 * replaced by user trimming values, using function
1026 * @ref LL_DAC_SetTrimmingValue().
1027 * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n
1028 * CR MODE2 LL_DAC_SetOutputBuffer
1029 * @param DACx DAC instance
1030 * @param DAC_Channel This parameter can be one of the following values:
1031 * @arg @ref LL_DAC_CHANNEL_1
1032 * @arg @ref LL_DAC_CHANNEL_2
1033 * @param OutputBuffer This parameter can be one of the following values:
1034 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1035 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1036 * @retval None
1037 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)1038 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
1039 {
1040 MODIFY_REG(DACx->MCR,
1041 (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1042 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1043 }
1044
1045 /**
1046 * @brief Get the output buffer state for the selected DAC channel.
1047 * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n
1048 * CR MODE2 LL_DAC_GetOutputBuffer
1049 * @param DACx DAC instance
1050 * @param DAC_Channel This parameter can be one of the following values:
1051 * @arg @ref LL_DAC_CHANNEL_1
1052 * @arg @ref LL_DAC_CHANNEL_2
1053 * @retval Returned value can be one of the following values:
1054 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1055 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1056 */
LL_DAC_GetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel)1057 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1058 {
1059 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1060 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1061 );
1062 }
1063
1064 /**
1065 * @brief Set the output connection for the selected DAC channel.
1066 * @note On this STM32 series, output connection depends on output mode (normal or
1067 * sample and hold) and output buffer state.
1068 * - if output connection is set to internal path and output buffer
1069 * is enabled (whatever output mode):
1070 * output connection is also connected to GPIO pin
1071 * (both connections to GPIO pin and internal path).
1072 * - if output connection is set to GPIO pin, output buffer
1073 * is disabled, output mode set to sample and hold:
1074 * output connection is also connected to internal path
1075 * (both connections to GPIO pin and internal path).
1076 * @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n
1077 * CR MODE2 LL_DAC_SetOutputConnection
1078 * @param DACx DAC instance
1079 * @param DAC_Channel This parameter can be one of the following values:
1080 * @arg @ref LL_DAC_CHANNEL_1
1081 * @arg @ref LL_DAC_CHANNEL_2
1082 * @param OutputConnection This parameter can be one of the following values:
1083 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1084 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1085 * @retval None
1086 */
LL_DAC_SetOutputConnection(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputConnection)1087 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
1088 {
1089 MODIFY_REG(DACx->MCR,
1090 (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1091 OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1092 }
1093
1094 /**
1095 * @brief Get the output connection for the selected DAC channel.
1096 * @note On this STM32 series, output connection depends on output mode (normal or
1097 * sample and hold) and output buffer state.
1098 * - if output connection is set to internal path and output buffer
1099 * is enabled (whatever output mode):
1100 * output connection is also connected to GPIO pin
1101 * (both connections to GPIO pin and internal path).
1102 * - if output connection is set to GPIO pin, output buffer
1103 * is disabled, output mode set to sample and hold:
1104 * output connection is also connected to internal path
1105 * (both connections to GPIO pin and internal path).
1106 * @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n
1107 * CR MODE2 LL_DAC_GetOutputConnection
1108 * @param DACx DAC instance
1109 * @param DAC_Channel This parameter can be one of the following values:
1110 * @arg @ref LL_DAC_CHANNEL_1
1111 * @arg @ref LL_DAC_CHANNEL_2
1112 * @retval Returned value can be one of the following values:
1113 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1114 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1115 */
LL_DAC_GetOutputConnection(DAC_TypeDef * DACx,uint32_t DAC_Channel)1116 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1117 {
1118 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1119 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1120 );
1121 }
1122
1123 /**
1124 * @brief Set the sample-and-hold timing for the selected DAC channel:
1125 * sample time
1126 * @note Sample time must be set when DAC channel is disabled
1127 * or during DAC operation when DAC channel flag BWSTx is reset,
1128 * otherwise the setting is ignored.
1129 * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
1130 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n
1131 * SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
1132 * @param DACx DAC instance
1133 * @param DAC_Channel This parameter can be one of the following values:
1134 * @arg @ref LL_DAC_CHANNEL_1
1135 * @arg @ref LL_DAC_CHANNEL_2
1136 * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
1137 * @retval None
1138 */
LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t SampleTime)1139 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
1140 {
1141 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1142 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1143
1144 MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
1145 }
1146
1147 /**
1148 * @brief Get the sample-and-hold timing for the selected DAC channel:
1149 * sample time
1150 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n
1151 * SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
1152 * @param DACx DAC instance
1153 * @param DAC_Channel This parameter can be one of the following values:
1154 * @arg @ref LL_DAC_CHANNEL_1
1155 * @arg @ref LL_DAC_CHANNEL_2
1156 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1157 */
LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef * DACx,uint32_t DAC_Channel)1158 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1159 {
1160 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1161 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1162
1163 return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
1164 }
1165
1166 /**
1167 * @brief Set the sample-and-hold timing for the selected DAC channel:
1168 * hold time
1169 * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n
1170 * SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
1171 * @param DACx DAC instance
1172 * @param DAC_Channel This parameter can be one of the following values:
1173 * @arg @ref LL_DAC_CHANNEL_1
1174 * @arg @ref LL_DAC_CHANNEL_2
1175 * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
1176 * @retval None
1177 */
LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t HoldTime)1178 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
1179 {
1180 MODIFY_REG(DACx->SHHR,
1181 DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1182 HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1183 }
1184
1185 /**
1186 * @brief Get the sample-and-hold timing for the selected DAC channel:
1187 * hold time
1188 * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n
1189 * SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
1190 * @param DACx DAC instance
1191 * @param DAC_Channel This parameter can be one of the following values:
1192 * @arg @ref LL_DAC_CHANNEL_1
1193 * @arg @ref LL_DAC_CHANNEL_2
1194 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1195 */
LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef * DACx,uint32_t DAC_Channel)1196 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1197 {
1198 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1199 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1200 );
1201 }
1202
1203 /**
1204 * @brief Set the sample-and-hold timing for the selected DAC channel:
1205 * refresh time
1206 * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n
1207 * SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
1208 * @param DACx DAC instance
1209 * @param DAC_Channel This parameter can be one of the following values:
1210 * @arg @ref LL_DAC_CHANNEL_1
1211 * @arg @ref LL_DAC_CHANNEL_2
1212 * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
1213 * @retval None
1214 */
LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t RefreshTime)1215 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
1216 {
1217 MODIFY_REG(DACx->SHRR,
1218 DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1219 RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1220 }
1221
1222 /**
1223 * @brief Get the sample-and-hold timing for the selected DAC channel:
1224 * refresh time
1225 * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n
1226 * SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
1227 * @param DACx DAC instance
1228 * @param DAC_Channel This parameter can be one of the following values:
1229 * @arg @ref LL_DAC_CHANNEL_1
1230 * @arg @ref LL_DAC_CHANNEL_2
1231 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1232 */
LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef * DACx,uint32_t DAC_Channel)1233 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1234 {
1235 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1236 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1237 );
1238 }
1239
1240 /**
1241 * @}
1242 */
1243
1244 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
1245 * @{
1246 */
1247
1248 /**
1249 * @brief Enable DAC DMA transfer request of the selected channel.
1250 * @note To configure DMA source address (peripheral address),
1251 * use function @ref LL_DAC_DMA_GetRegAddr().
1252 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
1253 * CR DMAEN2 LL_DAC_EnableDMAReq
1254 * @param DACx DAC instance
1255 * @param DAC_Channel This parameter can be one of the following values:
1256 * @arg @ref LL_DAC_CHANNEL_1
1257 * @arg @ref LL_DAC_CHANNEL_2
1258 * @retval None
1259 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1260 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1261 {
1262 SET_BIT(DACx->CR,
1263 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1264 }
1265
1266 /**
1267 * @brief Disable DAC DMA transfer request of the selected channel.
1268 * @note To configure DMA source address (peripheral address),
1269 * use function @ref LL_DAC_DMA_GetRegAddr().
1270 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
1271 * CR DMAEN2 LL_DAC_DisableDMAReq
1272 * @param DACx DAC instance
1273 * @param DAC_Channel This parameter can be one of the following values:
1274 * @arg @ref LL_DAC_CHANNEL_1
1275 * @arg @ref LL_DAC_CHANNEL_2
1276 * @retval None
1277 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1278 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1279 {
1280 CLEAR_BIT(DACx->CR,
1281 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1282 }
1283
1284 /**
1285 * @brief Get DAC DMA transfer request state of the selected channel.
1286 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
1287 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
1288 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
1289 * @param DACx DAC instance
1290 * @param DAC_Channel This parameter can be one of the following values:
1291 * @arg @ref LL_DAC_CHANNEL_1
1292 * @arg @ref LL_DAC_CHANNEL_2
1293 * @retval State of bit (1 or 0).
1294 */
LL_DAC_IsDMAReqEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1295 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1296 {
1297 return ((READ_BIT(DACx->CR,
1298 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1299 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1300 }
1301
1302 /**
1303 * @brief Function to help to configure DMA transfer to DAC: retrieve the
1304 * DAC register address from DAC instance and a list of DAC registers
1305 * intended to be used (most commonly) with DMA transfer.
1306 * @note These DAC registers are data holding registers:
1307 * when DAC conversion is requested, DAC generates a DMA transfer
1308 * request to have data available in DAC data holding registers.
1309 * @note This macro is intended to be used with LL DMA driver, refer to
1310 * function "LL_DMA_ConfigAddresses()".
1311 * Example:
1312 * LL_DMA_ConfigAddresses(DMA1,
1313 * LL_DMA_CHANNEL_1,
1314 * (uint32_t)&< array or variable >,
1315 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
1316 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
1317 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
1318 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1319 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1320 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1321 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1322 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1323 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
1324 * @param DACx DAC instance
1325 * @param DAC_Channel This parameter can be one of the following values:
1326 * @arg @ref LL_DAC_CHANNEL_1
1327 * @arg @ref LL_DAC_CHANNEL_2
1328 * @param Register This parameter can be one of the following values:
1329 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
1330 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
1331 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
1332 * @retval DAC register address
1333 */
LL_DAC_DMA_GetRegAddr(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)1334 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
1335 {
1336 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
1337 /* DAC channel selected. */
1338 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
1339 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
1340 }
1341 /**
1342 * @}
1343 */
1344
1345 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
1346 * @{
1347 */
1348
1349 /**
1350 * @brief Enable DAC selected channel.
1351 * @rmtoll CR EN1 LL_DAC_Enable\n
1352 * CR EN2 LL_DAC_Enable
1353 * @note After enable from off state, DAC channel requires a delay
1354 * for output voltage to reach accuracy +/- 1 LSB.
1355 * Refer to device datasheet, parameter "tWAKEUP".
1356 * @param DACx DAC instance
1357 * @param DAC_Channel This parameter can be one of the following values:
1358 * @arg @ref LL_DAC_CHANNEL_1
1359 * @arg @ref LL_DAC_CHANNEL_2
1360 * @retval None
1361 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1362 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1363 {
1364 SET_BIT(DACx->CR,
1365 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1366 }
1367
1368 /**
1369 * @brief Disable DAC selected channel.
1370 * @rmtoll CR EN1 LL_DAC_Disable\n
1371 * CR EN2 LL_DAC_Disable
1372 * @param DACx DAC instance
1373 * @param DAC_Channel This parameter can be one of the following values:
1374 * @arg @ref LL_DAC_CHANNEL_1
1375 * @arg @ref LL_DAC_CHANNEL_2
1376 * @retval None
1377 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1378 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1379 {
1380 CLEAR_BIT(DACx->CR,
1381 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1382 }
1383
1384 /**
1385 * @brief Get DAC enable state of the selected channel.
1386 * (0: DAC channel is disabled, 1: DAC channel is enabled)
1387 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
1388 * CR EN2 LL_DAC_IsEnabled
1389 * @param DACx DAC instance
1390 * @param DAC_Channel This parameter can be one of the following values:
1391 * @arg @ref LL_DAC_CHANNEL_1
1392 * @arg @ref LL_DAC_CHANNEL_2
1393 * @retval State of bit (1 or 0).
1394 */
LL_DAC_IsEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1395 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1396 {
1397 return ((READ_BIT(DACx->CR,
1398 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1399 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1400 }
1401
1402 /**
1403 * @brief Enable DAC trigger of the selected channel.
1404 * @note - If DAC trigger is disabled, DAC conversion is performed
1405 * automatically once the data holding register is updated,
1406 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1407 * @ref LL_DAC_ConvertData12RightAligned(), ...
1408 * - If DAC trigger is enabled, DAC conversion is performed
1409 * only when a hardware of software trigger event is occurring.
1410 * Select trigger source using
1411 * function @ref LL_DAC_SetTriggerSource().
1412 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1413 * CR TEN2 LL_DAC_EnableTrigger
1414 * @param DACx DAC instance
1415 * @param DAC_Channel This parameter can be one of the following values:
1416 * @arg @ref LL_DAC_CHANNEL_1
1417 * @arg @ref LL_DAC_CHANNEL_2
1418 * @retval None
1419 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1420 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1421 {
1422 SET_BIT(DACx->CR,
1423 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1424 }
1425
1426 /**
1427 * @brief Disable DAC trigger of the selected channel.
1428 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1429 * CR TEN2 LL_DAC_DisableTrigger
1430 * @param DACx DAC instance
1431 * @param DAC_Channel This parameter can be one of the following values:
1432 * @arg @ref LL_DAC_CHANNEL_1
1433 * @arg @ref LL_DAC_CHANNEL_2
1434 * @retval None
1435 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1436 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1437 {
1438 CLEAR_BIT(DACx->CR,
1439 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1440 }
1441
1442 /**
1443 * @brief Get DAC trigger state of the selected channel.
1444 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1445 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1446 * CR TEN2 LL_DAC_IsTriggerEnabled
1447 * @param DACx DAC instance
1448 * @param DAC_Channel This parameter can be one of the following values:
1449 * @arg @ref LL_DAC_CHANNEL_1
1450 * @arg @ref LL_DAC_CHANNEL_2
1451 * @retval State of bit (1 or 0).
1452 */
LL_DAC_IsTriggerEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1453 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1454 {
1455 return ((READ_BIT(DACx->CR,
1456 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1457 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1458 }
1459
1460 /**
1461 * @brief Trig DAC conversion by software for the selected DAC channel.
1462 * @note Preliminarily, DAC trigger must be set to software trigger
1463 * using function
1464 * @ref LL_DAC_Init()
1465 * @ref LL_DAC_SetTriggerSource()
1466 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1467 * and DAC trigger must be enabled using
1468 * function @ref LL_DAC_EnableTrigger().
1469 * @note For devices featuring DAC with 2 channels: this function
1470 * can perform a SW start of both DAC channels simultaneously.
1471 * Two channels can be selected as parameter.
1472 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1473 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1474 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1475 * @param DACx DAC instance
1476 * @param DAC_Channel This parameter can a combination of the following values:
1477 * @arg @ref LL_DAC_CHANNEL_1
1478 * @arg @ref LL_DAC_CHANNEL_2
1479 * @retval None
1480 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1481 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1482 {
1483 SET_BIT(DACx->SWTRIGR,
1484 (DAC_Channel & DAC_SWTR_CHX_MASK));
1485 }
1486
1487 /**
1488 * @brief Set the data to be loaded in the data holding register
1489 * in format 12 bits left alignment (LSB aligned on bit 0),
1490 * for the selected DAC channel.
1491 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1492 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1493 * @param DACx DAC instance
1494 * @param DAC_Channel This parameter can be one of the following values:
1495 * @arg @ref LL_DAC_CHANNEL_1
1496 * @arg @ref LL_DAC_CHANNEL_2
1497 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1498 * @retval None
1499 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1500 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1501 {
1502 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
1503 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1504
1505 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
1506 }
1507
1508 /**
1509 * @brief Set the data to be loaded in the data holding register
1510 * in format 12 bits left alignment (MSB aligned on bit 15),
1511 * for the selected DAC channel.
1512 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1513 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1514 * @param DACx DAC instance
1515 * @param DAC_Channel This parameter can be one of the following values:
1516 * @arg @ref LL_DAC_CHANNEL_1
1517 * @arg @ref LL_DAC_CHANNEL_2
1518 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1519 * @retval None
1520 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1521 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1522 {
1523 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
1524 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1525
1526 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
1527 }
1528
1529 /**
1530 * @brief Set the data to be loaded in the data holding register
1531 * in format 8 bits left alignment (LSB aligned on bit 0),
1532 * for the selected DAC channel.
1533 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1534 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1535 * @param DACx DAC instance
1536 * @param DAC_Channel This parameter can be one of the following values:
1537 * @arg @ref LL_DAC_CHANNEL_1
1538 * @arg @ref LL_DAC_CHANNEL_2
1539 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1540 * @retval None
1541 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1542 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1543 {
1544 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
1545 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1546
1547 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
1548 }
1549
1550
1551 /**
1552 * @brief Set the data to be loaded in the data holding register
1553 * in format 12 bits left alignment (LSB aligned on bit 0),
1554 * for both DAC channels.
1555 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1556 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1557 * @param DACx DAC instance
1558 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1559 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1560 * @retval None
1561 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1562 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1563 uint32_t DataChannel2)
1564 {
1565 MODIFY_REG(DACx->DHR12RD,
1566 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1567 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1568 }
1569
1570 /**
1571 * @brief Set the data to be loaded in the data holding register
1572 * in format 12 bits left alignment (MSB aligned on bit 15),
1573 * for both DAC channels.
1574 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1575 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1576 * @param DACx DAC instance
1577 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1578 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1579 * @retval None
1580 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1581 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1582 uint32_t DataChannel2)
1583 {
1584 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1585 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1586 /* the 4 LSB must be taken into account for the shift value. */
1587 MODIFY_REG(DACx->DHR12LD,
1588 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1589 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1590 }
1591
1592 /**
1593 * @brief Set the data to be loaded in the data holding register
1594 * in format 8 bits left alignment (LSB aligned on bit 0),
1595 * for both DAC channels.
1596 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1597 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1598 * @param DACx DAC instance
1599 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1600 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1601 * @retval None
1602 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1603 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1604 uint32_t DataChannel2)
1605 {
1606 MODIFY_REG(DACx->DHR8RD,
1607 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1608 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1609 }
1610
1611
1612 /**
1613 * @brief Retrieve output data currently generated for the selected DAC channel.
1614 * @note Whatever alignment and resolution settings
1615 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1616 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1617 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1618 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1619 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1620 * @param DACx DAC instance
1621 * @param DAC_Channel This parameter can be one of the following values:
1622 * @arg @ref LL_DAC_CHANNEL_1
1623 * @arg @ref LL_DAC_CHANNEL_2
1624 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1625 */
LL_DAC_RetrieveOutputData(DAC_TypeDef * DACx,uint32_t DAC_Channel)1626 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1627 {
1628 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
1629 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1630
1631 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1632 }
1633
1634 /**
1635 * @}
1636 */
1637
1638 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1639 * @{
1640 */
1641
1642 /**
1643 * @brief Get DAC calibration offset flag for DAC channel 1
1644 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
1645 * @param DACx DAC instance
1646 * @retval State of bit (1 or 0).
1647 */
LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef * DACx)1648 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
1649 {
1650 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
1651 }
1652
1653
1654 /**
1655 * @brief Get DAC calibration offset flag for DAC channel 2
1656 * @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
1657 * @param DACx DAC instance
1658 * @retval State of bit (1 or 0).
1659 */
LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef * DACx)1660 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
1661 {
1662 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
1663 }
1664
1665
1666 /**
1667 * @brief Get DAC busy writing sample time flag for DAC channel 1
1668 * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
1669 * @param DACx DAC instance
1670 * @retval State of bit (1 or 0).
1671 */
LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef * DACx)1672 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
1673 {
1674 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
1675 }
1676
1677 /**
1678 * @brief Get DAC busy writing sample time flag for DAC channel 2
1679 * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
1680 * @param DACx DAC instance
1681 * @retval State of bit (1 or 0).
1682 */
LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef * DACx)1683 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
1684 {
1685 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
1686 }
1687
1688
1689 /**
1690 * @brief Get DAC underrun flag for DAC channel 1
1691 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1692 * @param DACx DAC instance
1693 * @retval State of bit (1 or 0).
1694 */
LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef * DACx)1695 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1696 {
1697 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1698 }
1699
1700
1701 /**
1702 * @brief Get DAC underrun flag for DAC channel 2
1703 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1704 * @param DACx DAC instance
1705 * @retval State of bit (1 or 0).
1706 */
LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef * DACx)1707 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1708 {
1709 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1710 }
1711
1712
1713 /**
1714 * @brief Clear DAC underrun flag for DAC channel 1
1715 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1716 * @param DACx DAC instance
1717 * @retval None
1718 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1719 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1720 {
1721 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1722 }
1723
1724
1725 /**
1726 * @brief Clear DAC underrun flag for DAC channel 2
1727 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1728 * @param DACx DAC instance
1729 * @retval None
1730 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1731 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1732 {
1733 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1734 }
1735
1736
1737 /**
1738 * @}
1739 */
1740
1741 /** @defgroup DAC_LL_EF_IT_Management IT management
1742 * @{
1743 */
1744
1745 /**
1746 * @brief Enable DMA underrun interrupt for DAC channel 1
1747 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1748 * @param DACx DAC instance
1749 * @retval None
1750 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1751 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1752 {
1753 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1754 }
1755
1756
1757 /**
1758 * @brief Enable DMA underrun interrupt for DAC channel 2
1759 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1760 * @param DACx DAC instance
1761 * @retval None
1762 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1763 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1764 {
1765 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1766 }
1767
1768
1769 /**
1770 * @brief Disable DMA underrun interrupt for DAC channel 1
1771 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1772 * @param DACx DAC instance
1773 * @retval None
1774 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1775 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1776 {
1777 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1778 }
1779
1780
1781 /**
1782 * @brief Disable DMA underrun interrupt for DAC channel 2
1783 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1784 * @param DACx DAC instance
1785 * @retval None
1786 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1787 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1788 {
1789 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1790 }
1791
1792
1793 /**
1794 * @brief Get DMA underrun interrupt for DAC channel 1
1795 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1796 * @param DACx DAC instance
1797 * @retval State of bit (1 or 0).
1798 */
LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef * DACx)1799 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1800 {
1801 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1802 }
1803
1804
1805 /**
1806 * @brief Get DMA underrun interrupt for DAC channel 2
1807 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1808 * @param DACx DAC instance
1809 * @retval State of bit (1 or 0).
1810 */
LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef * DACx)1811 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1812 {
1813 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
1814 }
1815
1816
1817 /**
1818 * @}
1819 */
1820
1821 #if defined(USE_FULL_LL_DRIVER)
1822 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1823 * @{
1824 */
1825
1826 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
1827 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
1828 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1829
1830 /**
1831 * @}
1832 */
1833 #endif /* USE_FULL_LL_DRIVER */
1834
1835 /**
1836 * @}
1837 */
1838
1839 /**
1840 * @}
1841 */
1842
1843 #endif /* DAC1 */
1844
1845 /**
1846 * @}
1847 */
1848
1849 #ifdef __cplusplus
1850 }
1851 #endif
1852
1853 #endif /* STM32L5xx_LL_DAC_H */
1854
1855
