1 /**
2 ******************************************************************************
3 * @file stm32l5xx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 *
7 ******************************************************************************
8 * @attention
9 *
10 * Copyright (c) 2019 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file in
14 * the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 @verbatim
19 ==============================================================================
20 ##### How to use this driver #####
21 ==============================================================================
22 [..]
23 The LL CORTEX driver contains a set of generic APIs that can be
24 used by user:
25 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
26 functions
27 (+) Low power mode configuration (SCB register of Cortex-MCU)
28 (+) API to access to MCU info (CPUID register)
29 (+) API to enable fault handler (SHCSR accesses)
30 (+) API to enable and disable the MPU secure and non-secure
31 (+) API to configure the region of MPU secure and non-secure
32 (+) API to configure the attributes region of MPU secure and non-secure
33
34 @endverbatim
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef STM32L5xx_LL_CORTEX_H
40 #define STM32L5xx_LL_CORTEX_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32l5xx.h"
48
49 /** @addtogroup STM32L5xx_LL_Driver
50 * @{
51 */
52
53 /** @defgroup CORTEX_LL CORTEX
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59
60 /* Private constants ---------------------------------------------------------*/
61 /** @defgroup CORTEX_LL_EC_REGION_ACCESS CORTEX LL MPU Region Access Attributes
62 * @{
63 */
64 /* Register MPU_RBAR (Cortex-M33) : bits [4:0] */
65 #define MPU_ACCESS_MSK (MPU_RBAR_SH_Msk|MPU_RBAR_AP_Msk|MPU_RBAR_XN_Msk)
66 /**
67 * @}
68 */
69
70 /* Private macros ------------------------------------------------------------*/
71
72 /* Exported types ------------------------------------------------------------*/
73 /* Exported constants --------------------------------------------------------*/
74 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
75 * @{
76 */
77
78 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
79 * @{
80 */
81 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick
82 clock source */
83 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick
84 clock source */
85 /**
86 * @}
87 */
88
89 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
90 * @{
91 */
92 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
93 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
94 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
95 #define LL_HANDLER_FAULT_SECURE SCB_SHCSR_SECUREFAULTENA_Msk /*!< Secure fault */
96 /**
97 * @}
98 */
99
100 #if (__MPU_PRESENT == 1)
101 /** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
102 * @{
103 */
104 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U
105 #define LL_MPU_CTRL_HARDFAULT_NMI 2U
106 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U
107 #define LL_MPU_CTRL_HFNMI_PRIVDEF 6U
108 /**
109 * @}
110 */
111
112 /** @defgroup CORTEX_LL_MPU_Attributes MPU Attributes
113 * @{
114 */
115 #define LL_MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */
116 #define LL_MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */
117 #define LL_MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */
118 #define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */
119
120 #define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */
121 #define LL_MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */
122 #define LL_MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */
123
124 #define LL_MPU_TRANSIENT 0x0U /* Normal memory, transient. */
125 #define LL_MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */
126
127 #define LL_MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */
128 #define LL_MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */
129 #define LL_MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */
130 #define LL_MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */
131 /**
132 * @}
133 */
134
135 /** @defgroup CORTEX_LL_MPU_Region_Enable MPU Region Enable
136 * @{
137 */
138 #define LL_MPU_REGION_ENABLE 1U
139 #define LL_MPU_REGION_DISABLE 0U
140 /**
141 * @}
142 */
143
144 /** @defgroup CORTEX_LL_MPU_Instruction_Access MPU Instruction Access
145 * @{
146 */
147 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos)
148 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos)
149 /**
150 * @}
151 */
152
153 /** @defgroup CORTEX_LL_MPU_Access_Shareable MPU Instruction Access Shareable
154 * @{
155 */
156 #define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos)
157 #define LL_MPU_ACCESS_OUTER_SHAREABLE (1U << MPU_RBAR_SH_Pos)
158 #define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos)
159 /**
160 * @}
161 */
162
163 /** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes MPU Region Permission Attributes
164 * @{
165 */
166 #define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos)
167 #define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos)
168 #define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos)
169 #define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos)
170 /**
171 * @}
172 */
173
174 /** @defgroup CORTEX_LL_MPU_Region_Number MPU Region Number
175 * @{
176 */
177 #define LL_MPU_REGION_NUMBER0 0U
178 #define LL_MPU_REGION_NUMBER1 1U
179 #define LL_MPU_REGION_NUMBER2 2U
180 #define LL_MPU_REGION_NUMBER3 3U
181 #define LL_MPU_REGION_NUMBER4 4U
182 #define LL_MPU_REGION_NUMBER5 5U
183 #define LL_MPU_REGION_NUMBER6 6U
184 #define LL_MPU_REGION_NUMBER7 7U
185 /**
186 * @}
187 */
188
189 /** @defgroup CORTEX_LL_MPU_Attributes_Number MPU Memory Attributes Number
190 * @{
191 */
192 #define LL_MPU_ATTRIBUTES_NUMBER0 0U
193 #define LL_MPU_ATTRIBUTES_NUMBER1 1U
194 #define LL_MPU_ATTRIBUTES_NUMBER2 2U
195 #define LL_MPU_ATTRIBUTES_NUMBER3 3U
196 #define LL_MPU_ATTRIBUTES_NUMBER4 4U
197 #define LL_MPU_ATTRIBUTES_NUMBER5 5U
198 #define LL_MPU_ATTRIBUTES_NUMBER6 6U
199 #define LL_MPU_ATTRIBUTES_NUMBER7 7U
200 /**
201 * @}
202 */
203
204 #endif /* __MPU_PRESENT */
205
206 /**
207 * @}
208 */
209
210 /* Exported macro ------------------------------------------------------------*/
211
212 /* Exported functions --------------------------------------------------------*/
213 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
214 * @{
215 */
216
217 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
218 * @brief CORTEX SYSTICK LL module driver
219 * @{
220 */
221
222 /**
223 * @brief This function checks if the Systick counter flag is active or not.
224 * @note It can be used in timeout function on application side.
225 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
226 * @retval State of bit (1 or 0).
227 */
LL_SYSTICK_IsActiveCounterFlag(void)228 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
229 {
230 return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
231 }
232
233 /**
234 * @brief Configures the SysTick clock source
235 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
236 * @param Source This parameter can be one of the following values:
237 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
238 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
239 * @retval None
240 */
LL_SYSTICK_SetClkSource(uint32_t Source)241 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
242 {
243 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
244 {
245 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
246 }
247 else
248 {
249 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
250 }
251 }
252
253 /**
254 * @brief Get the SysTick clock source
255 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
256 * @retval Returned value can be one of the following values:
257 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
258 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
259 */
LL_SYSTICK_GetClkSource(void)260 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
261 {
262 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
263 }
264
265 /**
266 * @brief Enable SysTick exception request
267 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
268 * @retval None
269 */
LL_SYSTICK_EnableIT(void)270 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
271 {
272 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
273 }
274
275 /**
276 * @brief Disable SysTick exception request
277 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
278 * @retval None
279 */
LL_SYSTICK_DisableIT(void)280 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
281 {
282 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
283 }
284
285 /**
286 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
287 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
288 * @retval State of bit (1 or 0).
289 */
LL_SYSTICK_IsEnabledIT(void)290 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
291 {
292 return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
293 }
294
295 /**
296 * @}
297 */
298
299 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
300 * @{
301 */
302
303 /**
304 * @brief Processor uses sleep as its low power mode
305 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
306 * @retval None
307 */
LL_LPM_EnableSleep(void)308 __STATIC_INLINE void LL_LPM_EnableSleep(void)
309 {
310 /* Clear SLEEPDEEP bit of Cortex System Control Register */
311 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
312 }
313
314 /**
315 * @brief Processor uses deep sleep as its low power mode
316 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
317 * @retval None
318 */
LL_LPM_EnableDeepSleep(void)319 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
320 {
321 /* Set SLEEPDEEP bit of Cortex System Control Register */
322 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
323 }
324
325 /**
326 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
327 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
328 * empty main application.
329 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
330 * @retval None
331 */
LL_LPM_EnableSleepOnExit(void)332 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
333 {
334 /* Set SLEEPONEXIT bit of Cortex System Control Register */
335 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
336 }
337
338 /**
339 * @brief Do not sleep when returning to Thread mode.
340 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
341 * @retval None
342 */
LL_LPM_DisableSleepOnExit(void)343 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
344 {
345 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
346 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
347 }
348
349 /**
350 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
351 * processor.
352 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
353 * @retval None
354 */
LL_LPM_EnableEventOnPend(void)355 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
356 {
357 /* Set SEVEONPEND bit of Cortex System Control Register */
358 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
359 }
360
361 /**
362 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
363 * excluded
364 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
365 * @retval None
366 */
LL_LPM_DisableEventOnPend(void)367 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
368 {
369 /* Clear SEVEONPEND bit of Cortex System Control Register */
370 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
371 }
372
373 /**
374 * @}
375 */
376
377 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
378 * @{
379 */
380
381 /**
382 * @brief Enable a fault in System handler control register (SHCSR)
383 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n
384 * SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n
385 * SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault\n
386 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_EnableFault
387 * @param Fault This parameter can be a combination of the following values:
388 * @arg @ref LL_HANDLER_FAULT_USG
389 * @arg @ref LL_HANDLER_FAULT_BUS
390 * @arg @ref LL_HANDLER_FAULT_MEM
391 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
392 *
393 * (*) value applicable in secure when the system implements the security.
394 * @retval None
395 */
LL_HANDLER_EnableFault(uint32_t Fault)396 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
397 {
398 /* Enable the system handler fault */
399 SET_BIT(SCB->SHCSR, Fault);
400 }
401
402 /**
403 * @brief Disable a fault in System handler control register (SHCSR)
404 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n
405 * SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n
406 * SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault\n
407 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_DisableFault
408 * @param Fault This parameter can be a combination of the following values:
409 * @arg @ref LL_HANDLER_FAULT_USG
410 * @arg @ref LL_HANDLER_FAULT_BUS
411 * @arg @ref LL_HANDLER_FAULT_MEM
412 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
413 *
414 * (*) value applicable in secure when the system implements the security.
415 * @retval None
416 */
LL_HANDLER_DisableFault(uint32_t Fault)417 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
418 {
419 /* Disable the system handler fault */
420 CLEAR_BIT(SCB->SHCSR, Fault);
421 }
422
423 /**
424 * @}
425 */
426
427 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
428 * @{
429 */
430
431 /**
432 * @brief Get Implementer code
433 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
434 * @retval Value should be equal to 0x41 for ARM
435 */
LL_CPUID_GetImplementer(void)436 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
437 {
438 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
439 }
440
441 /**
442 * @brief Get Variant number (The r value in the rnpn product revision identifier)
443 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
444 * @retval Value between 0 and 255 (0x0: revision 0)
445 */
LL_CPUID_GetVariant(void)446 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
447 {
448 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
449 }
450
451 /**
452 * @brief Get Constant number
453 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
454 * @retval Value should be equal to 0xF for Cortex-M33 devices
455 */
LL_CPUID_GetConstant(void)456 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
457 {
458 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
459 }
460
461 /**
462 * @brief Get Part number
463 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
464 * @retval Value should be equal to 0xD21 for Cortex-M33
465 */
LL_CPUID_GetParNo(void)466 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
467 {
468 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
469 }
470
471 /**
472 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
473 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
474 * @retval Value between 0 and 255 (0x1: patch 1)
475 */
LL_CPUID_GetRevision(void)476 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
477 {
478 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
479 }
480
481 /**
482 * @}
483 */
484
485 #if __MPU_PRESENT
486 /** @defgroup CORTEX_LL_EF_MPU MPU
487 * @{
488 */
489
490 /**
491 * @brief Enable MPU with input options
492 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable\n
493 * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Enable\n
494 * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Enable
495 * @param MPU_Control This parameter can be one of the following values:
496 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
497 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
498 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
499 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
500 * @retval None
501 */
LL_MPU_Enable(uint32_t MPU_Control)502 __STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control)
503 {
504 /* Enable the MPU*/
505 MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
506
507 /* Ensure MPU settings take effects */
508 __DSB();
509
510 /* Sequence instruction fetches using update settings */
511 __ISB();
512 }
513
514 /**
515 * @brief Disable MPU
516 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable\n
517 * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Disable\n
518 * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Disable
519 * @retval None
520 */
LL_MPU_Disable(void)521 __STATIC_INLINE void LL_MPU_Disable(void)
522 {
523 /* Make sure outstanding transfers are done */
524 __DMB();
525 /* Disable MPU */
526 WRITE_REG(MPU->CTRL, 0U);
527 }
528
529 /**
530 * @brief Check if MPU is enabled or not
531 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
532 * @retval State of bit (1 or 0).
533 */
LL_MPU_IsEnabled(void)534 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
535 {
536 return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
537 }
538
539 /**
540 * @brief Enable a MPU region
541 * @rmtoll MPU_RNR REGION LL_MPU_EnableRegion\n
542 * @rmtoll MPU_RLAR EN LL_MPU_EnableRegion
543 * @param Region This parameter can be one of the following values:
544 * @arg @ref LL_MPU_REGION_NUMBER0
545 * @arg @ref LL_MPU_REGION_NUMBER1
546 * @arg @ref LL_MPU_REGION_NUMBER2
547 * @arg @ref LL_MPU_REGION_NUMBER3
548 * @arg @ref LL_MPU_REGION_NUMBER4
549 * @arg @ref LL_MPU_REGION_NUMBER5
550 * @arg @ref LL_MPU_REGION_NUMBER6
551 * @arg @ref LL_MPU_REGION_NUMBER7
552 * @note cortex-M33 supports 8 secure and 8 non secure regions.
553 * @retval None
554 */
LL_MPU_EnableRegion(uint32_t Region)555 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
556 {
557 /* Set Region number */
558 WRITE_REG(MPU->RNR, Region);
559
560 /* Enable the MPU region */
561 SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
562 }
563
564 /**
565 * @brief Check if MPU region is enabled or not
566 * @rmtoll MPU_RNR REGION LL_MPU_IsEnabledRegion\n
567 * @rmtoll MPU_RLAR EN LL_MPU_IsEnabledRegion
568 * @param Region This parameter can be one of the following values:
569 * @arg @ref LL_MPU_REGION_NUMBER0
570 * @arg @ref LL_MPU_REGION_NUMBER1
571 * @arg @ref LL_MPU_REGION_NUMBER2
572 * @arg @ref LL_MPU_REGION_NUMBER3
573 * @arg @ref LL_MPU_REGION_NUMBER4
574 * @arg @ref LL_MPU_REGION_NUMBER5
575 * @arg @ref LL_MPU_REGION_NUMBER6
576 * @arg @ref LL_MPU_REGION_NUMBER7
577 * @note cortex-M33 supports 8 secure and 8 non secure regions.
578 * @retval State of bit (1 or 0).
579 */
LL_MPU_IsEnabledRegion(uint32_t Region)580 __STATIC_INLINE uint32_t LL_MPU_IsEnabledRegion(uint32_t Region)
581 {
582 return ((READ_BIT(MPU->RNR, Region) == (Region)) ? 1UL : 0UL);
583 }
584
585 /**
586 * @brief Disable a MPU region
587 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
588 * @rmtoll MPU_RLAR EN LL_MPU_DisableRegion
589 * @param Region This parameter can be one of the following values:
590 * @arg @ref LL_MPU_REGION_NUMBER0
591 * @arg @ref LL_MPU_REGION_NUMBER1
592 * @arg @ref LL_MPU_REGION_NUMBER2
593 * @arg @ref LL_MPU_REGION_NUMBER3
594 * @arg @ref LL_MPU_REGION_NUMBER4
595 * @arg @ref LL_MPU_REGION_NUMBER5
596 * @arg @ref LL_MPU_REGION_NUMBER6
597 * @arg @ref LL_MPU_REGION_NUMBER7
598 * @note cortex-M33 supports 8 secure and 8 non secure regions.
599 * @retval None
600 */
LL_MPU_DisableRegion(uint32_t Region)601 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
602 {
603 /* Set Region number */
604 WRITE_REG(MPU->RNR, Region);
605
606 /* Disable the MPU region */
607 CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
608 }
609
610 /**
611 * @brief Configure and enable a MPU region
612 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
613 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
614 * MPU_RLAR ADDR LL_MPU_ConfigRegion\n
615 * MPU_RBAR XN LL_MPU_ConfigRegion\n
616 * MPU_RBAR AP LL_MPU_ConfigRegion\n
617 * MPU_RBAR SH LL_MPU_ConfigRegion\n
618 * MPU_RLAR EN LL_MPU_ConfigRegion\n
619 * MPU_RLAR AttrIndx LL_MPU_ConfigRegion
620 * @param Region This parameter can be one of the following values:
621 * @arg @ref LL_MPU_REGION_NUMBER0
622 * @arg @ref LL_MPU_REGION_NUMBER1
623 * @arg @ref LL_MPU_REGION_NUMBER2
624 * @arg @ref LL_MPU_REGION_NUMBER3
625 * @arg @ref LL_MPU_REGION_NUMBER4
626 * @arg @ref LL_MPU_REGION_NUMBER5
627 * @arg @ref LL_MPU_REGION_NUMBER6
628 * @arg @ref LL_MPU_REGION_NUMBER7
629 * @param Attributes This parameter can be a combination of the following values:
630 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
631 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
632 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
633 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
634 * or @ref LL_MPU_REGION_ALL_RO
635 * @param AttrIndx This parameter can be one of the following values:
636 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
637 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
638 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
639 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
640 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
641 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
642 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
643 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
644 * @param BaseAddress Value of region base address
645 * @param LimitAddress Value of region limit address
646 * @note cortex-M33 supports 8 secure and 8 non secure regions.
647 * @retval None
648 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)649 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress,
650 uint32_t LimitAddress)
651 {
652 /* Set Region number */
653 WRITE_REG(MPU->RNR, Region);
654
655 /* Set region base address and region access attributes */
656 WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
657
658 /* Set region limit address, memory attributes index and enable region */
659 WRITE_REG(MPU->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
660 }
661
662 /**
663 * @brief Configure a MPU region address range
664 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress\n
665 * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress\n
666 * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress\n
667 * @param Region This parameter can be one of the following values:
668 * @arg @ref LL_MPU_REGION_NUMBER0
669 * @arg @ref LL_MPU_REGION_NUMBER1
670 * @arg @ref LL_MPU_REGION_NUMBER2
671 * @arg @ref LL_MPU_REGION_NUMBER3
672 * @arg @ref LL_MPU_REGION_NUMBER4
673 * @arg @ref LL_MPU_REGION_NUMBER5
674 * @arg @ref LL_MPU_REGION_NUMBER6
675 * @arg @ref LL_MPU_REGION_NUMBER7
676 * @param BaseAddress Value of region base address
677 * @param LimitAddress Value of region limit address
678 * @note cortex-M33 supports 8 secure and 8 non secure regions.
679 * @retval None
680 */
LL_MPU_ConfigRegionAddress(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)681 __STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
682 {
683 /* Set Region number */
684 WRITE_REG(MPU->RNR, Region);
685
686 /* Modify region base address */
687 MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
688
689 /* Modify region limit address */
690 MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
691 }
692
693 /**
694 * @brief Configure a MPU attributes index
695 * @rmtoll MPU_MAIR0 ATTR0 LL_MPU_ConfigAttributes\n
696 * MPU_MAIR0 ATTR1 LL_MPU_ConfigAttributes\n
697 * MPU_MAIR0 ATTR2 LL_MPU_ConfigAttributes\n
698 * MPU_MAIR0 ATTR3 LL_MPU_ConfigAttributes\n
699 * MPU_MAIR1 ATTR4 LL_MPU_ConfigAttributes\n
700 * MPU_MAIR1 ATTR5 LL_MPU_ConfigAttributes\n
701 * MPU_MAIR1 ATTR6 LL_MPU_ConfigAttributes\n
702 * MPU_MAIR1 ATTR7 LL_MPU_ConfigAttributes
703 * @param AttIndex This parameter can be one of the following values:
704 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
705 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
706 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
707 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
708 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
709 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
710 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
711 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
712 * @param Attributes This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF
713 * @retval None
714 */
LL_MPU_ConfigAttributes(uint32_t AttIndex,uint32_t Attributes)715 __STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes)
716 {
717 /* When selected index is in range [0;3] */
718 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
719 {
720 /* Modify Attr<i> field of MPU_MAIR0 accordingly */
721 MODIFY_REG(MPU->MAIR0, (0xFFUL << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
722 }
723 /* When selected index is in range [4;7] */
724 else
725 {
726 /* Modify Attr<i> field of MPU_MAIR1 accordingly */
727 MODIFY_REG(MPU->MAIR1, (0xFFUL << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
728 }
729 }
730
731 /**
732 * @brief Configure a MPU region base address
733 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress\n
734 * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress
735 * @param Region This parameter can be one of the following values:
736 * @arg @ref LL_MPU_REGION_NUMBER0
737 * @arg @ref LL_MPU_REGION_NUMBER1
738 * @arg @ref LL_MPU_REGION_NUMBER2
739 * @arg @ref LL_MPU_REGION_NUMBER3
740 * @arg @ref LL_MPU_REGION_NUMBER4
741 * @arg @ref LL_MPU_REGION_NUMBER5
742 * @arg @ref LL_MPU_REGION_NUMBER6
743 * @arg @ref LL_MPU_REGION_NUMBER7
744 * @param BaseAddress Value of region base address
745 * @note cortex-M33 supports 8 secure and 8 non secure regions.
746 * @retval None
747 */
LL_MPU_SetRegionBaseAddress(uint32_t Region,uint32_t BaseAddress)748 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress)
749 {
750 /* Set Region number */
751 WRITE_REG(MPU->RNR, Region);
752
753 /* Set base address */
754 MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
755 }
756
757 /**
758 * @brief Get a MPU region base address
759 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress\n
760 * @rmtoll MPU_RBAR BASE LL_MPU_GetRegionBaseAddress
761 * @param Region This parameter can be one of the following values:
762 * @arg @ref LL_MPU_REGION_NUMBER0
763 * @arg @ref LL_MPU_REGION_NUMBER1
764 * @arg @ref LL_MPU_REGION_NUMBER2
765 * @arg @ref LL_MPU_REGION_NUMBER3
766 * @arg @ref LL_MPU_REGION_NUMBER4
767 * @arg @ref LL_MPU_REGION_NUMBER5
768 * @arg @ref LL_MPU_REGION_NUMBER6
769 * @arg @ref LL_MPU_REGION_NUMBER7
770 * @retval None
771 */
LL_MPU_GetRegionBaseAddress(uint32_t Region)772 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region)
773 {
774 /* Set Region number */
775 WRITE_REG(MPU->RNR, Region);
776
777 return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk));
778 }
779
780 /**
781 * @brief Configure a MPU region limit address
782 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress\n
783 * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress
784 * @param Region This parameter can be one of the following values:
785 * @arg @ref LL_MPU_REGION_NUMBER0
786 * @arg @ref LL_MPU_REGION_NUMBER1
787 * @arg @ref LL_MPU_REGION_NUMBER2
788 * @arg @ref LL_MPU_REGION_NUMBER3
789 * @arg @ref LL_MPU_REGION_NUMBER4
790 * @arg @ref LL_MPU_REGION_NUMBER5
791 * @arg @ref LL_MPU_REGION_NUMBER6
792 * @arg @ref LL_MPU_REGION_NUMBER7
793 * @param LimitAddress Value of region limit address
794 * @note cortex-M33 supports 8 secure and 8 non secure regions.
795 * @retval None
796 */
LL_MPU_SetRegionLimitAddress(uint32_t Region,uint32_t LimitAddress)797 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress)
798 {
799 /* Set Region number */
800 WRITE_REG(MPU->RNR, Region);
801
802 /* Set limit address */
803 MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
804 }
805
806 /**
807 * @brief Get a MPU region limit address
808 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress\n
809 * @rmtoll MPU_RLAR LIMIT LL_MPU_GetRegionLimitAddress
810 * @param Region This parameter can be one of the following values:
811 * @arg @ref LL_MPU_REGION_NUMBER0
812 * @arg @ref LL_MPU_REGION_NUMBER1
813 * @arg @ref LL_MPU_REGION_NUMBER2
814 * @arg @ref LL_MPU_REGION_NUMBER3
815 * @arg @ref LL_MPU_REGION_NUMBER4
816 * @arg @ref LL_MPU_REGION_NUMBER5
817 * @arg @ref LL_MPU_REGION_NUMBER6
818 * @arg @ref LL_MPU_REGION_NUMBER7
819 * @retval None
820 */
LL_MPU_GetRegionLimitAddress(uint32_t Region)821 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region)
822 {
823 /* Set Region number */
824 WRITE_REG(MPU->RNR, Region);
825
826 return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk));
827 }
828
829 /**
830 * @brief Configure a MPU region access attributes and enable a region
831 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess\n
832 * MPU_RBAR XN LL_MPU_SetRegionAccess\n
833 * MPU_RBAR AP LL_MPU_SetRegionAccess\n
834 * MPU_RBAR SH LL_MPU_SetRegionAccess
835 * @param Region This parameter can be one of the following values:
836 * @arg @ref LL_MPU_REGION_NUMBER0
837 * @arg @ref LL_MPU_REGION_NUMBER1
838 * @arg @ref LL_MPU_REGION_NUMBER2
839 * @arg @ref LL_MPU_REGION_NUMBER3
840 * @arg @ref LL_MPU_REGION_NUMBER4
841 * @arg @ref LL_MPU_REGION_NUMBER5
842 * @arg @ref LL_MPU_REGION_NUMBER6
843 * @arg @ref LL_MPU_REGION_NUMBER7
844 * @param Attributes This parameter can be a combination of the following values:
845 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
846 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
847 or @ref LL_MPU_ACCESS_INNER_SHAREABLE
848 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
849 or @ref LL_MPU_REGION_ALL_RO
850 * @note cortex-M33 supports 8 secure and 8 non secure regions.
851 * @retval None
852 */
LL_MPU_SetRegionAccess(uint32_t Region,uint32_t Attributes)853 __STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes)
854 {
855 /* Set Region number */
856 WRITE_REG(MPU->RNR, Region);
857
858 /* Set base address */
859 MODIFY_REG(MPU->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
860 }
861
862 /**
863 * @brief Get a MPU region access attributes
864 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess\n
865 * MPU_RBAR XN LL_MPU_GetRegionAccess\n
866 * MPU_RBAR AP LL_MPU_GetRegionAccess\n
867 * MPU_RBAR SH LL_MPU_GetRegionAccess
868 * @param Region This parameter can be one of the following values:
869 * @arg @ref LL_MPU_REGION_NUMBER0
870 * @arg @ref LL_MPU_REGION_NUMBER1
871 * @arg @ref LL_MPU_REGION_NUMBER2
872 * @arg @ref LL_MPU_REGION_NUMBER3
873 * @arg @ref LL_MPU_REGION_NUMBER4
874 * @arg @ref LL_MPU_REGION_NUMBER5
875 * @arg @ref LL_MPU_REGION_NUMBER6
876 * @arg @ref LL_MPU_REGION_NUMBER7
877 * @retval None
878 */
LL_MPU_GetRegionAccess(uint32_t Region)879 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region)
880 {
881 /* Set Region number */
882 WRITE_REG(MPU->RNR, Region);
883
884 return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
885 }
886
887 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
888 /**
889 * @brief Enable non-secure MPU with input options
890 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable_NS\n
891 * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Enable_NS\n
892 * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Enable_NS
893 * @param MPU_Control This parameter can be one of the following values:
894 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
895 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
896 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
897 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
898 * @retval None
899 */
LL_MPU_Enable_NS(uint32_t MPU_Control)900 __STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control)
901 {
902 /* Enable the MPU*/
903 MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
904
905 /* Ensure MPU settings take effects */
906 __DSB();
907
908 /* Sequence instruction fetches using update settings */
909 __ISB();
910 }
911
912 /**
913 * @brief Disable non-secure MPU
914 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable_NS\n
915 * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Disable_NS\n
916 * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Disable_NS
917 * @retval None
918 */
LL_MPU_Disable_NS(void)919 __STATIC_INLINE void LL_MPU_Disable_NS(void)
920 {
921 /* Make sure outstanding transfers are done */
922 __DMB();
923 /* Disable MPU*/
924 WRITE_REG(MPU_NS->CTRL, 0U);
925 }
926
927 /**
928 * @brief Check if non-secure MPU is enabled or not
929 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled_NS
930 * @retval State of bit (1 or 0).
931 */
LL_MPU_IsEnabled_NS(void)932 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void)
933 {
934 return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
935 }
936
937 /**
938 * @brief Enable a non-secure MPU region
939 * @rmtoll MPU_RNR REGION LL_MPU_EnableRegion_NS\n
940 * @rmtoll MPU_RLAR EN LL_MPU_EnableRegion_NS
941 * @param Region This parameter can be one of the following values:
942 * @arg @ref LL_MPU_REGION_NUMBER0
943 * @arg @ref LL_MPU_REGION_NUMBER1
944 * @arg @ref LL_MPU_REGION_NUMBER2
945 * @arg @ref LL_MPU_REGION_NUMBER3
946 * @arg @ref LL_MPU_REGION_NUMBER4
947 * @arg @ref LL_MPU_REGION_NUMBER5
948 * @arg @ref LL_MPU_REGION_NUMBER6
949 * @arg @ref LL_MPU_REGION_NUMBER7
950 * @note cortex-M33 supports 8 secure and 8 non secure regions.
951 * @retval None
952 */
LL_MPU_EnableRegion_NS(uint32_t Region)953 __STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region)
954 {
955 /* Set Region number */
956 WRITE_REG(MPU_NS->RNR, Region);
957
958 /* Enable the MPU region */
959 SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
960 }
961
962 /**
963 * @brief Disable a non-secure MPU region
964 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion_NS\n
965 * @rmtoll MPU_RLAR EN LL_MPU_DisableRegion_NS
966 * @param Region This parameter can be one of the following values:
967 * @arg @ref LL_MPU_REGION_NUMBER0
968 * @arg @ref LL_MPU_REGION_NUMBER1
969 * @arg @ref LL_MPU_REGION_NUMBER2
970 * @arg @ref LL_MPU_REGION_NUMBER3
971 * @arg @ref LL_MPU_REGION_NUMBER4
972 * @arg @ref LL_MPU_REGION_NUMBER5
973 * @arg @ref LL_MPU_REGION_NUMBER6
974 * @arg @ref LL_MPU_REGION_NUMBER7
975 * @note cortex-M33 supports 8 secure and 8 non secure regions.
976 * @retval None
977 */
LL_MPU_DisableRegion_NS(uint32_t Region)978 __STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region)
979 {
980 /* Set Region number */
981 WRITE_REG(MPU_NS->RNR, Region);
982
983 /* Disable the MPU region */
984 CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
985 }
986
987 /**
988 * @brief Check if non-secure MPU region is enabled or not
989 * @rmtoll MPU_RNR REGION LL_MPU_IsEnabledRegion_NS\n
990 * @rmtoll MPU_RLAR EN LL_MPU_IsEnabledRegion_NS
991 * @param Region This parameter can be one of the following values:
992 * @arg @ref LL_MPU_REGION_NUMBER0
993 * @arg @ref LL_MPU_REGION_NUMBER1
994 * @arg @ref LL_MPU_REGION_NUMBER2
995 * @arg @ref LL_MPU_REGION_NUMBER3
996 * @arg @ref LL_MPU_REGION_NUMBER4
997 * @arg @ref LL_MPU_REGION_NUMBER5
998 * @arg @ref LL_MPU_REGION_NUMBER6
999 * @arg @ref LL_MPU_REGION_NUMBER7
1000 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1001 * @retval State of bit (1 or 0).
1002 */
LL_MPU_IsEnabledRegion_NS(uint32_t Region)1003 __STATIC_INLINE uint32_t LL_MPU_IsEnabledRegion_NS(uint32_t Region)
1004 {
1005 return ((READ_BIT(MPU_NS->RNR, Region) == (Region)) ? 1UL : 0UL);
1006 }
1007
1008 /**
1009 * @brief Configure and enable a non-secure MPU region
1010 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion_NS\n
1011 * MPU_RBAR ADDR LL_MPU_ConfigRegion_NS\n
1012 * MPU_RLAR ADDR LL_MPU_ConfigRegion_NS\n
1013 * MPU_RBAR XN LL_MPU_ConfigRegion_NS\n
1014 * MPU_RBAR AP LL_MPU_ConfigRegion_NS\n
1015 * MPU_RBAR SH LL_MPU_ConfigRegion_NS\n
1016 * MPU_RLAR EN LL_MPU_ConfigRegion_NS\n
1017 * MPU_RLAR AttrIndx LL_MPU_ConfigRegion_NS
1018 * @param Region This parameter can be one of the following values:
1019 * @arg @ref LL_MPU_REGION_NUMBER0
1020 * @arg @ref LL_MPU_REGION_NUMBER1
1021 * @arg @ref LL_MPU_REGION_NUMBER2
1022 * @arg @ref LL_MPU_REGION_NUMBER3
1023 * @arg @ref LL_MPU_REGION_NUMBER4
1024 * @arg @ref LL_MPU_REGION_NUMBER5
1025 * @arg @ref LL_MPU_REGION_NUMBER6
1026 * @arg @ref LL_MPU_REGION_NUMBER7
1027 * @param Attributes This parameter can be a combination of the following values:
1028 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1029 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1030 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1031 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1032 * or @ref LL_MPU_REGION_ALL_RO
1033 * @param AttrIndx This parameter can be one of the following values:
1034 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
1035 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
1036 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
1037 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
1038 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
1039 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
1040 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
1041 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
1042 * @param BaseAddress Value of region base address
1043 * @param LimitAddress Value of region limit address
1044 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1045 * @retval None
1046 */
LL_MPU_ConfigRegion_NS(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)1047 __STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx,
1048 uint32_t BaseAddress, uint32_t LimitAddress)
1049 {
1050 /* Set Region number */
1051 WRITE_REG(MPU_NS->RNR, Region);
1052
1053 /* Set region base address and region access attributes */
1054 WRITE_REG(MPU_NS->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
1055
1056 /* Set region limit address, memory attributes index and enable region */
1057 WRITE_REG(MPU_NS->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
1058 }
1059
1060 /**
1061 * @brief Configure a non-secure MPU region address range
1062 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress_NS\n
1063 * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress_NS\n
1064 * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress_NS\n
1065 * @param Region This parameter can be one of the following values:
1066 * @arg @ref LL_MPU_REGION_NUMBER0
1067 * @arg @ref LL_MPU_REGION_NUMBER1
1068 * @arg @ref LL_MPU_REGION_NUMBER2
1069 * @arg @ref LL_MPU_REGION_NUMBER3
1070 * @arg @ref LL_MPU_REGION_NUMBER4
1071 * @arg @ref LL_MPU_REGION_NUMBER5
1072 * @arg @ref LL_MPU_REGION_NUMBER6
1073 * @arg @ref LL_MPU_REGION_NUMBER7
1074 * @param BaseAddress Value of region base address
1075 * @param LimitAddress Value of region limit address
1076 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1077 * @retval None
1078 */
LL_MPU_ConfigRegionAddress_NS(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)1079 __STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
1080 {
1081 /* Set Region number */
1082 WRITE_REG(MPU_NS->RNR, Region);
1083
1084 /* Set base address */
1085 MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
1086
1087 /* Set limit address */
1088 MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
1089 }
1090
1091 /**
1092 * @brief Configure a non-secure MPU attributes index
1093 * @rmtoll MPU_MAIR0 ATTR0 LL_MPU_ConfigAttributes_NS\n
1094 * MPU_MAIR0 ATTR1 LL_MPU_ConfigAttributes_NS\n
1095 * MPU_MAIR0 ATTR2 LL_MPU_ConfigAttributes_NS\n
1096 * MPU_MAIR0 ATTR3 LL_MPU_ConfigAttributes_NS\n
1097 * MPU_MAIR1 ATTR4 LL_MPU_ConfigAttributes_NS\n
1098 * MPU_MAIR1 ATTR5 LL_MPU_ConfigAttributes_NS\n
1099 * MPU_MAIR1 ATTR6 LL_MPU_ConfigAttributes_NS\n
1100 * MPU_MAIR1 ATTR7 LL_MPU_ConfigAttributes_NS
1101 * @param AttIndex This parameter can be one of the following values:
1102 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
1103 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
1104 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
1105 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
1106 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
1107 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
1108 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
1109 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
1110 * @param Attributes This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF
1111 * @retval None
1112 */
LL_MPU_ConfigAttributes_NS(uint32_t AttIndex,uint32_t Attributes)1113 __STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes)
1114 {
1115 /* When selected index is in range [0;3] */
1116 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
1117 {
1118 /* Modify Attr<i> field of MPU_MAIR0_NS accordingly */
1119 MODIFY_REG(MPU_NS->MAIR0, (0xFFUL << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
1120 }
1121 /* When selected index is in range [4;7] */
1122 else
1123 {
1124 /* Modify Attr<i> field of MPU_MAIR1_NS accordingly */
1125 MODIFY_REG(MPU_NS->MAIR1, (0xFFUL << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
1126 }
1127 }
1128
1129 /**
1130 * @brief Configure a non-secure MPU region base address
1131 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress_NS\n
1132 * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress_NS
1133 * @param Region This parameter can be one of the following values:
1134 * @arg @ref LL_MPU_REGION_NUMBER0
1135 * @arg @ref LL_MPU_REGION_NUMBER1
1136 * @arg @ref LL_MPU_REGION_NUMBER2
1137 * @arg @ref LL_MPU_REGION_NUMBER3
1138 * @arg @ref LL_MPU_REGION_NUMBER4
1139 * @arg @ref LL_MPU_REGION_NUMBER5
1140 * @arg @ref LL_MPU_REGION_NUMBER6
1141 * @arg @ref LL_MPU_REGION_NUMBER7
1142 * @param BaseAddress Value of region base address
1143 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1144 * @retval None
1145 */
LL_MPU_SetRegionBaseAddress_NS(uint32_t Region,uint32_t BaseAddress)1146 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress)
1147 {
1148 /* Set Region number */
1149 WRITE_REG(MPU_NS->RNR, Region);
1150
1151 /* Set base address */
1152 MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
1153 }
1154
1155 /**
1156 * @brief Get a non-secure MPU region base address
1157 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress_NS\n
1158 * @rmtoll MPU_RBAR BASE LL_MPU_GetRegionBaseAddress_NS
1159 * @param Region This parameter can be one of the following values:
1160 * @arg @ref LL_MPU_REGION_NUMBER0
1161 * @arg @ref LL_MPU_REGION_NUMBER1
1162 * @arg @ref LL_MPU_REGION_NUMBER2
1163 * @arg @ref LL_MPU_REGION_NUMBER3
1164 * @arg @ref LL_MPU_REGION_NUMBER4
1165 * @arg @ref LL_MPU_REGION_NUMBER5
1166 * @arg @ref LL_MPU_REGION_NUMBER6
1167 * @arg @ref LL_MPU_REGION_NUMBER7
1168 * @retval None
1169 */
LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)1170 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)
1171 {
1172 /* Set Region number */
1173 WRITE_REG(MPU_NS->RNR, Region);
1174
1175 return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk));
1176 }
1177
1178 /**
1179 * @brief Configure a non-secure MPU region limit address
1180 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress_NS\n
1181 * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress_NS
1182 * @param Region This parameter can be one of the following values:
1183 * @arg @ref LL_MPU_REGION_NUMBER0
1184 * @arg @ref LL_MPU_REGION_NUMBER1
1185 * @arg @ref LL_MPU_REGION_NUMBER2
1186 * @arg @ref LL_MPU_REGION_NUMBER3
1187 * @arg @ref LL_MPU_REGION_NUMBER4
1188 * @arg @ref LL_MPU_REGION_NUMBER5
1189 * @arg @ref LL_MPU_REGION_NUMBER6
1190 * @arg @ref LL_MPU_REGION_NUMBER7
1191 * @param LimitAddress Value of region limit address
1192 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1193 * @retval None
1194 */
LL_MPU_SetRegionLimitAddress_NS(uint32_t Region,uint32_t LimitAddress)1195 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress)
1196 {
1197 /* Set Region number */
1198 WRITE_REG(MPU_NS->RNR, Region);
1199
1200 /* Set limit address */
1201 MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
1202 }
1203
1204 /**
1205 * @brief Get a non-secure MPU region limit address
1206 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress_NS\n
1207 * @rmtoll MPU_RLAR LIMIT LL_MPU_GetRegionLimitAddress_NS
1208 * @param Region This parameter can be one of the following values:
1209 * @arg @ref LL_MPU_REGION_NUMBER0
1210 * @arg @ref LL_MPU_REGION_NUMBER1
1211 * @arg @ref LL_MPU_REGION_NUMBER2
1212 * @arg @ref LL_MPU_REGION_NUMBER3
1213 * @arg @ref LL_MPU_REGION_NUMBER4
1214 * @arg @ref LL_MPU_REGION_NUMBER5
1215 * @arg @ref LL_MPU_REGION_NUMBER6
1216 * @arg @ref LL_MPU_REGION_NUMBER7
1217 * @retval None
1218 */
LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)1219 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)
1220 {
1221 /* Set Region number */
1222 WRITE_REG(MPU_NS->RNR, Region);
1223
1224 return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk));
1225 }
1226
1227 /**
1228 * @brief Configure a non-secure MPU region access attributes and enable a region
1229 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess_NS\n
1230 * MPU_RBAR XN LL_MPU_SetRegionAccess_NS\n
1231 * MPU_RBAR AP LL_MPU_SetRegionAccess_NS\n
1232 * MPU_RBAR SH LL_MPU_SetRegionAccess_NS
1233 * @param Region This parameter can be one of the following values:
1234 * @arg @ref LL_MPU_REGION_NUMBER0
1235 * @arg @ref LL_MPU_REGION_NUMBER1
1236 * @arg @ref LL_MPU_REGION_NUMBER2
1237 * @arg @ref LL_MPU_REGION_NUMBER3
1238 * @arg @ref LL_MPU_REGION_NUMBER4
1239 * @arg @ref LL_MPU_REGION_NUMBER5
1240 * @arg @ref LL_MPU_REGION_NUMBER6
1241 * @arg @ref LL_MPU_REGION_NUMBER7
1242 * @param Attributes This parameter can be a combination of the following values:
1243 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1244 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1245 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1246 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1247 * or @ref LL_MPU_REGION_ALL_RO
1248 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1249 * @retval None
1250 */
LL_MPU_SetRegionAccess_NS(uint32_t Region,uint32_t Attributes)1251 __STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes)
1252 {
1253 /* Set Region number */
1254 WRITE_REG(MPU_NS->RNR, Region);
1255
1256 /* Set base address Attributes */
1257 MODIFY_REG(MPU_NS->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
1258 }
1259
1260 /**
1261 * @brief Get a non-secure MPU region access attributes
1262 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess_NS\n
1263 * MPU_RBAR XN LL_MPU_GetRegionAccess_NS\n
1264 * MPU_RBAR AP LL_MPU_GetRegionAccess_NS\n
1265 * MPU_RBAR SH LL_MPU_GetRegionAccess_NS
1266 * @param Region This parameter can be one of the following values:
1267 * @arg @ref LL_MPU_REGION_NUMBER0
1268 * @arg @ref LL_MPU_REGION_NUMBER1
1269 * @arg @ref LL_MPU_REGION_NUMBER2
1270 * @arg @ref LL_MPU_REGION_NUMBER3
1271 * @arg @ref LL_MPU_REGION_NUMBER4
1272 * @arg @ref LL_MPU_REGION_NUMBER5
1273 * @arg @ref LL_MPU_REGION_NUMBER6
1274 * @arg @ref LL_MPU_REGION_NUMBER7
1275 * @retval None
1276 */
LL_MPU_GetRegionAccess_NS(uint32_t Region)1277 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region)
1278 {
1279 /* Set Region number */
1280 WRITE_REG(MPU_NS->RNR, Region);
1281
1282 return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
1283 }
1284 #endif /* __ARM_FEATURE_CMSE */
1285
1286 /**
1287 * @}
1288 */
1289
1290 #endif /* __MPU_PRESENT */
1291 /**
1292 * @}
1293 */
1294
1295 /**
1296 * @}
1297 */
1298
1299 /**
1300 * @}
1301 */
1302
1303 #ifdef __cplusplus
1304 }
1305 #endif
1306
1307 #endif /* STM32L5xx_LL_CORTEX_H */
1308
1309
