1 /**
2 ******************************************************************************
3 * @file stm32l5xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L5xx_LL_ADC_H
21 #define STM32L5xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l5xx.h"
29
30 /** @addtogroup STM32L5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer register offset */
51 /* - sequencer rank bits position into the selected register */
52
53 /* Internal register offset for ADC group regular sequencer configuration */
54 /* (offset placed into a spare area of literal definition) */
55 #define ADC_SQR1_REGOFFSET (0x00000000UL)
56 #define ADC_SQR2_REGOFFSET (0x00000100UL)
57 #define ADC_SQR3_REGOFFSET (0x00000200UL)
58 #define ADC_SQR4_REGOFFSET (0x00000300UL)
59
60 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
61 | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
62 #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK*/
63 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
64
65 /* Definition of ADC group regular sequencer bits information to be inserted */
66 /* into ADC group regular sequencer ranks literals definition. */
67 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR1_SQ1" position in register */
68 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR1_SQ2" position in register */
69 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR1_SQ3" position in register */
70 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR1_SQ4" position in register */
71 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR2_SQ5" position in register */
72 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR2_SQ6" position in register */
73 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR2_SQ7" position in register */
74 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR2_SQ8" position in register */
75 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR2_SQ9" position in register */
76 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR3_SQ10" position in register */
77 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR3_SQ11" position in register */
78 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR3_SQ12" position in register */
79 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR3_SQ13" position in register */
80 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR3_SQ14" position in register */
81 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR4_SQ15" position in register */
82 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR4_SQ16" position in register */
83
84
85
86 /* Internal mask for ADC group injected sequencer: */
87 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
88 /* - data register offset */
89 /* - sequencer rank bits position into the selected register */
90
91 /* Internal register offset for ADC group injected data register */
92 /* (offset placed into a spare area of literal definition) */
93 #define ADC_JDR1_REGOFFSET (0x00000000UL)
94 #define ADC_JDR2_REGOFFSET (0x00000100UL)
95 #define ADC_JDR3_REGOFFSET (0x00000200UL)
96 #define ADC_JDR4_REGOFFSET (0x00000300UL)
97
98 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
99 | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
100 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
101 #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK*/
102
103 /* Definition of ADC group injected sequencer bits information to be inserted */
104 /* into ADC group injected sequencer ranks literals definition. */
105 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_JSQR_JSQ1" position in register */
106 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC_JSQR_JSQ2" position in register */
107 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_JSQR_JSQ3" position in register */
108 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (26UL) /* Equivalent to bitfield "ADC_JSQR_JSQ4" position in register */
109
110
111
112 /* Internal mask for ADC group regular trigger: */
113 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
114 /* - regular trigger source */
115 /* - regular trigger edge */
116 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for
117 compatibility with some ADC on other STM32 series
118 having this setting set by HW default value) */
119
120 /* Mask containing trigger source masks for each of possible */
121 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
122 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
123 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
124 ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \
125 ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
126 ((ADC_CFGR_EXTSEL) << (4U * 3UL)) )
127
128 /* Mask containing trigger edge masks for each of possible */
129 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
130 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
131 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
132 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
133 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
134 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
135
136 /* Definition of ADC group regular trigger bits information. */
137 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */
138 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR_EXTEN" position in register */
139
140
141
142 /* Internal mask for ADC group injected trigger: */
143 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
144 /* - injected trigger source */
145 /* - injected trigger edge */
146 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for
147 compatibility with some ADC on other STM32 series
148 having this setting set by HW default value) */
149
150 /* Mask containing trigger source masks for each of possible */
151 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
152 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
153 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
154 ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
155 ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
156 ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
157
158 /* Mask containing trigger edge masks for each of possible */
159 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
160 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
161 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
162 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
163 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
164 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
165
166 /* Definition of ADC group injected trigger bits information. */
167 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */
168 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */
169
170
171
172
173
174
175 /* Internal mask for ADC channel: */
176 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
177 /* - channel identifier defined by number */
178 /* - channel identifier defined by bitfield */
179 /* - channel differentiation between external channels (connected to */
180 /* GPIO pins) and internal channels (connected to internal paths) */
181 /* - channel sampling time defined by SMPRx register offset */
182 /* and SMPx bits positions into SMPRx register */
183 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
184 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
185 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL) /* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK"
186 position in register */
187 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
188 | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
189 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
190 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK
191 >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
192
193 /* Channel differentiation between external and internal channels */
194 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
195 #define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case
196 of different ADC internal channels mapped on same channel
197 number on different ADC instances */
198 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
199
200 /* Internal register offset for ADC channel sampling time configuration */
201 /* (offset placed into a spare area of literal definition) */
202 #define ADC_SMPR1_REGOFFSET (0x00000000UL)
203 #define ADC_SMPR2_REGOFFSET (0x02000000UL)
204 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
205 #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET
206 in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
207
208 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
209 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK"
210 position in register */
211
212 /* Definition of channels ID number information to be inserted into */
213 /* channels literals definition. */
214 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
215 #define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0)
216 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1)
217 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
218 #define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2)
219 #define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
220 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
221 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
222 #define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3)
223 #define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
224 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
225 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
226 #define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
227 #define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
228 #define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
229 #define ADC_CHANNEL_15_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \
230 ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
231 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4)
232 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
233 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
234
235 /* Definition of channels ID bitfield information to be inserted into */
236 /* channels literals definition. */
237 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
238 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
239 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
240 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
241 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
242 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
243 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
244 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
245 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
246 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
247 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
248 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
249 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
250 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
251 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
252 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
253 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
254 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
255 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
256
257 /* Definition of channels sampling time information to be inserted into */
258 /* channels literals definition. */
259 /* Value shifted are equivalent to bitfield "ADC_SMPRx_SMPy" position */
260 /* in register. */
261 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
262 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
263 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
264 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
265 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
266 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
267 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
268 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
269 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
270 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
271 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
272 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
273 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
274 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
275 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
276 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
277 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
278 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
279 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
280
281
282 /* Internal mask for ADC mode single or differential ended: */
283 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
284 /* the relevant bits for: */
285 /* (concatenation of multiple bits used in different registers) */
286 /* - ADC calibration: calibration start, calibration factor get or set */
287 /* - ADC channels: set each ADC channel ending mode */
288 #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
289 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
290 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
291 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen
292 to perform of shift when single mode is selected, shift value out of
293 channels bits range. */
294 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode:
295 mask of bit */
296 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode:
297 position of bit */
298 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit
299 ADC_SINGLEDIFF_CALIB_F_BIT_D to perform a shift of 4 ranks */
300
301 /* Internal mask for ADC analog watchdog: */
302 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
303 /* (concatenation of multiple bits used in different analog watchdogs, */
304 /* (feature of several watchdogs not available on all STM32 series)). */
305 /* - analog watchdog 1: monitored channel defined by number, */
306 /* selection of ADC group (ADC groups regular and-or injected). */
307 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
308 /* selection on groups. */
309
310 /* Internal register offset for ADC analog watchdog channel configuration */
311 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
312 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
313 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
314
315 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
316 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
317 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
318 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
319
320 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
321
322 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
323 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
324 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
325
326 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET
327 in ADC_AWD_CRX_REGOFFSET_MASK */
328
329 /* Internal register offset for ADC analog watchdog threshold configuration */
330 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
331 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
332 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
333 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
334 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET
335 in ADC_AWD_TRX_REGOFFSET_MASK */
336 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate
337 threshold high: mask of bit */
338 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate
339 threshold high: position of bit */
340 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to
341 position to perform a shift of 4 ranks */
342
343 /* Internal mask for ADC offset: */
344 /* Internal register offset for ADC offset instance configuration */
345 #define ADC_OFR1_REGOFFSET (0x00000000UL)
346 #define ADC_OFR2_REGOFFSET (0x00000001UL)
347 #define ADC_OFR3_REGOFFSET (0x00000002UL)
348 #define ADC_OFR4_REGOFFSET (0x00000003UL)
349 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
350 | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
351
352
353 /* ADC registers bits positions */
354 #define ADC_CFGR_RES_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CFGR_RES" position in register */
355 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC_CFGR_AWD1SGL" position in register */
356 #define ADC_CFGR_AWD1EN_BITOFFSET_POS (23UL) /* Equivalent to bitfield "ADC_CFGR_AWD1EN" position in register */
357 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_CFGR_JAWD1EN" position in register */
358 #define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_TR1_HT1" position in register */
359
360
361 /* ADC registers bits groups */
362 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \
363 | ADC_CR_JADSTART | ADC_CR_JADSTP \
364 | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with
365 HW property "rs": Software can read as well as set this bit.
366 Writing '0' has no effect on the bit value. */
367
368
369 /* ADC internal channels related definitions */
370 /* Internal voltage reference VrefInt */
371 #define VREFINT_CAL_ADDR ((uint16_t*) (0x0BFA05AAUL)) /* Internal voltage reference, address of
372 parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC
373 (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
374 #define VREFINT_CAL_VREF (3000UL) /* Analog voltage reference (Vref+) value
375 with which VrefInt has been calibrated in production
376 (tolerance: +-10 mV) (unit: mV). */
377 /* Temperature sensor */
378 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x0BFA05A8UL)) /* Address of parameter TS_CAL1: On STM32L5,
379 temperature sensor ADC raw data acquired at temperature 30 DegC
380 (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
381 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x0BFA05CAUL)) /* Address of parameter TS_CAL2: On STM32L5,
382 temperature sensor ADC raw data acquired at temperature 110 DegC
383 (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
384 #define TEMPSENSOR_CAL1_TEMP (30L) /* Temperature at which temperature sensor
385 has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR
386 (tolerance: +-5 DegC) (unit: DegC). */
387 #define TEMPSENSOR_CAL2_TEMP (110L) /* Temperature at which temperature sensor
388 has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
389 (tolerance: +-5 DegC) (unit: DegC). */
390 #define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) value
391 with which temperature sensor has been calibrated in production (tolerance +-10 mV) (unit: mV). */
392
393 /**
394 * @}
395 */
396
397
398 /* Private macros ------------------------------------------------------------*/
399 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
400 * @{
401 */
402
403 /**
404 * @brief Driver macro reserved for internal use: set a pointer to
405 * a register from a register basis from which an offset
406 * is applied.
407 * @param __REG__ Register basis from which the offset is applied.
408 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
409 * @retval Pointer to register address
410 */
411 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
412 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
413
414 /**
415 * @}
416 */
417
418
419 /* Exported types ------------------------------------------------------------*/
420 #if defined(USE_FULL_LL_DRIVER)
421 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
422 * @{
423 */
424
425 /**
426 * @brief Structure definition of some features of ADC common parameters
427 * and multimode
428 * (all ADC instances belonging to the same ADC common instance).
429 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
430 * is conditioned to ADC instances state (all ADC instances
431 * sharing the same ADC common instance):
432 * All ADC instances sharing the same ADC common instance must be
433 * disabled.
434 */
435 typedef struct
436 {
437 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
438 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
439 @note On this STM32 series, if ADC group injected is used, some clock ratio
440 constraints between ADC clock and AHB clock must be respected.
441 Refer to reference manual.
442 This feature can be modified afterwards using unitary function
443 @ref LL_ADC_SetCommonClock(). */
444
445 #if defined(ADC_MULTIMODE_SUPPORT)
446 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode
447 (for devices with several ADC instances).
448 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
449 This feature can be modified afterwards using unitary function
450 @ref LL_ADC_SetMultimode(). */
451
452 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
453 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
454 This feature can be modified afterwards using unitary function
455 @ref LL_ADC_SetMultiDMATransfer(). */
456
457 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
458 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
459 This feature can be modified afterwards using unitary function
460 @ref LL_ADC_SetMultiTwoSamplingDelay(). */
461 #endif /* ADC_MULTIMODE_SUPPORT */
462
463 } LL_ADC_CommonInitTypeDef;
464
465 /**
466 * @brief Structure definition of some features of ADC instance.
467 * @note These parameters have an impact on ADC scope: ADC instance.
468 * Affects both group regular and group injected (availability
469 * of ADC group injected depends on STM32 series).
470 * Refer to corresponding unitary functions into
471 * @ref ADC_LL_EF_Configuration_ADC_Instance .
472 * @note The setting of these parameters by function @ref LL_ADC_Init()
473 * is conditioned to ADC state:
474 * ADC instance must be disabled.
475 * This condition is applied to all ADC features, for efficiency
476 * and compatibility over all STM32 series. However, the different
477 * features can be set under different ADC state conditions
478 * (setting possible with ADC enabled without conversion on going,
479 * ADC enabled with conversion on going, ...)
480 * Each feature can be updated afterwards with a unitary function
481 * and potentially with ADC in a different state than disabled,
482 * refer to description of each function for setting
483 * conditioned to ADC state.
484 */
485 typedef struct
486 {
487 uint32_t Resolution; /*!< Set ADC resolution.
488 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
489 This feature can be modified afterwards using unitary function
490 @ref LL_ADC_SetResolution(). */
491
492 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
493 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
494 This feature can be modified afterwards using unitary function
495 @ref LL_ADC_SetDataAlignment(). */
496
497 uint32_t LowPowerMode; /*!< Set ADC low power mode.
498 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
499 This feature can be modified afterwards using unitary function
500 @ref LL_ADC_SetLowPowerMode(). */
501
502 } LL_ADC_InitTypeDef;
503
504 /**
505 * @brief Structure definition of some features of ADC group regular.
506 * @note These parameters have an impact on ADC scope: ADC group regular.
507 * Refer to corresponding unitary functions into
508 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
509 * (functions with prefix "REG").
510 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
511 * is conditioned to ADC state:
512 * ADC instance must be disabled.
513 * This condition is applied to all ADC features, for efficiency
514 * and compatibility over all STM32 series. However, the different
515 * features can be set under different ADC state conditions
516 * (setting possible with ADC enabled without conversion on going,
517 * ADC enabled with conversion on going, ...)
518 * Each feature can be updated afterwards with a unitary function
519 * and potentially with ADC in a different state than disabled,
520 * refer to description of each function for setting
521 * conditioned to ADC state.
522 */
523 typedef struct
524 {
525 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or
526 from external peripheral (timer event, external interrupt line).
527 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
528 @note On this STM32 series, setting trigger source to external trigger also
529 set trigger polarity to rising edge(default setting for compatibility
530 with some ADC on other STM32 series having this setting set by HW
531 default value).
532 In case of need to modify trigger edge, use function
533 @ref LL_ADC_REG_SetTriggerEdge().
534 This feature can be modified afterwards using unitary function
535 @ref LL_ADC_REG_SetTriggerSource(). */
536
537 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
538 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
539 This feature can be modified afterwards using unitary function
540 @ref LL_ADC_REG_SetSequencerLength(). */
541
542 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
543 and scan conversions interrupted every selected number of ranks.
544 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
545 @note This parameter has an effect only if group regular sequencer is
546 enabled (scan length of 2 ranks or more).
547 This feature can be modified afterwards using unitary function
548 @ref LL_ADC_REG_SetSequencerDiscont(). */
549
550 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC
551 conversions are performed in single mode (one conversion per trigger) or in
552 continuous mode (after the first trigger, following conversions launched
553 successively automatically).
554 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
555 Note: It is not possible to enable both ADC group regular continuous mode
556 and discontinuous mode.
557 This feature can be modified afterwards using unitary function
558 @ref LL_ADC_REG_SetContinuousMode(). */
559
560 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer
561 by DMA, and DMA requests mode.
562 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
563 This feature can be modified afterwards using unitary function
564 @ref LL_ADC_REG_SetDMATransfer(). */
565
566 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
567 data preserved or overwritten.
568 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
569 This feature can be modified afterwards using unitary function
570 @ref LL_ADC_REG_SetOverrun(). */
571
572 } LL_ADC_REG_InitTypeDef;
573
574 /**
575 * @brief Structure definition of some features of ADC group injected.
576 * @note These parameters have an impact on ADC scope: ADC group injected.
577 * Refer to corresponding unitary functions into
578 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
579 * (functions with prefix "INJ").
580 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
581 * is conditioned to ADC state:
582 * ADC instance must be disabled.
583 * This condition is applied to all ADC features, for efficiency
584 * and compatibility over all STM32 series. However, the different
585 * features can be set under different ADC state conditions
586 * (setting possible with ADC enabled without conversion on going,
587 * ADC enabled with conversion on going, ...)
588 * Each feature can be updated afterwards with a unitary function
589 * and potentially with ADC in a different state than disabled,
590 * refer to description of each function for setting
591 * conditioned to ADC state.
592 */
593 typedef struct
594 {
595 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start)
596 or from external peripheral (timer event, external interrupt line).
597 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
598 @note On this STM32 series, setting trigger source to external trigger also
599 set trigger polarity to rising edge (default setting for
600 compatibility with some ADC on other STM32 series having this
601 setting set by HW default value).
602 In case of need to modify trigger edge, use function
603 @ref LL_ADC_INJ_SetTriggerEdge().
604 This feature can be modified afterwards using unitary function
605 @ref LL_ADC_INJ_SetTriggerSource(). */
606
607 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
608 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
609 This feature can be modified afterwards using unitary function
610 @ref LL_ADC_INJ_SetSequencerLength(). */
611
612 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided
613 and scan conversions interrupted every selected number of ranks.
614 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
615 @note This parameter has an effect only if group injected sequencer is
616 enabled (scan length of 2 ranks or more).
617 This feature can be modified afterwards using unitary function
618 @ref LL_ADC_INJ_SetSequencerDiscont(). */
619
620 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group
621 regular.
622 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
623 Note: This parameter must be set to set to independent trigger if injected
624 trigger source is set to an external trigger.
625 This feature can be modified afterwards using unitary function
626 @ref LL_ADC_INJ_SetTrigAuto(). */
627
628 } LL_ADC_INJ_InitTypeDef;
629
630 /**
631 * @}
632 */
633 #endif /* USE_FULL_LL_DRIVER */
634
635 /* Exported constants --------------------------------------------------------*/
636 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
637 * @{
638 */
639
640 /** @defgroup ADC_LL_EC_FLAG ADC flags
641 * @brief Flags defines which can be used with LL_ADC_ReadReg function
642 * @{
643 */
644 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
645 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary
646 conversion */
647 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence
648 conversions */
649 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
650 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
651 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary
652 conversion */
653 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence
654 conversions */
655 #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue
656 overflow */
657 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
658 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
659 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
660 #if defined(ADC_MULTIMODE_SUPPORT)
661 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
662 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
663 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of
664 unitary conversion */
665 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of
666 unitary conversion */
667 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of
668 sequence conversions */
669 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of
670 sequence conversions */
671 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular
672 overrun */
673 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular
674 overrun */
675 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of
676 sampling phase */
677 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of
678 sampling phase */
679 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of
680 unitary conversion */
681 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of
682 unitary conversion */
683 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of
684 sequence conversions */
685 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of
686 sequence conversions */
687 #define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected
688 contexts queue overflow */
689 #define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected
690 contexts queue overflow */
691 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1
692 of the ADC master */
693 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1
694 of the ADC slave */
695 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2
696 of the ADC master */
697 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2
698 of the ADC slave */
699 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3
700 of the ADC master */
701 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3
702 of the ADC slave */
703 #endif /* ADC_MULTIMODE_SUPPORT */
704 /**
705 * @}
706 */
707
708 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
709 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
710 * @{
711 */
712 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
713 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary
714 conversion */
715 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence
716 conversions */
717 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
718 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling
719 phase */
720 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary
721 conversion */
722 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence
723 conversions */
724 #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue
725 overflow */
726 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
727 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
728 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
729 /**
730 * @}
731 */
732
733 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
734 * @{
735 */
736 /* List of ADC registers intended to be used (most commonly) with */
737 /* DMA transfer. */
738 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
739 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register
740 (corresponding to register DR) to be used with ADC configured in independent
741 mode. Without DMA transfer, register accessed by LL function
742 @ref LL_ADC_REG_ReadConversionData32() and other
743 functions @ref LL_ADC_REG_ReadConversionDatax() */
744 #if defined(ADC_MULTIMODE_SUPPORT)
745 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register
746 (corresponding to register CDR) to be used with ADC configured in multimode
747 (available on STM32 devices with several ADC instances).
748 Without DMA transfer, register accessed by LL function
749 @ref LL_ADC_REG_ReadMultiConversionData32() */
750 #endif /* ADC_MULTIMODE_SUPPORT */
751 /**
752 * @}
753 */
754
755 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
756 * @{
757 */
758 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from
759 AHB clock without prescaler */
760 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1) /*!< ADC synchronous clock derived from
761 AHB clock with prescaler division by 2 */
762 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from
763 AHB clock with prescaler division by 4 */
764 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without
765 prescaler */
766 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
767 prescaler division by 2 */
768 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
769 prescaler division by 4 */
770 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
771 prescaler division by 6 */
772 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with
773 prescaler division by 8 */
774 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
775 prescaler division by 10 */
776 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
777 prescaler division by 12 */
778 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \
779 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
780 prescaler division by 16 */
781 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with
782 prescaler division by 32 */
783 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
784 prescaler division by 64 */
785 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
786 prescaler division by 128 */
787 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \
788 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
789 prescaler division by 256 */
790 /**
791 * @}
792 */
793
794 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
795 * @{
796 */
797 /* Note: Other measurement paths to internal channels may be available */
798 /* (connections to other peripherals). */
799 /* If they are not listed below, they do not require any specific */
800 /* path enable. In this case, Access to measurement path is done */
801 /* only by selecting the corresponding ADC internal channel. */
802 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
803 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
804 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel
805 temperature sensor */
806 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
807 /**
808 * @}
809 */
810
811 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
812 * @{
813 */
814 #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
815 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
816 #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */
817 #define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */
818 /**
819 * @}
820 */
821
822 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
823 * @{
824 */
825 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned
826 (alignment on data register LSB bit 0)*/
827 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned
828 (alignment on data register MSB bit 15)*/
829 /**
830 * @}
831 */
832
833 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
834 * @{
835 */
836 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
837 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power
838 mode, ADC conversions are performed only when necessary
839 (when previous ADC conversion data is read).
840 See description with function @ref LL_ADC_SetLowPowerMode(). */
841 /**
842 * @}
843 */
844
845 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset instance
846 * @{
847 */
848 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset instance 1: ADC channel and offset level
849 to which the offset programmed will be applied (independently of channel
850 mapped on ADC group regular or injected) */
851 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset instance 2: ADC channel and offset level
852 to which the offset programmed will be applied (independently of channel
853 mapped on ADC group regular or injected) */
854 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset instance 3: ADC channel and offset level
855 to which the offset programmed will be applied (independently of channel
856 mapped on ADC group regular or injected) */
857 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset instance 4: ADC channel and offset level
858 to which the offset programmed will be applied (independently of channel
859 mapped on ADC group regular or injected) */
860 /**
861 * @}
862 */
863
864 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
865 * @{
866 */
867 #define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled
868 (setting offset instance wise) */
869 #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled
870 (setting offset instance wise) */
871 /**
872 * @}
873 */
874
875 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
876 * @{
877 */
878 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
879 #define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32
880 devices)*/
881 #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
882 /**
883 * @}
884 */
885
886 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
887 * @{
888 */
889 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP \
890 | ADC_CHANNEL_0_BITFIELD) /*!< ADC channel ADCx_IN0 */
891 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP \
892 | ADC_CHANNEL_1_BITFIELD) /*!< ADC channel ADCx_IN1 */
893 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP \
894 | ADC_CHANNEL_2_BITFIELD) /*!< ADC channel ADCx_IN2 */
895 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP \
896 | ADC_CHANNEL_3_BITFIELD) /*!< ADC channel ADCx_IN3 */
897 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP \
898 | ADC_CHANNEL_4_BITFIELD) /*!< ADC channel ADCx_IN4 */
899 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP \
900 | ADC_CHANNEL_5_BITFIELD) /*!< ADC channel ADCx_IN5 */
901 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP \
902 | ADC_CHANNEL_6_BITFIELD) /*!< ADC channel ADCx_IN6 */
903 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP \
904 | ADC_CHANNEL_7_BITFIELD) /*!< ADC channel ADCx_IN7 */
905 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP \
906 | ADC_CHANNEL_8_BITFIELD) /*!< ADC channel ADCx_IN8 */
907 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP \
908 | ADC_CHANNEL_9_BITFIELD) /*!< ADC channel ADCx_IN9 */
909 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP \
910 | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */
911 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP \
912 | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */
913 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP \
914 | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */
915 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP \
916 | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */
917 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP \
918 | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */
919 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP \
920 | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */
921 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | \
922 ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */
923 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | \
924 ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */
925 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | \
926 ADC_CHANNEL_18_BITFIELD) /*!< ADC channel ADCx_IN18 */
927 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
928 connected to VrefInt: Internal voltage reference, channel specific to ADC1.*/
929 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
930 connected to internal temperature sensor, channel specific to ADC1. */
931 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
932 connected to Vbat/2: Vbat voltage through a divider ladder of factor 1/2
933 to have channel voltage always below Vdda, channel specific to ADC1. */
934 #define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | \
935 ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel
936 connected to DAC1 channel 1, channel specific to ADC2. */
937 #define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | \
938 ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel
939 connected to DAC1 channel 2, channel specific to ADC2. */
940 /**
941 * @}
942 */
943
944 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
945 * @{
946 */
947 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular
948 conversion trigger internal: SW start. */
949 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | \
950 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
951 conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to
952 rising edge (default setting). */
953 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \
954 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
955 conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to
956 rising edge (default setting). */
957 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
958 conversion trigger from external peripheral: TIM1 channel 1 event (capture
959 compare: input capture or output capture). Trigger edge set to rising edge
960 (default setting). */
961 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
962 conversion trigger from external peripheral: TIM1 channel 2 event (capture
963 compare: input capture or output capture). Trigger edge set to rising edge
964 (default setting). */
965 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
966 conversion trigger from external peripheral: TIM1 channel 3 event (capture
967 compare: input capture or output capture). Trigger edge set to rising edge
968 (default setting). */
969 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \
970 ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
971 conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to
972 rising edge (default setting). */
973 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
974 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
975 conversion trigger from external peripheral: TIM2 channel 2 event (capture
976 compare: input capture or output capture). Trigger edge set to rising edge
977 (default setting). */
978 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
979 conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to
980 rising edge (default setting). */
981 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
982 ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
983 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
984 conversion trigger from external peripheral: TIM3 channel 4 event (capture
985 compare: input capture or output capture). Trigger edge set to rising edge
986 (default setting). */
987 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
988 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
989 conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to
990 rising edge (default setting). */
991 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \
992 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
993 conversion trigger from external peripheral: TIM4 channel 4 event (capture
994 compare: input capture or output capture). Trigger edge set to rising edge
995 (default setting). */
996 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
997 ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
998 conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to
999 rising edge (default setting). */
1000 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
1001 ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1002 conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to
1003 rising edge (default setting). */
1004 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1005 conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to
1006 rising edge (default setting). */
1007 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
1008 ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1009 conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to
1010 rising edge (default setting). */
1011 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
1012 ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
1013 conversion trigger from external peripheral: external interrupt line 11.
1014 Trigger edge set to rising edge (default setting). */
1015 /**
1016 * @}
1017 */
1018
1019 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
1020 * @{
1021 */
1022 #define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion
1023 trigger polarity set to rising edge */
1024 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1) /*!< ADC group regular conversion
1025 trigger polarity set to falling edge */
1026 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion
1027 trigger polarity set to both rising and falling edges */
1028 /**
1029 * @}
1030 */
1031
1032 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
1033 * @{
1034 */
1035 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode:
1036 one conversion per trigger */
1037 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions performed in continuous mode:
1038 after the first trigger, following conversions launched successively
1039 automatically */
1040 /**
1041 * @}
1042 */
1043
1044 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
1045 * @{
1046 */
1047 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
1048 #define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA
1049 in limited mode (one shot mode): DMA transfer requests are stopped when
1050 number of DMA data transfers (number of ADC conversions) is reached.
1051 This ADC mode is intended to be used with DMA mode non-circular. */
1052 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are
1053 transferred by DMA, in unlimited mode: DMA transfer requests are unlimited,
1054 whatever number of DMA data transferred (number of ADC conversions).
1055 This ADC mode is intended to be used with DMA mode circular. */
1056 /**
1057 * @}
1058 */
1059
1060 #if defined(DFSDM1_Channel0)
1061 /** @defgroup ADC_LL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data
1062 * @{
1063 */
1064 #define LL_ADC_REG_DFSDM_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */
1065 #define LL_ADC_REG_DFSDM_TRANSFER_ENABLE (ADC_CFGR_DFSDMCFG) /*!< ADC conversion data are transferred to DFSDM for
1066 post processing. The ADC conversion data format must be 16-bit signed and
1067 right aligned, refer to reference manual.
1068 DFSDM transfer cannot be used if DMA transfer is enabled. */
1069 /**
1070 * @}
1071 */
1072 #endif /* ADC_CFGR_DFSDMCFG */
1073
1074 #if defined(ADC_SMPR1_SMPPLUS)
1075 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration
1076 * @{
1077 */
1078 #define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL) /*!< ADC sampling time let to default settings. */
1079 #define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock
1080 cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped
1081 with selection sampling time 2.5 ADC clock cycles, whatever channels mapped
1082 on ADC groups regular or injected). */
1083 /**
1084 * @}
1085 */
1086 #endif /* ADC_SMPR1_SMPPLUS */
1087
1088 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
1089 * @{
1090 */
1091 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun:
1092 data preserved */
1093 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun:
1094 data overwritten */
1095 /**
1096 * @}
1097 */
1098
1099 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
1100 * @{
1101 */
1102 #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable
1103 (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1104 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1105 with 2 ranks in the sequence */
1106 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
1107 with 3 ranks in the sequence */
1108 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1109 with 4 ranks in the sequence */
1110 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_SQR1_L_2) /*!< ADC group regular sequencer enable
1111 with 5 ranks in the sequence */
1112 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1113 with 6 ranks in the sequence */
1114 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
1115 with 7 ranks in the sequence */
1116 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1 \
1117 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1118 with 8 ranks in the sequence */
1119 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3) /*!< ADC group regular sequencer enable
1120 with 9 ranks in the sequence */
1121 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1122 with 10 ranks in the sequence */
1123 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
1124 with 11 ranks in the sequence */
1125 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 \
1126 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1127 with 12 ranks in the sequence */
1128 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2) /*!< ADC group regular sequencer enable
1129 with 13 ranks in the sequence */
1130 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
1131 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1132 with 14 ranks in the sequence */
1133 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
1134 | ADC_SQR1_L_1) /*!< ADC group regular sequencerenable
1135 with 15 ranks in the sequence */
1136 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
1137 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
1138 with 16 ranks in the sequence */
1139 /**
1140 * @}
1141 */
1142
1143 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
1144 * @{
1145 */
1146 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer
1147 discontinuous mode disable */
1148 #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1149 discontinuous mode enable with sequence interruption every rank */
1150 #define LL_ADC_REG_SEQ_DISCONT_2RANKS (ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1151 discontinuous mode enabled with sequence interruption every 2 ranks */
1152 #define LL_ADC_REG_SEQ_DISCONT_3RANKS (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1153 discontinuous mode enable with sequence interruption every 3 ranks */
1154 #define LL_ADC_REG_SEQ_DISCONT_4RANKS (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 \
1155 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1156 discontinuous mode enable with sequence interruption every 4 ranks */
1157 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1158 discontinuous mode enable with sequence interruption every 5 ranks */
1159 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 \
1160 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1161 discontinuous mode enable with sequence interruption every 6 ranks */
1162 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \
1163 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1164 discontinuous mode enable with sequence interruption every 7 ranks */
1165 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \
1166 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer
1167 discontinuous mode enable with sequence interruption every 8 ranks */
1168 /**
1169 * @}
1170 */
1171
1172 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
1173 * @{
1174 */
1175 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group
1176 regular sequencer rank 1 */
1177 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group
1178 regular sequencer rank 2 */
1179 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group
1180 regular sequencer rank 3 */
1181 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group
1182 regular sequencer rank 4 */
1183 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group
1184 regular sequencer rank 5 */
1185 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group
1186 regular sequencer rank 6 */
1187 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group
1188 regular sequencer rank 7 */
1189 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group
1190 regular sequencer rank 8 */
1191 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group
1192 regular sequencer rank 9 */
1193 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group
1194 regular sequencer rank 10 */
1195 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group
1196 regular sequencer rank 11 */
1197 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group
1198 regular sequencer rank 12 */
1199 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group
1200 regular sequencer rank 13 */
1201 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group
1202 regular sequencer rank 14 */
1203 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group
1204 regular sequencer rank 15 */
1205 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group
1206 regular sequencer rank 16 */
1207 /**
1208 * @}
1209 */
1210
1211 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
1212 * @{
1213 */
1214 #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected
1215 conversion trigger internal: SW start. */
1216 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1217 conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to
1218 rising edge (default setting). */
1219 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1220 conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to
1221 rising edge (default setting). */
1222 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1223 conversion trigger from external peripheral: TIM1 channel 4 event (capture
1224 compare: input capture or output capture). Trigger edge set to rising edge
1225 (default setting). */
1226 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1227 conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to
1228 rising edge (default setting). */
1229 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
1230 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1231 conversion trigger from external peripheral: TIM2 channel 1 event (capture
1232 compare: input capture or output capture). Trigger edge set to rising edge
1233 (default setting). */
1234 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
1235 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1236 conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set t
1237 rising edge (default setting). */
1238 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
1239 ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1240 conversion trigger from external peripheral: TIM3 channel 1 event (capture
1241 compare: input capture or output capture). Trigger edge set to rising edge
1242 (default setting). */
1243 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
1244 ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1245 conversion trigger from external peripheral: TIM3 channel 3 event (capture
1246 compare: input capture or output capture). Trigger edge set to rising edge
1247 (default setting). */
1248 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1249 conversion trigger from external peripheral: TIM3 channel 4 event (capture
1250 compare: input capture or output capture). Trigger edge set to rising edge
1251 (default setting). */
1252 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | \
1253 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1254 conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to
1255 rising edge (default setting). */
1256 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
1257 ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1258 conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to
1259 rising edge (default setting). */
1260 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
1261 ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1262 conversion trigger from external peripheral: TIM8 channel 4 event (capture
1263 compare: input capture or output capture). Trigger edge set to rising edge
1264 (default setting). */
1265 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | \
1266 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1267 conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to
1268 rising edge (default setting). */
1269 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
1270 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1271 conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to
1272 rising edge (default setting). */
1273 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
1274 ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
1275 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1276 conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to
1277 rising edge (default setting). */
1278 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
1279 ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected
1280 conversion trigger from external peripheral: external interrupt line 15.
1281 Trigger edge set to rising edge (default setting). */
1282 /**
1283 * @}
1284 */
1285
1286 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
1287 * @{
1288 */
1289 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion
1290 trigger polarity set to rising edge */
1291 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion
1292 trigger polarity set to falling edge */
1293 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion
1294 trigger polarity set to both rising and falling edges */
1295 /**
1296 * @}
1297 */
1298
1299 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
1300 * @{
1301 */
1302 #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent.
1303 Setting mandatory if ADC group injected injected trigger source is set to
1304 an external trigger. */
1305 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group
1306 regular. Setting compliant only with group injected trigger source set to
1307 SW start, without any further action on ADC group injected conversion start
1308 or stop: in this case, ADC group injected is controlled only from ADC group
1309 regular. */
1310 /**
1311 * @}
1312 */
1313
1314 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
1315 * @{
1316 */
1317 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled
1318 and can contain up to 2 contexts. When all contexts have been processed,
1319 the queue maintains the last context active perpetually. */
1320 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled
1321 and can contain up to 2 contexts. When all contexts have been processed,
1322 the queue is empty and injected group triggers are disabled. */
1323 #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled:
1324 only 1 sequence can be configured and is active perpetually. */
1325 /**
1326 * @}
1327 */
1328
1329 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
1330 * @{
1331 */
1332 #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable
1333 (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1334 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable
1335 with 2 ranks in the sequence */
1336 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable
1337 with 3 ranks in the sequence */
1338 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable
1339 with 4 ranks in the sequence */
1340 /**
1341 * @}
1342 */
1343
1344 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
1345 * @{
1346 */
1347 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode
1348 disable */
1349 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode
1350 enable with sequence interruption every rank */
1351 /**
1352 * @}
1353 */
1354
1355 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
1356 * @{
1357 */
1358 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET \
1359 | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 1 */
1360 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET \
1361 | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 2 */
1362 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET \
1363 | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 3 */
1364 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET \
1365 | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 4 */
1366 /**
1367 * @}
1368 */
1369
1370 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1371 * @{
1372 */
1373 #define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */
1374 #define LL_ADC_SAMPLINGTIME_6CYCLES_5 (ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
1375 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR2_SMP10_1) /*!< Sampling time 12.5 ADC clock cycles */
1376 #define LL_ADC_SAMPLINGTIME_24CYCLES_5 (ADC_SMPR2_SMP10_1 \
1377 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
1378 #define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2) /*!< Sampling time 47.5 ADC clock cycles */
1379 #define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 \
1380 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
1381 #define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 \
1382 | ADC_SMPR2_SMP10_1) /*!< Sampling time 247.5 ADC clock cycles */
1383 #define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 \
1384 | ADC_SMPR2_SMP10_1 \
1385 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
1386 /**
1387 * @}
1388 */
1389
1390 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
1391 * @{
1392 */
1393 #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending
1394 set to single ended (literal also used to set calibration mode) */
1395 #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending
1396 set to differential (literal also used to set calibration mode) */
1397 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending
1398 set to both single ended and differential (literal used only to set
1399 calibration factors) */
1400 /**
1401 * @}
1402 */
1403
1404 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1405 * @{
1406 */
1407 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \
1408 | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1409 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \
1410 | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
1411 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \
1412 | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
1413 /**
1414 * @}
1415 */
1416
1417 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1418 * @{
1419 */
1420 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring
1421 disabled */
1422 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \
1423 | ADC_CFGR_AWD1EN) /*!< ADC analog watchdog monitoring
1424 of all channels, converted by group regular only */
1425 #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK \
1426 | ADC_CFGR_JAWD1EN) /*!< ADC analog watchdog monitoring
1427 of all channels, converted by group injected only */
1428 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK \
1429 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN) /*!< ADC analog watchdog monitoring
1430 of all channels, converted by either group regular or injected */
1431 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
1432 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1433 of ADC channel ADCx_IN0, converted by group regular only */
1434 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
1435 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1436 of ADC channel ADCx_IN0, converted by group injected only */
1437 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \
1438 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1439 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1440 of ADC channel ADCx_IN0, converted by either group regular or injected */
1441 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
1442 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1443 of ADC channel ADCx_IN1, converted by group regular only */
1444 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
1445 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1446 of ADC channel ADCx_IN1, converted by group injected only */
1447 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \
1448 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1449 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1450 of ADC channel ADCx_IN1, converted by either group regular or injected */
1451 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
1452 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1453 of ADC channel ADCx_IN2, converted by group regular only */
1454 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
1455 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1456 of ADC channel ADCx_IN2, converted by group injected only */
1457 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \
1458 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1459 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1460 of ADC channel ADCx_IN2, converted by either group regular or injected */
1461 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
1462 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1463 of ADC channel ADCx_IN3, converted by group regular only */
1464 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
1465 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1466 of ADC channel ADCx_IN3, converted by group injected only */
1467 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \
1468 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1469 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1470 of ADC channel ADCx_IN3, converted by either group regular or injected */
1471 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
1472 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1473 of ADC channel ADCx_IN4, converted by group regular only */
1474 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
1475 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1476 of ADC channel ADCx_IN4, converted by group injected only */
1477 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \
1478 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1479 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1480 of ADC channel ADCx_IN4, converted by either group regular or injected */
1481 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
1482 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1483 of ADC channel ADCx_IN5, converted by group regular only */
1484 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
1485 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1486 of ADC channel ADCx_IN5, converted by group injected only */
1487 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \
1488 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1489 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1490 of ADC channel ADCx_IN5, converted by either group regular or injected */
1491 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
1492 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1493 of ADC channel ADCx_IN6, converted by group regular only */
1494 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
1495 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1496 of ADC channel ADCx_IN6, converted by group injected only */
1497 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \
1498 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1499 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1500 of ADC channel ADCx_IN6, converted by either group regular or injected */
1501 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
1502 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1503 of ADC channel ADCx_IN7, converted by group regular only */
1504 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
1505 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1506 of ADC channel ADCx_IN7, converted by group injected only */
1507 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \
1508 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1509 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1510 of ADC channel ADCx_IN7, converted by either group regular or injected */
1511 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
1512 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1513 of ADC channel ADCx_IN8, converted by group regular only */
1514 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
1515 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1516 of ADC channel ADCx_IN8, converted by group injected only */
1517 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \
1518 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1519 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1520 of ADC channel ADCx_IN8, converted by either group regular or injected */
1521 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
1522 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1523 of ADC channel ADCx_IN9, converted by group regular only */
1524 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
1525 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1526 of ADC channel ADCx_IN9, converted by group injected only */
1527 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \
1528 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1529 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1530 of ADC channel ADCx_IN9, converted by either group regular or injected */
1531 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
1532 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1533 of ADC channel ADCx_IN10, converted by group regular only */
1534 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
1535 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1536 of ADC channel ADCx_IN10, converted by group injected only */
1537 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)\
1538 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1539 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1540 of ADC channel ADCx_IN10, converted by either group regular or injected */
1541 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
1542 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1543 of ADC channel ADCx_IN11, converted by group regular only */
1544 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
1545 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1546 of ADC channel ADCx_IN11, converted by group injected only */
1547 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
1548 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1549 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1550 of ADC channel ADCx_IN11, converted by either group regular or injected */
1551 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
1552 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1553 of ADC channel ADCx_IN12, converted by group regular only */
1554 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
1555 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1556 of ADC channel ADCx_IN12, converted by group injected only */
1557 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
1558 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1559 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1560 of ADC channel ADCx_IN12, converted by either group regular or injected */
1561 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
1562 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1563 of ADC channel ADCx_IN13, converted by group regular only */
1564 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
1565 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1566 of ADC channel ADCx_IN13, converted by group injected only */
1567 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
1568 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1569 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1570 of ADC channel ADCx_IN13, converted by either group regular or injected */
1571 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
1572 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1573 of ADC channel ADCx_IN14, converted by group regular only */
1574 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
1575 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1576 of ADC channel ADCx_IN14, converted by group only */
1577 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
1578 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1579 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1580 of ADC channel ADCx_IN14, converted by either group regular or injected */
1581 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
1582 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1583 monitoring of ADC channel ADCx_IN15, converted by group regular only */
1584 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
1585 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1586 of ADC channel ADCx_IN15, converted by group injected only */
1587 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
1588 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1589 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1590 of ADC channel ADCx_IN15, converted by either group
1591 regular or injected */
1592 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
1593 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1594 of ADC channel ADCx_IN16, converted by group regular only */
1595 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
1596 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1597 of ADC channel ADCx_IN16, converted by group injected only */
1598 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
1599 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1600 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1601 of ADC channel ADCx_IN16, converted by either group regular or injected */
1602 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
1603 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1604 of ADC channel ADCx_IN17, converted by group regular only */
1605 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
1606 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1607 of ADC channel ADCx_IN17, converted by group injected only */
1608 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
1609 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1610 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1611 of ADC channel ADCx_IN17, converted by either group
1612 regular or injected */
1613 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
1614 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1615 of ADC channel ADCx_IN18, converted by group regular only */
1616 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
1617 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1618 of ADC channel ADCx_IN18, converted by group injected only */
1619 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
1620 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1621 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1622 of ADC channel ADCx_IN18, converted by either group
1623 regular or injected */
1624 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
1625 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1626 of ADC internal channel connected to VrefInt: Internal
1627 voltage reference, channel specific to ADC1, converted by group regular
1628 only */
1629 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
1630 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1631 of ADC internal channel connected to VrefInt: Internal
1632 voltage reference, channel specific to ADC1, converted by group injected
1633 only */
1634 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \
1635 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1636 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1637 of ADC internal channel connected to VrefInt: Internal
1638 voltage reference, channel specific to ADC1, converted by either group
1639 regular or injected */
1640 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \
1641 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1642 of ADC internal channel connected to internal temperature sensor,
1643 channel specific to ADC1, converted by group regular only */
1644 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \
1645 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1646 of ADC internal channel connected to internal temperature sensor,
1647 channel specific to ADC1, converted by group injected only */
1648 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \
1649 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1650 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1651 of ADC internal channel connected to internal temperature sensor,
1652 channel specific to ADC1, converted by either group regular or injected */
1653 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \
1654 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1655 of ADC internal channel connected to Vbat/3: Vbat
1656 voltage through a divider ladder of factor 1/3 to have channel voltage always below
1657 Vdda, channel specific to ADC1, converted by group regular only */
1658 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \
1659 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1660 of ADC internal channel connected to Vbat/3: Vbat
1661 voltage through a divider ladder of factor 1/3 to have channel voltage always below
1662 Vdda, channel specific to ADC1, converted by group injected only */
1663 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \
1664 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1665 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1666 of ADC internal channel connected to Vbat/3: Vbat
1667 voltage through a divider ladder of factor 1/3 to have channel voltage always below
1668 Vdda, channel specific to ADC1 */
1669 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) \
1670 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1671 of ADC internal channel connected to DAC1 channel 1,
1672 channel specific to ADC2, converted by group regular only */
1673 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) \
1674 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1675 of ADC internal channel connected to DAC1 channel 1,
1676 channel specific to ADC2, converted by group injected only */
1677 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) \
1678 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1679 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1680 of ADC internal channel connected to DAC1 channel 1,
1681 channel specific to ADC2, converted by either group regular or injected */
1682 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) \
1683 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1684 of ADC internal channel connected to DAC1 channel 2,
1685 channel specific to ADC2, converted by group regular only */
1686 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) \
1687 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1688 of ADC internal channel connected to DAC1 channel 2,
1689 channel specific to ADC2, converted by group injected only */
1690 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) \
1691 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
1692 | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring
1693 of ADC internal channel connected to DAC1 channel 2,
1694 channel specific to ADC2, converted by either group regular or injected */
1695 /**
1696 * @}
1697 */
1698
1699 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1700 * @{
1701 */
1702 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1) /*!< ADC analog watchdog threshold high */
1703 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
1704 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 \
1705 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low
1706 concatenated into the same data */
1707 /**
1708 * @}
1709 */
1710
1711 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1712 * @{
1713 */
1714 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1715 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
1716 ADC group regular. If group injected interrupts group regular:
1717 when ADC group injected is triggered, the oversampling on ADC group regular
1718 is temporary stopped and continued afterwards. */
1719 #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
1720 ADC group regular. If group injected interrupts group regular:
1721 when ADC group injected is triggered, the oversampling on ADC group regular
1722 is resumed from start (oversampler buffer reset). */
1723 #define LL_ADC_OVS_GRP_INJECTED (ADC_CFGR2_JOVSE) /*!< ADC oversampling on conversions of
1724 ADC group injected. */
1725 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED (ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
1726 both ADC groups regular and injected. If group injected interrupting group
1727 regular: when ADC group injected is triggered, the oversampling on ADC group
1728 regular is resumed from start (oversampler buffer reset). */
1729 /**
1730 * @}
1731 */
1732
1733 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1734 * @{
1735 */
1736 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode
1737 (all conversions of oversampling ratio are done from 1 trigger) */
1738 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous
1739 mode (each conversion of oversampling ratio needs a trigger) */
1740 /**
1741 * @}
1742 */
1743
1744 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
1745 * @{
1746 */
1747 #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2
1748 (sum of conversions data computed to result as oversampling conversion data
1749 (before potential shift) */
1750 #define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4
1751 (sum of conversions data computed to result as oversampling conversion data
1752 (before potential shift) */
1753 #define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8
1754 (sum of conversions data computed to result as oversampling conversion data
1755 (before potential shift) */
1756 #define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16
1757 (sum of conversions data computed to result as oversampling conversion data
1758 (before potential shift) */
1759 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32
1760 (sum of conversions data computed to result as oversampling conversion data
1761 (before potential shift) */
1762 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64
1763 (sum of conversions data computed to result as oversampling conversion data
1764 (before potential shift) */
1765 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128
1766 (sum of conversions data computed to result as oversampling conversion data
1767 (before potential shift) */
1768 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \
1769 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256
1770 (sum of conversions data computed to result as oversampling conversion data
1771 (before potential shift) */
1772 /**
1773 * @}
1774 */
1775
1776 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift
1777 * @{
1778 */
1779 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift
1780 (sum of the ADC conversions data is not divided to result as oversampling
1781 conversion data) */
1782 #define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1
1783 (sum of the ADC conversions data (after OVS ratio) is divided by 2
1784 to result as oversampling conversion data) */
1785 #define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2
1786 (sum of the ADC conversions data (after OVS ratio) is divided by 4
1787 to result as oversampling conversion data) */
1788 #define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3
1789 (sum of the ADC conversions data (after OVS ratio) is divided by 8
1790 to result as oversampling conversion data) */
1791 #define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4
1792 (sum of the ADC conversions data (after OVS ratio) is divided by 16
1793 to result as oversampling conversion data) */
1794 #define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5
1795 (sum of the ADC conversions data (after OVS ratio) is divided by 32
1796 to result as oversampling conversion data) */
1797 #define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6
1798 (sum of the ADC conversions data (after OVS ratio) is divided by 64
1799 to result as oversampling conversion data) */
1800 #define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \
1801 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7
1802 (sum of the ADC conversions data (after OVS ratio) is divided by 128
1803 to result as oversampling conversion data) */
1804 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8
1805 (sum of the ADC conversions data (after OVS ratio) is divided by 256
1806 to result as oversampling conversion data) */
1807 /**
1808 * @}
1809 */
1810
1811 #if defined(ADC_MULTIMODE_SUPPORT)
1812 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
1813 * @{
1814 */
1815 #define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC
1816 independent mode) */
1817 #define LL_ADC_MULTI_DUAL_REG_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: group regular
1818 simultaneous */
1819 #define LL_ADC_MULTI_DUAL_REG_INTERL (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 \
1820 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
1821 regular interleaved */
1822 #define LL_ADC_MULTI_DUAL_INJ_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected
1823 simultaneous */
1824 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected
1825 alternate trigger. Works only with external triggers (not SW start) */
1826 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM (ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
1827 regular simultaneous + group injected simultaneous */
1828 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT (ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: Combined group
1829 regular simultaneous + group injected alternate trigger */
1830 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM (ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
1831 regular interleaved + group injected simultaneous */
1832 /**
1833 * @}
1834 */
1835
1836 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
1837 * @{
1838 */
1839 #define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular
1840 conversions are transferred by DMA: each ADC uses its own DMA channel,
1841 with its individual DMA transfer settings */
1842 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (ADC_CCR_MDMA_1) /*!< ADC multimode group regular
1843 conversions are transferred by DMA, one DMA channel for both ADC(DMA of
1844 ADC master), in limited mode (one shot mode): DMA transfer requests
1845 are stopped when number of DMA data transfers (number of ADC conversions)
1846 is reached. This ADC mode is intended to be used with DMA mode
1847 non-circular. Setting for ADC resolution of 12 and 10 bits */
1848 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B (ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular
1849 conversions are transferred by DMA, one DMA channel for both ADC(DMA of
1850 ADC master), in limited mode (one shot mode): DMA transfer requests
1851 are stopped when number of DMA data transfers (number of ADC conversions)
1852 is reached. This ADC mode is intended to be used with DMA mode
1853 non-circular. Setting for ADC resolution of 8 and 6 bits */
1854 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1) /*!< ADC multimode group regular
1855 conversions are transferred by DMA, one DMA channel for both ADC(DMA of
1856 ADC master), in unlimited mode: DMA transfer requests are unlimited,
1857 whatever number of DMA data transferred (number of ADC conversions).
1858 This ADC mode is intended to be used with DMA mode circular.
1859 Setting for ADC resolution of 12 and 10 bits */
1860 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 \
1861 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular
1862 conversions are transferred by DMA, one DMA channel for both ADC (DMA of
1863 ADC master), in unlimited mode: DMA transfer requests are unlimited,
1864 whatever number of DMA data transferred (number of ADC conversions).
1865 This ADC mode is intended to be used with DMA mode circular.
1866 Setting for ADC resolution of 8 and 6 bits */
1867 /**
1868 * @}
1869 */
1870
1871 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1872 * @{
1873 */
1874 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two
1875 sampling phases: 1 ADC clock cycle */
1876 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES (ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1877 sampling phases: 2 ADC clock cycles */
1878 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES (ADC_CCR_DELAY_1) /*!< ADC multimode delay between two
1879 sampling phases: 3 ADC clock cycles */
1880 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1881 sampling phases: 4 ADC clock cycles */
1882 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES (ADC_CCR_DELAY_2) /*!< ADC multimode delay between two
1883 sampling phases: 5 ADC clock cycles */
1884 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1885 sampling phases: 6 ADC clock cycles */
1886 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two
1887 sampling phases: 7 ADC clock cycles */
1888 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 \
1889 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1890 sampling phases: 8 ADC clock cycles */
1891 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3) /*!< ADC multimode delay between two
1892 sampling phases: 9 ADC clock cycles */
1893 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1894 sampling phases: 10 ADC clock cycles */
1895 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two
1896 sampling phases: 11 ADC clock cycles */
1897 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 \
1898 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
1899 sampling phases: 12 ADC clock cycles */
1900 /**
1901 * @}
1902 */
1903
1904 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1905 * @{
1906 */
1907 #define LL_ADC_MULTI_MASTER (ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC
1908 instances: ADC master */
1909 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV) /*!< In multimode, selection among several ADC
1910 instances: ADC slave */
1911 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV \
1912 | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC
1913 instances: both ADC master and ADC slave */
1914 /**
1915 * @}
1916 */
1917
1918 #endif /* ADC_MULTIMODE_SUPPORT */
1919
1920 /** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro
1921 * @{
1922 */
1923 #define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro
1924 @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on
1925 calibration parameters. This value is coded on 16 bits
1926 (to fit on signed word or double word) and corresponds
1927 to an inconsistent temperature value. */
1928 /**
1929 * @}
1930 */
1931
1932 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1933 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
1934 * not timeout values.
1935 * For details on delays values, refer to descriptions in source code
1936 * above each literal definition.
1937 * @{
1938 */
1939
1940 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
1941 /* not timeout values. */
1942 /* Timeout values for ADC operations are dependent to device clock */
1943 /* configuration (system clock versus ADC clock), */
1944 /* and therefore must be defined in user application. */
1945 /* Indications for estimation of ADC timeout delays, for this */
1946 /* STM32 series: */
1947 /* - ADC calibration time: maximum delay is 112/fADC. */
1948 /* (refer to device datasheet, parameter "tCAL") */
1949 /* - ADC enable time: maximum delay is 1 conversion cycle. */
1950 /* (refer to device datasheet, parameter "tSTAB") */
1951 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
1952 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
1953 /* cycles */
1954 /* - ADC conversion time: duration depending on ADC clock and ADC */
1955 /* configuration. */
1956 /* (refer to device reference manual, section "Timing") */
1957
1958 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1959 /* Delay set to maximum value (refer to device datasheet, */
1960 /* parameter "tADCVREG_STUP"). */
1961 /* Unit: us */
1962 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage
1963 regulator start-up time) */
1964
1965 /* Delay for internal voltage reference stabilization time. */
1966 /* Delay set to maximum value (refer to device datasheet, */
1967 /* parameter "tstart_vrefint"). */
1968 /* Unit: us */
1969 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization
1970 time */
1971
1972 /* Delay for temperature sensor stabilization time. */
1973 /* Literal set to maximum value (refer to device datasheet, */
1974 /* parameter "tSTART"). */
1975 /* Unit: us */
1976 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */
1977 #define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization
1978 time (starting from ADC enable, refer to
1979 @ref LL_ADC_Enable()) */
1980
1981 /* Delay required between ADC end of calibration and ADC enable. */
1982 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
1983 /* are required between ADC end of calibration and ADC enable. */
1984 /* Wait time can be computed in user application by waiting for the */
1985 /* equivalent number of CPU cycles, by taking into account */
1986 /* ratio of CPU clock versus ADC clock prescalers. */
1987 /* Unit: ADC clock cycles. */
1988 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration
1989 and ADC enable */
1990
1991 /**
1992 * @}
1993 */
1994
1995 /**
1996 * @}
1997 */
1998
1999
2000 /* Exported macro ------------------------------------------------------------*/
2001 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
2002 * @{
2003 */
2004
2005 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
2006 * @{
2007 */
2008
2009 /**
2010 * @brief Write a value in ADC register
2011 * @param __INSTANCE__ ADC Instance
2012 * @param __REG__ Register to be written
2013 * @param __VALUE__ Value to be written in the register
2014 * @retval None
2015 */
2016 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
2017
2018 /**
2019 * @brief Read a value in ADC register
2020 * @param __INSTANCE__ ADC Instance
2021 * @param __REG__ Register to be read
2022 * @retval Register value
2023 */
2024 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
2025 /**
2026 * @}
2027 */
2028
2029 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
2030 * @{
2031 */
2032
2033 /**
2034 * @brief Helper macro to get ADC channel number in decimal format
2035 * from literals LL_ADC_CHANNEL_x.
2036 * @note Example:
2037 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
2038 * will return decimal number "4".
2039 * @note The input can be a value from functions where a channel
2040 * number is returned, either defined with number
2041 * or with bitfield (only one bit must be set).
2042 * @param __CHANNEL__ This parameter can be one of the following values:
2043 * @arg @ref LL_ADC_CHANNEL_0
2044 * @arg @ref LL_ADC_CHANNEL_1 (7)
2045 * @arg @ref LL_ADC_CHANNEL_2 (7)
2046 * @arg @ref LL_ADC_CHANNEL_3 (7)
2047 * @arg @ref LL_ADC_CHANNEL_4 (7)
2048 * @arg @ref LL_ADC_CHANNEL_5 (7)
2049 * @arg @ref LL_ADC_CHANNEL_6
2050 * @arg @ref LL_ADC_CHANNEL_7
2051 * @arg @ref LL_ADC_CHANNEL_8
2052 * @arg @ref LL_ADC_CHANNEL_9
2053 * @arg @ref LL_ADC_CHANNEL_10
2054 * @arg @ref LL_ADC_CHANNEL_11
2055 * @arg @ref LL_ADC_CHANNEL_12
2056 * @arg @ref LL_ADC_CHANNEL_13
2057 * @arg @ref LL_ADC_CHANNEL_14
2058 * @arg @ref LL_ADC_CHANNEL_15
2059 * @arg @ref LL_ADC_CHANNEL_16
2060 * @arg @ref LL_ADC_CHANNEL_17
2061 * @arg @ref LL_ADC_CHANNEL_18
2062 * @arg @ref LL_ADC_CHANNEL_VREFINT
2063 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
2064 * @arg @ref LL_ADC_CHANNEL_VBAT
2065 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
2066 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
2067 *
2068 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
2069 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
2070 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
2071 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
2072 * @retval Value between Min_Data=0 and Max_Data=18
2073 */
2074 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
2075 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
2076 ( \
2077 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
2078 ) \
2079 : \
2080 ( \
2081 (uint32_t)POSITION_VAL((__CHANNEL__)) \
2082 ) \
2083 )
2084
2085 /**
2086 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
2087 * from number in decimal format.
2088 * @note Example:
2089 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
2090 * will return a data equivalent to "LL_ADC_CHANNEL_4".
2091 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
2092 * @retval Returned value can be one of the following values:
2093 * @arg @ref LL_ADC_CHANNEL_0 (7)
2094 * @arg @ref LL_ADC_CHANNEL_1 (7)
2095 * @arg @ref LL_ADC_CHANNEL_2 (7)
2096 * @arg @ref LL_ADC_CHANNEL_3 (7)
2097 * @arg @ref LL_ADC_CHANNEL_4 (7)
2098 * @arg @ref LL_ADC_CHANNEL_5 (7)
2099 * @arg @ref LL_ADC_CHANNEL_6
2100 * @arg @ref LL_ADC_CHANNEL_7
2101 * @arg @ref LL_ADC_CHANNEL_8
2102 * @arg @ref LL_ADC_CHANNEL_9
2103 * @arg @ref LL_ADC_CHANNEL_10
2104 * @arg @ref LL_ADC_CHANNEL_11
2105 * @arg @ref LL_ADC_CHANNEL_12
2106 * @arg @ref LL_ADC_CHANNEL_13
2107 * @arg @ref LL_ADC_CHANNEL_14
2108 * @arg @ref LL_ADC_CHANNEL_15
2109 * @arg @ref LL_ADC_CHANNEL_16
2110 * @arg @ref LL_ADC_CHANNEL_17
2111 * @arg @ref LL_ADC_CHANNEL_18
2112 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2113 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
2114 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
2115 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
2116 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
2117 *
2118 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
2119 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
2120 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
2121 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to
2122 * 4.21 Ms/s)).\n
2123 * (1, 2, 3, 4) For ADC channel read back from ADC register,
2124 * comparison with internal channel parameter to be done
2125 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2126 */
2127 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
2128 (((__DECIMAL_NB__) <= 9UL) ? \
2129 ( \
2130 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
2131 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
2132 (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
2133 ) \
2134 : \
2135 ( \
2136 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
2137 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
2138 (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
2139 ) \
2140 )
2141
2142 /**
2143 * @brief Helper macro to determine whether the selected channel
2144 * corresponds to literal definitions of driver.
2145 * @note The different literal definitions of ADC channels are:
2146 * - ADC internal channel:
2147 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
2148 * - ADC external channel (channel connected to a GPIO pin):
2149 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
2150 * @note The channel parameter must be a value defined from literal
2151 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2152 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2153 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
2154 * must not be a value from functions where a channel number is
2155 * returned from ADC registers,
2156 * because internal and external channels share the same channel
2157 * number in ADC registers. The differentiation is made only with
2158 * parameters definitions of driver.
2159 * @param __CHANNEL__ This parameter can be one of the following values:
2160 * @arg @ref LL_ADC_CHANNEL_0
2161 * @arg @ref LL_ADC_CHANNEL_1 (7)
2162 * @arg @ref LL_ADC_CHANNEL_2 (7)
2163 * @arg @ref LL_ADC_CHANNEL_3 (7)
2164 * @arg @ref LL_ADC_CHANNEL_4 (7)
2165 * @arg @ref LL_ADC_CHANNEL_5 (7)
2166 * @arg @ref LL_ADC_CHANNEL_6
2167 * @arg @ref LL_ADC_CHANNEL_7
2168 * @arg @ref LL_ADC_CHANNEL_8
2169 * @arg @ref LL_ADC_CHANNEL_9
2170 * @arg @ref LL_ADC_CHANNEL_10
2171 * @arg @ref LL_ADC_CHANNEL_11
2172 * @arg @ref LL_ADC_CHANNEL_12
2173 * @arg @ref LL_ADC_CHANNEL_13
2174 * @arg @ref LL_ADC_CHANNEL_14
2175 * @arg @ref LL_ADC_CHANNEL_15
2176 * @arg @ref LL_ADC_CHANNEL_16
2177 * @arg @ref LL_ADC_CHANNEL_17
2178 * @arg @ref LL_ADC_CHANNEL_18
2179 * @arg @ref LL_ADC_CHANNEL_VREFINT
2180 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
2181 * @arg @ref LL_ADC_CHANNEL_VBAT
2182 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
2183 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
2184 *
2185 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
2186 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
2187 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
2188 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
2189 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel
2190 connected to a GPIO pin).
2191 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
2192 */
2193 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
2194 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
2195
2196 /**
2197 * @brief Helper macro to convert a channel defined from parameter
2198 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2199 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2200 * to its equivalent parameter definition of a ADC external channel
2201 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
2202 * @note The channel parameter can be, additionally to a value
2203 * defined from parameter definition of a ADC internal channel
2204 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
2205 * a value defined from parameter definition of
2206 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
2207 * or a value from functions where a channel number is returned
2208 * from ADC registers.
2209 * @param __CHANNEL__ This parameter can be one of the following values:
2210 * @arg @ref LL_ADC_CHANNEL_0
2211 * @arg @ref LL_ADC_CHANNEL_1 (7)
2212 * @arg @ref LL_ADC_CHANNEL_2 (7)
2213 * @arg @ref LL_ADC_CHANNEL_3 (7)
2214 * @arg @ref LL_ADC_CHANNEL_4 (7)
2215 * @arg @ref LL_ADC_CHANNEL_5 (7)
2216 * @arg @ref LL_ADC_CHANNEL_6
2217 * @arg @ref LL_ADC_CHANNEL_7
2218 * @arg @ref LL_ADC_CHANNEL_8
2219 * @arg @ref LL_ADC_CHANNEL_9
2220 * @arg @ref LL_ADC_CHANNEL_10
2221 * @arg @ref LL_ADC_CHANNEL_11
2222 * @arg @ref LL_ADC_CHANNEL_12
2223 * @arg @ref LL_ADC_CHANNEL_13
2224 * @arg @ref LL_ADC_CHANNEL_14
2225 * @arg @ref LL_ADC_CHANNEL_15
2226 * @arg @ref LL_ADC_CHANNEL_16
2227 * @arg @ref LL_ADC_CHANNEL_17
2228 * @arg @ref LL_ADC_CHANNEL_18
2229 * @arg @ref LL_ADC_CHANNEL_VREFINT
2230 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
2231 * @arg @ref LL_ADC_CHANNEL_VBAT
2232 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
2233 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
2234 *
2235 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
2236 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
2237 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
2238 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
2239 * @retval Returned value can be one of the following values:
2240 * @arg @ref LL_ADC_CHANNEL_0
2241 * @arg @ref LL_ADC_CHANNEL_1
2242 * @arg @ref LL_ADC_CHANNEL_2
2243 * @arg @ref LL_ADC_CHANNEL_3
2244 * @arg @ref LL_ADC_CHANNEL_4
2245 * @arg @ref LL_ADC_CHANNEL_5
2246 * @arg @ref LL_ADC_CHANNEL_6
2247 * @arg @ref LL_ADC_CHANNEL_7
2248 * @arg @ref LL_ADC_CHANNEL_8
2249 * @arg @ref LL_ADC_CHANNEL_9
2250 * @arg @ref LL_ADC_CHANNEL_10
2251 * @arg @ref LL_ADC_CHANNEL_11
2252 * @arg @ref LL_ADC_CHANNEL_12
2253 * @arg @ref LL_ADC_CHANNEL_13
2254 * @arg @ref LL_ADC_CHANNEL_14
2255 * @arg @ref LL_ADC_CHANNEL_15
2256 * @arg @ref LL_ADC_CHANNEL_16
2257 * @arg @ref LL_ADC_CHANNEL_17
2258 * @arg @ref LL_ADC_CHANNEL_18
2259 */
2260 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
2261 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
2262
2263 /**
2264 * @brief Helper macro to determine whether the internal channel
2265 * selected is available on the ADC instance selected.
2266 * @note The channel parameter must be a value defined from parameter
2267 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
2268 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
2269 * must not be a value defined from parameter definition of
2270 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
2271 * or a value from functions where a channel number is
2272 * returned from ADC registers,
2273 * because internal and external channels share the same channel
2274 * number in ADC registers. The differentiation is made only with
2275 * parameters definitions of driver.
2276 * @param __ADC_INSTANCE__ ADC instance
2277 * @param __CHANNEL__ This parameter can be one of the following values:
2278 * @arg @ref LL_ADC_CHANNEL_VREFINT
2279 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
2280 * @arg @ref LL_ADC_CHANNEL_VBAT
2281 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2
2282 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2
2283 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
2284 * Value "1" if the internal channel selected is available on the ADC instance selected.
2285 */
2286 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
2287 (((__ADC_INSTANCE__) == ADC1) ? \
2288 ( \
2289 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
2290 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
2291 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
2292 ) \
2293 : \
2294 ((__ADC_INSTANCE__) == ADC2) ? \
2295 ( \
2296 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
2297 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
2298 ) \
2299 : \
2300 (0UL) \
2301 )
2302
2303 /**
2304 * @brief Helper macro to define ADC analog watchdog parameter:
2305 * define a single channel to monitor with analog watchdog
2306 * from sequencer channel and groups definition.
2307 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
2308 * Example:
2309 * LL_ADC_SetAnalogWDMonitChannels(
2310 * ADC1, LL_ADC_AWD1,
2311 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
2312 * @param __CHANNEL__ This parameter can be one of the following values:
2313 * @arg @ref LL_ADC_CHANNEL_0 (7)
2314 * @arg @ref LL_ADC_CHANNEL_1 (7)
2315 * @arg @ref LL_ADC_CHANNEL_2 (7)
2316 * @arg @ref LL_ADC_CHANNEL_3 (7)
2317 * @arg @ref LL_ADC_CHANNEL_4 (7)
2318 * @arg @ref LL_ADC_CHANNEL_5 (7)
2319 * @arg @ref LL_ADC_CHANNEL_6
2320 * @arg @ref LL_ADC_CHANNEL_7
2321 * @arg @ref LL_ADC_CHANNEL_8
2322 * @arg @ref LL_ADC_CHANNEL_9
2323 * @arg @ref LL_ADC_CHANNEL_10
2324 * @arg @ref LL_ADC_CHANNEL_11
2325 * @arg @ref LL_ADC_CHANNEL_12
2326 * @arg @ref LL_ADC_CHANNEL_13
2327 * @arg @ref LL_ADC_CHANNEL_14
2328 * @arg @ref LL_ADC_CHANNEL_15
2329 * @arg @ref LL_ADC_CHANNEL_16
2330 * @arg @ref LL_ADC_CHANNEL_17
2331 * @arg @ref LL_ADC_CHANNEL_18
2332 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2333 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
2334 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
2335 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
2336 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
2337 *
2338 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
2339 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
2340 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
2341 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to
2342 * 4.21 Ms/s)).\n
2343 * (1, 2, 3, 4) For ADC channel read back from ADC register,
2344 * comparison with internal channel parameter to be done
2345 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2346 * @param __GROUP__ This parameter can be one of the following values:
2347 * @arg @ref LL_ADC_GROUP_REGULAR
2348 * @arg @ref LL_ADC_GROUP_INJECTED
2349 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
2350 * @retval Returned value can be one of the following values:
2351 * @arg @ref LL_ADC_AWD_DISABLE
2352 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
2353 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
2354 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
2355 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
2356 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
2357 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
2358 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
2359 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
2360 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
2361 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
2362 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
2363 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
2364 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
2365 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
2366 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
2367 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
2368 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
2369 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
2370 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
2371 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
2372 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
2373 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
2374 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
2375 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
2376 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
2377 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
2378 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
2379 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
2380 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
2381 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
2382 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
2383 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
2384 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
2385 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
2386 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
2387 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
2388 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
2389 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
2390 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
2391 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
2392 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
2393 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
2394 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
2395 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
2396 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
2397 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
2398 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
2399 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
2400 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
2401 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
2402 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
2403 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
2404 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
2405 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
2406 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
2407 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
2408 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
2409 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
2410 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
2411 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
2412 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
2413 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)
2414 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
2415 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)
2416 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)
2417 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ
2418 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)
2419 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)
2420 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ
2421 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(1)
2422 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(1)
2423 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (1)
2424 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(1)
2425 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(1)
2426 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (1)
2427 *
2428 * (0) On STM32L5, parameter available only on analog watchdog number: AWD1.\n
2429 * (1) On STM32L5, parameter available only on ADC instance: ADC2.
2430 */
2431 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
2432 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
2433 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2434 : \
2435 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
2436 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
2437 : \
2438 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2439 )
2440
2441 /**
2442 * @brief Helper macro to set the value of ADC analog watchdog threshold high
2443 * or low in function of ADC resolution, when ADC resolution is
2444 * different of 12 bits.
2445 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
2446 * or @ref LL_ADC_SetAnalogWDThresholds().
2447 * Example, with a ADC resolution of 8 bits, to set the value of
2448 * analog watchdog threshold high (on 8 bits):
2449 * LL_ADC_SetAnalogWDThresholds
2450 * (< ADCx param >,
2451 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
2452 * );
2453 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2454 * @arg @ref LL_ADC_RESOLUTION_12B
2455 * @arg @ref LL_ADC_RESOLUTION_10B
2456 * @arg @ref LL_ADC_RESOLUTION_8B
2457 * @arg @ref LL_ADC_RESOLUTION_6B
2458 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
2459 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2460 */
2461 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
2462 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2463
2464 /**
2465 * @brief Helper macro to get the value of ADC analog watchdog threshold high
2466 * or low in function of ADC resolution, when ADC resolution is
2467 * different of 12 bits.
2468 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2469 * Example, with a ADC resolution of 8 bits, to get the value of
2470 * analog watchdog threshold high (on 8 bits):
2471 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
2472 * (LL_ADC_RESOLUTION_8B,
2473 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
2474 * );
2475 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2476 * @arg @ref LL_ADC_RESOLUTION_12B
2477 * @arg @ref LL_ADC_RESOLUTION_10B
2478 * @arg @ref LL_ADC_RESOLUTION_8B
2479 * @arg @ref LL_ADC_RESOLUTION_6B
2480 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
2481 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2482 */
2483 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
2484 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2485
2486 /**
2487 * @brief Helper macro to get the ADC analog watchdog threshold high
2488 * or low from raw value containing both thresholds concatenated.
2489 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2490 * Example, to get analog watchdog threshold high from the register raw value:
2491 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
2492 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
2493 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
2494 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
2495 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2496 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2497 */
2498 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
2499 (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \
2500 & LL_ADC_AWD_THRESHOLD_LOW)
2501
2502 /**
2503 * @brief Helper macro to set the ADC calibration value with both single ended
2504 * and differential modes calibration factors concatenated.
2505 * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
2506 * Example, to set calibration factors single ended to 0x55
2507 * and differential ended to 0x2A:
2508 * LL_ADC_SetCalibrationFactor(
2509 * ADC1,
2510 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
2511 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
2512 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
2513 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2514 */
2515 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
2516 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
2517
2518 #if defined(ADC_MULTIMODE_SUPPORT)
2519 /**
2520 * @brief Helper macro to get the ADC multimode conversion data of ADC master
2521 * or ADC slave from raw value with both ADC conversion data concatenated.
2522 * @note This macro is intended to be used when multimode transfer by DMA
2523 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
2524 * In this case the transferred data need to processed with this macro
2525 * to separate the conversion data of ADC master and ADC slave.
2526 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
2527 * @arg @ref LL_ADC_MULTI_MASTER
2528 * @arg @ref LL_ADC_MULTI_SLAVE
2529 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
2530 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2531 */
2532 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
2533 (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
2534 #endif /* ADC_MULTIMODE_SUPPORT */
2535
2536 #if defined(ADC_MULTIMODE_SUPPORT)
2537 /**
2538 * @brief Helper macro to select, from a ADC instance, to which ADC instance
2539 * it has a dependence in multimode (ADC master of the corresponding
2540 * ADC common instance).
2541 * @note In case of device with multimode available and a mix of
2542 * ADC instances compliant and not compliant with multimode feature,
2543 * ADC instances not compliant with multimode feature are
2544 * considered as master instances (do not depend to
2545 * any other ADC instance).
2546 * @param __ADCx__ ADC instance
2547 * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
2548 */
2549 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2550 ( ( ((__ADCx__) == ADC2) \
2551 )? \
2552 (ADC1) \
2553 : \
2554 (__ADCx__) \
2555 )
2556 #endif /* ADC_MULTIMODE_SUPPORT */
2557
2558 /**
2559 * @brief Helper macro to select the ADC common instance
2560 * to which is belonging the selected ADC instance.
2561 * @note ADC common register instance can be used for:
2562 * - Set parameters common to several ADC instances
2563 * - Multimode (for devices with several ADC instances)
2564 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2565 * @param __ADCx__ ADC instance
2566 * @retval ADC common register instance
2567 */
2568 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
2569 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2570 (ADC123_COMMON)
2571 #elif defined(ADC1) && defined(ADC2)
2572 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2573 (ADC12_COMMON)
2574 #else
2575 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2576 (ADC1_COMMON)
2577 #endif /* defined(ADC1) && defined(ADC2) && defined(ADC3) */
2578
2579 /**
2580 * @brief Helper macro to check if all ADC instances sharing the same
2581 * ADC common instance are disabled.
2582 * @note This check is required by functions with setting conditioned to
2583 * ADC state:
2584 * All ADC instances of the ADC common group must be disabled.
2585 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2586 * @note On devices with only 1 ADC common instance, parameter of this macro
2587 * is useless and can be ignored (parameter kept for compatibility
2588 * with devices featuring several ADC common instances).
2589 * @param __ADCXY_COMMON__ ADC common instance
2590 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2591 * @retval Value "0" if all ADC instances sharing the same ADC common instance
2592 * are disabled.
2593 * Value "1" if at least one ADC instance sharing the same ADC common instance
2594 * is enabled.
2595 */
2596 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
2597 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2598 (LL_ADC_IsEnabled(ADC1) | \
2599 LL_ADC_IsEnabled(ADC2) | \
2600 LL_ADC_IsEnabled(ADC3) )
2601 #elif defined(ADC1) && defined(ADC2)
2602 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2603 (LL_ADC_IsEnabled(ADC1) | \
2604 LL_ADC_IsEnabled(ADC2) )
2605 #else
2606 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2607 (LL_ADC_IsEnabled(ADC1))
2608 #endif /* defined(ADC1) && defined(ADC2) && defined(ADC3) */
2609
2610 /**
2611 * @brief Helper macro to define the ADC conversion data full-scale digital
2612 * value corresponding to the selected ADC resolution.
2613 * @note ADC conversion data full-scale corresponds to voltage range
2614 * determined by analog voltage references Vref+ and Vref-
2615 * (refer to reference manual).
2616 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2617 * @arg @ref LL_ADC_RESOLUTION_12B
2618 * @arg @ref LL_ADC_RESOLUTION_10B
2619 * @arg @ref LL_ADC_RESOLUTION_8B
2620 * @arg @ref LL_ADC_RESOLUTION_6B
2621 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
2622 */
2623 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2624 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
2625
2626 /**
2627 * @brief Helper macro to convert the ADC conversion data from
2628 * a resolution to another resolution.
2629 * @param __DATA__ ADC conversion data to be converted
2630 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
2631 * This parameter can be one of the following values:
2632 * @arg @ref LL_ADC_RESOLUTION_12B
2633 * @arg @ref LL_ADC_RESOLUTION_10B
2634 * @arg @ref LL_ADC_RESOLUTION_8B
2635 * @arg @ref LL_ADC_RESOLUTION_6B
2636 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
2637 * This parameter can be one of the following values:
2638 * @arg @ref LL_ADC_RESOLUTION_12B
2639 * @arg @ref LL_ADC_RESOLUTION_10B
2640 * @arg @ref LL_ADC_RESOLUTION_8B
2641 * @arg @ref LL_ADC_RESOLUTION_6B
2642 * @retval ADC conversion data to the requested resolution
2643 */
2644 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2645 __ADC_RESOLUTION_CURRENT__,\
2646 __ADC_RESOLUTION_TARGET__) \
2647 (((__DATA__) \
2648 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2649 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2650 )
2651
2652 /**
2653 * @brief Helper macro to calculate the voltage (unit: mVolt)
2654 * corresponding to a ADC conversion data (unit: digital value).
2655 * @note Analog reference voltage (Vref+) must be either known from
2656 * user board environment or can be calculated using ADC measurement
2657 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2658 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2659 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
2660 * (unit: digital value).
2661 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2662 * @arg @ref LL_ADC_RESOLUTION_12B
2663 * @arg @ref LL_ADC_RESOLUTION_10B
2664 * @arg @ref LL_ADC_RESOLUTION_8B
2665 * @arg @ref LL_ADC_RESOLUTION_6B
2666 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2667 */
2668 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2669 __ADC_DATA__,\
2670 __ADC_RESOLUTION__) \
2671 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
2672 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2673 )
2674
2675 /**
2676 * @brief Helper macro to calculate analog reference voltage (Vref+)
2677 * (unit: mVolt) from ADC conversion data of internal voltage
2678 * reference VrefInt.
2679 * @note Computation is using VrefInt calibration value
2680 * stored in system memory for each device during production.
2681 * @note This voltage depends on user board environment: voltage level
2682 * connected to pin Vref+.
2683 * On devices with small package, the pin Vref+ is not present
2684 * and internally bonded to pin Vdda.
2685 * @note On this STM32 series, calibration data of internal voltage reference
2686 * VrefInt corresponds to a resolution of 12 bits,
2687 * this is the recommended ADC resolution to convert voltage of
2688 * internal voltage reference VrefInt.
2689 * Otherwise, this macro performs the processing to scale
2690 * ADC conversion data to 12 bits.
2691 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
2692 * of internal voltage reference VrefInt (unit: digital value).
2693 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2694 * @arg @ref LL_ADC_RESOLUTION_12B
2695 * @arg @ref LL_ADC_RESOLUTION_10B
2696 * @arg @ref LL_ADC_RESOLUTION_8B
2697 * @arg @ref LL_ADC_RESOLUTION_6B
2698 * @retval Analog reference voltage (unit: mV)
2699 */
2700 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
2701 __ADC_RESOLUTION__) \
2702 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2703 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
2704 (__ADC_RESOLUTION__), \
2705 LL_ADC_RESOLUTION_12B) \
2706 )
2707
2708 /**
2709 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2710 * from ADC conversion data of internal temperature sensor.
2711 * @note Computation is using temperature sensor calibration values
2712 * stored in system memory for each device during production.
2713 * @note Calculation formula:
2714 * Temperature = ((TS_ADC_DATA - TS_CAL1)
2715 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
2716 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
2717 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2718 * Avg_Slope = (TS_CAL2 - TS_CAL1)
2719 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
2720 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
2721 * TEMP_DEGC_CAL1 (calibrated in factory)
2722 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
2723 * TEMP_DEGC_CAL2 (calibrated in factory)
2724 * Caution: Calculation relevancy under reserve that calibration
2725 * parameters are correct (address and data).
2726 * To calculate temperature using temperature sensor
2727 * datasheet typical values (generic values less, therefore
2728 * less accurate than calibrated values),
2729 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
2730 * @note As calculation input, the analog reference voltage (Vref+) must be
2731 * defined as it impacts the ADC LSB equivalent voltage.
2732 * @note Analog reference voltage (Vref+) must be either known from
2733 * user board environment or can be calculated using ADC measurement
2734 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2735 * @note On this STM32 series, calibration data of temperature sensor
2736 * corresponds to a resolution of 12 bits,
2737 * this is the recommended ADC resolution to convert voltage of
2738 * temperature sensor.
2739 * Otherwise, this macro performs the processing to scale
2740 * ADC conversion data to 12 bits.
2741 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2742 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
2743 * temperature sensor (unit: digital value).
2744 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
2745 * sensor voltage has been measured.
2746 * This parameter can be one of the following values:
2747 * @arg @ref LL_ADC_RESOLUTION_12B
2748 * @arg @ref LL_ADC_RESOLUTION_10B
2749 * @arg @ref LL_ADC_RESOLUTION_8B
2750 * @arg @ref LL_ADC_RESOLUTION_6B
2751 * @retval Temperature (unit: degree Celsius)
2752 * In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value)
2753 */
2754 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
2755 __TEMPSENSOR_ADC_DATA__,\
2756 __ADC_RESOLUTION__)\
2757 ((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ? \
2758 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
2759 (__ADC_RESOLUTION__), \
2760 LL_ADC_RESOLUTION_12B) \
2761 * (__VREFANALOG_VOLTAGE__)) \
2762 / TEMPSENSOR_CAL_VREFANALOG) \
2763 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2764 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2765 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2766 ) + TEMPSENSOR_CAL1_TEMP \
2767 ) \
2768 : \
2769 ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR) \
2770 )
2771
2772 /**
2773 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2774 * from ADC conversion data of internal temperature sensor.
2775 * @note Computation is using temperature sensor typical values
2776 * (refer to device datasheet).
2777 * @note Calculation formula:
2778 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
2779 * / Avg_Slope + CALx_TEMP
2780 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2781 * (unit: digital value)
2782 * Avg_Slope = temperature sensor slope
2783 * (unit: uV/Degree Celsius)
2784 * TS_TYP_CALx_VOLT = temperature sensor digital value at
2785 * temperature CALx_TEMP (unit: mV)
2786 * Caution: Calculation relevancy under reserve the temperature sensor
2787 * of the current device has characteristics in line with
2788 * datasheet typical values.
2789 * If temperature sensor calibration values are available on
2790 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
2791 * temperature calculation will be more accurate using
2792 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
2793 * @note As calculation input, the analog reference voltage (Vref+) must be
2794 * defined as it impacts the ADC LSB equivalent voltage.
2795 * @note Analog reference voltage (Vref+) must be either known from
2796 * user board environment or can be calculated using ADC measurement
2797 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2798 * @note ADC measurement data must correspond to a resolution of 12 bits
2799 * (full scale digital value 4095). If not the case, the data must be
2800 * preliminarily rescaled to an equivalent resolution of 12 bits.
2801 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
2802 * (unit: uV/DegCelsius).
2803 * On STM32L5, refer to device datasheet parameter "Avg_Slope".
2804 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value
2805 * (at temperature and Vref+ defined in parameters below) (unit: mV).
2806 * On STM32L5, refer to datasheet parameter "V30" (corresponding to TS_CAL1).
2807 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage
2808 * (see parameter above) is corresponding (unit: mV)
2809 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV)
2810 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
2811 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
2812 * This parameter can be one of the following values:
2813 * @arg @ref LL_ADC_RESOLUTION_12B
2814 * @arg @ref LL_ADC_RESOLUTION_10B
2815 * @arg @ref LL_ADC_RESOLUTION_8B
2816 * @arg @ref LL_ADC_RESOLUTION_6B
2817 * @retval Temperature (unit: degree Celsius)
2818 */
2819 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
2820 __TEMPSENSOR_TYP_CALX_V__,\
2821 __TEMPSENSOR_CALX_TEMP__,\
2822 __VREFANALOG_VOLTAGE__,\
2823 __TEMPSENSOR_ADC_DATA__,\
2824 __ADC_RESOLUTION__) \
2825 (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2826 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
2827 * 1000UL) \
2828 - \
2829 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2830 * 1000UL) \
2831 ) \
2832 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
2833 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
2834 )
2835
2836 /**
2837 * @}
2838 */
2839
2840 /**
2841 * @}
2842 */
2843
2844
2845 /* Exported functions --------------------------------------------------------*/
2846 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
2847 * @{
2848 */
2849
2850 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
2851 * @{
2852 */
2853 /* Note: LL ADC functions to set DMA transfer are located into sections of */
2854 /* configuration of ADC instance, groups and multimode (if available): */
2855 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
2856
2857 /**
2858 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2859 * ADC register address from ADC instance and a list of ADC registers
2860 * intended to be used (most commonly) with DMA transfer.
2861 * @note These ADC registers are data registers:
2862 * when ADC conversion data is available in ADC data registers,
2863 * ADC generates a DMA transfer request.
2864 * @note This macro is intended to be used with LL DMA driver, refer to
2865 * function "LL_DMA_ConfigAddresses()".
2866 * Example:
2867 * LL_DMA_ConfigAddresses(DMA1,
2868 * LL_DMA_CHANNEL_1,
2869 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2870 * (uint32_t)&< array or variable >,
2871 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
2872 * @note For devices with several ADC: in multimode, some devices
2873 * use a different data register outside of ADC instance scope
2874 * (common data register). This macro manages this register difference,
2875 * only ADC instance has to be set as parameter.
2876 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
2877 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
2878 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
2879 * @param ADCx ADC instance
2880 * @param Register This parameter can be one of the following values:
2881 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
2882 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
2883 *
2884 * (1) Available on devices with several ADC instances.
2885 * @retval ADC register address
2886 */
2887 #if defined(ADC_MULTIMODE_SUPPORT)
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t Register)2888 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
2889 {
2890 uint32_t data_reg_addr;
2891
2892 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
2893 {
2894 /* Retrieve address of register DR */
2895 data_reg_addr = (uint32_t) &(ADCx->DR);
2896 }
2897 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
2898 {
2899 /* Retrieve address of register CDR */
2900 data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
2901 }
2902
2903 return data_reg_addr;
2904 }
2905 #else
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t Register)2906 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
2907 {
2908 /* Prevent unused argument(s) compilation warning */
2909 (void)(Register);
2910
2911 /* Retrieve address of register DR */
2912 return (uint32_t) &(ADCx->DR);
2913 }
2914 #endif /* ADC_MULTIMODE_SUPPORT */
2915
2916 /**
2917 * @}
2918 */
2919
2920 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several
2921 * ADC instances
2922 * @{
2923 */
2924
2925 /**
2926 * @brief Set parameter common to several ADC: Clock source and prescaler.
2927 * @note On this STM32 series, if ADC group injected is used, some
2928 * clock ratio constraints between ADC clock and AHB clock
2929 * must be respected.
2930 * Refer to reference manual.
2931 * @note On this STM32 series, setting of this feature is conditioned to
2932 * ADC state:
2933 * All ADC instances of the ADC common group must be disabled.
2934 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2935 * ADC instance or by using helper macro helper macro
2936 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2937 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
2938 * CCR PRESC LL_ADC_SetCommonClock
2939 * @param ADCxy_COMMON ADC common instance
2940 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2941 * @param CommonClock This parameter can be one of the following values:
2942 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2943 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2944 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2945 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2946 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2947 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2948 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2949 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2950 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2951 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2952 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2953 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2954 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2955 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2956 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2957 * @retval None
2958 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)2959 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
2960 {
2961 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
2962 }
2963
2964 /**
2965 * @brief Get parameter common to several ADC: Clock source and prescaler.
2966 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
2967 * CCR PRESC LL_ADC_GetCommonClock
2968 * @param ADCxy_COMMON ADC common instance
2969 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2970 * @retval Returned value can be one of the following values:
2971 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2972 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2973 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2974 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2975 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2976 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2977 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2978 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2979 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2980 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2981 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2982 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2983 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2984 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2985 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2986 */
LL_ADC_GetCommonClock(const ADC_Common_TypeDef * ADCxy_COMMON)2987 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
2988 {
2989 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
2990 }
2991
2992 /**
2993 * @brief Set parameter common to several ADC: measurement path to
2994 * internal channels (VrefInt, temperature sensor, ...).
2995 * Configure all paths (overwrite current configuration).
2996 * @note One or several values can be selected.
2997 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2998 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2999 * The values not selected are removed from configuration.
3000 * @note Stabilization time of measurement path to internal channel:
3001 * After enabling internal paths, before starting ADC conversion,
3002 * a delay is required for internal voltage reference and
3003 * temperature sensor stabilization time.
3004 * Refer to device datasheet.
3005 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
3006 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
3007 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
3008 * @note ADC internal channel sampling time constraint:
3009 * For ADC conversion of internal channels,
3010 * a sampling time minimum value is required.
3011 * Refer to device datasheet.
3012 * @note On this STM32 series, setting of this feature is conditioned to
3013 * ADC state:
3014 * All ADC instances of the ADC common group must be disabled.
3015 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3016 * ADC instance or by using helper macro helper macro
3017 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
3018 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
3019 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
3020 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
3021 * @param ADCxy_COMMON ADC common instance
3022 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3023 * @param PathInternal This parameter can be a combination of the following values:
3024 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3025 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3026 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3027 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3028 * @retval None
3029 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3030 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3031 {
3032 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
3033 }
3034
3035 /**
3036 * @brief Set parameter common to several ADC: measurement path to
3037 * internal channels (VrefInt, temperature sensor, ...).
3038 * Add paths to the current configuration.
3039 * @note One or several values can be selected.
3040 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3041 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3042 * @note Stabilization time of measurement path to internal channel:
3043 * After enabling internal paths, before starting ADC conversion,
3044 * a delay is required for internal voltage reference and
3045 * temperature sensor stabilization time.
3046 * Refer to device datasheet.
3047 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
3048 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
3049 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
3050 * @note ADC internal channel sampling time constraint:
3051 * For ADC conversion of internal channels,
3052 * a sampling time minimum value is required.
3053 * Refer to device datasheet.
3054 * @note On this STM32 series, setting of this feature is conditioned to
3055 * ADC state:
3056 * All ADC instances of the ADC common group must be disabled.
3057 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3058 * ADC instance or by using helper macro helper macro
3059 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
3060 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
3061 * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n
3062 * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
3063 * @param ADCxy_COMMON ADC common instance
3064 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3065 * @param PathInternal This parameter can be a combination of the following values:
3066 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3067 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3068 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3069 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3070 * @retval None
3071 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3072 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3073 {
3074 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
3075 }
3076
3077 /**
3078 * @brief Set parameter common to several ADC: measurement path to
3079 * internal channels (VrefInt, temperature sensor, ...).
3080 * Remove paths to the current configuration.
3081 * @note One or several values can be selected.
3082 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3083 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3084 * @note On this STM32 series, setting of this feature is conditioned to
3085 * ADC state:
3086 * All ADC instances of the ADC common group must be disabled.
3087 * This check can be done with function @ref LL_ADC_IsEnabled() for each
3088 * ADC instance or by using helper macro helper macro
3089 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
3090 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
3091 * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n
3092 * CCR VBATEN LL_ADC_SetCommonPathInternalChRem
3093 * @param ADCxy_COMMON ADC common instance
3094 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3095 * @param PathInternal This parameter can be a combination of the following values:
3096 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3097 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3098 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3099 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3100 * @retval None
3101 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)3102 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
3103 {
3104 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
3105 }
3106
3107 /**
3108 * @brief Get parameter common to several ADC: measurement path to internal
3109 * channels (VrefInt, temperature sensor, ...).
3110 * @note One or several values can be selected.
3111 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
3112 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
3113 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
3114 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
3115 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
3116 * @param ADCxy_COMMON ADC common instance
3117 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3118 * @retval Returned value can be a combination of the following values:
3119 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
3120 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
3121 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
3122 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
3123 */
LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef * ADCxy_COMMON)3124 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
3125 {
3126 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
3127 }
3128
3129 /**
3130 * @}
3131 */
3132
3133 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
3134 * @{
3135 */
3136
3137 /**
3138 * @brief Set ADC calibration factor in the mode single-ended
3139 * or differential (for devices with differential mode available).
3140 * @note This function is intended to set calibration parameters
3141 * without having to perform a new calibration using
3142 * @ref LL_ADC_StartCalibration().
3143 * @note For devices with differential mode available:
3144 * Calibration of offset is specific to each of
3145 * single-ended and differential modes
3146 * (calibration factor must be specified for each of these
3147 * differential modes, if used afterwards and if the application
3148 * requires their calibration).
3149 * @note In case of setting calibration factors of both modes single ended
3150 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
3151 * both calibration factors must be concatenated.
3152 * To perform this processing, use helper macro
3153 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
3154 * @note On this STM32 series, setting of this feature is conditioned to
3155 * ADC state:
3156 * ADC must be enabled, without calibration on going, without conversion
3157 * on going on group regular.
3158 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
3159 * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
3160 * @param ADCx ADC instance
3161 * @param SingleDiff This parameter can be one of the following values:
3162 * @arg @ref LL_ADC_SINGLE_ENDED
3163 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
3164 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
3165 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
3166 * @retval None
3167 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff,uint32_t CalibrationFactor)3168 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
3169 {
3170 MODIFY_REG(ADCx->CALFACT,
3171 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
3172 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK)
3173 >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)
3174 & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
3175 }
3176
3177 /**
3178 * @brief Get ADC calibration factor in the mode single-ended
3179 * or differential (for devices with differential mode available).
3180 * @note Calibration factors are set by hardware after performing
3181 * a calibration run using function @ref LL_ADC_StartCalibration().
3182 * @note For devices with differential mode available:
3183 * Calibration of offset is specific to each of
3184 * single-ended and differential modes
3185 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
3186 * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
3187 * @param ADCx ADC instance
3188 * @param SingleDiff This parameter can be one of the following values:
3189 * @arg @ref LL_ADC_SINGLE_ENDED
3190 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
3191 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
3192 */
LL_ADC_GetCalibrationFactor(const ADC_TypeDef * ADCx,uint32_t SingleDiff)3193 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx, uint32_t SingleDiff)
3194 {
3195 /* Retrieve bits with position in register depending on parameter */
3196 /* "SingleDiff". */
3197 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
3198 /* containing other bits reserved for other purpose. */
3199 return (uint32_t)(READ_BIT(ADCx->CALFACT,
3200 (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK))
3201 >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
3202 ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
3203 }
3204
3205 /**
3206 * @brief Set ADC resolution.
3207 * Refer to reference manual for alignments formats
3208 * dependencies to ADC resolutions.
3209 * @note On this STM32 series, setting of this feature is conditioned to
3210 * ADC state:
3211 * ADC must be disabled or enabled without conversion on going
3212 * on either groups regular or injected.
3213 * @rmtoll CFGR RES LL_ADC_SetResolution
3214 * @param ADCx ADC instance
3215 * @param Resolution This parameter can be one of the following values:
3216 * @arg @ref LL_ADC_RESOLUTION_12B
3217 * @arg @ref LL_ADC_RESOLUTION_10B
3218 * @arg @ref LL_ADC_RESOLUTION_8B
3219 * @arg @ref LL_ADC_RESOLUTION_6B
3220 * @retval None
3221 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)3222 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
3223 {
3224 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
3225 }
3226
3227 /**
3228 * @brief Get ADC resolution.
3229 * Refer to reference manual for alignments formats
3230 * dependencies to ADC resolutions.
3231 * @rmtoll CFGR RES LL_ADC_GetResolution
3232 * @param ADCx ADC instance
3233 * @retval Returned value can be one of the following values:
3234 * @arg @ref LL_ADC_RESOLUTION_12B
3235 * @arg @ref LL_ADC_RESOLUTION_10B
3236 * @arg @ref LL_ADC_RESOLUTION_8B
3237 * @arg @ref LL_ADC_RESOLUTION_6B
3238 */
LL_ADC_GetResolution(const ADC_TypeDef * ADCx)3239 __STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
3240 {
3241 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
3242 }
3243
3244 /**
3245 * @brief Set ADC conversion data alignment.
3246 * @note Refer to reference manual for alignments formats
3247 * dependencies to ADC resolutions.
3248 * @note On this STM32 series, setting of this feature is conditioned to
3249 * ADC state:
3250 * ADC must be disabled or enabled without conversion on going
3251 * on either groups regular or injected.
3252 * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
3253 * @param ADCx ADC instance
3254 * @param DataAlignment This parameter can be one of the following values:
3255 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
3256 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
3257 * @retval None
3258 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)3259 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
3260 {
3261 MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
3262 }
3263
3264 /**
3265 * @brief Get ADC conversion data alignment.
3266 * @note Refer to reference manual for alignments formats
3267 * dependencies to ADC resolutions.
3268 * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
3269 * @param ADCx ADC instance
3270 * @retval Returned value can be one of the following values:
3271 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
3272 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
3273 */
LL_ADC_GetDataAlignment(const ADC_TypeDef * ADCx)3274 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx)
3275 {
3276 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
3277 }
3278
3279 /**
3280 * @brief Set ADC low power mode.
3281 * @note Description of ADC low power modes:
3282 * - ADC low power mode "auto wait": Dynamic low power mode,
3283 * ADC conversions occurrences are limited to the minimum necessary
3284 * in order to reduce power consumption.
3285 * New ADC conversion starts only when the previous
3286 * unitary conversion data (for ADC group regular)
3287 * or previous sequence conversions data (for ADC group injected)
3288 * has been retrieved by user software.
3289 * In the meantime, ADC remains idle: does not performs any
3290 * other conversion.
3291 * This mode allows to automatically adapt the ADC conversions
3292 * triggers to the speed of the software that reads the data.
3293 * Moreover, this avoids risk of overrun for low frequency
3294 * applications.
3295 * How to use this low power mode:
3296 * - It is not recommended to use with interruption or DMA
3297 * since these modes have to clear immediately the EOC flag
3298 * (by CPU to free the IRQ pending event or by DMA).
3299 * Auto wait will work but fort a very short time, discarding
3300 * its intended benefit (except specific case of high load of CPU
3301 * or DMA transfers which can justify usage of auto wait).
3302 * - Do use with polling: 1. Start conversion,
3303 * 2. Later on, when conversion data is needed: poll for end of
3304 * conversion to ensure that conversion is completed and
3305 * retrieve ADC conversion data. This will trig another
3306 * ADC conversion start.
3307 * @note With ADC low power mode "auto wait", the ADC conversion data read
3308 * is corresponding to previous ADC conversion start, independently
3309 * of delay during which ADC was idle.
3310 * Therefore, the ADC conversion data may be outdated: does not
3311 * correspond to the current voltage level on the selected
3312 * ADC channel.
3313 * @note On this STM32 series, setting of this feature is conditioned to
3314 * ADC state:
3315 * ADC must be disabled or enabled without conversion on going
3316 * on either groups regular or injected.
3317 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
3318 * @param ADCx ADC instance
3319 * @param LowPowerMode This parameter can be one of the following values:
3320 * @arg @ref LL_ADC_LP_MODE_NONE
3321 * @arg @ref LL_ADC_LP_AUTOWAIT
3322 * @retval None
3323 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)3324 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
3325 {
3326 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
3327 }
3328
3329 /**
3330 * @brief Get ADC low power mode:
3331 * @note Description of ADC low power modes:
3332 * - ADC low power mode "auto wait": Dynamic low power mode,
3333 * ADC conversions occurrences are limited to the minimum necessary
3334 * in order to reduce power consumption.
3335 * New ADC conversion starts only when the previous
3336 * unitary conversion data (for ADC group regular)
3337 * or previous sequence conversions data (for ADC group injected)
3338 * has been retrieved by user software.
3339 * In the meantime, ADC remains idle: does not performs any
3340 * other conversion.
3341 * This mode allows to automatically adapt the ADC conversions
3342 * triggers to the speed of the software that reads the data.
3343 * Moreover, this avoids risk of overrun for low frequency
3344 * applications.
3345 * How to use this low power mode:
3346 * - It is not recommended to use with interruption or DMA
3347 * since these modes have to clear immediately the EOC flag
3348 * (by CPU to free the IRQ pending event or by DMA).
3349 * Auto wait will work but fort a very short time, discarding
3350 * its intended benefit (except specific case of high load of CPU
3351 * or DMA transfers which can justify usage of auto wait).
3352 * - Do use with polling: 1. Start conversion,
3353 * 2. Later on, when conversion data is needed: poll for end of
3354 * conversion to ensure that conversion is completed and
3355 * retrieve ADC conversion data. This will trig another
3356 * ADC conversion start.
3357 * @note With ADC low power mode "auto wait", the ADC conversion data read
3358 * is corresponding to previous ADC conversion start, independently
3359 * of delay during which ADC was idle.
3360 * Therefore, the ADC conversion data may be outdated: does not
3361 * correspond to the current voltage level on the selected
3362 * ADC channel.
3363 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
3364 * @param ADCx ADC instance
3365 * @retval Returned value can be one of the following values:
3366 * @arg @ref LL_ADC_LP_MODE_NONE
3367 * @arg @ref LL_ADC_LP_AUTOWAIT
3368 */
LL_ADC_GetLowPowerMode(const ADC_TypeDef * ADCx)3369 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx)
3370 {
3371 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
3372 }
3373
3374 /**
3375 * @brief Set ADC selected offset instance 1, 2, 3 or 4.
3376 * @note This function set the 2 items of offset configuration:
3377 * - ADC channel to which the offset programmed will be applied
3378 * (independently of channel mapped on ADC group regular
3379 * or group injected)
3380 * - Offset level (offset to be subtracted from the raw
3381 * converted data).
3382 * @note Caution: Offset format is dependent to ADC resolution:
3383 * offset has to be left-aligned on bit 11, the LSB (right bits)
3384 * are set to 0.
3385 * @note This function enables the offset, by default. It can be forced
3386 * to disable state using function LL_ADC_SetOffsetState().
3387 * @note If a channel is mapped on several offsets numbers, only the offset
3388 * with the lowest value is considered for the subtraction.
3389 * @note On this STM32 series, setting of this feature is conditioned to
3390 * ADC state:
3391 * ADC must be disabled or enabled without conversion on going
3392 * on either groups regular or injected.
3393 * @note On STM32L5, some fast channels are available: fast analog inputs
3394 * coming from GPIO pads (ADC_IN0..5).
3395 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
3396 * OFR1 OFFSET1 LL_ADC_SetOffset\n
3397 * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
3398 * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
3399 * OFR2 OFFSET2 LL_ADC_SetOffset\n
3400 * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
3401 * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
3402 * OFR3 OFFSET3 LL_ADC_SetOffset\n
3403 * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
3404 * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
3405 * OFR4 OFFSET4 LL_ADC_SetOffset\n
3406 * OFR4 OFFSET4_EN LL_ADC_SetOffset
3407 * @param ADCx ADC instance
3408 * @param Offsety This parameter can be one of the following values:
3409 * @arg @ref LL_ADC_OFFSET_1
3410 * @arg @ref LL_ADC_OFFSET_2
3411 * @arg @ref LL_ADC_OFFSET_3
3412 * @arg @ref LL_ADC_OFFSET_4
3413 * @param Channel This parameter can be one of the following values:
3414 * @arg @ref LL_ADC_CHANNEL_0
3415 * @arg @ref LL_ADC_CHANNEL_1 (7)
3416 * @arg @ref LL_ADC_CHANNEL_2 (7)
3417 * @arg @ref LL_ADC_CHANNEL_3 (7)
3418 * @arg @ref LL_ADC_CHANNEL_4 (7)
3419 * @arg @ref LL_ADC_CHANNEL_5 (7)
3420 * @arg @ref LL_ADC_CHANNEL_6
3421 * @arg @ref LL_ADC_CHANNEL_7
3422 * @arg @ref LL_ADC_CHANNEL_8
3423 * @arg @ref LL_ADC_CHANNEL_9
3424 * @arg @ref LL_ADC_CHANNEL_10
3425 * @arg @ref LL_ADC_CHANNEL_11
3426 * @arg @ref LL_ADC_CHANNEL_12
3427 * @arg @ref LL_ADC_CHANNEL_13
3428 * @arg @ref LL_ADC_CHANNEL_14
3429 * @arg @ref LL_ADC_CHANNEL_15
3430 * @arg @ref LL_ADC_CHANNEL_16
3431 * @arg @ref LL_ADC_CHANNEL_17
3432 * @arg @ref LL_ADC_CHANNEL_18
3433 * @arg @ref LL_ADC_CHANNEL_VREFINT
3434 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3435 * @arg @ref LL_ADC_CHANNEL_VBAT
3436 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
3437 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
3438 *
3439 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
3440 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
3441 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
3442 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
3443 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
3444 * @retval None
3445 */
LL_ADC_SetOffset(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t Channel,uint32_t OffsetLevel)3446 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
3447 {
3448 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3449
3450 MODIFY_REG(*preg,
3451 ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
3452 ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
3453 }
3454
3455 /**
3456 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
3457 * Channel to which the offset programmed will be applied
3458 * (independently of channel mapped on ADC group regular
3459 * or group injected)
3460 * @note Usage of the returned channel number:
3461 * - To reinject this channel into another function LL_ADC_xxx:
3462 * the returned channel number is only partly formatted on definition
3463 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3464 * with parts of literals LL_ADC_CHANNEL_x or using
3465 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3466 * Then the selected literal LL_ADC_CHANNEL_x can be used
3467 * as parameter for another function.
3468 * - To get the channel number in decimal format:
3469 * process the returned value with the helper macro
3470 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3471 * @note On STM32L5, some fast channels are available: fast analog inputs
3472 * coming from GPIO pads (ADC_IN0..5).
3473 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
3474 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
3475 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
3476 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
3477 * @param ADCx ADC instance
3478 * @param Offsety This parameter can be one of the following values:
3479 * @arg @ref LL_ADC_OFFSET_1
3480 * @arg @ref LL_ADC_OFFSET_2
3481 * @arg @ref LL_ADC_OFFSET_3
3482 * @arg @ref LL_ADC_OFFSET_4
3483 * @retval Returned value can be one of the following values:
3484 * @arg @ref LL_ADC_CHANNEL_0 (7)
3485 * @arg @ref LL_ADC_CHANNEL_1 (7)
3486 * @arg @ref LL_ADC_CHANNEL_2 (7)
3487 * @arg @ref LL_ADC_CHANNEL_3 (7)
3488 * @arg @ref LL_ADC_CHANNEL_4 (7)
3489 * @arg @ref LL_ADC_CHANNEL_5 (7)
3490 * @arg @ref LL_ADC_CHANNEL_6
3491 * @arg @ref LL_ADC_CHANNEL_7
3492 * @arg @ref LL_ADC_CHANNEL_8
3493 * @arg @ref LL_ADC_CHANNEL_9
3494 * @arg @ref LL_ADC_CHANNEL_10
3495 * @arg @ref LL_ADC_CHANNEL_11
3496 * @arg @ref LL_ADC_CHANNEL_12
3497 * @arg @ref LL_ADC_CHANNEL_13
3498 * @arg @ref LL_ADC_CHANNEL_14
3499 * @arg @ref LL_ADC_CHANNEL_15
3500 * @arg @ref LL_ADC_CHANNEL_16
3501 * @arg @ref LL_ADC_CHANNEL_17
3502 * @arg @ref LL_ADC_CHANNEL_18
3503 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3504 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
3505 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
3506 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
3507 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
3508 *
3509 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
3510 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
3511 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
3512 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to
3513 * 4.21 Ms/s)).\n
3514 * (1, 2, 3, 4) For ADC channel read back from ADC register,
3515 * comparison with internal channel parameter to be done
3516 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3517 */
LL_ADC_GetOffsetChannel(const ADC_TypeDef * ADCx,uint32_t Offsety)3518 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
3519 {
3520 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3521
3522 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
3523 }
3524
3525 /**
3526 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
3527 * Offset level (offset to be subtracted from the raw
3528 * converted data).
3529 * @note Caution: Offset format is dependent to ADC resolution:
3530 * offset has to be left-aligned on bit 11, the LSB (right bits)
3531 * are set to 0.
3532 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
3533 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
3534 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
3535 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
3536 * @param ADCx ADC instance
3537 * @param Offsety This parameter can be one of the following values:
3538 * @arg @ref LL_ADC_OFFSET_1
3539 * @arg @ref LL_ADC_OFFSET_2
3540 * @arg @ref LL_ADC_OFFSET_3
3541 * @arg @ref LL_ADC_OFFSET_4
3542 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3543 */
LL_ADC_GetOffsetLevel(const ADC_TypeDef * ADCx,uint32_t Offsety)3544 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety)
3545 {
3546 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3547
3548 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
3549 }
3550
3551 /**
3552 * @brief Set for the ADC selected offset instance 1, 2, 3 or 4:
3553 * force offset state disable or enable
3554 * without modifying offset channel or offset value.
3555 * @note This function should be needed only in case of offset to be
3556 * enabled-disabled dynamically, and should not be needed in other cases:
3557 * function LL_ADC_SetOffset() automatically enables the offset.
3558 * @note On this STM32 series, setting of this feature is conditioned to
3559 * ADC state:
3560 * ADC must be disabled or enabled without conversion on going
3561 * on either groups regular or injected.
3562 * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
3563 * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
3564 * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
3565 * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
3566 * @param ADCx ADC instance
3567 * @param Offsety This parameter can be one of the following values:
3568 * @arg @ref LL_ADC_OFFSET_1
3569 * @arg @ref LL_ADC_OFFSET_2
3570 * @arg @ref LL_ADC_OFFSET_3
3571 * @arg @ref LL_ADC_OFFSET_4
3572 * @param OffsetState This parameter can be one of the following values:
3573 * @arg @ref LL_ADC_OFFSET_DISABLE
3574 * @arg @ref LL_ADC_OFFSET_ENABLE
3575 * @retval None
3576 */
LL_ADC_SetOffsetState(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetState)3577 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
3578 {
3579 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3580
3581 MODIFY_REG(*preg,
3582 ADC_OFR1_OFFSET1_EN,
3583 OffsetState);
3584 }
3585
3586 /**
3587 * @brief Get for the ADC selected offset instance 1, 2, 3 or 4:
3588 * offset state disabled or enabled.
3589 * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
3590 * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
3591 * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
3592 * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
3593 * @param ADCx ADC instance
3594 * @param Offsety This parameter can be one of the following values:
3595 * @arg @ref LL_ADC_OFFSET_1
3596 * @arg @ref LL_ADC_OFFSET_2
3597 * @arg @ref LL_ADC_OFFSET_3
3598 * @arg @ref LL_ADC_OFFSET_4
3599 * @retval Returned value can be one of the following values:
3600 * @arg @ref LL_ADC_OFFSET_DISABLE
3601 * @arg @ref LL_ADC_OFFSET_ENABLE
3602 */
LL_ADC_GetOffsetState(const ADC_TypeDef * ADCx,uint32_t Offsety)3603 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(const ADC_TypeDef *ADCx, uint32_t Offsety)
3604 {
3605 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3606
3607 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
3608 }
3609
3610 #if defined(ADC_SMPR1_SMPPLUS)
3611 /**
3612 * @brief Set ADC sampling time common configuration impacting
3613 * settings of sampling time channel wise.
3614 * @note On this STM32 series, setting of this feature is conditioned to
3615 * ADC state:
3616 * ADC must be disabled or enabled without conversion on going
3617 * on either groups regular or injected.
3618 * @rmtoll SMPR1 SMPPLUS LL_ADC_SetSamplingTimeCommonConfig
3619 * @param ADCx ADC instance
3620 * @param SamplingTimeCommonConfig This parameter can be one of the following values:
3621 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
3622 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
3623 * @retval None
3624 */
LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef * ADCx,uint32_t SamplingTimeCommonConfig)3625 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
3626 {
3627 MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
3628 }
3629
3630 /**
3631 * @brief Get ADC sampling time common configuration impacting
3632 * settings of sampling time channel wise.
3633 * @rmtoll SMPR1 SMPPLUS LL_ADC_GetSamplingTimeCommonConfig
3634 * @param ADCx ADC instance
3635 * @retval Returned value can be one of the following values:
3636 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
3637 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
3638 */
LL_ADC_GetSamplingTimeCommonConfig(const ADC_TypeDef * ADCx)3639 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(const ADC_TypeDef *ADCx)
3640 {
3641 return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
3642 }
3643 #endif /* ADC_SMPR1_SMPPLUS */
3644
3645 /**
3646 * @}
3647 */
3648
3649 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
3650 * @{
3651 */
3652
3653 /**
3654 * @brief Set ADC group regular conversion trigger source:
3655 * internal (SW start) or from external peripheral (timer event,
3656 * external interrupt line).
3657 * @note On this STM32 series, setting trigger source to external trigger
3658 * also set trigger polarity to rising edge
3659 * (default setting for compatibility with some ADC on other
3660 * STM32 series having this setting set by HW default value).
3661 * In case of need to modify trigger edge, use
3662 * function @ref LL_ADC_REG_SetTriggerEdge().
3663 * @note Availability of parameters of trigger sources from timer
3664 * depends on timers availability on the selected device.
3665 * @note On this STM32 series, setting of this feature is conditioned to
3666 * ADC state:
3667 * ADC must be disabled or enabled without conversion on going
3668 * on group regular.
3669 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
3670 * CFGR EXTEN LL_ADC_REG_SetTriggerSource
3671 * @param ADCx ADC instance
3672 * @param TriggerSource This parameter can be one of the following values:
3673 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3674 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3675 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3676 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3677 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3678 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3679 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3680 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3681 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3682 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3683 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3684 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3685 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3686 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3687 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3688 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3689 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3690 * @retval None
3691 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)3692 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3693 {
3694 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
3695 }
3696
3697 /**
3698 * @brief Get ADC group regular conversion trigger source:
3699 * internal (SW start) or from external peripheral (timer event,
3700 * external interrupt line).
3701 * @note To determine whether group regular trigger source is
3702 * internal (SW start) or external, without detail
3703 * of which peripheral is selected as external trigger,
3704 * (equivalent to
3705 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
3706 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
3707 * @note Availability of parameters of trigger sources from timer
3708 * depends on timers availability on the selected device.
3709 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
3710 * CFGR EXTEN LL_ADC_REG_GetTriggerSource
3711 * @param ADCx ADC instance
3712 * @retval Returned value can be one of the following values:
3713 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3714 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3715 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3716 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3717 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3718 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3719 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3720 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3721 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3722 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3723 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3724 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3725 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3726 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3727 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3728 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3729 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3730 */
LL_ADC_REG_GetTriggerSource(const ADC_TypeDef * ADCx)3731 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
3732 {
3733 __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
3734
3735 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3736 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
3737 uint32_t shift_exten = ((trigger_source & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3738
3739 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
3740 /* to match with triggers literals definition. */
3741 return ((trigger_source
3742 & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR_EXTSEL)
3743 | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR_EXTEN)
3744 );
3745 }
3746
3747 /**
3748 * @brief Get ADC group regular conversion trigger source internal (SW start)
3749 * or external.
3750 * @note In case of group regular trigger source set to external trigger,
3751 * to determine which peripheral is selected as external trigger,
3752 * use function @ref LL_ADC_REG_GetTriggerSource().
3753 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
3754 * @param ADCx ADC instance
3755 * @retval Value "0" if trigger source external trigger
3756 * Value "1" if trigger source SW start.
3757 */
LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)3758 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
3759 {
3760 return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
3761 }
3762
3763 /**
3764 * @brief Set ADC group regular conversion trigger polarity.
3765 * @note Applicable only for trigger source set to external trigger.
3766 * @note On this STM32 series, setting of this feature is conditioned to
3767 * ADC state:
3768 * ADC must be disabled or enabled without conversion on going
3769 * on group regular.
3770 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
3771 * @param ADCx ADC instance
3772 * @param ExternalTriggerEdge This parameter can be one of the following values:
3773 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3774 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3775 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3776 * @retval None
3777 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3778 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3779 {
3780 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
3781 }
3782
3783 /**
3784 * @brief Get ADC group regular conversion trigger polarity.
3785 * @note Applicable only for trigger source set to external trigger.
3786 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
3787 * @param ADCx ADC instance
3788 * @retval Returned value can be one of the following values:
3789 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3790 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3791 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3792 */
LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef * ADCx)3793 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
3794 {
3795 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
3796 }
3797
3798 /**
3799 * @brief Set ADC group regular sequencer length and scan direction.
3800 * @note Description of ADC group regular sequencer features:
3801 * - For devices with sequencer fully configurable
3802 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3803 * sequencer length and each rank affectation to a channel
3804 * are configurable.
3805 * This function performs configuration of:
3806 * - Sequence length: Number of ranks in the scan sequence.
3807 * - Sequence direction: Unless specified in parameters, sequencer
3808 * scan direction is forward (from rank 1 to rank n).
3809 * Sequencer ranks are selected using
3810 * function "LL_ADC_REG_SetSequencerRanks()".
3811 * - For devices with sequencer not fully configurable
3812 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3813 * sequencer length and each rank affectation to a channel
3814 * are defined by channel number.
3815 * This function performs configuration of:
3816 * - Sequence length: Number of ranks in the scan sequence is
3817 * defined by number of channels set in the sequence,
3818 * rank of each channel is fixed by channel HW number.
3819 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3820 * - Sequence direction: Unless specified in parameters, sequencer
3821 * scan direction is forward (from lowest channel number to
3822 * highest channel number).
3823 * Sequencer ranks are selected using
3824 * function "LL_ADC_REG_SetSequencerChannels()".
3825 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3826 * ADC conversion on only 1 channel.
3827 * @note On this STM32 series, setting of this feature is conditioned to
3828 * ADC state:
3829 * ADC must be disabled or enabled without conversion on going
3830 * on group regular.
3831 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
3832 * @param ADCx ADC instance
3833 * @param SequencerNbRanks This parameter can be one of the following values:
3834 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3835 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3836 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3837 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3838 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3839 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3840 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3841 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3842 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3843 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3844 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3845 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3846 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3847 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3848 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3849 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3850 * @retval None
3851 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)3852 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
3853 {
3854 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
3855 }
3856
3857 /**
3858 * @brief Get ADC group regular sequencer length and scan direction.
3859 * @note Description of ADC group regular sequencer features:
3860 * - For devices with sequencer fully configurable
3861 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3862 * sequencer length and each rank affectation to a channel
3863 * are configurable.
3864 * This function retrieves:
3865 * - Sequence length: Number of ranks in the scan sequence.
3866 * - Sequence direction: Unless specified in parameters, sequencer
3867 * scan direction is forward (from rank 1 to rank n).
3868 * Sequencer ranks are selected using
3869 * function "LL_ADC_REG_SetSequencerRanks()".
3870 * - For devices with sequencer not fully configurable
3871 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3872 * sequencer length and each rank affectation to a channel
3873 * are defined by channel number.
3874 * This function retrieves:
3875 * - Sequence length: Number of ranks in the scan sequence is
3876 * defined by number of channels set in the sequence,
3877 * rank of each channel is fixed by channel HW number.
3878 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3879 * - Sequence direction: Unless specified in parameters, sequencer
3880 * scan direction is forward (from lowest channel number to
3881 * highest channel number).
3882 * Sequencer ranks are selected using
3883 * function "LL_ADC_REG_SetSequencerChannels()".
3884 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3885 * ADC conversion on only 1 channel.
3886 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
3887 * @param ADCx ADC instance
3888 * @retval Returned value can be one of the following values:
3889 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3890 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3891 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3892 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3893 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3894 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3895 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3896 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3897 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3898 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3899 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3900 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3901 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3902 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3903 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3904 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3905 */
LL_ADC_REG_GetSequencerLength(const ADC_TypeDef * ADCx)3906 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
3907 {
3908 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
3909 }
3910
3911 /**
3912 * @brief Set ADC group regular sequencer discontinuous mode:
3913 * sequence subdivided and scan conversions interrupted every selected
3914 * number of ranks.
3915 * @note It is not possible to enable both ADC group regular
3916 * continuous mode and sequencer discontinuous mode.
3917 * @note It is not possible to enable both ADC auto-injected mode
3918 * and ADC group regular sequencer discontinuous mode.
3919 * @note On this STM32 series, setting of this feature is conditioned to
3920 * ADC state:
3921 * ADC must be disabled or enabled without conversion on going
3922 * on group regular.
3923 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
3924 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
3925 * @param ADCx ADC instance
3926 * @param SeqDiscont This parameter can be one of the following values:
3927 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3928 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3929 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
3930 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
3931 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
3932 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
3933 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
3934 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
3935 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
3936 * @retval None
3937 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)3938 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
3939 {
3940 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
3941 }
3942
3943 /**
3944 * @brief Get ADC group regular sequencer discontinuous mode:
3945 * sequence subdivided and scan conversions interrupted every selected
3946 * number of ranks.
3947 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
3948 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
3949 * @param ADCx ADC instance
3950 * @retval Returned value can be one of the following values:
3951 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3952 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3953 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
3954 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
3955 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
3956 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
3957 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
3958 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
3959 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
3960 */
LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef * ADCx)3961 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
3962 {
3963 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
3964 }
3965
3966 /**
3967 * @brief Set ADC group regular sequence: channel on the selected
3968 * scan sequence rank.
3969 * @note This function performs configuration of:
3970 * - Channels ordering into each rank of scan sequence:
3971 * whatever channel can be placed into whatever rank.
3972 * @note On this STM32 series, ADC group regular sequencer is
3973 * fully configurable: sequencer length and each rank
3974 * affectation to a channel are configurable.
3975 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3976 * @note Depending on devices and packages, some channels may not be available.
3977 * Refer to device datasheet for channels availability.
3978 * @note On this STM32 series, to measure internal channels (VrefInt,
3979 * TempSensor, ...), measurement paths to internal channels must be
3980 * enabled separately.
3981 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3982 * @note On this STM32 series, setting of this feature is conditioned to
3983 * ADC state:
3984 * ADC must be disabled or enabled without conversion on going
3985 * on group regular.
3986 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
3987 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
3988 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
3989 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
3990 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
3991 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
3992 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
3993 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
3994 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
3995 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
3996 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
3997 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
3998 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
3999 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
4000 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
4001 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
4002 * @param ADCx ADC instance
4003 * @param Rank This parameter can be one of the following values:
4004 * @arg @ref LL_ADC_REG_RANK_1
4005 * @arg @ref LL_ADC_REG_RANK_2
4006 * @arg @ref LL_ADC_REG_RANK_3
4007 * @arg @ref LL_ADC_REG_RANK_4
4008 * @arg @ref LL_ADC_REG_RANK_5
4009 * @arg @ref LL_ADC_REG_RANK_6
4010 * @arg @ref LL_ADC_REG_RANK_7
4011 * @arg @ref LL_ADC_REG_RANK_8
4012 * @arg @ref LL_ADC_REG_RANK_9
4013 * @arg @ref LL_ADC_REG_RANK_10
4014 * @arg @ref LL_ADC_REG_RANK_11
4015 * @arg @ref LL_ADC_REG_RANK_12
4016 * @arg @ref LL_ADC_REG_RANK_13
4017 * @arg @ref LL_ADC_REG_RANK_14
4018 * @arg @ref LL_ADC_REG_RANK_15
4019 * @arg @ref LL_ADC_REG_RANK_16
4020 * @param Channel This parameter can be one of the following values:
4021 * @arg @ref LL_ADC_CHANNEL_0
4022 * @arg @ref LL_ADC_CHANNEL_1 (7)
4023 * @arg @ref LL_ADC_CHANNEL_2 (7)
4024 * @arg @ref LL_ADC_CHANNEL_3 (7)
4025 * @arg @ref LL_ADC_CHANNEL_4 (7)
4026 * @arg @ref LL_ADC_CHANNEL_5 (7)
4027 * @arg @ref LL_ADC_CHANNEL_6
4028 * @arg @ref LL_ADC_CHANNEL_7
4029 * @arg @ref LL_ADC_CHANNEL_8
4030 * @arg @ref LL_ADC_CHANNEL_9
4031 * @arg @ref LL_ADC_CHANNEL_10
4032 * @arg @ref LL_ADC_CHANNEL_11
4033 * @arg @ref LL_ADC_CHANNEL_12
4034 * @arg @ref LL_ADC_CHANNEL_13
4035 * @arg @ref LL_ADC_CHANNEL_14
4036 * @arg @ref LL_ADC_CHANNEL_15
4037 * @arg @ref LL_ADC_CHANNEL_16
4038 * @arg @ref LL_ADC_CHANNEL_17
4039 * @arg @ref LL_ADC_CHANNEL_18
4040 * @arg @ref LL_ADC_CHANNEL_VREFINT
4041 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
4042 * @arg @ref LL_ADC_CHANNEL_VBAT
4043 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4044 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4045 *
4046 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
4047 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
4048 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4049 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4050 * @retval None
4051 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4052 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4053 {
4054 /* Set bits with content of parameter "Channel" with bits position */
4055 /* in register and register position depending on parameter "Rank". */
4056 /* Parameters "Rank" and "Channel" are used with masks because containing */
4057 /* other bits reserved for other purpose. */
4058 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
4059 ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4060
4061 MODIFY_REG(*preg,
4062 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
4063 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
4064 << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
4065 }
4066
4067 /**
4068 * @brief Get ADC group regular sequence: channel on the selected
4069 * scan sequence rank.
4070 * @note On this STM32 series, ADC group regular sequencer is
4071 * fully configurable: sequencer length and each rank
4072 * affectation to a channel are configurable.
4073 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4074 * @note Depending on devices and packages, some channels may not be available.
4075 * Refer to device datasheet for channels availability.
4076 * @note Usage of the returned channel number:
4077 * - To reinject this channel into another function LL_ADC_xxx:
4078 * the returned channel number is only partly formatted on definition
4079 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4080 * with parts of literals LL_ADC_CHANNEL_x or using
4081 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4082 * Then the selected literal LL_ADC_CHANNEL_x can be used
4083 * as parameter for another function.
4084 * - To get the channel number in decimal format:
4085 * process the returned value with the helper macro
4086 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4087 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
4088 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
4089 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
4090 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
4091 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
4092 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
4093 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
4094 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
4095 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
4096 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
4097 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
4098 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
4099 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
4100 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
4101 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
4102 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
4103 * @param ADCx ADC instance
4104 * @param Rank This parameter can be one of the following values:
4105 * @arg @ref LL_ADC_REG_RANK_1
4106 * @arg @ref LL_ADC_REG_RANK_2
4107 * @arg @ref LL_ADC_REG_RANK_3
4108 * @arg @ref LL_ADC_REG_RANK_4
4109 * @arg @ref LL_ADC_REG_RANK_5
4110 * @arg @ref LL_ADC_REG_RANK_6
4111 * @arg @ref LL_ADC_REG_RANK_7
4112 * @arg @ref LL_ADC_REG_RANK_8
4113 * @arg @ref LL_ADC_REG_RANK_9
4114 * @arg @ref LL_ADC_REG_RANK_10
4115 * @arg @ref LL_ADC_REG_RANK_11
4116 * @arg @ref LL_ADC_REG_RANK_12
4117 * @arg @ref LL_ADC_REG_RANK_13
4118 * @arg @ref LL_ADC_REG_RANK_14
4119 * @arg @ref LL_ADC_REG_RANK_15
4120 * @arg @ref LL_ADC_REG_RANK_16
4121 * @retval Returned value can be one of the following values:
4122 * @arg @ref LL_ADC_CHANNEL_0 (7)
4123 * @arg @ref LL_ADC_CHANNEL_1 (7)
4124 * @arg @ref LL_ADC_CHANNEL_2 (7)
4125 * @arg @ref LL_ADC_CHANNEL_3 (7)
4126 * @arg @ref LL_ADC_CHANNEL_4 (7)
4127 * @arg @ref LL_ADC_CHANNEL_5 (7)
4128 * @arg @ref LL_ADC_CHANNEL_6
4129 * @arg @ref LL_ADC_CHANNEL_7
4130 * @arg @ref LL_ADC_CHANNEL_8
4131 * @arg @ref LL_ADC_CHANNEL_9
4132 * @arg @ref LL_ADC_CHANNEL_10
4133 * @arg @ref LL_ADC_CHANNEL_11
4134 * @arg @ref LL_ADC_CHANNEL_12
4135 * @arg @ref LL_ADC_CHANNEL_13
4136 * @arg @ref LL_ADC_CHANNEL_14
4137 * @arg @ref LL_ADC_CHANNEL_15
4138 * @arg @ref LL_ADC_CHANNEL_16
4139 * @arg @ref LL_ADC_CHANNEL_17
4140 * @arg @ref LL_ADC_CHANNEL_18
4141 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4142 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4143 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4144 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4145 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4146 *
4147 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
4148 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
4149 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4150 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to
4151 * 4.21 Ms/s)).\n
4152 * (1, 2, 3, 4) For ADC channel read back from ADC register,
4153 * comparison with internal channel parameter to be done
4154 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4155 */
LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)4156 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
4157 {
4158 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
4159 ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4160
4161 return (uint32_t)((READ_BIT(*preg,
4162 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
4163 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4164 );
4165 }
4166
4167 /**
4168 * @brief Set ADC continuous conversion mode on ADC group regular.
4169 * @note Description of ADC continuous conversion mode:
4170 * - single mode: one conversion per trigger
4171 * - continuous mode: after the first trigger, following
4172 * conversions launched successively automatically.
4173 * @note It is not possible to enable both ADC group regular
4174 * continuous mode and sequencer discontinuous mode.
4175 * @note On this STM32 series, setting of this feature is conditioned to
4176 * ADC state:
4177 * ADC must be disabled or enabled without conversion on going
4178 * on group regular.
4179 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
4180 * @param ADCx ADC instance
4181 * @param Continuous This parameter can be one of the following values:
4182 * @arg @ref LL_ADC_REG_CONV_SINGLE
4183 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4184 * @retval None
4185 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)4186 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
4187 {
4188 MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
4189 }
4190
4191 /**
4192 * @brief Get ADC continuous conversion mode on ADC group regular.
4193 * @note Description of ADC continuous conversion mode:
4194 * - single mode: one conversion per trigger
4195 * - continuous mode: after the first trigger, following
4196 * conversions launched successively automatically.
4197 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
4198 * @param ADCx ADC instance
4199 * @retval Returned value can be one of the following values:
4200 * @arg @ref LL_ADC_REG_CONV_SINGLE
4201 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4202 */
LL_ADC_REG_GetContinuousMode(const ADC_TypeDef * ADCx)4203 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
4204 {
4205 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
4206 }
4207
4208 /**
4209 * @brief Set ADC group regular conversion data transfer: no transfer or
4210 * transfer by DMA, and DMA requests mode.
4211 * @note If transfer by DMA selected, specifies the DMA requests
4212 * mode:
4213 * - Limited mode (One shot mode): DMA transfer requests are stopped
4214 * when number of DMA data transfers (number of
4215 * ADC conversions) is reached.
4216 * This ADC mode is intended to be used with DMA mode non-circular.
4217 * - Unlimited mode: DMA transfer requests are unlimited,
4218 * whatever number of DMA data transfers (number of
4219 * ADC conversions).
4220 * This ADC mode is intended to be used with DMA mode circular.
4221 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
4222 * mode non-circular:
4223 * when DMA transfers size will be reached, DMA will stop transfers of
4224 * ADC conversions data ADC will raise an overrun error
4225 * (overrun flag and interruption if enabled).
4226 * @note For devices with several ADC instances: ADC multimode DMA
4227 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
4228 * @note To configure DMA source address (peripheral address),
4229 * use function @ref LL_ADC_DMA_GetRegAddr().
4230 * @note On this STM32 series, setting of this feature is conditioned to
4231 * ADC state:
4232 * ADC must be disabled or enabled without conversion on going
4233 * on either groups regular or injected.
4234 * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
4235 * CFGR DMACFG LL_ADC_REG_SetDMATransfer
4236 * @param ADCx ADC instance
4237 * @param DMATransfer This parameter can be one of the following values:
4238 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
4239 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
4240 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
4241 * @retval None
4242 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)4243 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
4244 {
4245 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
4246 }
4247
4248 /**
4249 * @brief Get ADC group regular conversion data transfer: no transfer or
4250 * transfer by DMA, and DMA requests mode.
4251 * @note If transfer by DMA selected, specifies the DMA requests
4252 * mode:
4253 * - Limited mode (One shot mode): DMA transfer requests are stopped
4254 * when number of DMA data transfers (number of
4255 * ADC conversions) is reached.
4256 * This ADC mode is intended to be used with DMA mode non-circular.
4257 * - Unlimited mode: DMA transfer requests are unlimited,
4258 * whatever number of DMA data transfers (number of
4259 * ADC conversions).
4260 * This ADC mode is intended to be used with DMA mode circular.
4261 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
4262 * mode non-circular:
4263 * when DMA transfers size will be reached, DMA will stop transfers of
4264 * ADC conversions data ADC will raise an overrun error
4265 * (overrun flag and interruption if enabled).
4266 * @note For devices with several ADC instances: ADC multimode DMA
4267 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
4268 * @note To configure DMA source address (peripheral address),
4269 * use function @ref LL_ADC_DMA_GetRegAddr().
4270 * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
4271 * CFGR DMACFG LL_ADC_REG_GetDMATransfer
4272 * @param ADCx ADC instance
4273 * @retval Returned value can be one of the following values:
4274 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
4275 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
4276 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
4277 */
LL_ADC_REG_GetDMATransfer(const ADC_TypeDef * ADCx)4278 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx)
4279 {
4280 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
4281 }
4282
4283 #if defined(DFSDM1_Channel0)
4284 /**
4285 * @brief Set ADC group regular conversion data transfer to DFSDM.
4286 * @note DFSDM transfer cannot be used if DMA transfer is enabled.
4287 * @note To configure DFSDM source address (peripheral address),
4288 * use the same function as for DMA transfer:
4289 * function @ref LL_ADC_DMA_GetRegAddr().
4290 * @note On this STM32 series, setting of this feature is conditioned to
4291 * ADC state:
4292 * ADC must be disabled or enabled without conversion on going
4293 * on either groups regular or injected.
4294 * @rmtoll CFGR DFSDMCFG LL_ADC_REG_GetDFSDMTransfer
4295 * @param ADCx ADC instance
4296 * @param DFSDMTransfer This parameter can be one of the following values:
4297 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_NONE
4298 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_ENABLE
4299 * @retval None
4300 */
LL_ADC_REG_SetDFSDMTransfer(ADC_TypeDef * ADCx,uint32_t DFSDMTransfer)4301 __STATIC_INLINE void LL_ADC_REG_SetDFSDMTransfer(ADC_TypeDef *ADCx, uint32_t DFSDMTransfer)
4302 {
4303 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DFSDMCFG, DFSDMTransfer);
4304 }
4305
4306 /**
4307 * @brief Get ADC group regular conversion data transfer to DFSDM.
4308 * @rmtoll CFGR DFSDMCFG LL_ADC_REG_GetDFSDMTransfer
4309 * @param ADCx ADC instance
4310 * @retval Returned value can be one of the following values:
4311 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_NONE
4312 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_ENABLE
4313 */
LL_ADC_REG_GetDFSDMTransfer(const ADC_TypeDef * ADCx)4314 __STATIC_INLINE uint32_t LL_ADC_REG_GetDFSDMTransfer(const ADC_TypeDef *ADCx)
4315 {
4316 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DFSDMCFG));
4317 }
4318 #endif /* ADC_CFGR_DFSDMCFG */
4319
4320 /**
4321 * @brief Set ADC group regular behavior in case of overrun:
4322 * data preserved or overwritten.
4323 * @note Compatibility with devices without feature overrun:
4324 * other devices without this feature have a behavior
4325 * equivalent to data overwritten.
4326 * The default setting of overrun is data preserved.
4327 * Therefore, for compatibility with all devices, parameter
4328 * overrun should be set to data overwritten.
4329 * @note On this STM32 series, setting of this feature is conditioned to
4330 * ADC state:
4331 * ADC must be disabled or enabled without conversion on going
4332 * on group regular.
4333 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
4334 * @param ADCx ADC instance
4335 * @param Overrun This parameter can be one of the following values:
4336 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4337 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4338 * @retval None
4339 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)4340 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
4341 {
4342 MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
4343 }
4344
4345 /**
4346 * @brief Get ADC group regular behavior in case of overrun:
4347 * data preserved or overwritten.
4348 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
4349 * @param ADCx ADC instance
4350 * @retval Returned value can be one of the following values:
4351 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4352 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4353 */
LL_ADC_REG_GetOverrun(const ADC_TypeDef * ADCx)4354 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx)
4355 {
4356 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
4357 }
4358
4359 /**
4360 * @}
4361 */
4362
4363 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
4364 * @{
4365 */
4366
4367 /**
4368 * @brief Set ADC group injected conversion trigger source:
4369 * internal (SW start) or from external peripheral (timer event,
4370 * external interrupt line).
4371 * @note On this STM32 series, setting trigger source to external trigger
4372 * also set trigger polarity to rising edge
4373 * (default setting for compatibility with some ADC on other
4374 * STM32 series having this setting set by HW default value).
4375 * In case of need to modify trigger edge, use
4376 * function @ref LL_ADC_INJ_SetTriggerEdge().
4377 * @note Availability of parameters of trigger sources from timer
4378 * depends on timers availability on the selected device.
4379 * @note On this STM32 series, setting of this feature is conditioned to
4380 * ADC state:
4381 * ADC must not be disabled. Can be enabled with or without conversion
4382 * on going on either groups regular or injected.
4383 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
4384 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
4385 * @param ADCx ADC instance
4386 * @param TriggerSource This parameter can be one of the following values:
4387 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4388 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4389 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4390 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4391 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4392 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4393 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4394 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
4395 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4396 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4397 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4398 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4399 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4400 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4401 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4402 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4403 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4404 * @retval None
4405 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)4406 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
4407 {
4408 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
4409 }
4410
4411 /**
4412 * @brief Get ADC group injected conversion trigger source:
4413 * internal (SW start) or from external peripheral (timer event,
4414 * external interrupt line).
4415 * @note To determine whether group injected trigger source is
4416 * internal (SW start) or external, without detail
4417 * of which peripheral is selected as external trigger,
4418 * (equivalent to
4419 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
4420 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
4421 * @note Availability of parameters of trigger sources from timer
4422 * depends on timers availability on the selected device.
4423 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
4424 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
4425 * @param ADCx ADC instance
4426 * @retval Returned value can be one of the following values:
4427 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4428 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4429 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4430 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4431 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4432 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4433 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4434 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
4435 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4436 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4437 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4438 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4439 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4440 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4441 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4442 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4443 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4444 */
LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef * ADCx)4445 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx)
4446 {
4447 __IO uint32_t trigger_source = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
4448
4449 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4450 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
4451 uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
4452
4453 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
4454 /* to match with triggers literals definition. */
4455 return ((trigger_source
4456 & (ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) & ADC_JSQR_JEXTSEL)
4457 | ((ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN)
4458 );
4459 }
4460
4461 /**
4462 * @brief Get ADC group injected conversion trigger source internal (SW start)
4463 or external
4464 * @note In case of group injected trigger source set to external trigger,
4465 * to determine which peripheral is selected as external trigger,
4466 * use function @ref LL_ADC_INJ_GetTriggerSource.
4467 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
4468 * @param ADCx ADC instance
4469 * @retval Value "0" if trigger source external trigger
4470 * Value "1" if trigger source SW start.
4471 */
LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)4472 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
4473 {
4474 return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
4475 }
4476
4477 /**
4478 * @brief Set ADC group injected conversion trigger polarity.
4479 * Applicable only for trigger source set to external trigger.
4480 * @note On this STM32 series, setting of this feature is conditioned to
4481 * ADC state:
4482 * ADC must not be disabled. Can be enabled with or without conversion
4483 * on going on either groups regular or injected.
4484 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
4485 * @param ADCx ADC instance
4486 * @param ExternalTriggerEdge This parameter can be one of the following values:
4487 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4488 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4489 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4490 * @retval None
4491 */
LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)4492 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4493 {
4494 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
4495 }
4496
4497 /**
4498 * @brief Get ADC group injected conversion trigger polarity.
4499 * Applicable only for trigger source set to external trigger.
4500 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
4501 * @param ADCx ADC instance
4502 * @retval Returned value can be one of the following values:
4503 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4504 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4505 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4506 */
LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef * ADCx)4507 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx)
4508 {
4509 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
4510 }
4511
4512 /**
4513 * @brief Set ADC group injected sequencer length and scan direction.
4514 * @note This function performs configuration of:
4515 * - Sequence length: Number of ranks in the scan sequence.
4516 * - Sequence direction: Unless specified in parameters, sequencer
4517 * scan direction is forward (from rank 1 to rank n).
4518 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4519 * ADC conversion on only 1 channel.
4520 * @note On this STM32 series, setting of this feature is conditioned to
4521 * ADC state:
4522 * ADC must not be disabled. Can be enabled with or without conversion
4523 * on going on either groups regular or injected.
4524 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
4525 * @param ADCx ADC instance
4526 * @param SequencerNbRanks This parameter can be one of the following values:
4527 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4528 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4529 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4530 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4531 * @retval None
4532 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)4533 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4534 {
4535 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
4536 }
4537
4538 /**
4539 * @brief Get ADC group injected sequencer length and scan direction.
4540 * @note This function retrieves:
4541 * - Sequence length: Number of ranks in the scan sequence.
4542 * - Sequence direction: Unless specified in parameters, sequencer
4543 * scan direction is forward (from rank 1 to rank n).
4544 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4545 * ADC conversion on only 1 channel.
4546 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
4547 * @param ADCx ADC instance
4548 * @retval Returned value can be one of the following values:
4549 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4550 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4551 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4552 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4553 */
LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef * ADCx)4554 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx)
4555 {
4556 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
4557 }
4558
4559 /**
4560 * @brief Set ADC group injected sequencer discontinuous mode:
4561 * sequence subdivided and scan conversions interrupted every selected
4562 * number of ranks.
4563 * @note It is not possible to enable both ADC group injected
4564 * auto-injected mode and sequencer discontinuous mode.
4565 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
4566 * @param ADCx ADC instance
4567 * @param SeqDiscont This parameter can be one of the following values:
4568 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4569 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4570 * @retval None
4571 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)4572 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4573 {
4574 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
4575 }
4576
4577 /**
4578 * @brief Get ADC group injected sequencer discontinuous mode:
4579 * sequence subdivided and scan conversions interrupted every selected
4580 * number of ranks.
4581 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
4582 * @param ADCx ADC instance
4583 * @retval Returned value can be one of the following values:
4584 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4585 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4586 */
LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef * ADCx)4587 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx)
4588 {
4589 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
4590 }
4591
4592 /**
4593 * @brief Set ADC group injected sequence: channel on the selected
4594 * sequence rank.
4595 * @note Depending on devices and packages, some channels may not be available.
4596 * Refer to device datasheet for channels availability.
4597 * @note On this STM32 series, to measure internal channels (VrefInt,
4598 * TempSensor, ...), measurement paths to internal channels must be
4599 * enabled separately.
4600 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4601 * @note On STM32L5, some fast channels are available: fast analog inputs
4602 * coming from GPIO pads (ADC_IN0..5).
4603 * @note On this STM32 series, setting of this feature is conditioned to
4604 * ADC state:
4605 * ADC must not be disabled. Can be enabled with or without conversion
4606 * on going on either groups regular or injected.
4607 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
4608 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
4609 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
4610 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
4611 * @param ADCx ADC instance
4612 * @param Rank This parameter can be one of the following values:
4613 * @arg @ref LL_ADC_INJ_RANK_1
4614 * @arg @ref LL_ADC_INJ_RANK_2
4615 * @arg @ref LL_ADC_INJ_RANK_3
4616 * @arg @ref LL_ADC_INJ_RANK_4
4617 * @param Channel This parameter can be one of the following values:
4618 * @arg @ref LL_ADC_CHANNEL_0
4619 * @arg @ref LL_ADC_CHANNEL_1 (7)
4620 * @arg @ref LL_ADC_CHANNEL_2 (7)
4621 * @arg @ref LL_ADC_CHANNEL_3 (7)
4622 * @arg @ref LL_ADC_CHANNEL_4 (7)
4623 * @arg @ref LL_ADC_CHANNEL_5 (7)
4624 * @arg @ref LL_ADC_CHANNEL_6
4625 * @arg @ref LL_ADC_CHANNEL_7
4626 * @arg @ref LL_ADC_CHANNEL_8
4627 * @arg @ref LL_ADC_CHANNEL_9
4628 * @arg @ref LL_ADC_CHANNEL_10
4629 * @arg @ref LL_ADC_CHANNEL_11
4630 * @arg @ref LL_ADC_CHANNEL_12
4631 * @arg @ref LL_ADC_CHANNEL_13
4632 * @arg @ref LL_ADC_CHANNEL_14
4633 * @arg @ref LL_ADC_CHANNEL_15
4634 * @arg @ref LL_ADC_CHANNEL_16
4635 * @arg @ref LL_ADC_CHANNEL_17
4636 * @arg @ref LL_ADC_CHANNEL_18
4637 * @arg @ref LL_ADC_CHANNEL_VREFINT
4638 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
4639 * @arg @ref LL_ADC_CHANNEL_VBAT
4640 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4641 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4642 *
4643 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
4644 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
4645 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4646 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4647 * @retval None
4648 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4649 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4650 {
4651 /* Set bits with content of parameter "Channel" with bits position */
4652 /* in register depending on parameter "Rank". */
4653 /* Parameters "Rank" and "Channel" are used with masks because containing */
4654 /* other bits reserved for other purpose. */
4655 MODIFY_REG(ADCx->JSQR,
4656 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
4657 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
4658 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
4659 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
4660 }
4661
4662 /**
4663 * @brief Get ADC group injected sequence: channel on the selected
4664 * sequence rank.
4665 * @note Depending on devices and packages, some channels may not be available.
4666 * Refer to device datasheet for channels availability.
4667 * @note Usage of the returned channel number:
4668 * - To reinject this channel into another function LL_ADC_xxx:
4669 * the returned channel number is only partly formatted on definition
4670 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4671 * with parts of literals LL_ADC_CHANNEL_x or using
4672 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4673 * Then the selected literal LL_ADC_CHANNEL_x can be used
4674 * as parameter for another function.
4675 * - To get the channel number in decimal format:
4676 * process the returned value with the helper macro
4677 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4678 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
4679 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
4680 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
4681 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
4682 * @param ADCx ADC instance
4683 * @param Rank This parameter can be one of the following values:
4684 * @arg @ref LL_ADC_INJ_RANK_1
4685 * @arg @ref LL_ADC_INJ_RANK_2
4686 * @arg @ref LL_ADC_INJ_RANK_3
4687 * @arg @ref LL_ADC_INJ_RANK_4
4688 * @retval Returned value can be one of the following values:
4689 * @arg @ref LL_ADC_CHANNEL_0 (7)
4690 * @arg @ref LL_ADC_CHANNEL_1 (7)
4691 * @arg @ref LL_ADC_CHANNEL_2 (7)
4692 * @arg @ref LL_ADC_CHANNEL_3 (7)
4693 * @arg @ref LL_ADC_CHANNEL_4 (7)
4694 * @arg @ref LL_ADC_CHANNEL_5 (7)
4695 * @arg @ref LL_ADC_CHANNEL_6
4696 * @arg @ref LL_ADC_CHANNEL_7
4697 * @arg @ref LL_ADC_CHANNEL_8
4698 * @arg @ref LL_ADC_CHANNEL_9
4699 * @arg @ref LL_ADC_CHANNEL_10
4700 * @arg @ref LL_ADC_CHANNEL_11
4701 * @arg @ref LL_ADC_CHANNEL_12
4702 * @arg @ref LL_ADC_CHANNEL_13
4703 * @arg @ref LL_ADC_CHANNEL_14
4704 * @arg @ref LL_ADC_CHANNEL_15
4705 * @arg @ref LL_ADC_CHANNEL_16
4706 * @arg @ref LL_ADC_CHANNEL_17
4707 * @arg @ref LL_ADC_CHANNEL_18
4708 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4709 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4710 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4711 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4712 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4713 *
4714 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
4715 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
4716 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4717 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to
4718 * 4.21 Ms/s)).\n
4719 * (1, 2, 3, 4) For ADC channel read back from ADC register,
4720 * comparison with internal channel parameter to be done
4721 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4722 */
LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)4723 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
4724 {
4725 return (uint32_t)((READ_BIT(ADCx->JSQR,
4726 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
4727 << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
4728 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4729 );
4730 }
4731
4732 /**
4733 * @brief Set ADC group injected conversion trigger:
4734 * independent or from ADC group regular.
4735 * @note This mode can be used to extend number of data registers
4736 * updated after one ADC conversion trigger and with data
4737 * permanently kept (not erased by successive conversions of scan of
4738 * ADC sequencer ranks), up to 5 data registers:
4739 * 1 data register on ADC group regular, 4 data registers
4740 * on ADC group injected.
4741 * @note If ADC group injected injected trigger source is set to an
4742 * external trigger, this feature must be must be set to
4743 * independent trigger.
4744 * ADC group injected automatic trigger is compliant only with
4745 * group injected trigger source set to SW start, without any
4746 * further action on ADC group injected conversion start or stop:
4747 * in this case, ADC group injected is controlled only
4748 * from ADC group regular.
4749 * @note It is not possible to enable both ADC group injected
4750 * auto-injected mode and sequencer discontinuous mode.
4751 * @note On this STM32 series, setting of this feature is conditioned to
4752 * ADC state:
4753 * ADC must be disabled or enabled without conversion on going
4754 * on either groups regular or injected.
4755 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
4756 * @param ADCx ADC instance
4757 * @param TrigAuto This parameter can be one of the following values:
4758 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4759 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4760 * @retval None
4761 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)4762 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
4763 {
4764 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
4765 }
4766
4767 /**
4768 * @brief Get ADC group injected conversion trigger:
4769 * independent or from ADC group regular.
4770 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
4771 * @param ADCx ADC instance
4772 * @retval Returned value can be one of the following values:
4773 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4774 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4775 */
LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef * ADCx)4776 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx)
4777 {
4778 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
4779 }
4780
4781 /**
4782 * @brief Set ADC group injected contexts queue mode.
4783 * @note A context is a setting of group injected sequencer:
4784 * - group injected trigger
4785 * - sequencer length
4786 * - sequencer ranks
4787 * If contexts queue is disabled:
4788 * - only 1 sequence can be configured
4789 * and is active perpetually.
4790 * If contexts queue is enabled:
4791 * - up to 2 contexts can be queued
4792 * and are checked in and out as a FIFO stack (first-in, first-out).
4793 * - If a new context is set when queues is full, error is triggered
4794 * by interruption "Injected Queue Overflow".
4795 * - Two behaviors are possible when all contexts have been processed:
4796 * the contexts queue can maintain the last context active perpetually
4797 * or can be empty and injected group triggers are disabled.
4798 * - Triggers can be only external (not internal SW start)
4799 * - Caution: The sequence must be fully configured in one time
4800 * (one write of register JSQR makes a check-in of a new context
4801 * into the queue).
4802 * Therefore functions to set separately injected trigger and
4803 * sequencer channels cannot be used, register JSQR must be set
4804 * using function @ref LL_ADC_INJ_ConfigQueueContext().
4805 * @note This parameter can be modified only when no conversion is on going
4806 * on either groups regular or injected.
4807 * @note A modification of the context mode (bit JQDIS) causes the contexts
4808 * queue to be flushed and the register JSQR is cleared.
4809 * @note On this STM32 series, setting of this feature is conditioned to
4810 * ADC state:
4811 * ADC must be disabled or enabled without conversion on going
4812 * on either groups regular or injected.
4813 * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
4814 * CFGR JQDIS LL_ADC_INJ_SetQueueMode
4815 * @param ADCx ADC instance
4816 * @param QueueMode This parameter can be one of the following values:
4817 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
4818 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4819 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4820 * @retval None
4821 */
LL_ADC_INJ_SetQueueMode(ADC_TypeDef * ADCx,uint32_t QueueMode)4822 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
4823 {
4824 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
4825 }
4826
4827 /**
4828 * @brief Get ADC group injected context queue mode.
4829 * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
4830 * CFGR JQDIS LL_ADC_INJ_GetQueueMode
4831 * @param ADCx ADC instance
4832 * @retval Returned value can be one of the following values:
4833 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
4834 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4835 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4836 */
LL_ADC_INJ_GetQueueMode(const ADC_TypeDef * ADCx)4837 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(const ADC_TypeDef *ADCx)
4838 {
4839 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
4840 }
4841
4842 /**
4843 * @brief Set one context on ADC group injected that will be checked in
4844 * contexts queue.
4845 * @note A context is a setting of group injected sequencer:
4846 * - group injected trigger
4847 * - sequencer length
4848 * - sequencer ranks
4849 * This function is intended to be used when contexts queue is enabled,
4850 * because the sequence must be fully configured in one time
4851 * (functions to set separately injected trigger and sequencer channels
4852 * cannot be used):
4853 * Refer to function @ref LL_ADC_INJ_SetQueueMode().
4854 * @note In the contexts queue, only the active context can be read.
4855 * The parameters of this function can be read using functions:
4856 * @arg @ref LL_ADC_INJ_GetTriggerSource()
4857 * @arg @ref LL_ADC_INJ_GetTriggerEdge()
4858 * @arg @ref LL_ADC_INJ_GetSequencerRanks()
4859 * @note On this STM32 series, to measure internal channels (VrefInt,
4860 * TempSensor, ...), measurement paths to internal channels must be
4861 * enabled separately.
4862 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4863 * @note On STM32L5, some fast channels are available: fast analog inputs
4864 * coming from GPIO pads (ADC_IN0..5).
4865 * @note On this STM32 series, setting of this feature is conditioned to
4866 * ADC state:
4867 * ADC must not be disabled. Can be enabled with or without conversion
4868 * on going on either groups regular or injected.
4869 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
4870 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
4871 * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
4872 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
4873 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
4874 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
4875 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
4876 * @param ADCx ADC instance
4877 * @param TriggerSource This parameter can be one of the following values:
4878 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4879 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4880 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4881 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4882 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4883 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4884 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4885 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
4886 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4887 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4888 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4889 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4890 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4891 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4892 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4893 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4894 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4895 * @param ExternalTriggerEdge This parameter can be one of the following values:
4896 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4897 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4898 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4899 *
4900 * Note: This parameter is discarded in case of SW start:
4901 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
4902 * @param SequencerNbRanks This parameter can be one of the following values:
4903 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4904 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4905 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4906 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4907 * @param Rank1_Channel This parameter can be one of the following values:
4908 * @arg @ref LL_ADC_CHANNEL_0
4909 * @arg @ref LL_ADC_CHANNEL_1 (7)
4910 * @arg @ref LL_ADC_CHANNEL_2 (7)
4911 * @arg @ref LL_ADC_CHANNEL_3 (7)
4912 * @arg @ref LL_ADC_CHANNEL_4 (7)
4913 * @arg @ref LL_ADC_CHANNEL_5 (7)
4914 * @arg @ref LL_ADC_CHANNEL_6
4915 * @arg @ref LL_ADC_CHANNEL_7
4916 * @arg @ref LL_ADC_CHANNEL_8
4917 * @arg @ref LL_ADC_CHANNEL_9
4918 * @arg @ref LL_ADC_CHANNEL_10
4919 * @arg @ref LL_ADC_CHANNEL_11
4920 * @arg @ref LL_ADC_CHANNEL_12
4921 * @arg @ref LL_ADC_CHANNEL_13
4922 * @arg @ref LL_ADC_CHANNEL_14
4923 * @arg @ref LL_ADC_CHANNEL_15
4924 * @arg @ref LL_ADC_CHANNEL_16
4925 * @arg @ref LL_ADC_CHANNEL_17
4926 * @arg @ref LL_ADC_CHANNEL_18
4927 * @arg @ref LL_ADC_CHANNEL_VREFINT
4928 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
4929 * @arg @ref LL_ADC_CHANNEL_VBAT
4930 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4931 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4932 *
4933 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
4934 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
4935 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4936 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4937 * @param Rank2_Channel This parameter can be one of the following values:
4938 * @arg @ref LL_ADC_CHANNEL_0
4939 * @arg @ref LL_ADC_CHANNEL_1 (7)
4940 * @arg @ref LL_ADC_CHANNEL_2 (7)
4941 * @arg @ref LL_ADC_CHANNEL_3 (7)
4942 * @arg @ref LL_ADC_CHANNEL_4 (7)
4943 * @arg @ref LL_ADC_CHANNEL_5 (7)
4944 * @arg @ref LL_ADC_CHANNEL_6
4945 * @arg @ref LL_ADC_CHANNEL_7
4946 * @arg @ref LL_ADC_CHANNEL_8
4947 * @arg @ref LL_ADC_CHANNEL_9
4948 * @arg @ref LL_ADC_CHANNEL_10
4949 * @arg @ref LL_ADC_CHANNEL_11
4950 * @arg @ref LL_ADC_CHANNEL_12
4951 * @arg @ref LL_ADC_CHANNEL_13
4952 * @arg @ref LL_ADC_CHANNEL_14
4953 * @arg @ref LL_ADC_CHANNEL_15
4954 * @arg @ref LL_ADC_CHANNEL_16
4955 * @arg @ref LL_ADC_CHANNEL_17
4956 * @arg @ref LL_ADC_CHANNEL_18
4957 * @arg @ref LL_ADC_CHANNEL_VREFINT
4958 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
4959 * @arg @ref LL_ADC_CHANNEL_VBAT
4960 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4961 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4962 *
4963 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
4964 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
4965 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4966 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4967 * @param Rank3_Channel This parameter can be one of the following values:
4968 * @arg @ref LL_ADC_CHANNEL_0
4969 * @arg @ref LL_ADC_CHANNEL_1 (7)
4970 * @arg @ref LL_ADC_CHANNEL_2 (7)
4971 * @arg @ref LL_ADC_CHANNEL_3 (7)
4972 * @arg @ref LL_ADC_CHANNEL_4 (7)
4973 * @arg @ref LL_ADC_CHANNEL_5 (7)
4974 * @arg @ref LL_ADC_CHANNEL_6
4975 * @arg @ref LL_ADC_CHANNEL_7
4976 * @arg @ref LL_ADC_CHANNEL_8
4977 * @arg @ref LL_ADC_CHANNEL_9
4978 * @arg @ref LL_ADC_CHANNEL_10
4979 * @arg @ref LL_ADC_CHANNEL_11
4980 * @arg @ref LL_ADC_CHANNEL_12
4981 * @arg @ref LL_ADC_CHANNEL_13
4982 * @arg @ref LL_ADC_CHANNEL_14
4983 * @arg @ref LL_ADC_CHANNEL_15
4984 * @arg @ref LL_ADC_CHANNEL_16
4985 * @arg @ref LL_ADC_CHANNEL_17
4986 * @arg @ref LL_ADC_CHANNEL_18
4987 * @arg @ref LL_ADC_CHANNEL_VREFINT
4988 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
4989 * @arg @ref LL_ADC_CHANNEL_VBAT
4990 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4991 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4992 *
4993 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
4994 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
4995 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4996 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4997 * @param Rank4_Channel This parameter can be one of the following values:
4998 * @arg @ref LL_ADC_CHANNEL_0
4999 * @arg @ref LL_ADC_CHANNEL_1 (7)
5000 * @arg @ref LL_ADC_CHANNEL_2 (7)
5001 * @arg @ref LL_ADC_CHANNEL_3 (7)
5002 * @arg @ref LL_ADC_CHANNEL_4 (7)
5003 * @arg @ref LL_ADC_CHANNEL_5 (7)
5004 * @arg @ref LL_ADC_CHANNEL_6
5005 * @arg @ref LL_ADC_CHANNEL_7
5006 * @arg @ref LL_ADC_CHANNEL_8
5007 * @arg @ref LL_ADC_CHANNEL_9
5008 * @arg @ref LL_ADC_CHANNEL_10
5009 * @arg @ref LL_ADC_CHANNEL_11
5010 * @arg @ref LL_ADC_CHANNEL_12
5011 * @arg @ref LL_ADC_CHANNEL_13
5012 * @arg @ref LL_ADC_CHANNEL_14
5013 * @arg @ref LL_ADC_CHANNEL_15
5014 * @arg @ref LL_ADC_CHANNEL_16
5015 * @arg @ref LL_ADC_CHANNEL_17
5016 * @arg @ref LL_ADC_CHANNEL_18
5017 * @arg @ref LL_ADC_CHANNEL_VREFINT
5018 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
5019 * @arg @ref LL_ADC_CHANNEL_VBAT
5020 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
5021 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
5022 *
5023 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
5024 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
5025 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
5026 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
5027 * @retval None
5028 */
LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef * ADCx,uint32_t TriggerSource,uint32_t ExternalTriggerEdge,uint32_t SequencerNbRanks,uint32_t Rank1_Channel,uint32_t Rank2_Channel,uint32_t Rank3_Channel,uint32_t Rank4_Channel)5029 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
5030 uint32_t TriggerSource,
5031 uint32_t ExternalTriggerEdge,
5032 uint32_t SequencerNbRanks,
5033 uint32_t Rank1_Channel,
5034 uint32_t Rank2_Channel,
5035 uint32_t Rank3_Channel,
5036 uint32_t Rank4_Channel)
5037 {
5038 /* Set bits with content of parameter "Rankx_Channel" with bits position */
5039 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
5040 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
5041 /* because containing other bits reserved for other purpose. */
5042 /* If parameter "TriggerSource" is set to SW start, then parameter */
5043 /* "ExternalTriggerEdge" is discarded. */
5044 uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
5045 MODIFY_REG(ADCx->JSQR,
5046 ADC_JSQR_JEXTSEL |
5047 ADC_JSQR_JEXTEN |
5048 ADC_JSQR_JSQ4 |
5049 ADC_JSQR_JSQ3 |
5050 ADC_JSQR_JSQ2 |
5051 ADC_JSQR_JSQ1 |
5052 ADC_JSQR_JL,
5053 (TriggerSource & ADC_JSQR_JEXTSEL) |
5054 (ExternalTriggerEdge * (is_trigger_not_sw)) |
5055 (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5056 << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5057 (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5058 << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5059 (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5060 << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5061 (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
5062 << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5063 SequencerNbRanks
5064 );
5065 }
5066
5067 /**
5068 * @}
5069 */
5070
5071 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
5072 * @{
5073 */
5074
5075 /**
5076 * @brief Set sampling time of the selected ADC channel
5077 * Unit: ADC clock cycles.
5078 * @note On this device, sampling time is on channel scope: independently
5079 * of channel mapped on ADC group regular or injected.
5080 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
5081 * converted:
5082 * sampling time constraints must be respected (sampling time can be
5083 * adjusted in function of ADC clock frequency and sampling time
5084 * setting).
5085 * Refer to device datasheet for timings values (parameters TS_vrefint,
5086 * TS_temp, ...).
5087 * @note Conversion time is the addition of sampling time and processing time.
5088 * On this STM32 series, ADC processing time is:
5089 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5090 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5091 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5092 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5093 * @note In case of ADC conversion of internal channel (VrefInt,
5094 * temperature sensor, ...), a sampling time minimum value
5095 * is required.
5096 * Refer to device datasheet.
5097 * @note On this STM32 series, setting of this feature is conditioned to
5098 * ADC state:
5099 * ADC must be disabled or enabled without conversion on going
5100 * on either groups regular or injected.
5101 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
5102 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
5103 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
5104 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
5105 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
5106 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
5107 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
5108 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
5109 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
5110 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
5111 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
5112 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
5113 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
5114 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
5115 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
5116 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
5117 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
5118 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
5119 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
5120 * @param ADCx ADC instance
5121 * @param Channel This parameter can be one of the following values:
5122 * @arg @ref LL_ADC_CHANNEL_0
5123 * @arg @ref LL_ADC_CHANNEL_1 (7)
5124 * @arg @ref LL_ADC_CHANNEL_2 (7)
5125 * @arg @ref LL_ADC_CHANNEL_3 (7)
5126 * @arg @ref LL_ADC_CHANNEL_4 (7)
5127 * @arg @ref LL_ADC_CHANNEL_5 (7)
5128 * @arg @ref LL_ADC_CHANNEL_6
5129 * @arg @ref LL_ADC_CHANNEL_7
5130 * @arg @ref LL_ADC_CHANNEL_8
5131 * @arg @ref LL_ADC_CHANNEL_9
5132 * @arg @ref LL_ADC_CHANNEL_10
5133 * @arg @ref LL_ADC_CHANNEL_11
5134 * @arg @ref LL_ADC_CHANNEL_12
5135 * @arg @ref LL_ADC_CHANNEL_13
5136 * @arg @ref LL_ADC_CHANNEL_14
5137 * @arg @ref LL_ADC_CHANNEL_15
5138 * @arg @ref LL_ADC_CHANNEL_16
5139 * @arg @ref LL_ADC_CHANNEL_17
5140 * @arg @ref LL_ADC_CHANNEL_18
5141 * @arg @ref LL_ADC_CHANNEL_VREFINT
5142 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
5143 * @arg @ref LL_ADC_CHANNEL_VBAT
5144 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
5145 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
5146 *
5147 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
5148 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
5149 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
5150 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
5151 * @param SamplingTime This parameter can be one of the following values:
5152 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
5153 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
5154 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
5155 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
5156 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
5157 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
5158 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
5159 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
5160 *
5161 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
5162 * can be replaced by 3.5 ADC clock cycles.
5163 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
5164 * @retval None
5165 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)5166 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
5167 {
5168 /* Set bits with content of parameter "SamplingTime" with bits position */
5169 /* in register and register position depending on parameter "Channel". */
5170 /* Parameter "Channel" is used with masks because containing */
5171 /* other bits reserved for other purpose. */
5172 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1,
5173 ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
5174
5175 MODIFY_REG(*preg,
5176 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
5177 SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
5178 }
5179
5180 /**
5181 * @brief Get sampling time of the selected ADC channel
5182 * Unit: ADC clock cycles.
5183 * @note On this device, sampling time is on channel scope: independently
5184 * of channel mapped on ADC group regular or injected.
5185 * @note Conversion time is the addition of sampling time and processing time.
5186 * On this STM32 series, ADC processing time is:
5187 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5188 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5189 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5190 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5191 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
5192 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
5193 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
5194 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
5195 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
5196 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
5197 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
5198 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
5199 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
5200 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
5201 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
5202 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
5203 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
5204 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
5205 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
5206 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
5207 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
5208 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
5209 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
5210 * @param ADCx ADC instance
5211 * @param Channel This parameter can be one of the following values:
5212 * @arg @ref LL_ADC_CHANNEL_0
5213 * @arg @ref LL_ADC_CHANNEL_1 (7)
5214 * @arg @ref LL_ADC_CHANNEL_2 (7)
5215 * @arg @ref LL_ADC_CHANNEL_3 (7)
5216 * @arg @ref LL_ADC_CHANNEL_4 (7)
5217 * @arg @ref LL_ADC_CHANNEL_5 (7)
5218 * @arg @ref LL_ADC_CHANNEL_6
5219 * @arg @ref LL_ADC_CHANNEL_7
5220 * @arg @ref LL_ADC_CHANNEL_8
5221 * @arg @ref LL_ADC_CHANNEL_9
5222 * @arg @ref LL_ADC_CHANNEL_10
5223 * @arg @ref LL_ADC_CHANNEL_11
5224 * @arg @ref LL_ADC_CHANNEL_12
5225 * @arg @ref LL_ADC_CHANNEL_13
5226 * @arg @ref LL_ADC_CHANNEL_14
5227 * @arg @ref LL_ADC_CHANNEL_15
5228 * @arg @ref LL_ADC_CHANNEL_16
5229 * @arg @ref LL_ADC_CHANNEL_17
5230 * @arg @ref LL_ADC_CHANNEL_18
5231 * @arg @ref LL_ADC_CHANNEL_VREFINT
5232 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
5233 * @arg @ref LL_ADC_CHANNEL_VBAT
5234 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
5235 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
5236 *
5237 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
5238 * (6) On STM32L5, parameter available on devices with several ADC instances.\n
5239 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
5240 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
5241 * @retval Returned value can be one of the following values:
5242 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
5243 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
5244 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
5245 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
5246 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
5247 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
5248 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
5249 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
5250 *
5251 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
5252 * can be replaced by 3.5 ADC clock cycles.
5253 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
5254 */
LL_ADC_GetChannelSamplingTime(const ADC_TypeDef * ADCx,uint32_t Channel)5255 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
5256 {
5257 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK)
5258 >> ADC_SMPRX_REGOFFSET_POS));
5259
5260 return (uint32_t)(READ_BIT(*preg,
5261 ADC_SMPR1_SMP0
5262 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
5263 >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
5264 );
5265 }
5266
5267 /**
5268 * @brief Set mode single-ended or differential input of the selected
5269 * ADC channel.
5270 * @note Channel ending is on channel scope: independently of channel mapped
5271 * on ADC group regular or injected.
5272 * In differential mode: Differential measurement is carried out
5273 * between the selected channel 'i' (positive input) and
5274 * channel 'i+1' (negative input). Only channel 'i' has to be
5275 * configured, channel 'i+1' is configured automatically.
5276 * @note Refer to Reference Manual to ensure the selected channel is
5277 * available in differential mode.
5278 * For example, internal channels (VrefInt, TempSensor, ...) are
5279 * not available in differential mode.
5280 * @note When configuring a channel 'i' in differential mode,
5281 * the channel 'i+1' is not usable separately.
5282 * @note On STM32L5, channels 0, 16, 17, 18 of ADC1 and ADC2
5283 * are internally fixed to single-ended inputs configuration.
5284 * @note For ADC channels configured in differential mode, both inputs
5285 * should be biased at (Vref+)/2 +/-200mV.
5286 * (Vref+ is the analog voltage reference)
5287 * @note On this STM32 series, setting of this feature is conditioned to
5288 * ADC state:
5289 * ADC must be ADC disabled.
5290 * @note One or several values can be selected.
5291 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5292 * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
5293 * @param ADCx ADC instance
5294 * @param Channel This parameter can be one of the following values:
5295 * @arg @ref LL_ADC_CHANNEL_1
5296 * @arg @ref LL_ADC_CHANNEL_2
5297 * @arg @ref LL_ADC_CHANNEL_3
5298 * @arg @ref LL_ADC_CHANNEL_4
5299 * @arg @ref LL_ADC_CHANNEL_5
5300 * @arg @ref LL_ADC_CHANNEL_6
5301 * @arg @ref LL_ADC_CHANNEL_7
5302 * @arg @ref LL_ADC_CHANNEL_8
5303 * @arg @ref LL_ADC_CHANNEL_9
5304 * @arg @ref LL_ADC_CHANNEL_10
5305 * @arg @ref LL_ADC_CHANNEL_11
5306 * @arg @ref LL_ADC_CHANNEL_12
5307 * @arg @ref LL_ADC_CHANNEL_13
5308 * @arg @ref LL_ADC_CHANNEL_14
5309 * @param SingleDiff This parameter can be a combination of the following values:
5310 * @arg @ref LL_ADC_SINGLE_ENDED
5311 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
5312 * @retval None
5313 */
LL_ADC_SetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SingleDiff)5314 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
5315 {
5316 /* Bits of channels in single or differential mode are set only for */
5317 /* differential mode (for single mode, mask of bits allowed to be set is */
5318 /* shifted out of range of bits of channels in single or differential mode. */
5319 MODIFY_REG(ADCx->DIFSEL,
5320 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
5321 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)
5322 & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
5323 }
5324
5325 /**
5326 * @brief Get mode single-ended or differential input of the selected
5327 * ADC channel.
5328 * @note When configuring a channel 'i' in differential mode,
5329 * the channel 'i+1' is not usable separately.
5330 * Therefore, to ensure a channel is configured in single-ended mode,
5331 * the configuration of channel itself and the channel 'i-1' must be
5332 * read back (to ensure that the selected channel channel has not been
5333 * configured in differential mode by the previous channel).
5334 * @note Refer to Reference Manual to ensure the selected channel is
5335 * available in differential mode.
5336 * For example, internal channels (VrefInt, TempSensor, ...) are
5337 * not available in differential mode.
5338 * @note When configuring a channel 'i' in differential mode,
5339 * the channel 'i+1' is not usable separately.
5340 * @note On STM32L5, channels 0, 16, 17, 18 of ADC1 and ADC2
5341 * are internally fixed to single-ended inputs configuration.
5342 */
5343 /*
5344 * @note One or several values can be selected. In this case, the value
5345 * returned is null if all channels are in single ended-mode.
5346 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5347 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
5348 * @param ADCx ADC instance
5349 * @param Channel This parameter can be a combination of the following values:
5350 * @arg @ref LL_ADC_CHANNEL_1
5351 * @arg @ref LL_ADC_CHANNEL_2
5352 * @arg @ref LL_ADC_CHANNEL_3
5353 * @arg @ref LL_ADC_CHANNEL_4
5354 * @arg @ref LL_ADC_CHANNEL_5
5355 * @arg @ref LL_ADC_CHANNEL_6
5356 * @arg @ref LL_ADC_CHANNEL_7
5357 * @arg @ref LL_ADC_CHANNEL_8
5358 * @arg @ref LL_ADC_CHANNEL_9
5359 * @arg @ref LL_ADC_CHANNEL_10
5360 * @arg @ref LL_ADC_CHANNEL_11
5361 * @arg @ref LL_ADC_CHANNEL_12
5362 * @arg @ref LL_ADC_CHANNEL_13
5363 * @arg @ref LL_ADC_CHANNEL_14
5364 * @retval 0: channel in single-ended mode, else: channel in differential mode
5365 */
LL_ADC_GetChannelSingleDiff(const ADC_TypeDef * ADCx,uint32_t Channel)5366 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel)
5367 {
5368 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
5369 }
5370
5371 /**
5372 * @}
5373 */
5374
5375 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
5376 * @{
5377 */
5378
5379 /**
5380 * @brief Set ADC analog watchdog monitored channels:
5381 * a single channel, multiple channels or all channels,
5382 * on ADC groups regular and-or injected.
5383 * @note Once monitored channels are selected, analog watchdog
5384 * is enabled.
5385 * @note In case of need to define a single channel to monitor
5386 * with analog watchdog from sequencer channel definition,
5387 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
5388 * @note On this STM32 series, there are 2 kinds of analog watchdog
5389 * instance:
5390 * - AWD standard (instance AWD1):
5391 * - channels monitored: can monitor 1 channel or all channels.
5392 * - groups monitored: ADC groups regular and-or injected.
5393 * - resolution: resolution is not limited (corresponds to
5394 * ADC resolution configured).
5395 * - AWD flexible (instances AWD2, AWD3):
5396 * - channels monitored: flexible on channels monitored, selection is
5397 * channel wise, from from 1 to all channels.
5398 * Specificity of this analog watchdog: Multiple channels can
5399 * be selected. For example:
5400 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5401 * - groups monitored: not selection possible (monitoring on both
5402 * groups regular and injected).
5403 * Channels selected are monitored on groups regular and injected:
5404 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5405 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5406 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5407 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5408 * the 2 LSB are ignored.
5409 * @note On this STM32 series, setting of this feature is conditioned to
5410 * ADC state:
5411 * ADC must be disabled or enabled without conversion on going
5412 * on either groups regular or injected.
5413 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
5414 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
5415 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5416 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5417 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
5418 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
5419 * @param ADCx ADC instance
5420 * @param AWDy This parameter can be one of the following values:
5421 * @arg @ref LL_ADC_AWD1
5422 * @arg @ref LL_ADC_AWD2
5423 * @arg @ref LL_ADC_AWD3
5424 * @param AWDChannelGroup This parameter can be one of the following values:
5425 * @arg @ref LL_ADC_AWD_DISABLE
5426 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5427 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5428 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5429 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5430 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5431 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5432 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5433 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5434 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5435 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5436 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5437 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5438 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5439 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5440 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5441 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5442 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5443 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5444 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5445 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5446 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5447 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5448 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5449 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5450 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5451 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5452 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5453 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5454 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5455 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5456 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5457 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5458 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5459 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5460 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5461 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5462 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5463 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5464 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5465 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5466 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5467 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5468 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5469 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5470 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5471 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5472 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5473 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5474 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5475 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5476 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5477 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5478 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5479 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5480 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5481 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5482 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5483 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5484 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5485 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5486 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
5487 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)
5488 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
5489 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)
5490 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)
5491 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ
5492 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)
5493 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)
5494 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ
5495 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(1)
5496 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(1)
5497 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (1)
5498 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(1)
5499 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(1)
5500 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (1)
5501 *
5502 * (0) On STM32L5, parameter available only on analog watchdog number: AWD1.\n
5503 * (1) On STM32L5, parameter available only on ADC instance: ADC2.
5504 * @retval None
5505 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)5506 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
5507 {
5508 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
5509 /* in register and register position depending on parameter "AWDy". */
5510 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
5511 /* containing other bits reserved for other purpose. */
5512 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR,
5513 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5514 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
5515 * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5516
5517 MODIFY_REG(*preg,
5518 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
5519 AWDChannelGroup & AWDy);
5520 }
5521
5522 /**
5523 * @brief Get ADC analog watchdog monitored channel.
5524 * @note Usage of the returned channel number:
5525 * - To reinject this channel into another function LL_ADC_xxx:
5526 * the returned channel number is only partly formatted on definition
5527 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
5528 * with parts of literals LL_ADC_CHANNEL_x or using
5529 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5530 * Then the selected literal LL_ADC_CHANNEL_x can be used
5531 * as parameter for another function.
5532 * - To get the channel number in decimal format:
5533 * process the returned value with the helper macro
5534 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5535 * Applicable only when the analog watchdog is set to monitor
5536 * one channel.
5537 * @note On this STM32 series, there are 2 kinds of analog watchdog
5538 * instance:
5539 * - AWD standard (instance AWD1):
5540 * - channels monitored: can monitor 1 channel or all channels.
5541 * - groups monitored: ADC groups regular and-or injected.
5542 * - resolution: resolution is not limited (corresponds to
5543 * ADC resolution configured).
5544 * - AWD flexible (instances AWD2, AWD3):
5545 * - channels monitored: flexible on channels monitored, selection is
5546 * channel wise, from from 1 to all channels.
5547 * Specificity of this analog watchdog: Multiple channels can
5548 * be selected. For example:
5549 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5550 * - groups monitored: not selection possible (monitoring on both
5551 * groups regular and injected).
5552 * Channels selected are monitored on groups regular and injected:
5553 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5554 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5555 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5556 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5557 * the 2 LSB are ignored.
5558 * @note On this STM32 series, setting of this feature is conditioned to
5559 * ADC state:
5560 * ADC must be disabled or enabled without conversion on going
5561 * on either groups regular or injected.
5562 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
5563 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
5564 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5565 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5566 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
5567 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
5568 * @param ADCx ADC instance
5569 * @param AWDy This parameter can be one of the following values:
5570 * @arg @ref LL_ADC_AWD1
5571 * @arg @ref LL_ADC_AWD2 (1)
5572 * @arg @ref LL_ADC_AWD3 (1)
5573 *
5574 * (1) On this AWD number, monitored channel can be retrieved
5575 * if only 1 channel is programmed (or none or all channels).
5576 * This function cannot retrieve monitored channel if
5577 * multiple channels are programmed simultaneously
5578 * by bitfield.
5579 * @retval Returned value can be one of the following values:
5580 * @arg @ref LL_ADC_AWD_DISABLE
5581 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5582 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5583 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5584 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5585 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5586 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5587 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5588 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5589 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5590 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5591 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5592 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5593 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5594 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5595 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5596 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5597 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5598 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5599 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5600 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5601 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5602 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5603 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5604 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5605 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5606 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5607 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5608 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5609 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5610 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5611 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5612 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5613 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5614 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5615 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5616 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5617 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5618 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5619 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5620 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5621 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5622 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5623 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5624 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5625 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5626 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5627 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5628 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5629 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5630 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5631 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5632 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5633 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5634 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5635 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5636 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5637 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5638 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5639 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5640 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5641 *
5642 * (0) On STM32L5, parameter available only on analog watchdog number: AWD1.
5643 */
LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef * ADCx,uint32_t AWDy)5644 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
5645 {
5646 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR,
5647 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5648 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
5649 * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5650
5651 uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
5652
5653 /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */
5654 /* (parameter value LL_ADC_AWD_DISABLE). */
5655 /* Else, the selected AWD is enabled and is monitoring a group of channels */
5656 /* or a single channel. */
5657 if (analog_wd_monit_channels != 0UL)
5658 {
5659 if (AWDy == LL_ADC_AWD1)
5660 {
5661 if ((analog_wd_monit_channels & ADC_CFGR_AWD1SGL) == 0UL)
5662 {
5663 /* AWD monitoring a group of channels */
5664 analog_wd_monit_channels = ((analog_wd_monit_channels
5665 | (ADC_AWD_CR23_CHANNEL_MASK)
5666 )
5667 & (~(ADC_CFGR_AWD1CH))
5668 );
5669 }
5670 else
5671 {
5672 /* AWD monitoring a single channel */
5673 analog_wd_monit_channels = (analog_wd_monit_channels
5674 | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR_AWD1CH_Pos))
5675 );
5676 }
5677 }
5678 else
5679 {
5680 if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
5681 {
5682 /* AWD monitoring a group of channels */
5683 analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK
5684 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
5685 );
5686 }
5687 else
5688 {
5689 /* AWD monitoring a single channel */
5690 /* AWD monitoring a group of channels */
5691 analog_wd_monit_channels = (analog_wd_monit_channels
5692 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
5693 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR_AWD1CH_Pos)
5694 );
5695 }
5696 }
5697 }
5698
5699 return analog_wd_monit_channels;
5700 }
5701
5702 /**
5703 * @brief Set ADC analog watchdog thresholds value of both thresholds
5704 * high and low.
5705 * @note If value of only one threshold high or low must be set,
5706 * use function @ref LL_ADC_SetAnalogWDThresholds().
5707 * @note In case of ADC resolution different of 12 bits,
5708 * analog watchdog thresholds data require a specific shift.
5709 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5710 * @note On this STM32 series, there are 2 kinds of analog watchdog
5711 * instance:
5712 * - AWD standard (instance AWD1):
5713 * - channels monitored: can monitor 1 channel or all channels.
5714 * - groups monitored: ADC groups regular and-or injected.
5715 * - resolution: resolution is not limited (corresponds to
5716 * ADC resolution configured).
5717 * - AWD flexible (instances AWD2, AWD3):
5718 * - channels monitored: flexible on channels monitored, selection is
5719 * channel wise, from from 1 to all channels.
5720 * Specificity of this analog watchdog: Multiple channels can
5721 * be selected. For example:
5722 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5723 * - groups monitored: not selection possible (monitoring on both
5724 * groups regular and injected).
5725 * Channels selected are monitored on groups regular and injected:
5726 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5727 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5728 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5729 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5730 * the 2 LSB are ignored.
5731 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
5732 * impacted: the comparison of analog watchdog thresholds is done on
5733 * oversampling final computation (after ratio and shift application):
5734 * ADC data register bitfield [15:4] (12 most significant bits).
5735 * Examples:
5736 * - Oversampling ratio and shift selected to have ADC conversion data
5737 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
5738 * ADC analog watchdog thresholds must be divided by 16.
5739 * - Oversampling ratio and shift selected to have ADC conversion data
5740 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
5741 * ADC analog watchdog thresholds must be divided by 4.
5742 * - Oversampling ratio and shift selected to have ADC conversion data
5743 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
5744 * ADC analog watchdog thresholds match directly to ADC data register.
5745 * @note On this STM32 series, setting of this feature is conditioned to
5746 * ADC state:
5747 * ADC must be disabled or enabled without conversion on going
5748 * on either groups regular or injected.
5749 * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
5750 * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
5751 * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
5752 * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
5753 * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
5754 * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
5755 * @param ADCx ADC instance
5756 * @param AWDy This parameter can be one of the following values:
5757 * @arg @ref LL_ADC_AWD1
5758 * @arg @ref LL_ADC_AWD2
5759 * @arg @ref LL_ADC_AWD3
5760 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
5761 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
5762 * @retval None
5763 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)5764 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
5765 uint32_t AWDThresholdLowValue)
5766 {
5767 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
5768 /* position in register and register position depending on parameter */
5769 /* "AWDy". */
5770 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
5771 /* containing other bits reserved for other purpose. */
5772 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
5773 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5774
5775 MODIFY_REG(*preg,
5776 ADC_TR1_HT1 | ADC_TR1_LT1,
5777 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
5778 }
5779
5780 /**
5781 * @brief Set ADC analog watchdog threshold value of threshold
5782 * high or low.
5783 * @note If values of both thresholds high or low must be set,
5784 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
5785 * @note In case of ADC resolution different of 12 bits,
5786 * analog watchdog thresholds data require a specific shift.
5787 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5788 * @note On this STM32 series, there are 2 kinds of analog watchdog
5789 * instance:
5790 * - AWD standard (instance AWD1):
5791 * - channels monitored: can monitor 1 channel or all channels.
5792 * - groups monitored: ADC groups regular and-or injected.
5793 * - resolution: resolution is not limited (corresponds to
5794 * ADC resolution configured).
5795 * - AWD flexible (instances AWD2, AWD3):
5796 * - channels monitored: flexible on channels monitored, selection is
5797 * channel wise, from from 1 to all channels.
5798 * Specificity of this analog watchdog: Multiple channels can
5799 * be selected. For example:
5800 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5801 * - groups monitored: not selection possible (monitoring on both
5802 * groups regular and injected).
5803 * Channels selected are monitored on groups regular and injected:
5804 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5805 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5806 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5807 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5808 * the 2 LSB are ignored.
5809 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
5810 * impacted: the comparison of analog watchdog thresholds is done on
5811 * oversampling final computation (after ratio and shift application):
5812 * ADC data register bitfield [15:4] (12 most significant bits).
5813 * Examples:
5814 * - Oversampling ratio and shift selected to have ADC conversion data
5815 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
5816 * ADC analog watchdog thresholds must be divided by 16.
5817 * - Oversampling ratio and shift selected to have ADC conversion data
5818 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
5819 * ADC analog watchdog thresholds must be divided by 4.
5820 * - Oversampling ratio and shift selected to have ADC conversion data
5821 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
5822 * ADC analog watchdog thresholds match directly to ADC data register.
5823 * @note On this STM32 series, setting of this feature is conditioned to
5824 * ADC state:
5825 * ADC must be disabled or enabled without conversion on going
5826 * on either ADC groups regular or injected.
5827 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
5828 * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
5829 * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
5830 * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
5831 * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
5832 * TR3 LT3 LL_ADC_SetAnalogWDThresholds
5833 * @param ADCx ADC instance
5834 * @param AWDy This parameter can be one of the following values:
5835 * @arg @ref LL_ADC_AWD1
5836 * @arg @ref LL_ADC_AWD2
5837 * @arg @ref LL_ADC_AWD3
5838 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5839 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5840 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5841 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
5842 * @retval None
5843 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)5844 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
5845 uint32_t AWDThresholdValue)
5846 {
5847 /* Set bits with content of parameter "AWDThresholdValue" with bits */
5848 /* position in register and register position depending on parameters */
5849 /* "AWDThresholdsHighLow" and "AWDy". */
5850 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
5851 /* containing other bits reserved for other purpose. */
5852 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
5853 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5854
5855 MODIFY_REG(*preg,
5856 AWDThresholdsHighLow,
5857 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
5858 }
5859
5860 /**
5861 * @brief Get ADC analog watchdog threshold value of threshold high,
5862 * threshold low or raw data with ADC thresholds high and low
5863 * concatenated.
5864 * @note If raw data with ADC thresholds high and low is retrieved,
5865 * the data of each threshold high or low can be isolated
5866 * using helper macro:
5867 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
5868 * @note In case of ADC resolution different of 12 bits,
5869 * analog watchdog thresholds data require a specific shift.
5870 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
5871 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
5872 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
5873 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
5874 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
5875 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
5876 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
5877 * @param ADCx ADC instance
5878 * @param AWDy This parameter can be one of the following values:
5879 * @arg @ref LL_ADC_AWD1
5880 * @arg @ref LL_ADC_AWD2
5881 * @arg @ref LL_ADC_AWD3
5882 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5883 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5884 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5885 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
5886 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
5887 */
LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)5888 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx,
5889 uint32_t AWDy, uint32_t AWDThresholdsHighLow)
5890 {
5891 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
5892 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5893
5894 return (uint32_t)(READ_BIT(*preg,
5895 (AWDThresholdsHighLow | ADC_TR1_LT1))
5896 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
5897 & ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
5898 }
5899
5900 /**
5901 * @}
5902 */
5903
5904 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
5905 * @{
5906 */
5907
5908 /**
5909 * @brief Set ADC oversampling scope: ADC groups regular and-or injected
5910 * (availability of ADC group injected depends on STM32 series).
5911 * @note If both groups regular and injected are selected,
5912 * specify behavior of ADC group injected interrupting
5913 * group regular: when ADC group injected is triggered,
5914 * the oversampling on ADC group regular is either
5915 * temporary stopped and continued, or resumed from start
5916 * (oversampler buffer reset).
5917 * @note On this STM32 series, setting of this feature is conditioned to
5918 * ADC state:
5919 * ADC must be disabled or enabled without conversion on going
5920 * on either groups regular or injected.
5921 * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
5922 * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
5923 * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
5924 * @param ADCx ADC instance
5925 * @param OvsScope This parameter can be one of the following values:
5926 * @arg @ref LL_ADC_OVS_DISABLE
5927 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
5928 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
5929 * @arg @ref LL_ADC_OVS_GRP_INJECTED
5930 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
5931 * @retval None
5932 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)5933 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
5934 {
5935 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
5936 }
5937
5938 /**
5939 * @brief Get ADC oversampling scope: ADC groups regular and-or injected
5940 * (availability of ADC group injected depends on STM32 series).
5941 * @note If both groups regular and injected are selected,
5942 * specify behavior of ADC group injected interrupting
5943 * group regular: when ADC group injected is triggered,
5944 * the oversampling on ADC group regular is either
5945 * temporary stopped and continued, or resumed from start
5946 * (oversampler buffer reset).
5947 * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
5948 * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
5949 * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
5950 * @param ADCx ADC instance
5951 * @retval Returned value can be one of the following values:
5952 * @arg @ref LL_ADC_OVS_DISABLE
5953 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
5954 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
5955 * @arg @ref LL_ADC_OVS_GRP_INJECTED
5956 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
5957 */
LL_ADC_GetOverSamplingScope(const ADC_TypeDef * ADCx)5958 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
5959 {
5960 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
5961 }
5962
5963 /**
5964 * @brief Set ADC oversampling discontinuous mode (triggered mode)
5965 * on the selected ADC group.
5966 * @note Number of oversampled conversions are done either in:
5967 * - continuous mode (all conversions of oversampling ratio
5968 * are done from 1 trigger)
5969 * - discontinuous mode (each conversion of oversampling ratio
5970 * needs a trigger)
5971 * @note On this STM32 series, setting of this feature is conditioned to
5972 * ADC state:
5973 * ADC must be disabled or enabled without conversion on going
5974 * on group regular.
5975 * @note On this STM32 series, oversampling discontinuous mode
5976 * (triggered mode) can be used only when oversampling is
5977 * set on group regular only and in resumed mode.
5978 * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
5979 * @param ADCx ADC instance
5980 * @param OverSamplingDiscont This parameter can be one of the following values:
5981 * @arg @ref LL_ADC_OVS_REG_CONT
5982 * @arg @ref LL_ADC_OVS_REG_DISCONT
5983 * @retval None
5984 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)5985 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
5986 {
5987 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
5988 }
5989
5990 /**
5991 * @brief Get ADC oversampling discontinuous mode (triggered mode)
5992 * on the selected ADC group.
5993 * @note Number of oversampled conversions are done either in:
5994 * - continuous mode (all conversions of oversampling ratio
5995 * are done from 1 trigger)
5996 * - discontinuous mode (each conversion of oversampling ratio
5997 * needs a trigger)
5998 * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
5999 * @param ADCx ADC instance
6000 * @retval Returned value can be one of the following values:
6001 * @arg @ref LL_ADC_OVS_REG_CONT
6002 * @arg @ref LL_ADC_OVS_REG_DISCONT
6003 */
LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef * ADCx)6004 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
6005 {
6006 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
6007 }
6008
6009 /**
6010 * @brief Set ADC oversampling
6011 * (impacting both ADC groups regular and injected)
6012 * @note This function set the 2 items of oversampling configuration:
6013 * - ratio
6014 * - shift
6015 * @note On this STM32 series, setting of this feature is conditioned to
6016 * ADC state:
6017 * ADC must be disabled or enabled without conversion on going
6018 * on either groups regular or injected.
6019 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
6020 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
6021 * @param ADCx ADC instance
6022 * @param Ratio This parameter can be one of the following values:
6023 * @arg @ref LL_ADC_OVS_RATIO_2
6024 * @arg @ref LL_ADC_OVS_RATIO_4
6025 * @arg @ref LL_ADC_OVS_RATIO_8
6026 * @arg @ref LL_ADC_OVS_RATIO_16
6027 * @arg @ref LL_ADC_OVS_RATIO_32
6028 * @arg @ref LL_ADC_OVS_RATIO_64
6029 * @arg @ref LL_ADC_OVS_RATIO_128
6030 * @arg @ref LL_ADC_OVS_RATIO_256
6031 * @param Shift This parameter can be one of the following values:
6032 * @arg @ref LL_ADC_OVS_SHIFT_NONE
6033 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
6034 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
6035 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
6036 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
6037 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
6038 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
6039 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
6040 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
6041 * @retval None
6042 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)6043 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
6044 {
6045 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
6046 }
6047
6048 /**
6049 * @brief Get ADC oversampling ratio
6050 * (impacting both ADC groups regular and injected)
6051 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
6052 * @param ADCx ADC instance
6053 * @retval Ratio This parameter can be one of the following values:
6054 * @arg @ref LL_ADC_OVS_RATIO_2
6055 * @arg @ref LL_ADC_OVS_RATIO_4
6056 * @arg @ref LL_ADC_OVS_RATIO_8
6057 * @arg @ref LL_ADC_OVS_RATIO_16
6058 * @arg @ref LL_ADC_OVS_RATIO_32
6059 * @arg @ref LL_ADC_OVS_RATIO_64
6060 * @arg @ref LL_ADC_OVS_RATIO_128
6061 * @arg @ref LL_ADC_OVS_RATIO_256
6062 */
LL_ADC_GetOverSamplingRatio(const ADC_TypeDef * ADCx)6063 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
6064 {
6065 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
6066 }
6067
6068 /**
6069 * @brief Get ADC oversampling shift
6070 * (impacting both ADC groups regular and injected)
6071 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
6072 * @param ADCx ADC instance
6073 * @retval Shift This parameter can be one of the following values:
6074 * @arg @ref LL_ADC_OVS_SHIFT_NONE
6075 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
6076 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
6077 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
6078 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
6079 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
6080 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
6081 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
6082 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
6083 */
LL_ADC_GetOverSamplingShift(const ADC_TypeDef * ADCx)6084 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
6085 {
6086 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
6087 }
6088
6089 /**
6090 * @}
6091 */
6092
6093 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
6094 * @{
6095 */
6096
6097 #if defined(ADC_MULTIMODE_SUPPORT)
6098 /**
6099 * @brief Set ADC multimode configuration to operate in independent mode
6100 * or multimode (for devices with several ADC instances).
6101 * @note If multimode configuration: the selected ADC instance is
6102 * either master or slave depending on hardware.
6103 * Refer to reference manual.
6104 * @note On this STM32 series, setting of this feature is conditioned to
6105 * ADC state:
6106 * All ADC instances of the ADC common group must be disabled.
6107 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6108 * ADC instance or by using helper macro
6109 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
6110 * @rmtoll CCR DUAL LL_ADC_SetMultimode
6111 * @param ADCxy_COMMON ADC common instance
6112 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6113 * @param Multimode This parameter can be one of the following values:
6114 * @arg @ref LL_ADC_MULTI_INDEPENDENT
6115 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
6116 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
6117 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
6118 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
6119 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
6120 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
6121 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
6122 * @retval None
6123 */
LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)6124 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
6125 {
6126 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
6127 }
6128
6129 /**
6130 * @brief Get ADC multimode configuration to operate in independent mode
6131 * or multimode (for devices with several ADC instances).
6132 * @note If multimode configuration: the selected ADC instance is
6133 * either master or slave depending on hardware.
6134 * Refer to reference manual.
6135 * @rmtoll CCR DUAL LL_ADC_GetMultimode
6136 * @param ADCxy_COMMON ADC common instance
6137 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6138 * @retval Returned value can be one of the following values:
6139 * @arg @ref LL_ADC_MULTI_INDEPENDENT
6140 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
6141 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
6142 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
6143 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
6144 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
6145 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
6146 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
6147 */
LL_ADC_GetMultimode(const ADC_Common_TypeDef * ADCxy_COMMON)6148 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
6149 {
6150 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
6151 }
6152
6153 /**
6154 * @brief Set ADC multimode conversion data transfer: no transfer
6155 * or transfer by DMA.
6156 * @note If ADC multimode transfer by DMA is not selected:
6157 * each ADC uses its own DMA channel, with its individual
6158 * DMA transfer settings.
6159 * If ADC multimode transfer by DMA is selected:
6160 * One DMA channel is used for both ADC (DMA of ADC master)
6161 * Specifies the DMA requests mode:
6162 * - Limited mode (One shot mode): DMA transfer requests are stopped
6163 * when number of DMA data transfers (number of
6164 * ADC conversions) is reached.
6165 * This ADC mode is intended to be used with DMA mode non-circular.
6166 * - Unlimited mode: DMA transfer requests are unlimited,
6167 * whatever number of DMA data transfers (number of
6168 * ADC conversions).
6169 * This ADC mode is intended to be used with DMA mode circular.
6170 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
6171 * mode non-circular:
6172 * when DMA transfers size will be reached, DMA will stop transfers of
6173 * ADC conversions data ADC will raise an overrun error
6174 * (overrun flag and interruption if enabled).
6175 * @note How to retrieve multimode conversion data:
6176 * Whatever multimode transfer by DMA setting: using function
6177 * @ref LL_ADC_REG_ReadMultiConversionData32().
6178 * If ADC multimode transfer by DMA is selected: conversion data
6179 * is a raw data with ADC master and slave concatenated.
6180 * A macro is available to get the conversion data of
6181 * ADC master or ADC slave: see helper macro
6182 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6183 * @note On this STM32 series, setting of this feature is conditioned to
6184 * ADC state:
6185 * All ADC instances of the ADC common group must be disabled
6186 * or enabled without conversion on going on group regular.
6187 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
6188 * CCR DMACFG LL_ADC_SetMultiDMATransfer
6189 * @param ADCxy_COMMON ADC common instance
6190 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6191 * @param MultiDMATransfer This parameter can be one of the following values:
6192 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
6193 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
6194 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
6195 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
6196 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
6197 * @retval None
6198 */
LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDMATransfer)6199 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
6200 {
6201 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
6202 }
6203
6204 /**
6205 * @brief Get ADC multimode conversion data transfer: no transfer
6206 * or transfer by DMA.
6207 * @note If ADC multimode transfer by DMA is not selected:
6208 * each ADC uses its own DMA channel, with its individual
6209 * DMA transfer settings.
6210 * If ADC multimode transfer by DMA is selected:
6211 * One DMA channel is used for both ADC (DMA of ADC master)
6212 * Specifies the DMA requests mode:
6213 * - Limited mode (One shot mode): DMA transfer requests are stopped
6214 * when number of DMA data transfers (number of
6215 * ADC conversions) is reached.
6216 * This ADC mode is intended to be used with DMA mode non-circular.
6217 * - Unlimited mode: DMA transfer requests are unlimited,
6218 * whatever number of DMA data transfers (number of
6219 * ADC conversions).
6220 * This ADC mode is intended to be used with DMA mode circular.
6221 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
6222 * mode non-circular:
6223 * when DMA transfers size will be reached, DMA will stop transfers of
6224 * ADC conversions data ADC will raise an overrun error
6225 * (overrun flag and interruption if enabled).
6226 * @note How to retrieve multimode conversion data:
6227 * Whatever multimode transfer by DMA setting: using function
6228 * @ref LL_ADC_REG_ReadMultiConversionData32().
6229 * If ADC multimode transfer by DMA is selected: conversion data
6230 * is a raw data with ADC master and slave concatenated.
6231 * A macro is available to get the conversion data of
6232 * ADC master or ADC slave: see helper macro
6233 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6234 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
6235 * CCR DMACFG LL_ADC_GetMultiDMATransfer
6236 * @param ADCxy_COMMON ADC common instance
6237 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6238 * @retval Returned value can be one of the following values:
6239 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
6240 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
6241 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
6242 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
6243 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
6244 */
LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef * ADCxy_COMMON)6245 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON)
6246 {
6247 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
6248 }
6249
6250 /**
6251 * @brief Set ADC multimode delay between 2 sampling phases.
6252 * @note The sampling delay range depends on ADC resolution:
6253 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
6254 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
6255 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
6256 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
6257 * @note On this STM32 series, setting of this feature is conditioned to
6258 * ADC state:
6259 * All ADC instances of the ADC common group must be disabled.
6260 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6261 * ADC instance or by using helper macro helper macro
6262 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
6263 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
6264 * @param ADCxy_COMMON ADC common instance
6265 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6266 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
6267 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
6268 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
6269 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
6270 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
6271 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
6272 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
6273 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
6274 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
6275 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
6276 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
6277 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
6278 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
6279 *
6280 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
6281 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
6282 * (3) Parameter available only if ADC resolution is 12 bits.
6283 * @retval None
6284 */
LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)6285 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
6286 {
6287 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
6288 }
6289
6290 /**
6291 * @brief Get ADC multimode delay between 2 sampling phases.
6292 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
6293 * @param ADCxy_COMMON ADC common instance
6294 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6295 * @retval Returned value can be one of the following values:
6296 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
6297 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
6298 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
6299 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
6300 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
6301 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
6302 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
6303 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
6304 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
6305 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
6306 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
6307 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
6308 *
6309 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
6310 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
6311 * (3) Parameter available only if ADC resolution is 12 bits.
6312 */
LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef * ADCxy_COMMON)6313 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON)
6314 {
6315 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
6316 }
6317 #endif /* ADC_MULTIMODE_SUPPORT */
6318
6319 /**
6320 * @}
6321 */
6322 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
6323 * @{
6324 */
6325
6326 /**
6327 * @brief Put ADC instance in deep power down state.
6328 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6329 * state, the internal analog calibration is lost. After exiting from
6330 * deep power down, calibration must be relaunched or calibration factor
6331 * (preliminarily saved) must be set back into calibration register.
6332 * @note On this STM32 series, setting of this feature is conditioned to
6333 * ADC state:
6334 * ADC must be ADC disabled.
6335 * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
6336 * @param ADCx ADC instance
6337 * @retval None
6338 */
LL_ADC_EnableDeepPowerDown(ADC_TypeDef * ADCx)6339 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
6340 {
6341 /* Note: Write register with some additional bits forced to state reset */
6342 /* instead of modifying only the selected bit for this function, */
6343 /* to not interfere with bits with HW property "rs". */
6344 MODIFY_REG(ADCx->CR,
6345 ADC_CR_BITS_PROPERTY_RS,
6346 ADC_CR_DEEPPWD);
6347 }
6348
6349 /**
6350 * @brief Disable ADC deep power down mode.
6351 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6352 * state, the internal analog calibration is lost. After exiting from
6353 * deep power down, calibration must be relaunched or calibration factor
6354 * (preliminarily saved) must be set back into calibration register.
6355 * @note On this STM32 series, setting of this feature is conditioned to
6356 * ADC state:
6357 * ADC must be ADC disabled.
6358 * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
6359 * @param ADCx ADC instance
6360 * @retval None
6361 */
LL_ADC_DisableDeepPowerDown(ADC_TypeDef * ADCx)6362 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
6363 {
6364 /* Note: Write register with some additional bits forced to state reset */
6365 /* instead of modifying only the selected bit for this function, */
6366 /* to not interfere with bits with HW property "rs". */
6367 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
6368 }
6369
6370 /**
6371 * @brief Get the selected ADC instance deep power down state.
6372 * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
6373 * @param ADCx ADC instance
6374 * @retval 0: deep power down is disabled, 1: deep power down is enabled.
6375 */
LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef * ADCx)6376 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
6377 {
6378 return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
6379 }
6380
6381 /**
6382 * @brief Enable ADC instance internal voltage regulator.
6383 * @note On this STM32 series, after ADC internal voltage regulator enable,
6384 * a delay for ADC internal voltage regulator stabilization
6385 * is required before performing a ADC calibration or ADC enable.
6386 * Refer to device datasheet, parameter tADCVREG_STUP.
6387 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
6388 * @note On this STM32 series, setting of this feature is conditioned to
6389 * ADC state:
6390 * ADC must be ADC disabled.
6391 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
6392 * @param ADCx ADC instance
6393 * @retval None
6394 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)6395 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
6396 {
6397 /* Note: Write register with some additional bits forced to state reset */
6398 /* instead of modifying only the selected bit for this function, */
6399 /* to not interfere with bits with HW property "rs". */
6400 MODIFY_REG(ADCx->CR,
6401 ADC_CR_BITS_PROPERTY_RS,
6402 ADC_CR_ADVREGEN);
6403 }
6404
6405 /**
6406 * @brief Disable ADC internal voltage regulator.
6407 * @note On this STM32 series, setting of this feature is conditioned to
6408 * ADC state:
6409 * ADC must be ADC disabled.
6410 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
6411 * @param ADCx ADC instance
6412 * @retval None
6413 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)6414 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
6415 {
6416 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
6417 }
6418
6419 /**
6420 * @brief Get the selected ADC instance internal voltage regulator state.
6421 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
6422 * @param ADCx ADC instance
6423 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
6424 */
LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef * ADCx)6425 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
6426 {
6427 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
6428 }
6429
6430 /**
6431 * @brief Enable the selected ADC instance.
6432 * @note On this STM32 series, after ADC enable, a delay for
6433 * ADC internal analog stabilization is required before performing a
6434 * ADC conversion start.
6435 * Refer to device datasheet, parameter tSTAB.
6436 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6437 * is enabled and when conversion clock is active.
6438 * (not only core clock: this ADC has a dual clock domain)
6439 * @note On this STM32 series, setting of this feature is conditioned to
6440 * ADC state:
6441 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
6442 * @rmtoll CR ADEN LL_ADC_Enable
6443 * @param ADCx ADC instance
6444 * @retval None
6445 */
LL_ADC_Enable(ADC_TypeDef * ADCx)6446 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
6447 {
6448 /* Note: Write register with some additional bits forced to state reset */
6449 /* instead of modifying only the selected bit for this function, */
6450 /* to not interfere with bits with HW property "rs". */
6451 MODIFY_REG(ADCx->CR,
6452 ADC_CR_BITS_PROPERTY_RS,
6453 ADC_CR_ADEN);
6454 }
6455
6456 /**
6457 * @brief Disable the selected ADC instance.
6458 * @note On this STM32 series, setting of this feature is conditioned to
6459 * ADC state:
6460 * ADC must be not disabled. Must be enabled without conversion on going
6461 * on either groups regular or injected.
6462 * @rmtoll CR ADDIS LL_ADC_Disable
6463 * @param ADCx ADC instance
6464 * @retval None
6465 */
LL_ADC_Disable(ADC_TypeDef * ADCx)6466 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
6467 {
6468 /* Note: Write register with some additional bits forced to state reset */
6469 /* instead of modifying only the selected bit for this function, */
6470 /* to not interfere with bits with HW property "rs". */
6471 MODIFY_REG(ADCx->CR,
6472 ADC_CR_BITS_PROPERTY_RS,
6473 ADC_CR_ADDIS);
6474 }
6475
6476 /**
6477 * @brief Get the selected ADC instance enable state.
6478 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6479 * is enabled and when conversion clock is active.
6480 * (not only core clock: this ADC has a dual clock domain)
6481 * @rmtoll CR ADEN LL_ADC_IsEnabled
6482 * @param ADCx ADC instance
6483 * @retval 0: ADC is disabled, 1: ADC is enabled.
6484 */
LL_ADC_IsEnabled(const ADC_TypeDef * ADCx)6485 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
6486 {
6487 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
6488 }
6489
6490 /**
6491 * @brief Get the selected ADC instance disable state.
6492 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
6493 * @param ADCx ADC instance
6494 * @retval 0: no ADC disable command on going.
6495 */
LL_ADC_IsDisableOngoing(const ADC_TypeDef * ADCx)6496 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
6497 {
6498 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
6499 }
6500
6501 /**
6502 * @brief Start ADC calibration in the mode single-ended
6503 * or differential (for devices with differential mode available).
6504 * @note On this STM32 series, a minimum number of ADC clock cycles
6505 * are required between ADC end of calibration and ADC enable.
6506 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
6507 * @note For devices with differential mode available:
6508 * Calibration of offset is specific to each of
6509 * single-ended and differential modes
6510 * (calibration run must be performed for each of these
6511 * differential modes, if used afterwards and if the application
6512 * requires their calibration).
6513 * @note On this STM32 series, setting of this feature is conditioned to
6514 * ADC state:
6515 * ADC must be ADC disabled.
6516 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
6517 * CR ADCALDIF LL_ADC_StartCalibration
6518 * @param ADCx ADC instance
6519 * @param SingleDiff This parameter can be one of the following values:
6520 * @arg @ref LL_ADC_SINGLE_ENDED
6521 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
6522 * @retval None
6523 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx,uint32_t SingleDiff)6524 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
6525 {
6526 /* Note: Write register with some additional bits forced to state reset */
6527 /* instead of modifying only the selected bit for this function, */
6528 /* to not interfere with bits with HW property "rs". */
6529 MODIFY_REG(ADCx->CR,
6530 ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
6531 ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
6532 }
6533
6534 /**
6535 * @brief Get ADC calibration state.
6536 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
6537 * @param ADCx ADC instance
6538 * @retval 0: calibration complete, 1: calibration in progress.
6539 */
LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef * ADCx)6540 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx)
6541 {
6542 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
6543 }
6544
6545 /**
6546 * @}
6547 */
6548
6549 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
6550 * @{
6551 */
6552
6553 /**
6554 * @brief Start ADC group regular conversion.
6555 * @note On this STM32 series, this function is relevant for both
6556 * internal trigger (SW start) and external trigger:
6557 * - If ADC trigger has been set to software start, ADC conversion
6558 * starts immediately.
6559 * - If ADC trigger has been set to external trigger, ADC conversion
6560 * will start at next trigger event (on the selected trigger edge)
6561 * following the ADC start conversion command.
6562 * @note On this STM32 series, setting of this feature is conditioned to
6563 * ADC state:
6564 * ADC must be enabled without conversion on going on group regular,
6565 * without conversion stop command on going on group regular,
6566 * without ADC disable command on going.
6567 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
6568 * @param ADCx ADC instance
6569 * @retval None
6570 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)6571 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
6572 {
6573 /* Note: Write register with some additional bits forced to state reset */
6574 /* instead of modifying only the selected bit for this function, */
6575 /* to not interfere with bits with HW property "rs". */
6576 MODIFY_REG(ADCx->CR,
6577 ADC_CR_BITS_PROPERTY_RS,
6578 ADC_CR_ADSTART);
6579 }
6580
6581 /**
6582 * @brief Stop ADC group regular conversion.
6583 * @note On this STM32 series, setting of this feature is conditioned to
6584 * ADC state:
6585 * ADC must be enabled with conversion on going on group regular,
6586 * without ADC disable command on going.
6587 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
6588 * @param ADCx ADC instance
6589 * @retval None
6590 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)6591 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
6592 {
6593 /* Note: Write register with some additional bits forced to state reset */
6594 /* instead of modifying only the selected bit for this function, */
6595 /* to not interfere with bits with HW property "rs". */
6596 MODIFY_REG(ADCx->CR,
6597 ADC_CR_BITS_PROPERTY_RS,
6598 ADC_CR_ADSTP);
6599 }
6600
6601 /**
6602 * @brief Get ADC group regular conversion state.
6603 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
6604 * @param ADCx ADC instance
6605 * @retval 0: no conversion is on going on ADC group regular.
6606 */
LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef * ADCx)6607 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
6608 {
6609 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
6610 }
6611
6612 /**
6613 * @brief Get ADC group regular command of conversion stop state
6614 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
6615 * @param ADCx ADC instance
6616 * @retval 0: no command of conversion stop is on going on ADC group regular.
6617 */
LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef * ADCx)6618 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
6619 {
6620 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
6621 }
6622
6623 /**
6624 * @brief Get ADC group regular conversion data, range fit for
6625 * all ADC configurations: all ADC resolutions and
6626 * all oversampling increased data width (for devices
6627 * with feature oversampling).
6628 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
6629 * @param ADCx ADC instance
6630 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6631 */
LL_ADC_REG_ReadConversionData32(const ADC_TypeDef * ADCx)6632 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
6633 {
6634 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6635 }
6636
6637 /**
6638 * @brief Get ADC group regular conversion data, range fit for
6639 * ADC resolution 12 bits.
6640 * @note For devices with feature oversampling: Oversampling
6641 * can increase data width, function for extended range
6642 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6643 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
6644 * @param ADCx ADC instance
6645 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6646 */
LL_ADC_REG_ReadConversionData12(const ADC_TypeDef * ADCx)6647 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
6648 {
6649 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6650 }
6651
6652 /**
6653 * @brief Get ADC group regular conversion data, range fit for
6654 * ADC resolution 10 bits.
6655 * @note For devices with feature oversampling: Oversampling
6656 * can increase data width, function for extended range
6657 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6658 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
6659 * @param ADCx ADC instance
6660 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
6661 */
LL_ADC_REG_ReadConversionData10(const ADC_TypeDef * ADCx)6662 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
6663 {
6664 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6665 }
6666
6667 /**
6668 * @brief Get ADC group regular conversion data, range fit for
6669 * ADC resolution 8 bits.
6670 * @note For devices with feature oversampling: Oversampling
6671 * can increase data width, function for extended range
6672 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6673 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
6674 * @param ADCx ADC instance
6675 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
6676 */
LL_ADC_REG_ReadConversionData8(const ADC_TypeDef * ADCx)6677 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
6678 {
6679 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6680 }
6681
6682 /**
6683 * @brief Get ADC group regular conversion data, range fit for
6684 * ADC resolution 6 bits.
6685 * @note For devices with feature oversampling: Oversampling
6686 * can increase data width, function for extended range
6687 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6688 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
6689 * @param ADCx ADC instance
6690 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
6691 */
LL_ADC_REG_ReadConversionData6(const ADC_TypeDef * ADCx)6692 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx)
6693 {
6694 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6695 }
6696
6697 #if defined(ADC_MULTIMODE_SUPPORT)
6698 /**
6699 * @brief Get ADC multimode conversion data of ADC master, ADC slave
6700 * or raw data with ADC master and slave concatenated.
6701 * @note If raw data with ADC master and slave concatenated is retrieved,
6702 * a macro is available to get the conversion data of
6703 * ADC master or ADC slave: see helper macro
6704 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6705 * (however this macro is mainly intended for multimode
6706 * transfer by DMA, because this function can do the same
6707 * by getting multimode conversion data of ADC master or ADC slave
6708 * separately).
6709 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
6710 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
6711 * @param ADCxy_COMMON ADC common instance
6712 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6713 * @param ConversionData This parameter can be one of the following values:
6714 * @arg @ref LL_ADC_MULTI_MASTER
6715 * @arg @ref LL_ADC_MULTI_SLAVE
6716 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
6717 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6718 */
LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef * ADCxy_COMMON,uint32_t ConversionData)6719 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON,
6720 uint32_t ConversionData)
6721 {
6722 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
6723 ConversionData)
6724 >> (POSITION_VAL(ConversionData) & 0x1FUL)
6725 );
6726 }
6727 #endif /* ADC_MULTIMODE_SUPPORT */
6728
6729 /**
6730 * @}
6731 */
6732
6733 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
6734 * @{
6735 */
6736
6737 /**
6738 * @brief Start ADC group injected conversion.
6739 * @note On this STM32 series, this function is relevant for both
6740 * internal trigger (SW start) and external trigger:
6741 * - If ADC trigger has been set to software start, ADC conversion
6742 * starts immediately.
6743 * - If ADC trigger has been set to external trigger, ADC conversion
6744 * will start at next trigger event (on the selected trigger edge)
6745 * following the ADC start conversion command.
6746 * @note On this STM32 series, setting of this feature is conditioned to
6747 * ADC state:
6748 * ADC must be enabled without conversion on going on group injected,
6749 * without conversion stop command on going on group injected,
6750 * without ADC disable command on going.
6751 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
6752 * @param ADCx ADC instance
6753 * @retval None
6754 */
LL_ADC_INJ_StartConversion(ADC_TypeDef * ADCx)6755 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
6756 {
6757 /* Note: Write register with some additional bits forced to state reset */
6758 /* instead of modifying only the selected bit for this function, */
6759 /* to not interfere with bits with HW property "rs". */
6760 MODIFY_REG(ADCx->CR,
6761 ADC_CR_BITS_PROPERTY_RS,
6762 ADC_CR_JADSTART);
6763 }
6764
6765 /**
6766 * @brief Stop ADC group injected conversion.
6767 * @note On this STM32 series, setting of this feature is conditioned to
6768 * ADC state:
6769 * ADC must be enabled with conversion on going on group injected,
6770 * without ADC disable command on going.
6771 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
6772 * @param ADCx ADC instance
6773 * @retval None
6774 */
LL_ADC_INJ_StopConversion(ADC_TypeDef * ADCx)6775 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
6776 {
6777 /* Note: Write register with some additional bits forced to state reset */
6778 /* instead of modifying only the selected bit for this function, */
6779 /* to not interfere with bits with HW property "rs". */
6780 MODIFY_REG(ADCx->CR,
6781 ADC_CR_BITS_PROPERTY_RS,
6782 ADC_CR_JADSTP);
6783 }
6784
6785 /**
6786 * @brief Get ADC group injected conversion state.
6787 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
6788 * @param ADCx ADC instance
6789 * @retval 0: no conversion is on going on ADC group injected.
6790 */
LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef * ADCx)6791 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
6792 {
6793 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
6794 }
6795
6796 /**
6797 * @brief Get ADC group injected command of conversion stop state
6798 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
6799 * @param ADCx ADC instance
6800 * @retval 0: no command of conversion stop is on going on ADC group injected.
6801 */
LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef * ADCx)6802 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
6803 {
6804 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
6805 }
6806
6807 /**
6808 * @brief Get ADC group injected conversion data, range fit for
6809 * all ADC configurations: all ADC resolutions and
6810 * all oversampling increased data width (for devices
6811 * with feature oversampling).
6812 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
6813 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
6814 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
6815 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
6816 * @param ADCx ADC instance
6817 * @param Rank This parameter can be one of the following values:
6818 * @arg @ref LL_ADC_INJ_RANK_1
6819 * @arg @ref LL_ADC_INJ_RANK_2
6820 * @arg @ref LL_ADC_INJ_RANK_3
6821 * @arg @ref LL_ADC_INJ_RANK_4
6822 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6823 */
LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef * ADCx,uint32_t Rank)6824 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank)
6825 {
6826 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
6827 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6828
6829 return (uint32_t)(READ_BIT(*preg,
6830 ADC_JDR1_JDATA)
6831 );
6832 }
6833
6834 /**
6835 * @brief Get ADC group injected conversion data, range fit for
6836 * ADC resolution 12 bits.
6837 * @note For devices with feature oversampling: Oversampling
6838 * can increase data width, function for extended range
6839 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6840 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
6841 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
6842 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
6843 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
6844 * @param ADCx ADC instance
6845 * @param Rank This parameter can be one of the following values:
6846 * @arg @ref LL_ADC_INJ_RANK_1
6847 * @arg @ref LL_ADC_INJ_RANK_2
6848 * @arg @ref LL_ADC_INJ_RANK_3
6849 * @arg @ref LL_ADC_INJ_RANK_4
6850 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6851 */
LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef * ADCx,uint32_t Rank)6852 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank)
6853 {
6854 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
6855 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6856
6857 return (uint16_t)(READ_BIT(*preg,
6858 ADC_JDR1_JDATA)
6859 );
6860 }
6861
6862 /**
6863 * @brief Get ADC group injected conversion data, range fit for
6864 * ADC resolution 10 bits.
6865 * @note For devices with feature oversampling: Oversampling
6866 * can increase data width, function for extended range
6867 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6868 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
6869 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
6870 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
6871 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
6872 * @param ADCx ADC instance
6873 * @param Rank This parameter can be one of the following values:
6874 * @arg @ref LL_ADC_INJ_RANK_1
6875 * @arg @ref LL_ADC_INJ_RANK_2
6876 * @arg @ref LL_ADC_INJ_RANK_3
6877 * @arg @ref LL_ADC_INJ_RANK_4
6878 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
6879 */
LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef * ADCx,uint32_t Rank)6880 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank)
6881 {
6882 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
6883 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6884
6885 return (uint16_t)(READ_BIT(*preg,
6886 ADC_JDR1_JDATA)
6887 );
6888 }
6889
6890 /**
6891 * @brief Get ADC group injected conversion data, range fit for
6892 * ADC resolution 8 bits.
6893 * @note For devices with feature oversampling: Oversampling
6894 * can increase data width, function for extended range
6895 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6896 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
6897 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
6898 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
6899 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
6900 * @param ADCx ADC instance
6901 * @param Rank This parameter can be one of the following values:
6902 * @arg @ref LL_ADC_INJ_RANK_1
6903 * @arg @ref LL_ADC_INJ_RANK_2
6904 * @arg @ref LL_ADC_INJ_RANK_3
6905 * @arg @ref LL_ADC_INJ_RANK_4
6906 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
6907 */
LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef * ADCx,uint32_t Rank)6908 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank)
6909 {
6910 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
6911 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6912
6913 return (uint8_t)(READ_BIT(*preg,
6914 ADC_JDR1_JDATA)
6915 );
6916 }
6917
6918 /**
6919 * @brief Get ADC group injected conversion data, range fit for
6920 * ADC resolution 6 bits.
6921 * @note For devices with feature oversampling: Oversampling
6922 * can increase data width, function for extended range
6923 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6924 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
6925 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
6926 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
6927 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
6928 * @param ADCx ADC instance
6929 * @param Rank This parameter can be one of the following values:
6930 * @arg @ref LL_ADC_INJ_RANK_1
6931 * @arg @ref LL_ADC_INJ_RANK_2
6932 * @arg @ref LL_ADC_INJ_RANK_3
6933 * @arg @ref LL_ADC_INJ_RANK_4
6934 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
6935 */
LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef * ADCx,uint32_t Rank)6936 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef *ADCx, uint32_t Rank)
6937 {
6938 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
6939 ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6940
6941 return (uint8_t)(READ_BIT(*preg,
6942 ADC_JDR1_JDATA)
6943 );
6944 }
6945
6946 /**
6947 * @}
6948 */
6949
6950 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
6951 * @{
6952 */
6953
6954 /**
6955 * @brief Get flag ADC ready.
6956 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6957 * is enabled and when conversion clock is active.
6958 * (not only core clock: this ADC has a dual clock domain)
6959 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
6960 * @param ADCx ADC instance
6961 * @retval State of bit (1 or 0).
6962 */
LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef * ADCx)6963 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
6964 {
6965 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
6966 }
6967
6968 /**
6969 * @brief Get flag ADC group regular end of unitary conversion.
6970 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
6971 * @param ADCx ADC instance
6972 * @retval State of bit (1 or 0).
6973 */
LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef * ADCx)6974 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
6975 {
6976 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
6977 }
6978
6979 /**
6980 * @brief Get flag ADC group regular end of sequence conversions.
6981 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
6982 * @param ADCx ADC instance
6983 * @retval State of bit (1 or 0).
6984 */
LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef * ADCx)6985 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
6986 {
6987 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
6988 }
6989
6990 /**
6991 * @brief Get flag ADC group regular overrun.
6992 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
6993 * @param ADCx ADC instance
6994 * @retval State of bit (1 or 0).
6995 */
LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef * ADCx)6996 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
6997 {
6998 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
6999 }
7000
7001 /**
7002 * @brief Get flag ADC group regular end of sampling phase.
7003 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
7004 * @param ADCx ADC instance
7005 * @retval State of bit (1 or 0).
7006 */
LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef * ADCx)7007 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
7008 {
7009 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
7010 }
7011
7012 /**
7013 * @brief Get flag ADC group injected end of unitary conversion.
7014 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
7015 * @param ADCx ADC instance
7016 * @retval State of bit (1 or 0).
7017 */
LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef * ADCx)7018 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx)
7019 {
7020 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
7021 }
7022
7023 /**
7024 * @brief Get flag ADC group injected end of sequence conversions.
7025 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
7026 * @param ADCx ADC instance
7027 * @retval State of bit (1 or 0).
7028 */
LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef * ADCx)7029 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx)
7030 {
7031 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
7032 }
7033
7034 /**
7035 * @brief Get flag ADC group injected contexts queue overflow.
7036 * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
7037 * @param ADCx ADC instance
7038 * @retval State of bit (1 or 0).
7039 */
LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef * ADCx)7040 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef *ADCx)
7041 {
7042 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
7043 }
7044
7045 /**
7046 * @brief Get flag ADC analog watchdog 1 flag
7047 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
7048 * @param ADCx ADC instance
7049 * @retval State of bit (1 or 0).
7050 */
LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef * ADCx)7051 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
7052 {
7053 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
7054 }
7055
7056 /**
7057 * @brief Get flag ADC analog watchdog 2.
7058 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
7059 * @param ADCx ADC instance
7060 * @retval State of bit (1 or 0).
7061 */
LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef * ADCx)7062 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
7063 {
7064 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
7065 }
7066
7067 /**
7068 * @brief Get flag ADC analog watchdog 3.
7069 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
7070 * @param ADCx ADC instance
7071 * @retval State of bit (1 or 0).
7072 */
LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef * ADCx)7073 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
7074 {
7075 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
7076 }
7077
7078 /**
7079 * @brief Clear flag ADC ready.
7080 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7081 * is enabled and when conversion clock is active.
7082 * (not only core clock: this ADC has a dual clock domain)
7083 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
7084 * @param ADCx ADC instance
7085 * @retval None
7086 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)7087 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
7088 {
7089 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
7090 }
7091
7092 /**
7093 * @brief Clear flag ADC group regular end of unitary conversion.
7094 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
7095 * @param ADCx ADC instance
7096 * @retval None
7097 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)7098 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
7099 {
7100 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
7101 }
7102
7103 /**
7104 * @brief Clear flag ADC group regular end of sequence conversions.
7105 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
7106 * @param ADCx ADC instance
7107 * @retval None
7108 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)7109 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
7110 {
7111 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
7112 }
7113
7114 /**
7115 * @brief Clear flag ADC group regular overrun.
7116 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
7117 * @param ADCx ADC instance
7118 * @retval None
7119 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)7120 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
7121 {
7122 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
7123 }
7124
7125 /**
7126 * @brief Clear flag ADC group regular end of sampling phase.
7127 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
7128 * @param ADCx ADC instance
7129 * @retval None
7130 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)7131 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
7132 {
7133 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
7134 }
7135
7136 /**
7137 * @brief Clear flag ADC group injected end of unitary conversion.
7138 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
7139 * @param ADCx ADC instance
7140 * @retval None
7141 */
LL_ADC_ClearFlag_JEOC(ADC_TypeDef * ADCx)7142 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
7143 {
7144 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
7145 }
7146
7147 /**
7148 * @brief Clear flag ADC group injected end of sequence conversions.
7149 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
7150 * @param ADCx ADC instance
7151 * @retval None
7152 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)7153 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
7154 {
7155 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
7156 }
7157
7158 /**
7159 * @brief Clear flag ADC group injected contexts queue overflow.
7160 * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
7161 * @param ADCx ADC instance
7162 * @retval None
7163 */
LL_ADC_ClearFlag_JQOVF(ADC_TypeDef * ADCx)7164 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
7165 {
7166 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
7167 }
7168
7169 /**
7170 * @brief Clear flag ADC analog watchdog 1.
7171 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
7172 * @param ADCx ADC instance
7173 * @retval None
7174 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)7175 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
7176 {
7177 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
7178 }
7179
7180 /**
7181 * @brief Clear flag ADC analog watchdog 2.
7182 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
7183 * @param ADCx ADC instance
7184 * @retval None
7185 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)7186 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
7187 {
7188 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
7189 }
7190
7191 /**
7192 * @brief Clear flag ADC analog watchdog 3.
7193 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
7194 * @param ADCx ADC instance
7195 * @retval None
7196 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)7197 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
7198 {
7199 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
7200 }
7201
7202 #if defined(ADC_MULTIMODE_SUPPORT)
7203 /**
7204 * @brief Get flag multimode ADC ready of the ADC master.
7205 * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
7206 * @param ADCxy_COMMON ADC common instance
7207 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7208 * @retval State of bit (1 or 0).
7209 */
LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef * ADCxy_COMMON)7210 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
7211 {
7212 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
7213 }
7214
7215 /**
7216 * @brief Get flag multimode ADC ready of the ADC slave.
7217 * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
7218 * @param ADCxy_COMMON ADC common instance
7219 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7220 * @retval State of bit (1 or 0).
7221 */
LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef * ADCxy_COMMON)7222 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
7223 {
7224 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
7225 }
7226
7227 /**
7228 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
7229 * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
7230 * @param ADCxy_COMMON ADC common instance
7231 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7232 * @retval State of bit (1 or 0).
7233 */
LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef * ADCxy_COMMON)7234 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7235 {
7236 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7237 }
7238
7239 /**
7240 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
7241 * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
7242 * @param ADCxy_COMMON ADC common instance
7243 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7244 * @retval State of bit (1 or 0).
7245 */
LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef * ADCxy_COMMON)7246 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7247 {
7248 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7249 }
7250
7251 /**
7252 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
7253 * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
7254 * @param ADCxy_COMMON ADC common instance
7255 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7256 * @retval State of bit (1 or 0).
7257 */
LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef * ADCxy_COMMON)7258 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7259 {
7260 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
7261 }
7262
7263 /**
7264 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
7265 * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
7266 * @param ADCxy_COMMON ADC common instance
7267 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7268 * @retval State of bit (1 or 0).
7269 */
LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef * ADCxy_COMMON)7270 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7271 {
7272 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
7273 }
7274
7275 /**
7276 * @brief Get flag multimode ADC group regular overrun of the ADC master.
7277 * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
7278 * @param ADCxy_COMMON ADC common instance
7279 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7280 * @retval State of bit (1 or 0).
7281 */
LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef * ADCxy_COMMON)7282 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
7283 {
7284 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
7285 }
7286
7287 /**
7288 * @brief Get flag multimode ADC group regular overrun of the ADC slave.
7289 * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
7290 * @param ADCxy_COMMON ADC common instance
7291 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7292 * @retval State of bit (1 or 0).
7293 */
LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef * ADCxy_COMMON)7294 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
7295 {
7296 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
7297 }
7298
7299 /**
7300 * @brief Get flag multimode ADC group regular end of sampling of the ADC master.
7301 * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
7302 * @param ADCxy_COMMON ADC common instance
7303 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7304 * @retval State of bit (1 or 0).
7305 */
LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef * ADCxy_COMMON)7306 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
7307 {
7308 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
7309 }
7310
7311 /**
7312 * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
7313 * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
7314 * @param ADCxy_COMMON ADC common instance
7315 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7316 * @retval State of bit (1 or 0).
7317 */
LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef * ADCxy_COMMON)7318 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
7319 {
7320 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
7321 }
7322
7323 /**
7324 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
7325 * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
7326 * @param ADCxy_COMMON ADC common instance
7327 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7328 * @retval State of bit (1 or 0).
7329 */
LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef * ADCxy_COMMON)7330 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7331 {
7332 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
7333 }
7334
7335 /**
7336 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
7337 * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
7338 * @param ADCxy_COMMON ADC common instance
7339 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7340 * @retval State of bit (1 or 0).
7341 */
LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef * ADCxy_COMMON)7342 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
7343 {
7344 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
7345 }
7346
7347 /**
7348 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
7349 * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
7350 * @param ADCxy_COMMON ADC common instance
7351 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7352 * @retval State of bit (1 or 0).
7353 */
LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef * ADCxy_COMMON)7354 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7355 {
7356 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
7357 }
7358
7359 /**
7360 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
7361 * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
7362 * @param ADCxy_COMMON ADC common instance
7363 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7364 * @retval State of bit (1 or 0).
7365 */
LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef * ADCxy_COMMON)7366 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
7367 {
7368 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
7369 }
7370
7371 /**
7372 * @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
7373 * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
7374 * @param ADCxy_COMMON ADC common instance
7375 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7376 * @retval State of bit (1 or 0).
7377 */
LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef * ADCxy_COMMON)7378 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON)
7379 {
7380 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
7381 }
7382
7383 /**
7384 * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
7385 * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
7386 * @param ADCxy_COMMON ADC common instance
7387 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7388 * @retval State of bit (1 or 0).
7389 */
LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef * ADCxy_COMMON)7390 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON)
7391 {
7392 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
7393 }
7394
7395 /**
7396 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
7397 * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
7398 * @param ADCxy_COMMON ADC common instance
7399 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7400 * @retval State of bit (1 or 0).
7401 */
LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef * ADCxy_COMMON)7402 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
7403 {
7404 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
7405 }
7406
7407 /**
7408 * @brief Get flag multimode analog watchdog 1 of the ADC slave.
7409 * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
7410 * @param ADCxy_COMMON ADC common instance
7411 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7412 * @retval State of bit (1 or 0).
7413 */
LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef * ADCxy_COMMON)7414 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
7415 {
7416 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
7417 }
7418
7419 /**
7420 * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
7421 * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
7422 * @param ADCxy_COMMON ADC common instance
7423 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7424 * @retval State of bit (1 or 0).
7425 */
LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef * ADCxy_COMMON)7426 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
7427 {
7428 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
7429 }
7430
7431 /**
7432 * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
7433 * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
7434 * @param ADCxy_COMMON ADC common instance
7435 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7436 * @retval State of bit (1 or 0).
7437 */
LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef * ADCxy_COMMON)7438 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
7439 {
7440 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
7441 }
7442
7443 /**
7444 * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
7445 * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
7446 * @param ADCxy_COMMON ADC common instance
7447 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7448 * @retval State of bit (1 or 0).
7449 */
LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef * ADCxy_COMMON)7450 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
7451 {
7452 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
7453 }
7454
7455 /**
7456 * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
7457 * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
7458 * @param ADCxy_COMMON ADC common instance
7459 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7460 * @retval State of bit (1 or 0).
7461 */
LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef * ADCxy_COMMON)7462 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
7463 {
7464 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
7465 }
7466 #endif /* ADC_MULTIMODE_SUPPORT */
7467
7468 /**
7469 * @}
7470 */
7471
7472 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
7473 * @{
7474 */
7475
7476 /**
7477 * @brief Enable ADC ready.
7478 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
7479 * @param ADCx ADC instance
7480 * @retval None
7481 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)7482 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
7483 {
7484 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7485 }
7486
7487 /**
7488 * @brief Enable interruption ADC group regular end of unitary conversion.
7489 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
7490 * @param ADCx ADC instance
7491 * @retval None
7492 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)7493 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
7494 {
7495 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
7496 }
7497
7498 /**
7499 * @brief Enable interruption ADC group regular end of sequence conversions.
7500 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
7501 * @param ADCx ADC instance
7502 * @retval None
7503 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)7504 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
7505 {
7506 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
7507 }
7508
7509 /**
7510 * @brief Enable ADC group regular interruption overrun.
7511 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
7512 * @param ADCx ADC instance
7513 * @retval None
7514 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)7515 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
7516 {
7517 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
7518 }
7519
7520 /**
7521 * @brief Enable interruption ADC group regular end of sampling.
7522 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
7523 * @param ADCx ADC instance
7524 * @retval None
7525 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)7526 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
7527 {
7528 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7529 }
7530
7531 /**
7532 * @brief Enable interruption ADC group injected end of unitary conversion.
7533 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
7534 * @param ADCx ADC instance
7535 * @retval None
7536 */
LL_ADC_EnableIT_JEOC(ADC_TypeDef * ADCx)7537 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
7538 {
7539 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7540 }
7541
7542 /**
7543 * @brief Enable interruption ADC group injected end of sequence conversions.
7544 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
7545 * @param ADCx ADC instance
7546 * @retval None
7547 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)7548 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
7549 {
7550 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7551 }
7552
7553 /**
7554 * @brief Enable interruption ADC group injected context queue overflow.
7555 * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
7556 * @param ADCx ADC instance
7557 * @retval None
7558 */
LL_ADC_EnableIT_JQOVF(ADC_TypeDef * ADCx)7559 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
7560 {
7561 SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7562 }
7563
7564 /**
7565 * @brief Enable interruption ADC analog watchdog 1.
7566 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
7567 * @param ADCx ADC instance
7568 * @retval None
7569 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)7570 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
7571 {
7572 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7573 }
7574
7575 /**
7576 * @brief Enable interruption ADC analog watchdog 2.
7577 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
7578 * @param ADCx ADC instance
7579 * @retval None
7580 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)7581 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
7582 {
7583 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7584 }
7585
7586 /**
7587 * @brief Enable interruption ADC analog watchdog 3.
7588 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
7589 * @param ADCx ADC instance
7590 * @retval None
7591 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)7592 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
7593 {
7594 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7595 }
7596
7597 /**
7598 * @brief Disable interruption ADC ready.
7599 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
7600 * @param ADCx ADC instance
7601 * @retval None
7602 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)7603 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
7604 {
7605 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7606 }
7607
7608 /**
7609 * @brief Disable interruption ADC group regular end of unitary conversion.
7610 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
7611 * @param ADCx ADC instance
7612 * @retval None
7613 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)7614 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
7615 {
7616 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
7617 }
7618
7619 /**
7620 * @brief Disable interruption ADC group regular end of sequence conversions.
7621 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
7622 * @param ADCx ADC instance
7623 * @retval None
7624 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)7625 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
7626 {
7627 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
7628 }
7629
7630 /**
7631 * @brief Disable interruption ADC group regular overrun.
7632 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
7633 * @param ADCx ADC instance
7634 * @retval None
7635 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)7636 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
7637 {
7638 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
7639 }
7640
7641 /**
7642 * @brief Disable interruption ADC group regular end of sampling.
7643 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
7644 * @param ADCx ADC instance
7645 * @retval None
7646 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)7647 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
7648 {
7649 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7650 }
7651
7652 /**
7653 * @brief Disable interruption ADC group regular end of unitary conversion.
7654 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
7655 * @param ADCx ADC instance
7656 * @retval None
7657 */
LL_ADC_DisableIT_JEOC(ADC_TypeDef * ADCx)7658 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
7659 {
7660 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7661 }
7662
7663 /**
7664 * @brief Disable interruption ADC group injected end of sequence conversions.
7665 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
7666 * @param ADCx ADC instance
7667 * @retval None
7668 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)7669 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
7670 {
7671 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7672 }
7673
7674 /**
7675 * @brief Disable interruption ADC group injected context queue overflow.
7676 * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
7677 * @param ADCx ADC instance
7678 * @retval None
7679 */
LL_ADC_DisableIT_JQOVF(ADC_TypeDef * ADCx)7680 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
7681 {
7682 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7683 }
7684
7685 /**
7686 * @brief Disable interruption ADC analog watchdog 1.
7687 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
7688 * @param ADCx ADC instance
7689 * @retval None
7690 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)7691 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
7692 {
7693 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7694 }
7695
7696 /**
7697 * @brief Disable interruption ADC analog watchdog 2.
7698 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
7699 * @param ADCx ADC instance
7700 * @retval None
7701 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)7702 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
7703 {
7704 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7705 }
7706
7707 /**
7708 * @brief Disable interruption ADC analog watchdog 3.
7709 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
7710 * @param ADCx ADC instance
7711 * @retval None
7712 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)7713 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
7714 {
7715 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7716 }
7717
7718 /**
7719 * @brief Get state of interruption ADC ready
7720 * (0: interrupt disabled, 1: interrupt enabled).
7721 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
7722 * @param ADCx ADC instance
7723 * @retval State of bit (1 or 0).
7724 */
LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef * ADCx)7725 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
7726 {
7727 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
7728 }
7729
7730 /**
7731 * @brief Get state of interruption ADC group regular end of unitary conversion
7732 * (0: interrupt disabled, 1: interrupt enabled).
7733 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
7734 * @param ADCx ADC instance
7735 * @retval State of bit (1 or 0).
7736 */
LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef * ADCx)7737 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
7738 {
7739 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
7740 }
7741
7742 /**
7743 * @brief Get state of interruption ADC group regular end of sequence conversions
7744 * (0: interrupt disabled, 1: interrupt enabled).
7745 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
7746 * @param ADCx ADC instance
7747 * @retval State of bit (1 or 0).
7748 */
LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef * ADCx)7749 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
7750 {
7751 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
7752 }
7753
7754 /**
7755 * @brief Get state of interruption ADC group regular overrun
7756 * (0: interrupt disabled, 1: interrupt enabled).
7757 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
7758 * @param ADCx ADC instance
7759 * @retval State of bit (1 or 0).
7760 */
LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef * ADCx)7761 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
7762 {
7763 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
7764 }
7765
7766 /**
7767 * @brief Get state of interruption ADC group regular end of sampling
7768 * (0: interrupt disabled, 1: interrupt enabled).
7769 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
7770 * @param ADCx ADC instance
7771 * @retval State of bit (1 or 0).
7772 */
LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef * ADCx)7773 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
7774 {
7775 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
7776 }
7777
7778 /**
7779 * @brief Get state of interruption ADC group injected end of unitary conversion
7780 * (0: interrupt disabled, 1: interrupt enabled).
7781 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
7782 * @param ADCx ADC instance
7783 * @retval State of bit (1 or 0).
7784 */
LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef * ADCx)7785 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx)
7786 {
7787 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
7788 }
7789
7790 /**
7791 * @brief Get state of interruption ADC group injected end of sequence conversions
7792 * (0: interrupt disabled, 1: interrupt enabled).
7793 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
7794 * @param ADCx ADC instance
7795 * @retval State of bit (1 or 0).
7796 */
LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef * ADCx)7797 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx)
7798 {
7799 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
7800 }
7801
7802 /**
7803 * @brief Get state of interruption ADC group injected context queue overflow interrupt state
7804 * (0: interrupt disabled, 1: interrupt enabled).
7805 * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
7806 * @param ADCx ADC instance
7807 * @retval State of bit (1 or 0).
7808 */
LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef * ADCx)7809 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef *ADCx)
7810 {
7811 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
7812 }
7813
7814 /**
7815 * @brief Get state of interruption ADC analog watchdog 1
7816 * (0: interrupt disabled, 1: interrupt enabled).
7817 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
7818 * @param ADCx ADC instance
7819 * @retval State of bit (1 or 0).
7820 */
LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef * ADCx)7821 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
7822 {
7823 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
7824 }
7825
7826 /**
7827 * @brief Get state of interruption Get ADC analog watchdog 2
7828 * (0: interrupt disabled, 1: interrupt enabled).
7829 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
7830 * @param ADCx ADC instance
7831 * @retval State of bit (1 or 0).
7832 */
LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef * ADCx)7833 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
7834 {
7835 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
7836 }
7837
7838 /**
7839 * @brief Get state of interruption Get ADC analog watchdog 3
7840 * (0: interrupt disabled, 1: interrupt enabled).
7841 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
7842 * @param ADCx ADC instance
7843 * @retval State of bit (1 or 0).
7844 */
LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef * ADCx)7845 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
7846 {
7847 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
7848 }
7849
7850 /**
7851 * @}
7852 */
7853
7854 #if defined(USE_FULL_LL_DRIVER)
7855 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
7856 * @{
7857 */
7858
7859 /* Initialization of some features of ADC common parameters and multimode */
7860 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
7861 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
7862 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
7863
7864 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
7865 /* (availability of ADC group injected depends on STM32 series) */
7866 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
7867
7868 /* Initialization of some features of ADC instance */
7869 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct);
7870 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct);
7871
7872 /* Initialization of some features of ADC instance and ADC group regular */
7873 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
7874 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
7875
7876 /* Initialization of some features of ADC instance and ADC group injected */
7877 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
7878 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
7879
7880 /**
7881 * @}
7882 */
7883 #endif /* USE_FULL_LL_DRIVER */
7884
7885 /**
7886 * @}
7887 */
7888
7889 /**
7890 * @}
7891 */
7892
7893 #endif /* ADC1 || ADC2 */
7894
7895 /**
7896 * @}
7897 */
7898
7899 #ifdef __cplusplus
7900 }
7901 #endif
7902
7903 #endif /* STM32L5xx_LL_ADC_H */
7904
