1 /**
2   ******************************************************************************
3   * @file    stm32l5xx_hal_smbus.h
4   * @author  MCD Application Team
5   * @brief   Header file of SMBUS HAL module.
6   ******************************************************************************
7   * @attention
8   *
9   * Copyright (c) 2019 STMicroelectronics.
10   * All rights reserved.
11   *
12   * This software is licensed under terms that can be found in the LICENSE file
13   * in the root directory of this software component.
14   * If no LICENSE file comes with this software, it is provided AS-IS.
15   *
16   ******************************************************************************
17   */
18 
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L5xx_HAL_SMBUS_H
21 #define STM32L5xx_HAL_SMBUS_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l5xx_hal_def.h"
29 
30 /** @addtogroup STM32L5xx_HAL_Driver
31   * @{
32   */
33 
34 /** @addtogroup SMBUS
35   * @{
36   */
37 
38 /* Exported types ------------------------------------------------------------*/
39 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types
40   * @{
41   */
42 
43 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
44   * @brief  SMBUS Configuration Structure definition
45   * @{
46   */
47 typedef struct
48 {
49   uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.
50                                         This parameter calculated by referring to SMBUS initialization section
51                                         in Reference manual */
52   uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.
53                                         This parameter can be a value of @ref SMBUS_Analog_Filter */
54 
55   uint32_t OwnAddress1;            /*!< Specifies the first device own address.
56                                         This parameter can be a 7-bit or 10-bit address. */
57 
58   uint32_t AddressingMode;         /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
59                                         This parameter can be a value of @ref SMBUS_addressing_mode */
60 
61   uint32_t DualAddressMode;        /*!< Specifies if dual addressing mode is selected.
62                                         This parameter can be a value of @ref SMBUS_dual_addressing_mode */
63 
64   uint32_t OwnAddress2;            /*!< Specifies the second device own address if dual addressing mode is selected
65                                         This parameter can be a 7-bit address. */
66 
67   uint32_t OwnAddress2Masks;       /*!< Specifies the acknowledge mask address second device own address
68                                         if dual addressing mode is selected
69                                         This parameter can be a value of @ref SMBUS_own_address2_masks. */
70 
71   uint32_t GeneralCallMode;        /*!< Specifies if general call mode is selected.
72                                         This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
73 
74   uint32_t NoStretchMode;          /*!< Specifies if nostretch mode is selected.
75                                         This parameter can be a value of @ref SMBUS_nostretch_mode */
76 
77   uint32_t PacketErrorCheckMode;   /*!< Specifies if Packet Error Check mode is selected.
78                                         This parameter can be a value of @ref SMBUS_packet_error_check_mode */
79 
80   uint32_t PeripheralMode;         /*!< Specifies which mode of Periphal is selected.
81                                         This parameter can be a value of @ref SMBUS_peripheral_mode */
82 
83   uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
84                                         (Enable bits and different timeout values)
85                                         This parameter calculated by referring to SMBUS initialization section
86                                         in Reference manual */
87 } SMBUS_InitTypeDef;
88 /**
89   * @}
90   */
91 
92 /** @defgroup HAL_state_definition HAL state definition
93   * @brief  HAL State definition
94   * @{
95   */
96 #define HAL_SMBUS_STATE_RESET           (0x00000000U)  /*!< SMBUS not yet initialized or disabled         */
97 #define HAL_SMBUS_STATE_READY           (0x00000001U)  /*!< SMBUS initialized and ready for use           */
98 #define HAL_SMBUS_STATE_BUSY            (0x00000002U)  /*!< SMBUS internal process is ongoing             */
99 #define HAL_SMBUS_STATE_MASTER_BUSY_TX  (0x00000012U)  /*!< Master Data Transmission process is ongoing   */
100 #define HAL_SMBUS_STATE_MASTER_BUSY_RX  (0x00000022U)  /*!< Master Data Reception process is ongoing      */
101 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX   (0x00000032U)  /*!< Slave Data Transmission process is ongoing    */
102 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX   (0x00000042U)  /*!< Slave Data Reception process is ongoing       */
103 #define HAL_SMBUS_STATE_TIMEOUT         (0x00000003U)  /*!< Timeout state                                 */
104 #define HAL_SMBUS_STATE_ERROR           (0x00000004U)  /*!< Reception process is ongoing                  */
105 #define HAL_SMBUS_STATE_LISTEN          (0x00000008U)  /*!< Address Listen Mode is ongoing                */
106 /**
107   * @}
108   */
109 
110 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
111   * @brief  SMBUS Error Code definition
112   * @{
113   */
114 #define HAL_SMBUS_ERROR_NONE            (0x00000000U)    /*!< No error             */
115 #define HAL_SMBUS_ERROR_BERR            (0x00000001U)    /*!< BERR error           */
116 #define HAL_SMBUS_ERROR_ARLO            (0x00000002U)    /*!< ARLO error           */
117 #define HAL_SMBUS_ERROR_ACKF            (0x00000004U)    /*!< ACKF error           */
118 #define HAL_SMBUS_ERROR_OVR             (0x00000008U)    /*!< OVR error            */
119 #define HAL_SMBUS_ERROR_HALTIMEOUT      (0x00000010U)    /*!< Timeout error        */
120 #define HAL_SMBUS_ERROR_BUSTIMEOUT      (0x00000020U)    /*!< Bus Timeout error    */
121 #define HAL_SMBUS_ERROR_ALERT           (0x00000040U)    /*!< Alert error          */
122 #define HAL_SMBUS_ERROR_PECERR          (0x00000080U)    /*!< PEC error            */
123 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
124 #define HAL_SMBUS_ERROR_INVALID_CALLBACK  (0x00000100U)  /*!< Invalid Callback error   */
125 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
126 #define HAL_SMBUS_ERROR_INVALID_PARAM    (0x00000200U)   /*!< Invalid Parameters error */
127 /**
128   * @}
129   */
130 
131 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
132   * @brief  SMBUS handle Structure definition
133   * @{
134   */
135 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
136 typedef struct __SMBUS_HandleTypeDef
137 #else
138 typedef struct
139 #endif  /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
140 {
141   I2C_TypeDef                  *Instance;       /*!< SMBUS registers base address       */
142 
143   SMBUS_InitTypeDef            Init;            /*!< SMBUS communication parameters     */
144 
145   uint8_t                      *pBuffPtr;       /*!< Pointer to SMBUS transfer buffer   */
146 
147   uint16_t                     XferSize;        /*!< SMBUS transfer size                */
148 
149   __IO uint16_t                XferCount;       /*!< SMBUS transfer counter             */
150 
151   __IO uint32_t                XferOptions;     /*!< SMBUS transfer options             */
152 
153   __IO uint32_t                PreviousState;   /*!< SMBUS communication Previous state */
154 
155   HAL_LockTypeDef              Lock;            /*!< SMBUS locking object               */
156 
157   __IO uint32_t                State;           /*!< SMBUS communication state          */
158 
159   __IO uint32_t                ErrorCode;       /*!< SMBUS Error code                   */
160 
161 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
162   void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
163   /*!< SMBUS Master Tx Transfer completed callback */
164   void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
165   /*!< SMBUS Master Rx Transfer completed callback */
166   void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
167   /*!< SMBUS Slave Tx Transfer completed callback  */
168   void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
169   /*!< SMBUS Slave Rx Transfer completed callback  */
170   void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
171   /*!< SMBUS Listen Complete callback              */
172   void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
173   /*!< SMBUS Error callback                        */
174 
175   void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
176   /*!< SMBUS Slave Address Match callback */
177 
178   void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
179   /*!< SMBUS Msp Init callback                     */
180   void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
181   /*!< SMBUS Msp DeInit callback                   */
182 
183 #endif  /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
184 } SMBUS_HandleTypeDef;
185 
186 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
187 /**
188   * @brief  HAL SMBUS Callback ID enumeration definition
189   */
190 typedef enum
191 {
192   HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< SMBUS Master Tx Transfer completed callback ID  */
193   HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< SMBUS Master Rx Transfer completed callback ID  */
194   HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< SMBUS Slave Tx Transfer completed callback ID   */
195   HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< SMBUS Slave Rx Transfer completed callback ID   */
196   HAL_SMBUS_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< SMBUS Listen Complete callback ID               */
197   HAL_SMBUS_ERROR_CB_ID                   = 0x05U,    /*!< SMBUS Error callback ID                         */
198 
199   HAL_SMBUS_MSPINIT_CB_ID                 = 0x06U,    /*!< SMBUS Msp Init callback ID                      */
200   HAL_SMBUS_MSPDEINIT_CB_ID               = 0x07U     /*!< SMBUS Msp DeInit callback ID                    */
201 
202 } HAL_SMBUS_CallbackIDTypeDef;
203 
204 /**
205   * @brief  HAL SMBUS Callback pointer definition
206   */
207 typedef  void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus);
208 /*!< pointer to an SMBUS callback function */
209 typedef  void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
210                                             uint16_t AddrMatchCode);
211 /*!< pointer to an SMBUS Address Match callback function */
212 
213 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
214 /**
215   * @}
216   */
217 
218 /**
219   * @}
220   */
221 /* Exported constants --------------------------------------------------------*/
222 
223 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
224   * @{
225   */
226 
227 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
228   * @{
229   */
230 #define SMBUS_ANALOGFILTER_ENABLE               (0x00000000U)
231 #define SMBUS_ANALOGFILTER_DISABLE              I2C_CR1_ANFOFF
232 /**
233   * @}
234   */
235 
236 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode
237   * @{
238   */
239 #define SMBUS_ADDRESSINGMODE_7BIT               (0x00000001U)
240 #define SMBUS_ADDRESSINGMODE_10BIT              (0x00000002U)
241 /**
242   * @}
243   */
244 
245 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
246   * @{
247   */
248 
249 #define SMBUS_DUALADDRESS_DISABLE               (0x00000000U)
250 #define SMBUS_DUALADDRESS_ENABLE                I2C_OAR2_OA2EN
251 /**
252   * @}
253   */
254 
255 /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
256   * @{
257   */
258 
259 #define SMBUS_OA2_NOMASK                        ((uint8_t)0x00U)
260 #define SMBUS_OA2_MASK01                        ((uint8_t)0x01U)
261 #define SMBUS_OA2_MASK02                        ((uint8_t)0x02U)
262 #define SMBUS_OA2_MASK03                        ((uint8_t)0x03U)
263 #define SMBUS_OA2_MASK04                        ((uint8_t)0x04U)
264 #define SMBUS_OA2_MASK05                        ((uint8_t)0x05U)
265 #define SMBUS_OA2_MASK06                        ((uint8_t)0x06U)
266 #define SMBUS_OA2_MASK07                        ((uint8_t)0x07U)
267 /**
268   * @}
269   */
270 
271 
272 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
273   * @{
274   */
275 #define SMBUS_GENERALCALL_DISABLE               (0x00000000U)
276 #define SMBUS_GENERALCALL_ENABLE                I2C_CR1_GCEN
277 /**
278   * @}
279   */
280 
281 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
282   * @{
283   */
284 #define SMBUS_NOSTRETCH_DISABLE                 (0x00000000U)
285 #define SMBUS_NOSTRETCH_ENABLE                  I2C_CR1_NOSTRETCH
286 /**
287   * @}
288   */
289 
290 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
291   * @{
292   */
293 #define SMBUS_PEC_DISABLE                       (0x00000000U)
294 #define SMBUS_PEC_ENABLE                        I2C_CR1_PECEN
295 /**
296   * @}
297   */
298 
299 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
300   * @{
301   */
302 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST        I2C_CR1_SMBHEN
303 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE       (0x00000000U)
304 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP   I2C_CR1_SMBDEN
305 /**
306   * @}
307   */
308 
309 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
310   * @{
311   */
312 
313 #define  SMBUS_SOFTEND_MODE                     (0x00000000U)
314 #define  SMBUS_RELOAD_MODE                      I2C_CR2_RELOAD
315 #define  SMBUS_AUTOEND_MODE                     I2C_CR2_AUTOEND
316 #define  SMBUS_SENDPEC_MODE                     I2C_CR2_PECBYTE
317 /**
318   * @}
319   */
320 
321 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
322   * @{
323   */
324 
325 #define  SMBUS_NO_STARTSTOP                     (0x00000000U)
326 #define  SMBUS_GENERATE_STOP                    (uint32_t)(0x80000000U | I2C_CR2_STOP)
327 #define  SMBUS_GENERATE_START_READ              (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
328 #define  SMBUS_GENERATE_START_WRITE             (uint32_t)(0x80000000U | I2C_CR2_START)
329 /**
330   * @}
331   */
332 
333 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
334   * @{
335   */
336 
337 /* List of XferOptions in usage of :
338  * 1- Restart condition when direction change
339  * 2- No Restart condition in other use cases
340  */
341 #define  SMBUS_FIRST_FRAME                      SMBUS_SOFTEND_MODE
342 #define  SMBUS_NEXT_FRAME                       ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
343 #define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE
344 #define  SMBUS_LAST_FRAME_NO_PEC                SMBUS_AUTOEND_MODE
345 #define  SMBUS_FIRST_FRAME_WITH_PEC             ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
346 #define  SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC    ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
347 #define  SMBUS_LAST_FRAME_WITH_PEC              ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
348 
349 /* List of XferOptions in usage of :
350  * 1- Restart condition in all use cases (direction change or not)
351  */
352 #define  SMBUS_OTHER_FRAME_NO_PEC               (0x000000AAU)
353 #define  SMBUS_OTHER_FRAME_WITH_PEC             (0x0000AA00U)
354 #define  SMBUS_OTHER_AND_LAST_FRAME_NO_PEC      (0x00AA0000U)
355 #define  SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC    (0xAA000000U)
356 /**
357   * @}
358   */
359 
360 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
361   * @brief SMBUS Interrupt definition
362   *        Elements values convention: 0xXXXXXXXX
363   *           - XXXXXXXX  : Interrupt control mask
364   * @{
365   */
366 #define SMBUS_IT_ERRI                           I2C_CR1_ERRIE
367 #define SMBUS_IT_TCI                            I2C_CR1_TCIE
368 #define SMBUS_IT_STOPI                          I2C_CR1_STOPIE
369 #define SMBUS_IT_NACKI                          I2C_CR1_NACKIE
370 #define SMBUS_IT_ADDRI                          I2C_CR1_ADDRIE
371 #define SMBUS_IT_RXI                            I2C_CR1_RXIE
372 #define SMBUS_IT_TXI                            I2C_CR1_TXIE
373 #define SMBUS_IT_TX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
374                                                  SMBUS_IT_NACKI | SMBUS_IT_TXI)
375 #define SMBUS_IT_RX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
376                                                  SMBUS_IT_RXI)
377 #define SMBUS_IT_ALERT                          (SMBUS_IT_ERRI)
378 #define SMBUS_IT_ADDR                           (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
379 /**
380   * @}
381   */
382 
383 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition
384   * @brief Flag definition
385   *        Elements values convention: 0xXXXXYYYY
386   *           - XXXXXXXX  : Flag mask
387   * @{
388   */
389 
390 #define  SMBUS_FLAG_TXE                         I2C_ISR_TXE
391 #define  SMBUS_FLAG_TXIS                        I2C_ISR_TXIS
392 #define  SMBUS_FLAG_RXNE                        I2C_ISR_RXNE
393 #define  SMBUS_FLAG_ADDR                        I2C_ISR_ADDR
394 #define  SMBUS_FLAG_AF                          I2C_ISR_NACKF
395 #define  SMBUS_FLAG_STOPF                       I2C_ISR_STOPF
396 #define  SMBUS_FLAG_TC                          I2C_ISR_TC
397 #define  SMBUS_FLAG_TCR                         I2C_ISR_TCR
398 #define  SMBUS_FLAG_BERR                        I2C_ISR_BERR
399 #define  SMBUS_FLAG_ARLO                        I2C_ISR_ARLO
400 #define  SMBUS_FLAG_OVR                         I2C_ISR_OVR
401 #define  SMBUS_FLAG_PECERR                      I2C_ISR_PECERR
402 #define  SMBUS_FLAG_TIMEOUT                     I2C_ISR_TIMEOUT
403 #define  SMBUS_FLAG_ALERT                       I2C_ISR_ALERT
404 #define  SMBUS_FLAG_BUSY                        I2C_ISR_BUSY
405 #define  SMBUS_FLAG_DIR                         I2C_ISR_DIR
406 /**
407   * @}
408   */
409 
410 /**
411   * @}
412   */
413 
414 /* Exported macros ------------------------------------------------------------*/
415 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
416   * @{
417   */
418 
419 /** @brief  Reset SMBUS handle state.
420   * @param  __HANDLE__ specifies the SMBUS Handle.
421   * @retval None
422   */
423 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
424 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)           do{                                               \
425                                                                  (__HANDLE__)->State = HAL_SMBUS_STATE_RESET;  \
426                                                                  (__HANDLE__)->MspInitCallback = NULL;            \
427                                                                  (__HANDLE__)->MspDeInitCallback = NULL;          \
428                                                                } while(0)
429 #else
430 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)         ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
431 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
432 
433 /** @brief  Enable the specified SMBUS interrupts.
434   * @param  __HANDLE__ specifies the SMBUS Handle.
435   * @param  __INTERRUPT__ specifies the interrupt source to enable.
436   *        This parameter can be one of the following values:
437   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
438   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
439   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
440   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
441   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
442   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
443   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
444   *
445   * @retval None
446   */
447 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
448 
449 /** @brief  Disable the specified SMBUS interrupts.
450   * @param  __HANDLE__ specifies the SMBUS Handle.
451   * @param  __INTERRUPT__ specifies the interrupt source to disable.
452   *        This parameter can be one of the following values:
453   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
454   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
455   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
456   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
457   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
458   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
459   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
460   *
461   * @retval None
462   */
463 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
464 
465 /** @brief  Check whether the specified SMBUS interrupt source is enabled or not.
466   * @param  __HANDLE__ specifies the SMBUS Handle.
467   * @param  __INTERRUPT__ specifies the SMBUS interrupt source to check.
468   *          This parameter can be one of the following values:
469   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
470   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
471   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
472   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
473   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
474   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
475   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
476   *
477   * @retval The new state of __IT__ (SET or RESET).
478   */
479 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
480   ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
481 
482 /** @brief  Check whether the specified SMBUS flag is set or not.
483   * @param  __HANDLE__ specifies the SMBUS Handle.
484   * @param  __FLAG__ specifies the flag to check.
485   *        This parameter can be one of the following values:
486   *            @arg @ref SMBUS_FLAG_TXE     Transmit data register empty
487   *            @arg @ref SMBUS_FLAG_TXIS    Transmit interrupt status
488   *            @arg @ref SMBUS_FLAG_RXNE    Receive data register not empty
489   *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
490   *            @arg @ref SMBUS_FLAG_AF      NACK received flag
491   *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
492   *            @arg @ref SMBUS_FLAG_TC      Transfer complete (master mode)
493   *            @arg @ref SMBUS_FLAG_TCR     Transfer complete reload
494   *            @arg @ref SMBUS_FLAG_BERR    Bus error
495   *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
496   *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
497   *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
498   *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
499   *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
500   *            @arg @ref SMBUS_FLAG_BUSY    Bus busy
501   *            @arg @ref SMBUS_FLAG_DIR     Transfer direction (slave mode)
502   *
503   * @retval The new state of __FLAG__ (SET or RESET).
504   */
505 #define SMBUS_FLAG_MASK  (0x0001FFFFU)
506 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
507   (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
508     ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
509 
510 /** @brief  Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
511   * @param  __HANDLE__ specifies the SMBUS Handle.
512   * @param  __FLAG__ specifies the flag to clear.
513   *          This parameter can be any combination of the following values:
514   *            @arg @ref SMBUS_FLAG_TXE     Transmit data register empty
515   *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
516   *            @arg @ref SMBUS_FLAG_AF      NACK received flag
517   *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
518   *            @arg @ref SMBUS_FLAG_BERR    Bus error
519   *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
520   *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
521   *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
522   *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
523   *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
524   *
525   * @retval None
526   */
527 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__)  (((__FLAG__) == SMBUS_FLAG_TXE) ? \
528                                                        ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
529                                                        ((__HANDLE__)->Instance->ICR = (__FLAG__)))
530 
531 /** @brief  Enable the specified SMBUS peripheral.
532   * @param  __HANDLE__ specifies the SMBUS Handle.
533   * @retval None
534   */
535 #define __HAL_SMBUS_ENABLE(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
536 
537 /** @brief  Disable the specified SMBUS peripheral.
538   * @param  __HANDLE__ specifies the SMBUS Handle.
539   * @retval None
540   */
541 #define __HAL_SMBUS_DISABLE(__HANDLE__)                 (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
542 
543 /** @brief  Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
544   * @param  __HANDLE__ specifies the SMBUS Handle.
545   * @retval None
546   */
547 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__)           (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
548 
549 /**
550   * @}
551   */
552 
553 
554 /* Private constants ---------------------------------------------------------*/
555 
556 /* Private macros ------------------------------------------------------------*/
557 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros
558   * @{
559   */
560 
561 #define IS_SMBUS_ANALOG_FILTER(FILTER)                  (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
562                                                          ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
563 
564 #define IS_SMBUS_DIGITAL_FILTER(FILTER)                 ((FILTER) <= 0x0000000FU)
565 
566 #define IS_SMBUS_ADDRESSING_MODE(MODE)                  (((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
567                                                          ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
568 
569 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS)                  (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
570                                                          ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
571 
572 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK)                (((MASK) == SMBUS_OA2_NOMASK)    || \
573                                                          ((MASK) == SMBUS_OA2_MASK01)    || \
574                                                          ((MASK) == SMBUS_OA2_MASK02)    || \
575                                                          ((MASK) == SMBUS_OA2_MASK03)    || \
576                                                          ((MASK) == SMBUS_OA2_MASK04)    || \
577                                                          ((MASK) == SMBUS_OA2_MASK05)    || \
578                                                          ((MASK) == SMBUS_OA2_MASK06)    || \
579                                                          ((MASK) == SMBUS_OA2_MASK07))
580 
581 #define IS_SMBUS_GENERAL_CALL(CALL)                     (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
582                                                          ((CALL) == SMBUS_GENERALCALL_ENABLE))
583 
584 #define IS_SMBUS_NO_STRETCH(STRETCH)                    (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
585                                                          ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
586 
587 #define IS_SMBUS_PEC(PEC)                               (((PEC) == SMBUS_PEC_DISABLE) || \
588                                                          ((PEC) == SMBUS_PEC_ENABLE))
589 
590 #define IS_SMBUS_PERIPHERAL_MODE(MODE)                  (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)   || \
591                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
592                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
593 
594 #define IS_SMBUS_TRANSFER_MODE(MODE)                 (((MODE) == SMBUS_RELOAD_MODE)                          || \
595                                                       ((MODE) == SMBUS_AUTOEND_MODE)                         || \
596                                                       ((MODE) == SMBUS_SOFTEND_MODE)                         || \
597                                                       ((MODE) == SMBUS_SENDPEC_MODE)                         || \
598                                                       ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
599                                                       ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
600                                                       ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
601                                                       ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
602                                                                   SMBUS_RELOAD_MODE )))
603 
604 
605 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST)              (((REQUEST) == SMBUS_GENERATE_STOP)              || \
606                                                          ((REQUEST) == SMBUS_GENERATE_START_READ)        || \
607                                                          ((REQUEST) == SMBUS_GENERATE_START_WRITE)       || \
608                                                          ((REQUEST) == SMBUS_NO_STARTSTOP))
609 
610 
611 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)   (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)       || \
612                                                       ((REQUEST) == SMBUS_FIRST_FRAME)                       || \
613                                                       ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
614                                                       ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
615                                                       ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
616                                                       ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC)              || \
617                                                       ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
618                                                       ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
619 
620 #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)             || \
621                                                           ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)    || \
622                                                           ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)           || \
623                                                           ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
624 
625 #define SMBUS_RESET_CR1(__HANDLE__)                    ((__HANDLE__)->Instance->CR1 &= \
626                                                         (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
627                                                                                I2C_CR1_PECEN)))
628 #define SMBUS_RESET_CR2(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 &= \
629                                                         (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
630                                                                                I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
631                                                                                I2C_CR2_RD_WRN)))
632 
633 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)     (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
634                                                            (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
635                                                                        (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
636                                                                       (~I2C_CR2_RD_WRN)) : \
637                                                            (uint32_t)((((uint32_t)(__ADDRESS__) & \
638                                                                         (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
639                                                                        (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
640 
641 #define SMBUS_GET_ADDR_MATCH(__HANDLE__)                  (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
642 #define SMBUS_GET_DIR(__HANDLE__)                         (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
643 #define SMBUS_GET_STOP_MODE(__HANDLE__)                   ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
644 #define SMBUS_GET_PEC_MODE(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
645 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__)                ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
646 
647 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__)             ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
648                                                           ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
649 #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__)          ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
650 
651 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1)                         ((ADDRESS1) <= 0x000003FFU)
652 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2)                         ((ADDRESS2) <= (uint16_t)0x00FFU)
653 
654 /**
655   * @}
656   */
657 
658 /* Include SMBUS HAL Extended module */
659 #include "stm32l5xx_hal_smbus_ex.h"
660 
661 /* Exported functions --------------------------------------------------------*/
662 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
663   * @{
664   */
665 
666 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
667   * @{
668   */
669 
670 /* Initialization and de-initialization functions  ****************************/
671 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
672 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
673 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
674 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
675 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
676 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
677 
678 /* Callbacks Register/UnRegister functions  ***********************************/
679 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
680 HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
681                                              HAL_SMBUS_CallbackIDTypeDef CallbackID,
682                                              pSMBUS_CallbackTypeDef pCallback);
683 HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
684                                                HAL_SMBUS_CallbackIDTypeDef CallbackID);
685 
686 HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
687                                                  pSMBUS_AddrCallbackTypeDef pCallback);
688 HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
689 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
690 /**
691   * @}
692   */
693 
694 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
695   * @{
696   */
697 
698 /* IO operation functions  *****************************************************/
699 /** @addtogroup Blocking_mode_Polling Blocking mode Polling
700   * @{
701   */
702 /******* Blocking mode: Polling */
703 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
704                                           uint32_t Timeout);
705 /**
706   * @}
707   */
708 
709 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
710   * @{
711   */
712 /******* Non-Blocking mode: Interrupt */
713 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
714                                                uint8_t *pData, uint16_t Size, uint32_t XferOptions);
715 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
716                                               uint8_t *pData, uint16_t Size, uint32_t XferOptions);
717 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
718 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
719                                               uint32_t XferOptions);
720 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
721                                              uint32_t XferOptions);
722 
723 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
724 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
725 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
726 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
727 /**
728   * @}
729   */
730 
731 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
732   * @{
733   */
734 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
735 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
736 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
737 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
738 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
739 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
740 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
741 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
742 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
743 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
744 
745 /**
746   * @}
747   */
748 
749 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
750   *  @{
751   */
752 
753 /* Peripheral State and Errors functions  **************************************************/
754 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
755 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
756 
757 /**
758   * @}
759   */
760 
761 /**
762   * @}
763   */
764 
765 /* Private Functions ---------------------------------------------------------*/
766 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions
767   * @{
768   */
769 /* Private functions are defined in stm32l5xx_hal_smbus.c file */
770 /**
771   * @}
772   */
773 
774 /**
775   * @}
776   */
777 
778 /**
779   * @}
780   */
781 
782 /**
783   * @}
784   */
785 
786 #ifdef __cplusplus
787 }
788 #endif
789 
790 
791 #endif /* STM32L5xx_HAL_SMBUS_H */
792