1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_pwr_ex.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32L5xx_HAL_PWR_EX_H 20 #define STM32L5xx_HAL_PWR_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32l5xx_hal_def.h" 28 29 /** @addtogroup STM32L5xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup PWREx 34 * @{ 35 */ 36 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types 41 * @{ 42 */ 43 44 45 /** 46 * @brief PWR PVM configuration structure definition 47 */ 48 typedef struct 49 { 50 uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. 51 This parameter can be a value of @ref PWREx_PVM_Type. 52 @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). 53 @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device). 54 @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. 55 @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 1.8 V. */ 56 57 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. 58 This parameter can be a value of @ref PWREx_PVM_Mode. */ 59 } PWR_PVMTypeDef; 60 61 /** 62 * @} 63 */ 64 65 /* Exported constants --------------------------------------------------------*/ 66 67 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants 68 * @{ 69 */ 70 71 /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants 72 * @{ 73 */ 74 #define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polariry */ 75 /** 76 * @} 77 */ 78 79 80 /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins 81 * @{ 82 */ 83 #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 84 #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 85 #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 86 #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 87 #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 88 #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 89 #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 90 #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 91 #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 92 #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 93 #define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WUPP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */ 94 #define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WUPP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */ 95 #define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WUPP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */ 96 #define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WUPP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */ 97 #define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WUPP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */ 98 /** 99 * @} 100 */ 101 102 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type 103 * @{ 104 */ 105 #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */ 106 #define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V */ 107 #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */ 108 #define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 1.8 V */ 109 /** 110 * @} 111 */ 112 113 /** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode 114 * @{ 115 */ 116 #define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ 117 #define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ 118 #define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ 119 #define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 120 #define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ 121 #define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ 122 #define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ 123 /** 124 * @} 125 */ 126 127 128 129 /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale 130 * @{ 131 */ 132 #define PWR_REGULATOR_VOLTAGE_SCALE0 0U /*!< Voltage scaling range 0 */ 133 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 */ 134 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */ 135 /** 136 * @} 137 */ 138 139 140 /** @defgroup PWREx_SMPS_Mode PWR SMPS step down converter mode 141 * @{ 142 */ 143 #define PWR_SMPS_HIGH_POWER 0U /*!< SMPS step down converter in high-power mode (default) */ 144 #define PWR_SMPS_LOW_POWER PWR_CR4_SMPSLPEN /*!< SMPS step down converter in low-power mode */ 145 #define PWR_SMPS_BYPASS PWR_CR4_SMPSBYP /*!< SMPS step down converter in bypass mode */ 146 /** 147 * @} 148 */ 149 150 /** @defgroup PWREx_EXT_SMPS_MAIN_REG_READY PWR SMPS main regulator ready for external SMPS 151 * @{ 152 */ 153 #define PWR_MAINREG_READY_FOR_EXTSMPS PWR_SR1_EXTSMPSRDY /*!< Main Regulator ready for use with external SMPS */ 154 #define PWR_MAINREG_NOT_READY_FOR_EXTSMPS 0U /*!< Main Regulator not ready for use with external SMPS */ 155 /** 156 * @} 157 */ 158 159 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection 160 * @{ 161 */ 162 #define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor */ 163 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ 164 /** 165 * @} 166 */ 167 168 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging 169 * @{ 170 */ 171 #define PWR_BATTERY_CHARGING_DISABLE ((uint32_t)0x00000000) 172 #define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE 173 /** 174 * @} 175 */ 176 177 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode 178 * @{ 179 */ 180 #define PWR_GPIO_BIT_0 PWR_PUCRA_PU0 /*!< GPIO port I/O pin 0 */ 181 #define PWR_GPIO_BIT_1 PWR_PUCRA_PU1 /*!< GPIO port I/O pin 1 */ 182 #define PWR_GPIO_BIT_2 PWR_PUCRA_PU2 /*!< GPIO port I/O pin 2 */ 183 #define PWR_GPIO_BIT_3 PWR_PUCRA_PU3 /*!< GPIO port I/O pin 3 */ 184 #define PWR_GPIO_BIT_4 PWR_PUCRA_PU4 /*!< GPIO port I/O pin 4 */ 185 #define PWR_GPIO_BIT_5 PWR_PUCRA_PU5 /*!< GPIO port I/O pin 5 */ 186 #define PWR_GPIO_BIT_6 PWR_PUCRA_PU6 /*!< GPIO port I/O pin 6 */ 187 #define PWR_GPIO_BIT_7 PWR_PUCRA_PU7 /*!< GPIO port I/O pin 7 */ 188 #define PWR_GPIO_BIT_8 PWR_PUCRA_PU8 /*!< GPIO port I/O pin 8 */ 189 #define PWR_GPIO_BIT_9 PWR_PUCRA_PU9 /*!< GPIO port I/O pin 9 */ 190 #define PWR_GPIO_BIT_10 PWR_PUCRA_PU10 /*!< GPIO port I/O pin 10 */ 191 #define PWR_GPIO_BIT_11 PWR_PUCRA_PU11 /*!< GPIO port I/O pin 11 */ 192 #define PWR_GPIO_BIT_12 PWR_PUCRA_PU12 /*!< GPIO port I/O pin 12 */ 193 #define PWR_GPIO_BIT_13 PWR_PUCRA_PU13 /*!< GPIO port I/O pin 13 */ 194 #define PWR_GPIO_BIT_14 PWR_PUCRA_PU14 /*!< GPIO port I/O pin 14 */ 195 #define PWR_GPIO_BIT_15 PWR_PUCRA_PU15 /*!< GPIO port I/O pin 15 */ 196 /** 197 * @} 198 */ 199 200 /** @defgroup PWREx_GPIO GPIO port 201 * @{ 202 */ 203 #define PWR_GPIO_A 0x00000000U /*!< GPIO port A */ 204 #define PWR_GPIO_B 0x00000001U /*!< GPIO port B */ 205 #define PWR_GPIO_C 0x00000002U /*!< GPIO port C */ 206 #define PWR_GPIO_D 0x00000003U /*!< GPIO port D */ 207 #define PWR_GPIO_E 0x00000004U /*!< GPIO port E */ 208 #define PWR_GPIO_F 0x00000005U /*!< GPIO port F */ 209 #define PWR_GPIO_G 0x00000006U /*!< GPIO port G */ 210 #define PWR_GPIO_H 0x00000007U /*!< GPIO port H */ 211 /** 212 * @} 213 */ 214 215 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines 216 * @{ 217 */ 218 #define PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008) /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */ 219 #define PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010) /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */ 220 #define PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020) /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */ 221 #define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */ 222 /** 223 * @} 224 */ 225 226 /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines 227 * @{ 228 */ 229 #define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008) /*!< Event line 35 Connected to the PVM1 EXTI Line */ 230 #define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010) /*!< Event line 36 Connected to the PVM2 EXTI Line */ 231 #define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020) /*!< Event line 37 Connected to the PVM3 EXTI Line */ 232 #define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /*!< Event line 38 Connected to the PVM4 EXTI Line */ 233 /** 234 * @} 235 */ 236 237 /** @defgroup PWREx_Flag PWR Status Flags 238 * Elements values convention: 0000 0000 0XXY YYYYb 239 * - Y YYYY : Flag position in the XX register (5 bits) 240 * - XX : Status register (2 bits) 241 * - 01: SR1 register 242 * - 10: SR2 register 243 * The only exception is PWR_FLAG_WU, encompassing all 244 * wake-up flags and set to PWR_SR1_WUF. 245 * @{ 246 */ 247 #define PWR_FLAG_WUF1 ((uint32_t)0x0020) /*!< Wakeup event on wakeup pin 1 */ 248 #define PWR_FLAG_WUF2 ((uint32_t)0x0021) /*!< Wakeup event on wakeup pin 2 */ 249 #define PWR_FLAG_WUF3 ((uint32_t)0x0022) /*!< Wakeup event on wakeup pin 3 */ 250 #define PWR_FLAG_WUF4 ((uint32_t)0x0023) /*!< Wakeup event on wakeup pin 4 */ 251 #define PWR_FLAG_WUF5 ((uint32_t)0x0024) /*!< Wakeup event on wakeup pin 5 */ 252 #define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */ 253 #define PWR_FLAG_SB ((uint32_t)0x0028) /*!< Standby flag */ 254 #define PWR_FLAG_SMPS_BYPASS_RDY ((uint32_t)0x002C) /*!< SMPS bypass mode ready */ 255 #define PWR_FLAG_EXT_SMPS_RDY ((uint32_t)0x002D) /*!< External SMPS mode ready */ 256 #define PWR_FLAG_SMPS_HP_RDY ((uint32_t)0x002E) /*!< SMPS high-power mode ready */ 257 #define PWR_FLAG_REGLPS ((uint32_t)0x0048) /*!< Low-power regulator start flag */ 258 #define PWR_FLAG_REGLPF ((uint32_t)0x0049) /*!< Low-power regulator flag */ 259 #define PWR_FLAG_VOSF ((uint32_t)0x004A) /*!< Voltage scaling flag */ 260 #define PWR_FLAG_PVDO ((uint32_t)0x004B) /*!< Power Voltage Detector output flag */ 261 #define PWR_FLAG_PVMO1 ((uint32_t)0x004C) /*!< Power Voltage Monitoring 1 output flag */ 262 #define PWR_FLAG_PVMO2 ((uint32_t)0x004D) /*!< Power Voltage Monitoring 2 output flag */ 263 #define PWR_FLAG_PVMO3 ((uint32_t)0x004E) /*!< Power Voltage Monitoring 3 output flag */ 264 #define PWR_FLAG_PVMO4 ((uint32_t)0x004F) /*!< Power Voltage Monitoring 4 output flag */ 265 /** 266 * @} 267 */ 268 269 /** @defgroup PWREx_SecureMode PWREx Secure Mode 270 * @note Only available when system implements security (TZEN=1) 271 * @{ 272 */ 273 #define PWR_SECURE_NONE 0U /*!< No security on PWR resources (default) */ 274 #define PWR_SECURE_ALL 0x0F1FU /*!< Security on all PWR resources */ 275 276 #define PWR_SECURE_WUP PWR_SECCFGR_WUPSEC /*!< All Wakeup pins secure configuration */ 277 #define PWR_SECURE_WUP1 PWR_SECCFGR_WUP1SEC /*!< Wakeup pin 1 secure configuration */ 278 #define PWR_SECURE_WUP2 PWR_SECCFGR_WUP2SEC /*!< Wakeup pin 2 secure configuration */ 279 #define PWR_SECURE_WUP3 PWR_SECCFGR_WUP3SEC /*!< Wakeup pin 3 secure configuration */ 280 #define PWR_SECURE_WUP4 PWR_SECCFGR_WUP4SEC /*!< Wakeup pin 4 secure configuration */ 281 #define PWR_SECURE_WUP5 PWR_SECCFGR_WUP5SEC /*!< Wakeup pin 5 secure configuration */ 282 #define PWR_SECURE_LPM PWR_SECCFGR_LPMSEC /*!< Low-power mode secure configuration */ 283 #define PWR_SECURE_VDM PWR_SECCFGR_VDMSEC /*!< Voltage Detection and Monitoring secure configuration */ 284 #define PWR_SECURE_VB PWR_SECCFGR_VBSEC /*!< VBAT mode secure configuration */ 285 #define PWR_SECURE_APC PWR_SECCFGR_APCSEC /*!< Pull-up/down Control secure configuration */ 286 /** 287 * @} 288 */ 289 290 /** @defgroup PWREx_SRAM2_Contents_Retention PWR SRAM2 Content Retention 291 * @{ 292 */ 293 #define PWR_NO_SRAM2_RETENTION 0U /*!< SRAM2 is powered off in Standby mode (SRAM2 content is lost)*/ 294 #define PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS_0 /*!< : Full SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 content is kept) */ 295 #define PWR_4KBYTES_SRAM2_RETENTION PWR_CR3_RRS_1 /*!< Only 4kB of SRAM2 is powered by the low-power regulator in Standby mode (4kB of SRAM2 content is kept) */ 296 /** 297 * @} 298 */ 299 300 /** 301 * @} 302 */ 303 304 /* Exported macros -----------------------------------------------------------*/ 305 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros 306 * @{ 307 */ 308 309 /** 310 * @brief Enable the PVM1 Extended Interrupt Line. 311 * @retval None 312 */ 313 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) 314 315 /** 316 * @brief Disable the PVM1 Extended Interrupt Line. 317 * @retval None 318 */ 319 #define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) 320 321 /** 322 * @brief Enable the PVM1 Event Line. 323 * @retval None 324 */ 325 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) 326 327 /** 328 * @brief Disable the PVM1 Event Line. 329 * @retval None 330 */ 331 #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) 332 333 /** 334 * @brief Enable the PVM1 Extended Interrupt Rising Trigger. 335 * @retval None 336 */ 337 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) 338 339 /** 340 * @brief Disable the PVM1 Extended Interrupt Rising Trigger. 341 * @retval None 342 */ 343 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) 344 345 /** 346 * @brief Enable the PVM1 Extended Interrupt Falling Trigger. 347 * @retval None 348 */ 349 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) 350 351 352 /** 353 * @brief Disable the PVM1 Extended Interrupt Falling Trigger. 354 * @retval None 355 */ 356 #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) 357 358 359 /** 360 * @brief PVM1 EXTI line configuration: set rising & falling edge trigger. 361 * @retval None 362 */ 363 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ 364 do { \ 365 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \ 366 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \ 367 } while(0) 368 369 /** 370 * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger. 371 * @retval None 372 */ 373 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ 374 do { \ 375 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \ 376 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \ 377 } while(0) 378 379 /** 380 * @brief Generate a Software interrupt on selected EXTI line. 381 * @retval None 382 */ 383 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1) 384 385 /** 386 * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not. 387 * @retval EXTI PVM1 Line Status. 388 */ 389 #define __HAL_PWR_PVM1_EXTI_GET_FLAG() ((EXTI->RPR2 | EXTI->FPR2) & PWR_EXTI_LINE_PVM1) 390 391 /** 392 * @brief Clear the PVM1 EXTI flag. 393 * @retval None 394 */ 395 #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() \ 396 do { \ 397 WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM1); \ 398 WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM1); \ 399 } while(0) 400 401 402 /** 403 * @brief Enable the PVM2 Extended Interrupt Line. 404 * @retval None 405 */ 406 #define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) 407 408 /** 409 * @brief Disable the PVM2 Extended Interrupt Line. 410 * @retval None 411 */ 412 #define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) 413 414 /** 415 * @brief Enable the PVM2 Event Line. 416 * @retval None 417 */ 418 #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) 419 420 /** 421 * @brief Disable the PVM2 Event Line. 422 * @retval None 423 */ 424 #define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) 425 426 /** 427 * @brief Enable the PVM2 Extended Interrupt Rising Trigger. 428 * @retval None 429 */ 430 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) 431 432 /** 433 * @brief Disable the PVM2 Extended Interrupt Rising Trigger. 434 * @retval None 435 */ 436 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) 437 438 /** 439 * @brief Enable the PVM2 Extended Interrupt Falling Trigger. 440 * @retval None 441 */ 442 #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) 443 444 445 /** 446 * @brief Disable the PVM2 Extended Interrupt Falling Trigger. 447 * @retval None 448 */ 449 #define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) 450 451 452 /** 453 * @brief PVM2 EXTI line configuration: set rising & falling edge trigger. 454 * @retval None 455 */ 456 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \ 457 do { \ 458 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \ 459 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \ 460 } while(0) 461 462 /** 463 * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger. 464 * @retval None 465 */ 466 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \ 467 do { \ 468 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \ 469 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \ 470 } while(0) 471 472 /** 473 * @brief Generate a Software interrupt on selected EXTI line. 474 * @retval None 475 */ 476 #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2) 477 478 /** 479 * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not. 480 * @retval EXTI PVM2 Line Status. 481 */ 482 #define __HAL_PWR_PVM2_EXTI_GET_FLAG() ((EXTI->RPR2 | EXTI->FPR2) & PWR_EXTI_LINE_PVM2) 483 484 /** 485 * @brief Clear the PVM2 EXTI flag. 486 * @retval None 487 */ 488 #define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() \ 489 do { \ 490 WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM2); \ 491 WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM2); \ 492 } while(0) 493 494 495 /** 496 * @brief Enable the PVM3 Extended Interrupt Line. 497 * @retval None 498 */ 499 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) 500 501 /** 502 * @brief Disable the PVM3 Extended Interrupt Line. 503 * @retval None 504 */ 505 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) 506 507 /** 508 * @brief Enable the PVM3 Event Line. 509 * @retval None 510 */ 511 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) 512 513 /** 514 * @brief Disable the PVM3 Event Line. 515 * @retval None 516 */ 517 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) 518 519 /** 520 * @brief Enable the PVM3 Extended Interrupt Rising Trigger. 521 * @retval None 522 */ 523 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) 524 525 /** 526 * @brief Disable the PVM3 Extended Interrupt Rising Trigger. 527 * @retval None 528 */ 529 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) 530 531 /** 532 * @brief Enable the PVM3 Extended Interrupt Falling Trigger. 533 * @retval None 534 */ 535 #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) 536 537 538 /** 539 * @brief Disable the PVM3 Extended Interrupt Falling Trigger. 540 * @retval None 541 */ 542 #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) 543 544 545 /** 546 * @brief PVM3 EXTI line configuration: set rising & falling edge trigger. 547 * @retval None 548 */ 549 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \ 550 do { \ 551 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ 552 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ 553 } while(0) 554 555 /** 556 * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger. 557 * @retval None 558 */ 559 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \ 560 do { \ 561 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \ 562 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \ 563 } while(0) 564 565 /** 566 * @brief Generate a Software interrupt on selected EXTI line. 567 * @retval None 568 */ 569 #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3) 570 571 /** 572 * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not. 573 * @retval EXTI PVM3 Line Status. 574 */ 575 #define __HAL_PWR_PVM3_EXTI_GET_FLAG() ((EXTI->RPR2 | EXTI->FPR2) & PWR_EXTI_LINE_PVM3) 576 577 /** 578 * @brief Clear the PVM3 EXTI flag. 579 * @retval None 580 */ 581 #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() \ 582 do { \ 583 WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM3); \ 584 WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM3); \ 585 } while(0) 586 587 588 589 /** 590 * @brief Enable the PVM4 Extended Interrupt Line. 591 * @retval None 592 */ 593 #define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) 594 595 /** 596 * @brief Disable the PVM4 Extended Interrupt Line. 597 * @retval None 598 */ 599 #define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) 600 601 /** 602 * @brief Enable the PVM4 Event Line. 603 * @retval None 604 */ 605 #define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) 606 607 /** 608 * @brief Disable the PVM4 Event Line. 609 * @retval None 610 */ 611 #define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) 612 613 /** 614 * @brief Enable the PVM4 Extended Interrupt Rising Trigger. 615 * @retval None 616 */ 617 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) 618 619 /** 620 * @brief Disable the PVM4 Extended Interrupt Rising Trigger. 621 * @retval None 622 */ 623 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) 624 625 /** 626 * @brief Enable the PVM4 Extended Interrupt Falling Trigger. 627 * @retval None 628 */ 629 #define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) 630 631 632 /** 633 * @brief Disable the PVM4 Extended Interrupt Falling Trigger. 634 * @retval None 635 */ 636 #define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) 637 638 639 /** 640 * @brief PVM4 EXTI line configuration: set rising & falling edge trigger. 641 * @retval None 642 */ 643 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \ 644 do { \ 645 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \ 646 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \ 647 } while(0) 648 649 /** 650 * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger. 651 * @retval None 652 */ 653 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \ 654 do { \ 655 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \ 656 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \ 657 } while(0) 658 659 /** 660 * @brief Generate a Software interrupt on selected EXTI line. 661 * @retval None 662 */ 663 #define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4) 664 665 /** 666 * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set. 667 * @retval EXTI PVM4 Line Status. 668 */ 669 #define __HAL_PWR_PVM4_EXTI_GET_FLAG() ((EXTI->RPR2 | EXTI->FPR2) & PWR_EXTI_LINE_PVM4) 670 671 /** 672 * @brief Clear the PVM4 EXTI flag. 673 * @retval None 674 */ 675 #define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() \ 676 do { \ 677 WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM4); \ 678 WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM4); \ 679 } while(0) 680 681 682 /** 683 * @brief Configure the main internal regulator output voltage. 684 * @param __REGULATOR__ specifies the regulator output voltage to achieve 685 * a tradeoff between performance and power consumption. 686 * This parameter can be one of the following values: 687 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE0 Regulator voltage output range 0 mode, 688 * typical output voltage at 1.28 V, 689 * system frequency up to 110 MHz. 690 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, 691 * typical output voltage at 1.2 V, 692 * system frequency up to 80 MHz. 693 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, 694 * typical output voltage at 1.0 V, 695 * system frequency up to 26 MHz. 696 * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check 697 * whether or not VOSF flag is cleared when moving from range 2 to range 1. User 698 * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. 699 * @retval None 700 */ 701 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ 702 __IO uint32_t tmpreg; \ 703 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ 704 /* Delay after an RCC peripheral clock enabling */ \ 705 tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ 706 UNUSED(tmpreg); \ 707 } while(0) 708 709 /** 710 * @} 711 */ 712 713 /* Private macros --------------------------------------------------------*/ 714 /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros 715 * @{ 716 */ 717 718 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ 719 ((PIN) == PWR_WAKEUP_PIN2) || \ 720 ((PIN) == PWR_WAKEUP_PIN3) || \ 721 ((PIN) == PWR_WAKEUP_PIN4) || \ 722 ((PIN) == PWR_WAKEUP_PIN5) || \ 723 ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ 724 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ 725 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ 726 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ 727 ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \ 728 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ 729 ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ 730 ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ 731 ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ 732 ((PIN) == PWR_WAKEUP_PIN5_LOW)) 733 734 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ 735 ((TYPE) == PWR_PVM_2) ||\ 736 ((TYPE) == PWR_PVM_3) ||\ 737 ((TYPE) == PWR_PVM_4)) 738 739 #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ 740 ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ 741 ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ 742 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ 743 ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ 744 ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ 745 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) 746 747 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \ 748 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ 749 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) 750 751 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ 752 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) 753 754 #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ 755 ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) 756 757 #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00) 758 759 760 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 761 ((GPIO) == PWR_GPIO_B) ||\ 762 ((GPIO) == PWR_GPIO_C) ||\ 763 ((GPIO) == PWR_GPIO_D) ||\ 764 ((GPIO) == PWR_GPIO_E) ||\ 765 ((GPIO) == PWR_GPIO_F) ||\ 766 ((GPIO) == PWR_GPIO_G) ||\ 767 ((GPIO) == PWR_GPIO_H)) 768 769 #define IS_PWR_SRAM2CONTENT_RETENTION(CONTENT) (((CONTENT) == PWR_NO_SRAM2_RETENTION) ||\ 770 ((CONTENT) == PWR_FULL_SRAM2_RETENTION) ||\ 771 ((CONTENT) == PWR_4KBYTES_SRAM2_RETENTION)) 772 773 #define IS_PWR_SMPS_MODE(__MODE__) (((__MODE__) == PWR_SMPS_HIGH_POWER) || \ 774 ((__MODE__) == PWR_SMPS_LOW_POWER) || \ 775 ((__MODE__) == PWR_SMPS_BYPASS)) 776 777 #define IS_PWR_SECURE_CONFIG(__CONFIG__) (((__CONFIG__) == PWR_SECURE_NONE) || \ 778 ((__CONFIG__) == PWR_SECURE_ALL) || \ 779 (((__CONFIG__) & PWR_SECURE_WUP) == PWR_SECURE_WUP) || \ 780 (((__CONFIG__) & PWR_SECURE_WUP1) == PWR_SECURE_WUP1) || \ 781 (((__CONFIG__) & PWR_SECURE_WUP2) == PWR_SECURE_WUP2) || \ 782 (((__CONFIG__) & PWR_SECURE_WUP3) == PWR_SECURE_WUP3) || \ 783 (((__CONFIG__) & PWR_SECURE_WUP4) == PWR_SECURE_WUP4) || \ 784 (((__CONFIG__) & PWR_SECURE_WUP5) == PWR_SECURE_WUP5) || \ 785 (((__CONFIG__) & PWR_SECURE_LPM) == PWR_SECURE_LPM) || \ 786 (((__CONFIG__) & PWR_SECURE_VDM) == PWR_SECURE_VDM) || \ 787 (((__CONFIG__) & PWR_SECURE_VB) == PWR_SECURE_VB) || \ 788 (((__CONFIG__) & PWR_SECURE_APC) == PWR_SECURE_APC)) 789 /** 790 * @} 791 */ 792 793 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions 794 * @{ 795 */ 796 797 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions 798 * @{ 799 */ 800 801 802 /* Peripheral Control functions **********************************************/ 803 uint32_t HAL_PWREx_GetVoltageRange(void); 804 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); 805 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); 806 void HAL_PWREx_DisableBatteryCharging(void); 807 void HAL_PWREx_EnableVddUSB(void); 808 void HAL_PWREx_DisableVddUSB(void); 809 void HAL_PWREx_EnableVddIO2(void); 810 void HAL_PWREx_DisableVddIO2(void); 811 void HAL_PWREx_EnableInternalWakeUpLine(void); 812 void HAL_PWREx_DisableInternalWakeUpLine(void); 813 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 814 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 815 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 816 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 817 void HAL_PWREx_EnablePullUpPullDownConfig(void); 818 void HAL_PWREx_DisablePullUpPullDownConfig(void); 819 void HAL_PWREx_EnablePVM1(void); 820 void HAL_PWREx_DisablePVM1(void); 821 void HAL_PWREx_EnablePVM2(void); 822 void HAL_PWREx_DisablePVM2(void); 823 void HAL_PWREx_EnablePVM3(void); 824 void HAL_PWREx_DisablePVM3(void); 825 void HAL_PWREx_EnablePVM4(void); 826 void HAL_PWREx_DisablePVM4(void); 827 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); 828 829 /* Low Power modes configuration functions ************************************/ 830 void HAL_PWREx_EnableLowPowerRunMode(void); 831 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); 832 void HAL_PWREx_EnableUltraLowPowerMode(void); 833 void HAL_PWREx_DisableUltraLowPowerMode(void); 834 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry); 835 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); 836 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); 837 void HAL_PWREx_EnterSHUTDOWNMode(void); 838 839 void HAL_PWREx_PVD_PVM_IRQHandler(void); 840 void HAL_PWREx_PVM1Callback(void); 841 void HAL_PWREx_PVM2Callback(void); 842 void HAL_PWREx_PVM3Callback(void); 843 void HAL_PWREx_PVM4Callback(void); 844 845 HAL_StatusTypeDef HAL_PWREx_ConfigSRAM2ContentRetention(uint32_t SRAM2ContentRetention); 846 void HAL_PWREx_EnableSRAM2ContentRetention(void); 847 void HAL_PWREx_DisableSRAM2ContentRetention(void); 848 849 void HAL_PWREx_EnableUCPDStandbyMode(void); 850 void HAL_PWREx_DisableUCPDStandbyMode(void); 851 void HAL_PWREx_EnableUCPDDeadBattery(void); 852 void HAL_PWREx_DisableUCPDDeadBattery(void); 853 854 /** 855 * @} 856 */ 857 858 /** @addtogroup PWREx_Exported_Functions_Group2 859 * @{ 860 */ 861 862 HAL_StatusTypeDef HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode); 863 uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void); 864 uint32_t HAL_PWREx_SMPS_GetMainRegulatorExtSMPSReadyStatus(void); 865 void HAL_PWREx_SMPS_EnableFastStart(void); 866 void HAL_PWREx_SMPS_DisableFastStart(void); 867 868 void HAL_PWREx_SMPS_EnableExternal(void); 869 void HAL_PWREx_SMPS_DisableExternal(void); 870 void HAL_PWREx_SMPS_DisableBypassMode(void); 871 void HAL_PWREx_SMPS_EnableBypassMode(void); 872 873 /** 874 * @} 875 */ 876 877 /** 878 * @} 879 */ 880 881 /** 882 * @} 883 */ 884 885 /** 886 * @} 887 */ 888 889 #ifdef __cplusplus 890 } 891 #endif 892 893 894 #endif /* STM32L5xx_HAL_PWR_EX_H */ 895
