1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_ospi.h 4 * @author MCD Application Team 5 * @brief Header file of OSPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L5xx_HAL_OSPI_H 21 #define STM32L5xx_HAL_OSPI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l5xx_hal_def.h" 29 30 #if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2) 31 32 /** @addtogroup STM32L5xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup OSPI 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup OSPI_Exported_Types OSPI Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief OSPI Init structure definition 47 */ 48 typedef struct 49 { 50 uint32_t FifoThreshold; /*!< This is the threshold used by the Peripheral to generate the interrupt 51 indicating that data are available in reception or free place 52 is available in transmission. 53 This parameter can be a value between 1 and 32 */ 54 uint32_t DualQuad; /*!< It enables or not the dual-quad mode which allow to access up to 55 quad mode on two different devices to increase the throughput. 56 This parameter can be a value of @ref OSPI_DualQuad */ 57 uint32_t MemoryType; /*!< It indicates the external device type connected to the OSPI. 58 This parameter can be a value of @ref OSPI_MemoryType */ 59 uint32_t DeviceSize; /*!< It defines the size of the external device connected to the OSPI, 60 it corresponds to the number of address bits required to access 61 the external device. 62 This parameter can be a value between 1 and 32 */ 63 uint32_t ChipSelectHighTime; /*!< It defines the minimum number of clocks which the chip select 64 must remain high between commands. 65 This parameter can be a value between 1 and 8 */ 66 uint32_t FreeRunningClock; /*!< It enables or not the free running clock. 67 This parameter can be a value of @ref OSPI_FreeRunningClock */ 68 uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released. 69 This parameter can be a value of @ref OSPI_ClockMode */ 70 uint32_t WrapSize; /*!< It indicates the wrap-size corresponding the external device configuration. 71 This parameter can be a value of @ref OSPI_WrapSize */ 72 uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating 73 the external clock based on the AHB clock. 74 This parameter can be a value between 1 and 256 */ 75 uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order 76 to take in account external signal delays. 77 This parameter can be a value of @ref OSPI_SampleShifting */ 78 uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data. 79 This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */ 80 uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and 81 defines the boundary of bytes to release the chip select. 82 This parameter can be a value between 0 and 31 */ 83 uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected 84 by the delay block. 85 This parameter can be a value of @ref OSPI_DelayBlockBypass */ 86 uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every 87 Refresh+1 clock cycles. 88 This parameter can be a value between 0 and 0xFFFFFFFF */ 89 }OSPI_InitTypeDef; 90 91 /** 92 * @brief HAL OSPI Handle Structure definition 93 */ 94 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 95 typedef struct __OSPI_HandleTypeDef 96 #else 97 typedef struct 98 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 99 { 100 OCTOSPI_TypeDef *Instance; /*!< OSPI registers base address */ 101 OSPI_InitTypeDef Init; /*!< OSPI initialization parameters */ 102 uint8_t *pBuffPtr; /*!< Address of the OSPI buffer for transfer */ 103 __IO uint32_t XferSize; /*!< Number of data to transfer */ 104 __IO uint32_t XferCount; /*!< Counter of data transferred */ 105 DMA_HandleTypeDef *hdma; /*!< Handle of the DMA channel used for the transfer */ 106 __IO uint32_t State; /*!< Internal state of the OSPI HAL driver */ 107 __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */ 108 uint32_t Timeout; /*!< Timeout used for the OSPI external device access */ 109 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 110 void (* ErrorCallback) (struct __OSPI_HandleTypeDef *hospi); 111 void (* AbortCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 112 void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi); 113 void (* CmdCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 114 void (* RxCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 115 void (* TxCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 116 void (* RxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 117 void (* TxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 118 void (* StatusMatchCallback) (struct __OSPI_HandleTypeDef *hospi); 119 void (* TimeOutCallback) (struct __OSPI_HandleTypeDef *hospi); 120 121 void (* MspInitCallback) (struct __OSPI_HandleTypeDef *hospi); 122 void (* MspDeInitCallback) (struct __OSPI_HandleTypeDef *hospi); 123 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 124 }OSPI_HandleTypeDef; 125 126 /** 127 * @brief HAL OSPI Regular Command Structure definition 128 */ 129 typedef struct 130 { 131 uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or 132 to the registers for the write operation (these registers are only 133 used for memory-mapped mode). 134 This parameter can be a value of @ref OSPI_OperationType */ 135 uint32_t FlashId; /*!< It indicates which external device is selected for this command (it 136 applies only if Dualquad is disabled in the initialization structure). 137 This parameter can be a value of @ref OSPI_FlashID */ 138 uint32_t Instruction; /*!< It contains the instruction to be sent to the device. 139 This parameter can be a value between 0 and 0xFFFFFFFF */ 140 uint32_t InstructionMode; /*!< It indicates the mode of the instruction. 141 This parameter can be a value of @ref OSPI_InstructionMode */ 142 uint32_t InstructionSize; /*!< It indicates the size of the instruction. 143 This parameter can be a value of @ref OSPI_InstructionSize */ 144 uint32_t InstructionDtrMode; /*!< It enables or not the DTR mode for the instruction phase. 145 This parameter can be a value of @ref OSPI_InstructionDtrMode */ 146 uint32_t Address; /*!< It contains the address to be sent to the device. 147 This parameter can be a value between 0 and 0xFFFFFFFF */ 148 uint32_t AddressMode; /*!< It indicates the mode of the address. 149 This parameter can be a value of @ref OSPI_AddressMode */ 150 uint32_t AddressSize; /*!< It indicates the size of the address. 151 This parameter can be a value of @ref OSPI_AddressSize */ 152 uint32_t AddressDtrMode; /*!< It enables or not the DTR mode for the address phase. 153 This parameter can be a value of @ref OSPI_AddressDtrMode */ 154 uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device. 155 This parameter can be a value between 0 and 0xFFFFFFFF */ 156 uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes. 157 This parameter can be a value of @ref OSPI_AlternateBytesMode */ 158 uint32_t AlternateBytesSize; /*!< It indicates the size of the alternate bytes. 159 This parameter can be a value of @ref OSPI_AlternateBytesSize */ 160 uint32_t AlternateBytesDtrMode; /*!< It enables or not the DTR mode for the alternate bytes phase. 161 This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */ 162 uint32_t DataMode; /*!< It indicates the mode of the data. 163 This parameter can be a value of @ref OSPI_DataMode */ 164 uint32_t NbData; /*!< It indicates the number of data transferred with this command. 165 This field is only used for indirect mode. 166 This parameter can be a value between 1 and 0xFFFFFFFF */ 167 uint32_t DataDtrMode; /*!< It enables or not the DTR mode for the data phase. 168 This parameter can be a value of @ref OSPI_DataDtrMode */ 169 uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase. 170 This parameter can be a value between 0 and 31 */ 171 uint32_t DQSMode; /*!< It enables or not the data strobe management. 172 This parameter can be a value of @ref OSPI_DQSMode */ 173 uint32_t SIOOMode; /*!< It enables or not the SIOO mode. 174 This parameter can be a value of @ref OSPI_SIOOMode */ 175 }OSPI_RegularCmdTypeDef; 176 177 /** 178 * @brief HAL OSPI Hyperbus Configuration Structure definition 179 */ 180 typedef struct 181 { 182 uint32_t RWRecoveryTime; /*!< It indicates the number of cycles for the device read write recovery time. 183 This parameter can be a value between 0 and 255 */ 184 uint32_t AccessTime; /*!< It indicates the number of cycles for the device access time. 185 This parameter can be a value between 0 and 255 */ 186 uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access. 187 This parameter can be a value of @ref OSPI_WriteZeroLatency */ 188 uint32_t LatencyMode; /*!< It configures the latency mode. 189 This parameter can be a value of @ref OSPI_LatencyMode */ 190 }OSPI_HyperbusCfgTypeDef; 191 192 /** 193 * @brief HAL OSPI Hyperbus Command Structure definition 194 */ 195 typedef struct 196 { 197 uint32_t AddressSpace; /*!< It indicates the address space accessed by the command. 198 This parameter can be a value of @ref OSPI_AddressSpace */ 199 uint32_t Address; /*!< It contains the address to be sent tot he device. 200 This parameter can be a value between 0 and 0xFFFFFFFF */ 201 uint32_t AddressSize; /*!< It indicates the size of the address. 202 This parameter can be a value of @ref OSPI_AddressSize */ 203 uint32_t NbData; /*!< It indicates the number of data transferred with this command. 204 This field is only used for indirect mode. 205 This parameter can be a value between 1 and 0xFFFFFFFF 206 In case of autopolling mode, this parameter can be any value between 1 and 4 */ 207 uint32_t DQSMode; /*!< It enables or not the data strobe management. 208 This parameter can be a value of @ref OSPI_DQSMode */ 209 }OSPI_HyperbusCmdTypeDef; 210 211 /** 212 * @brief HAL OSPI Auto Polling mode configuration structure definition 213 */ 214 typedef struct 215 { 216 uint32_t Match; /*!< Specifies the value to be compared with the masked status register to get a match. 217 This parameter can be any value between 0 and 0xFFFFFFFF */ 218 uint32_t Mask; /*!< Specifies the mask to be applied to the status bytes received. 219 This parameter can be any value between 0 and 0xFFFFFFFF */ 220 uint32_t MatchMode; /*!< Specifies the method used for determining a match. 221 This parameter can be a value of @ref OSPI_MatchMode */ 222 uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match. 223 This parameter can be a value of @ref OSPI_AutomaticStop */ 224 uint32_t Interval; /*!< Specifies the number of clock cycles between two read during automatic polling phases. 225 This parameter can be any value between 0 and 0xFFFF */ 226 }OSPI_AutoPollingTypeDef; 227 228 /** 229 * @brief HAL OSPI Memory Mapped mode configuration structure definition 230 */ 231 typedef struct 232 { 233 uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select. 234 This parameter can be a value of @ref OSPI_TimeOutActivation */ 235 uint32_t TimeOutPeriod; /*!< Specifies the number of clock to wait when the FIFO is full before to release the chip select. 236 This parameter can be any value between 0 and 0xFFFF */ 237 }OSPI_MemoryMappedTypeDef; 238 239 240 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 241 /** 242 * @brief HAL OSPI Callback ID enumeration definition 243 */ 244 typedef enum 245 { 246 HAL_OSPI_ERROR_CB_ID = 0x00U, /*!< OSPI Error Callback ID */ 247 HAL_OSPI_ABORT_CB_ID = 0x01U, /*!< OSPI Abort Callback ID */ 248 HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< OSPI FIFO Threshold Callback ID */ 249 HAL_OSPI_CMD_CPLT_CB_ID = 0x03U, /*!< OSPI Command Complete Callback ID */ 250 HAL_OSPI_RX_CPLT_CB_ID = 0x04U, /*!< OSPI Rx Complete Callback ID */ 251 HAL_OSPI_TX_CPLT_CB_ID = 0x05U, /*!< OSPI Tx Complete Callback ID */ 252 HAL_OSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< OSPI Rx Half Complete Callback ID */ 253 HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< OSPI Tx Half Complete Callback ID */ 254 HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< OSPI Status Match Callback ID */ 255 HAL_OSPI_TIMEOUT_CB_ID = 0x09U, /*!< OSPI Timeout Callback ID */ 256 257 HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, /*!< OSPI MspInit Callback ID */ 258 HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< OSPI MspDeInit Callback ID */ 259 }HAL_OSPI_CallbackIDTypeDef; 260 261 /** 262 * @brief HAL OSPI Callback pointer definition 263 */ 264 typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); 265 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 266 /** 267 * @} 268 */ 269 270 /* Exported constants --------------------------------------------------------*/ 271 /** @defgroup OSPI_Exported_Constants OSPI Exported Constants 272 * @{ 273 */ 274 275 /** @defgroup OSPI_State OSPI State 276 * @{ 277 */ 278 #define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U) /*!< Initial state */ 279 #define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ 280 #define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U) /*!< Driver ready to be used */ 281 #define HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */ 282 #define HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U) /*!< Read command configuration done, not the write command configuration */ 283 #define HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U) /*!< Write command configuration done, not the read command configuration */ 284 #define HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U) /*!< Command without data on-going */ 285 #define HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U) /*!< Indirect Tx on-going */ 286 #define HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U) /*!< Indirect Rx on-going */ 287 #define HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U) /*!< Auto-polling on-going */ 288 #define HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U) /*!< Memory-mapped on-going */ 289 #define HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U) /*!< Abort on-going */ 290 #define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U) /*!< Blocking error, driver should be re-initialized */ 291 /** 292 * @} 293 */ 294 295 /** @defgroup OSPI_ErrorCode OSPI Error Code 296 * @{ 297 */ 298 #define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 299 #define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ 300 #define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */ 301 #define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ 302 #define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ 303 #define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */ 304 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 305 #define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */ 306 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ 307 /** 308 * @} 309 */ 310 311 /** @defgroup OSPI_DualQuad OSPI Dual-Quad 312 * @{ 313 */ 314 #define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */ 315 #define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */ 316 /** 317 * @} 318 */ 319 320 /** @defgroup OSPI_MemoryType OSPI Memory Type 321 * @{ 322 */ 323 #define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U) /*!< Micron mode */ 324 #define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */ 325 #define HAL_OSPI_MEMTYPE_APMEMORY ((uint32_t)OCTOSPI_DCR1_MTYP_1) /*!< AP Memory mode */ 326 #define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */ 327 #define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ 328 /** 329 * @} 330 */ 331 332 /** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock 333 * @{ 334 */ 335 #define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U) /*!< CLK is not free running */ 336 #define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK) /*!< CLK is free running (always provided) */ 337 /** 338 * @} 339 */ 340 341 /** @defgroup OSPI_ClockMode OSPI Clock Mode 342 * @{ 343 */ 344 #define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!< CLK must stay low while nCS is high */ 345 #define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ 346 /** 347 * @} 348 */ 349 350 /** @defgroup OSPI_WrapSize OSPI Wrap-Size 351 * @{ 352 */ 353 #define HAL_OSPI_WRAP_NOT_SUPPORTED ((uint32_t)0x00000000U) /*!< wrapped reads are not supported by the memory */ 354 #define HAL_OSPI_WRAP_16_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */ 355 #define HAL_OSPI_WRAP_32_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */ 356 #define HAL_OSPI_WRAP_64_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 64 bytes */ 357 #define HAL_OSPI_WRAP_128_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */ 358 /** 359 * @} 360 */ 361 362 /** @defgroup OSPI_SampleShifting OSPI Sample Shifting 363 * @{ 364 */ 365 #define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!< No shift */ 366 #define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ 367 /** 368 * @} 369 */ 370 371 /** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle 372 * @{ 373 */ 374 #define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U) /*!< No Delay */ 375 #define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ 376 /** 377 * @} 378 */ 379 380 /** @defgroup OSPI_DelayBlockBypass OSPI Delay Block Bypaas 381 * @{ 382 */ 383 #define HAL_OSPI_DELAY_BLOCK_USED ((uint32_t)0x00000000U) /*!< Sampling clock is delayed by the delay block */ 384 #define HAL_OSPI_DELAY_BLOCK_BYPASSED ((uint32_t)OCTOSPI_DCR1_DLYBYP) /*!< Delay block is bypassed */ 385 /** 386 * @} 387 */ 388 389 /** @defgroup OSPI_OperationType OSPI Operation Type 390 * @{ 391 */ 392 #define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ 393 #define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U) /*!< Read configuration (memory-mapped mode) */ 394 #define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U) /*!< Write configuration (memory-mapped mode) */ 395 #define HAL_OSPI_OPTYPE_WRAP_CFG ((uint32_t)0x00000003U) /*!< Wrap configuration (memory-mapped mode) */ 396 /** 397 * @} 398 */ 399 400 /** @defgroup OSPI_FlashID OSPI Flash Id 401 * @{ 402 */ 403 #define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */ 404 #define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL) /*!< FLASH 2 selected */ 405 /** 406 * @} 407 */ 408 409 /** @defgroup OSPI_InstructionMode OSPI Instruction Mode 410 * @{ 411 */ 412 #define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!< No instruction */ 413 #define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0) /*!< Instruction on a single line */ 414 #define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1) /*!< Instruction on two lines */ 415 #define HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1)) /*!< Instruction on four lines */ 416 #define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ 417 /** 418 * @} 419 */ 420 421 /** @defgroup OSPI_InstructionSize OSPI Instruction Size 422 * @{ 423 */ 424 #define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit instruction */ 425 #define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ 426 #define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ 427 #define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE) /*!< 32-bit instruction */ 428 /** 429 * @} 430 */ 431 432 /** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode 433 * @{ 434 */ 435 #define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for instruction phase */ 436 #define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ 437 /** 438 * @} 439 */ 440 441 /** @defgroup OSPI_AddressMode OSPI Address Mode 442 * @{ 443 */ 444 #define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!< No address */ 445 #define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0) /*!< Address on a single line */ 446 #define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1) /*!< Address on two lines */ 447 #define HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1)) /*!< Address on four lines */ 448 #define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2) /*!< Address on eight lines */ 449 /** 450 * @} 451 */ 452 453 /** @defgroup OSPI_AddressSize OSPI Address Size 454 * @{ 455 */ 456 #define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit address */ 457 #define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0) /*!< 16-bit address */ 458 #define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1) /*!< 24-bit address */ 459 #define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE) /*!< 32-bit address */ 460 /** 461 * @} 462 */ 463 464 /** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode 465 * @{ 466 */ 467 #define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for address phase */ 468 #define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ 469 /** 470 * @} 471 */ 472 473 /** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode 474 * @{ 475 */ 476 #define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!< No alternate bytes */ 477 #define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ 478 #define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ 479 #define HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */ 480 #define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ 481 /** 482 * @} 483 */ 484 485 /** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size 486 * @{ 487 */ 488 #define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit alternate bytes */ 489 #define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ 490 #define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ 491 #define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ 492 /** 493 * @} 494 */ 495 496 /** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode 497 * @{ 498 */ 499 #define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ 500 #define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ 501 /** 502 * @} 503 */ 504 505 /** @defgroup OSPI_DataMode OSPI Data Mode 506 * @{ 507 */ 508 #define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U) /*!< No data */ 509 #define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0) /*!< Data on a single line */ 510 #define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1) /*!< Data on two lines */ 511 #define HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1)) /*!< Data on four lines */ 512 #define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2) /*!< Data on eight lines */ 513 /** 514 * @} 515 */ 516 517 /** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode 518 * @{ 519 */ 520 #define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for data phase */ 521 #define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ 522 /** 523 * @} 524 */ 525 526 /** @defgroup OSPI_DQSMode OSPI DQS Mode 527 * @{ 528 */ 529 #define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U) /*!< DQS disabled */ 530 #define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE) /*!< DQS enabled */ 531 /** 532 * @} 533 */ 534 535 /** @defgroup OSPI_SIOOMode OSPI SIOO Mode 536 * @{ 537 */ 538 #define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!< Send instruction on every transaction */ 539 #define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO) /*!< Send instruction only for the first command */ 540 /** 541 * @} 542 */ 543 544 /** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation 545 * @{ 546 */ 547 #define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U) /*!< Latency on write accesses */ 548 #define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL) /*!< No latency on write accesses */ 549 /** 550 * @} 551 */ 552 553 /** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode 554 * @{ 555 */ 556 #define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U) /*!< Variable initial latency */ 557 #define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM) /*!< Fixed latency */ 558 /** 559 * @} 560 */ 561 562 /** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space 563 * @{ 564 */ 565 #define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U) /*!< HyperBus memory mode */ 566 #define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ 567 /** 568 * @} 569 */ 570 571 /** @defgroup OSPI_MatchMode OSPI Match Mode 572 * @{ 573 */ 574 #define HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!< AND match mode between unmasked bits */ 575 #define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bits */ 576 /** 577 * @} 578 */ 579 580 /** @defgroup OSPI_AutomaticStop OSPI Automatic Stop 581 * @{ 582 */ 583 #define HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!< AutoPolling stops only with abort or OSPI disabling */ 584 #define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ 585 /** 586 * @} 587 */ 588 589 /** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation 590 * @{ 591 */ 592 #define HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!< Timeout counter disabled, nCS remains active */ 593 #define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ 594 /** 595 * @} 596 */ 597 598 /** @defgroup OSPI_Flags OSPI Flags 599 * @{ 600 */ 601 #define HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY /*!< Busy flag: operation is ongoing */ 602 #define HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */ 603 #define HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */ 604 #define HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */ 605 #define HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */ 606 #define HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */ 607 /** 608 * @} 609 */ 610 611 /** @defgroup OSPI_Interrupts OSPI Interrupts 612 * @{ 613 */ 614 #define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE /*!< Interrupt on the timeout flag */ 615 #define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE /*!< Interrupt on the status match flag */ 616 #define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ 617 #define HAL_OSPI_IT_TC OCTOSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */ 618 #define HAL_OSPI_IT_TE OCTOSPI_CR_TEIE /*!< Interrupt on the transfer error flag */ 619 /** 620 * @} 621 */ 622 623 /** @defgroup OSPI_Timeout_definition OSPI Timeout definition 624 * @{ 625 */ 626 #define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */ 627 /** 628 * @} 629 */ 630 631 /** 632 * @} 633 */ 634 635 /* Exported macros -----------------------------------------------------------*/ 636 /** @defgroup OSPI_Exported_Macros OSPI Exported Macros 637 * @{ 638 */ 639 /** @brief Reset OSPI handle state. 640 * @param __HANDLE__ specifies the OSPI Handle. 641 * @retval None 642 */ 643 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 644 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 645 (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \ 646 (__HANDLE__)->MspInitCallback = NULL; \ 647 (__HANDLE__)->MspDeInitCallback = NULL; \ 648 } while(0) 649 #else 650 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET) 651 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 652 653 /** @brief Enable the OSPI peripheral. 654 * @param __HANDLE__ specifies the OSPI Handle. 655 * @retval None 656 */ 657 #define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) 658 659 /** @brief Disable the OSPI peripheral. 660 * @param __HANDLE__ specifies the OSPI Handle. 661 * @retval None 662 */ 663 #define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) 664 665 /** @brief Enable the specified OSPI interrupt. 666 * @param __HANDLE__ specifies the OSPI Handle. 667 * @param __INTERRUPT__ specifies the OSPI interrupt source to enable. 668 * This parameter can be one of the following values: 669 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 670 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 671 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 672 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 673 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 674 * @retval None 675 */ 676 #define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 677 678 679 /** @brief Disable the specified OSPI interrupt. 680 * @param __HANDLE__ specifies the OSPI Handle. 681 * @param __INTERRUPT__ specifies the OSPI interrupt source to disable. 682 * This parameter can be one of the following values: 683 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 684 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 685 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 686 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 687 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 688 * @retval None 689 */ 690 #define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 691 692 /** @brief Check whether the specified OSPI interrupt source is enabled or not. 693 * @param __HANDLE__ specifies the OSPI Handle. 694 * @param __INTERRUPT__ specifies the OSPI interrupt source to check. 695 * This parameter can be one of the following values: 696 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 697 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 698 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 699 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 700 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 701 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 702 */ 703 #define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\ 704 == (__INTERRUPT__)) 705 706 /** 707 * @brief Check whether the selected OSPI flag is set or not. 708 * @param __HANDLE__ specifies the OSPI Handle. 709 * @param __FLAG__ specifies the OSPI flag to check. 710 * This parameter can be one of the following values: 711 * @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag 712 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag 713 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag 714 * @arg HAL_OSPI_FLAG_FT: OSPI FIFO threshold flag 715 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag 716 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag 717 * @retval None 718 */ 719 #define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \ 720 != 0U) ? SET : RESET) 721 722 /** @brief Clears the specified OSPI's flag status. 723 * @param __HANDLE__ specifies the OSPI Handle. 724 * @param __FLAG__ specifies the OSPI clear register flag that needs to be set 725 * This parameter can be one of the following values: 726 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag 727 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag 728 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag 729 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag 730 * @retval None 731 */ 732 #define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 733 734 /** 735 * @} 736 */ 737 738 /* Exported functions --------------------------------------------------------*/ 739 /** @addtogroup OSPI_Exported_Functions 740 * @{ 741 */ 742 743 /* Initialization/de-initialization functions ********************************/ 744 /** @addtogroup OSPI_Exported_Functions_Group1 745 * @{ 746 */ 747 HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi); 748 void HAL_OSPI_MspInit (OSPI_HandleTypeDef *hospi); 749 HAL_StatusTypeDef HAL_OSPI_DeInit (OSPI_HandleTypeDef *hospi); 750 void HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi); 751 752 /** 753 * @} 754 */ 755 756 /* IO operation functions *****************************************************/ 757 /** @addtogroup OSPI_Exported_Functions_Group2 758 * @{ 759 */ 760 /* OSPI IRQ handler function */ 761 void HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi); 762 763 /* OSPI command configuration functions */ 764 HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout); 765 HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); 766 HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout); 767 HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout); 768 769 /* OSPI indirect mode functions */ 770 HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); 771 HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); 772 HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData); 773 HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData); 774 HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData); 775 HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData); 776 777 /* OSPI status flag polling mode functions */ 778 HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 779 HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg); 780 781 /* OSPI memory-mapped mode functions */ 782 HAL_StatusTypeDef HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg); 783 784 /* Callback functions in non-blocking modes ***********************************/ 785 void HAL_OSPI_ErrorCallback (OSPI_HandleTypeDef *hospi); 786 void HAL_OSPI_AbortCpltCallback (OSPI_HandleTypeDef *hospi); 787 void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi); 788 789 /* OSPI indirect mode functions */ 790 void HAL_OSPI_CmdCpltCallback (OSPI_HandleTypeDef *hospi); 791 void HAL_OSPI_RxCpltCallback (OSPI_HandleTypeDef *hospi); 792 void HAL_OSPI_TxCpltCallback (OSPI_HandleTypeDef *hospi); 793 void HAL_OSPI_RxHalfCpltCallback (OSPI_HandleTypeDef *hospi); 794 void HAL_OSPI_TxHalfCpltCallback (OSPI_HandleTypeDef *hospi); 795 796 /* OSPI status flag polling mode functions */ 797 void HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi); 798 799 /* OSPI memory-mapped mode functions */ 800 void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi); 801 802 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 803 /* OSPI callback registering/unregistering */ 804 HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, 805 pOSPI_CallbackTypeDef pCallback); 806 HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID); 807 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 808 /** 809 * @} 810 */ 811 812 /* Peripheral Control and State functions ************************************/ 813 /** @addtogroup OSPI_Exported_Functions_Group3 814 * @{ 815 */ 816 HAL_StatusTypeDef HAL_OSPI_Abort (OSPI_HandleTypeDef *hospi); 817 HAL_StatusTypeDef HAL_OSPI_Abort_IT (OSPI_HandleTypeDef *hospi); 818 HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold (OSPI_HandleTypeDef *hospi, uint32_t Threshold); 819 uint32_t HAL_OSPI_GetFifoThreshold (OSPI_HandleTypeDef *hospi); 820 HAL_StatusTypeDef HAL_OSPI_SetTimeout (OSPI_HandleTypeDef *hospi, uint32_t Timeout); 821 uint32_t HAL_OSPI_GetError (OSPI_HandleTypeDef *hospi); 822 uint32_t HAL_OSPI_GetState (OSPI_HandleTypeDef *hospi); 823 824 /** 825 * @} 826 */ 827 828 /** 829 * @} 830 */ 831 /* End of exported functions -------------------------------------------------*/ 832 833 /* Private macros ------------------------------------------------------------*/ 834 /** 835 @cond 0 836 */ 837 #define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U)) 838 839 #define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ 840 ((MODE) == HAL_OSPI_DUALQUAD_ENABLE)) 841 842 #define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ 843 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ 844 ((TYPE) == HAL_OSPI_MEMTYPE_APMEMORY) || \ 845 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \ 846 ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) 847 848 #define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U)) 849 850 #define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U)) 851 852 #define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \ 853 ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE)) 854 855 #define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \ 856 ((MODE) == HAL_OSPI_CLOCK_MODE_3)) 857 858 #define IS_OSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_OSPI_WRAP_NOT_SUPPORTED) || \ 859 ((SIZE) == HAL_OSPI_WRAP_16_BYTES) || \ 860 ((SIZE) == HAL_OSPI_WRAP_32_BYTES) || \ 861 ((SIZE) == HAL_OSPI_WRAP_64_BYTES) || \ 862 ((SIZE) == HAL_OSPI_WRAP_128_BYTES)) 863 864 #define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U)) 865 866 #define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \ 867 ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE)) 868 869 #define IS_OSPI_DHQC(CYCLE) (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \ 870 ((CYCLE) == HAL_OSPI_DHQC_ENABLE)) 871 872 #define IS_OSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \ 873 ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG) || \ 874 ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG) || \ 875 ((TYPE) == HAL_OSPI_OPTYPE_WRAP_CFG)) 876 877 #define IS_OSPI_FLASH_ID(FLASHID) (((FLASHID) == HAL_OSPI_FLASH_ID_1) || \ 878 ((FLASHID) == HAL_OSPI_FLASH_ID_2)) 879 880 #define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \ 881 ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \ 882 ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \ 883 ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \ 884 ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES)) 885 886 #define IS_OSPI_INSTRUCTION_SIZE(SIZE) (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS) || \ 887 ((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \ 888 ((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \ 889 ((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS)) 890 891 #define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \ 892 ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) 893 894 #define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \ 895 ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \ 896 ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \ 897 ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \ 898 ((MODE) == HAL_OSPI_ADDRESS_8_LINES)) 899 900 #define IS_OSPI_ADDRESS_SIZE(SIZE) (((SIZE) == HAL_OSPI_ADDRESS_8_BITS) || \ 901 ((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \ 902 ((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \ 903 ((SIZE) == HAL_OSPI_ADDRESS_32_BITS)) 904 905 #define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \ 906 ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE)) 907 908 #define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \ 909 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \ 910 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \ 911 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \ 912 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES)) 913 914 #define IS_OSPI_ALT_BYTES_SIZE(SIZE) (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS) || \ 915 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \ 916 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \ 917 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS)) 918 919 #define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \ 920 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE)) 921 922 #define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \ 923 ((MODE) == HAL_OSPI_DATA_1_LINE) || \ 924 ((MODE) == HAL_OSPI_DATA_2_LINES) || \ 925 ((MODE) == HAL_OSPI_DATA_4_LINES) || \ 926 ((MODE) == HAL_OSPI_DATA_8_LINES)) 927 928 #define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1U) 929 930 #define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \ 931 ((MODE) == HAL_OSPI_DATA_DTR_ENABLE)) 932 933 #define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U) 934 935 #define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \ 936 ((MODE) == HAL_OSPI_DQS_ENABLE)) 937 938 #define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \ 939 ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD)) 940 941 #define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255U) 942 943 #define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255U) 944 945 #define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \ 946 ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE)) 947 948 #define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \ 949 ((MODE) == HAL_OSPI_FIXED_LATENCY)) 950 951 #define IS_OSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \ 952 ((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE)) 953 954 #define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \ 955 ((MODE) == HAL_OSPI_MATCH_MODE_OR)) 956 957 #define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \ 958 ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE)) 959 960 #define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU) 961 962 #define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 963 964 #define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ 965 ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)) 966 967 #define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 968 969 #define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U) 970 971 #define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \ 972 ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED)) 973 /** 974 @endcond 975 */ 976 977 /* End of private macros -----------------------------------------------------*/ 978 979 /** 980 * @} 981 */ 982 983 /** 984 * @} 985 */ 986 987 #endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */ 988 989 #ifdef __cplusplus 990 } 991 #endif 992 993 #endif /* STM32L5xx_HAL_OSPI_H */ 994
