1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_nand.h 4 * @author MCD Application Team 5 * @brief Header file of NAND HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L5xx_HAL_NAND_H 21 #define STM32L5xx_HAL_NAND_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l5xx_ll_fmc.h" 30 31 /** @addtogroup STM32L5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup NAND 36 * @{ 37 */ 38 39 /* Exported typedef ----------------------------------------------------------*/ 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup NAND_Exported_Types NAND Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief HAL NAND State structures definition 47 */ 48 typedef enum 49 { 50 HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ 51 HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ 52 HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ 53 HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ 54 } HAL_NAND_StateTypeDef; 55 56 /** 57 * @brief NAND Memory electronic signature Structure definition 58 */ 59 typedef struct 60 { 61 /*<! NAND memory electronic signature maker and device IDs */ 62 63 uint8_t Maker_Id; 64 65 uint8_t Device_Id; 66 67 uint8_t Third_Id; 68 69 uint8_t Fourth_Id; 70 } NAND_IDTypeDef; 71 72 /** 73 * @brief NAND Memory address Structure definition 74 */ 75 typedef struct 76 { 77 uint16_t Page; /*!< NAND memory Page address */ 78 79 uint16_t Plane; /*!< NAND memory Zone address */ 80 81 uint16_t Block; /*!< NAND memory Block address */ 82 83 } NAND_AddressTypeDef; 84 85 /** 86 * @brief NAND Memory info Structure definition 87 */ 88 typedef struct 89 { 90 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes 91 for 8 bits addressing or words for 16 bits addressing */ 92 93 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes 94 for 8 bits addressing or words for 16 bits addressing */ 95 96 uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ 97 98 uint32_t BlockNbr; /*!< NAND memory number of total blocks */ 99 100 uint32_t PlaneNbr; /*!< NAND memory number of planes */ 101 102 uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */ 103 104 FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This 105 parameter is mandatory for some NAND parts after the read 106 command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. 107 Example: Toshiba THTH58BYG3S0HBAI6. 108 This parameter could be ENABLE or DISABLE 109 Please check the Read Mode sequnece in the NAND device datasheet */ 110 } NAND_DeviceConfigTypeDef; 111 112 /** 113 * @brief NAND handle Structure definition 114 */ 115 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 116 typedef struct __NAND_HandleTypeDef 117 #else 118 typedef struct 119 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 120 { 121 FMC_NAND_TypeDef *Instance; /*!< Register base address */ 122 123 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ 124 125 HAL_LockTypeDef Lock; /*!< NAND locking object */ 126 127 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ 128 129 NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ 130 131 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 132 void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ 133 void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */ 134 void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */ 135 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 136 } NAND_HandleTypeDef; 137 138 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 139 /** 140 * @brief HAL NAND Callback ID enumeration definition 141 */ 142 typedef enum 143 { 144 HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */ 145 HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */ 146 HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */ 147 } HAL_NAND_CallbackIDTypeDef; 148 149 /** 150 * @brief HAL NAND Callback pointer definition 151 */ 152 typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); 153 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 154 155 /** 156 * @} 157 */ 158 159 /* Exported constants --------------------------------------------------------*/ 160 /* Exported macro ------------------------------------------------------------*/ 161 /** @defgroup NAND_Exported_Macros NAND Exported Macros 162 * @{ 163 */ 164 165 /** @brief Reset NAND handle state 166 * @param __HANDLE__ specifies the NAND handle. 167 * @retval None 168 */ 169 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 170 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \ 171 (__HANDLE__)->State = HAL_NAND_STATE_RESET; \ 172 (__HANDLE__)->MspInitCallback = NULL; \ 173 (__HANDLE__)->MspDeInitCallback = NULL; \ 174 } while(0) 175 #else 176 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) 177 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 178 179 /** 180 * @} 181 */ 182 183 /* Exported functions --------------------------------------------------------*/ 184 /** @addtogroup NAND_Exported_Functions NAND Exported Functions 185 * @{ 186 */ 187 188 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions 189 * @{ 190 */ 191 192 /* Initialization/de-initialization functions ********************************/ 193 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, 194 FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); 195 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); 196 197 HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); 198 199 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); 200 201 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); 202 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); 203 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); 204 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); 205 206 /** 207 * @} 208 */ 209 210 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions 211 * @{ 212 */ 213 214 /* IO operation functions ****************************************************/ 215 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); 216 217 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, 218 uint32_t NumPageToRead); 219 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, 220 uint32_t NumPageToWrite); 221 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 222 uint8_t *pBuffer, uint32_t NumSpareAreaToRead); 223 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 224 uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); 225 226 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, 227 uint32_t NumPageToRead); 228 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, 229 uint32_t NumPageToWrite); 230 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 231 uint16_t *pBuffer, uint32_t NumSpareAreaToRead); 232 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 233 uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); 234 235 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); 236 237 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); 238 239 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 240 /* NAND callback registering/unregistering */ 241 HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, 242 pNAND_CallbackTypeDef pCallback); 243 HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId); 244 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 245 246 /** 247 * @} 248 */ 249 250 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions 251 * @{ 252 */ 253 254 /* NAND Control functions ****************************************************/ 255 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); 256 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); 257 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); 258 259 /** 260 * @} 261 */ 262 263 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions 264 * @{ 265 */ 266 /* NAND State functions *******************************************************/ 267 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); 268 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); 269 /** 270 * @} 271 */ 272 273 /** 274 * @} 275 */ 276 277 /* Private types -------------------------------------------------------------*/ 278 /* Private variables ---------------------------------------------------------*/ 279 /* Private constants ---------------------------------------------------------*/ 280 /** @defgroup NAND_Private_Constants NAND Private Constants 281 * @{ 282 */ 283 #define NAND_DEVICE 0x80000000UL 284 #define NAND_WRITE_TIMEOUT 0x01000000UL 285 286 #define CMD_AREA (1UL<<16U) /* A16 = CLE high */ 287 #define ADDR_AREA (1UL<<17U) /* A17 = ALE high */ 288 289 #define NAND_CMD_AREA_A ((uint8_t)0x00) 290 #define NAND_CMD_AREA_B ((uint8_t)0x01) 291 #define NAND_CMD_AREA_C ((uint8_t)0x50) 292 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) 293 294 #define NAND_CMD_WRITE0 ((uint8_t)0x80) 295 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) 296 #define NAND_CMD_ERASE0 ((uint8_t)0x60) 297 #define NAND_CMD_ERASE1 ((uint8_t)0xD0) 298 #define NAND_CMD_READID ((uint8_t)0x90) 299 #define NAND_CMD_STATUS ((uint8_t)0x70) 300 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) 301 #define NAND_CMD_RESET ((uint8_t)0xFF) 302 303 /* NAND memory status */ 304 #define NAND_VALID_ADDRESS 0x00000100UL 305 #define NAND_INVALID_ADDRESS 0x00000200UL 306 #define NAND_TIMEOUT_ERROR 0x00000400UL 307 #define NAND_BUSY 0x00000000UL 308 #define NAND_ERROR 0x00000001UL 309 #define NAND_READY 0x00000040UL 310 /** 311 * @} 312 */ 313 314 /* Private macros ------------------------------------------------------------*/ 315 /** @defgroup NAND_Private_Macros NAND Private Macros 316 * @{ 317 */ 318 319 /** 320 * @brief NAND memory address computation. 321 * @param __ADDRESS__ NAND memory address. 322 * @param __HANDLE__ NAND handle. 323 * @retval NAND Raw address value 324 */ 325 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ 326 (((__ADDRESS__)->Block + \ 327 (((__ADDRESS__)->Plane) * \ 328 ((__HANDLE__)->Config.PlaneSize))) * \ 329 ((__HANDLE__)->Config.BlockSize))) 330 331 /** 332 * @brief NAND memory Column address computation. 333 * @param __HANDLE__ NAND handle. 334 * @retval NAND Raw address value 335 */ 336 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) 337 338 /** 339 * @brief NAND memory address cycling. 340 * @param __ADDRESS__ NAND memory address. 341 * @retval NAND address cycling value. 342 */ 343 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ 344 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ 345 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ 346 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ 347 348 /** 349 * @brief NAND memory Columns cycling. 350 * @param __ADDRESS__ NAND memory address. 351 * @retval NAND Column address cycling value. 352 */ 353 #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */ 354 #define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ 355 356 /** 357 * @} 358 */ 359 360 /** 361 * @} 362 */ 363 364 /** 365 * @} 366 */ 367 368 /** 369 * @} 370 */ 371 372 373 #ifdef __cplusplus 374 } 375 #endif 376 377 #endif /* STM32L5xx_HAL_NAND_H */ 378
