1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_gtzc.h 4 * @author MCD Application Team 5 * @brief Header file of GTZC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32L5xx_HAL_GTZC_H 20 #define STM32L5xx_HAL_GTZC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32l5xx_hal_def.h" 28 29 /** @addtogroup STM32L5xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup GTZC 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 39 /** @defgroup GTZC_Exported_Types GTZC Exported Types 40 * @{ 41 */ 42 43 /*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing. */ 44 #define GTZC_MCPBB_NB_VCTR_REG_MAX (24U) 45 #define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX (1U) 46 typedef struct 47 { 48 uint32_t MPCBB_SecConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for a super-block. 49 Each bit corresponds to a block inside the super block. 50 0 means non-secure, 1 means secure */ 51 uint32_t MPCBB_LockConfig_array[GTZC_MCPBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of a super-block (32 blocks). 52 0 means unlocked, 1 means locked */ 53 } MPCBB_Attribute_ConfigTypeDef; 54 55 typedef struct 56 { 57 uint32_t SecureRWIllegalMode; /*!< Secure read/write illegal access field. 58 It can be a value of @ref GTZC_MPCBB_SecureRWIllegalMode */ 59 uint32_t InvertSecureState; /*!< Default security state field (can be inverted or not). 60 It can be a value of @ref GTZC_MPCBB_InvertSecureState */ 61 MPCBB_Attribute_ConfigTypeDef AttributeConfig; /*!< MPCBB attribute configuration sub-structure */ 62 } MPCBB_ConfigTypeDef; 63 64 typedef struct 65 { 66 uint32_t AreaId; /*!< Area identifier field. It can be a value of @ref 67 GTZC_MPCWM_AreaId */ 68 uint32_t Offset; /*!< Offset of the watermark area, starting from the selected 69 memory base address. It must aligned on 128KB for FMC 70 and OCTOSPI memories */ 71 uint32_t Length; /*!< Length of the watermark area, starting from the selected 72 Offset. It must aligned on 128KB for FMC and OCTOSPI 73 memories */ 74 uint32_t Attribute; /*!< Attributes of the watermark area. It can be a value 75 of @ref GTZC_MPCWM_Attribute */ 76 } MPCWM_ConfigTypeDef; 77 78 /** 79 * @} 80 */ 81 82 /* Private constants ---------------------------------------------------------*/ 83 84 /** @defgroup GTZC_Private_Constants GTZC Private Constants 85 * @{ 86 */ 87 88 /** @defgroup GTZC_Private_PeriphId_composition GTZC Peripheral identifier composition 89 * @{ 90 */ 91 92 /* composition definition for Peripheral identifier parameter (PeriphId) used in 93 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 94 * functions and also in all HAL_GTZC_TZIC relative functions. 95 * Bitmap Definition 96 * bits[31:28] Field "register". Define the register index a peripheral belongs to. 97 * Each bit is dedicated to a single register. 98 * bit[5] Field "all peripherals". If this bit is set then the PeriphId targets 99 * all peripherals within all registers. 100 * bits[4:0] Field "bit position". Define the bit position within the 101 * register dedicated to the peripheral, value from 0 to 31. 102 */ 103 #define GTZC_PERIPH_REG_SHIFT (28U) 104 #define GTZC_PERIPH_REG (0xF0000000UL) 105 #define GTZC_PERIPH_REG1 (0x00000000UL) 106 #define GTZC_PERIPH_REG2 (0x10000000UL) 107 #define GTZC_PERIPH_REG3 (0x20000000UL) 108 #define GTZC_PERIPH_BIT_POSITION (0x0000001FUL) 109 110 /** 111 * @} 112 */ 113 114 /** @defgroup GTZC_Private_Attributes_Msk GTZC Attributes Masks 115 * @{ 116 */ 117 #define GTZC_ATTR_SEC_MASK 0x100U 118 #define GTZC_ATTR_PRIV_MASK 0x200U 119 120 /** 121 * @} 122 */ 123 124 /** 125 * @} 126 */ 127 128 /* Exported constants --------------------------------------------------------*/ 129 130 /** @defgroup GTZC_Exported_Constants GTZC Exported Constants 131 * @{ 132 */ 133 134 /** @defgroup GTZC_MPCBB_SecureRWIllegalMode GTZC MPCBB SRWILADIS values 135 * @{ 136 */ 137 138 #define GTZC_MPCBB_SRWILADIS_ENABLE (0U) 139 #define GTZC_MPCBB_SRWILADIS_DISABLE (GTZC_MPCBB_CR_SRWILADIS_Msk) 140 141 /** 142 * @} 143 */ 144 145 /** @defgroup GTZC_MPCBB_InvertSecureState GTZC MPCBB INVSECSTATE values 146 * @{ 147 */ 148 149 #define GTZC_MPCBB_INVSECSTATE_NOT_INVERTED (0U) 150 #define GTZC_MPCBB_INVSECSTATE_INVERTED (GTZC_MPCBB_CR_INVSECSTATE_Msk) 151 152 /** 153 * @} 154 */ 155 156 /** @defgroup GTZC_MPCWM_AreaId GTZC MPCWM area identifier values 157 * @{ 158 */ 159 160 #define GTZC_TZSC_MPCWM_ID1 (0U) 161 #define GTZC_TZSC_MPCWM_ID2 (1U) 162 163 /** 164 * @} 165 */ 166 167 /** @defgroup GTZC_TZSC_TZIC_PeriphId GTZC TZSC and TZIC Peripheral identifier values 168 * @{ 169 */ 170 #define GTZC_PERIPH_TIM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM2_Pos) 171 #define GTZC_PERIPH_TIM3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM3_Pos) 172 #define GTZC_PERIPH_TIM4 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM4_Pos) 173 #define GTZC_PERIPH_TIM5 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM5_Pos) 174 #define GTZC_PERIPH_TIM6 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM6_Pos) 175 #define GTZC_PERIPH_TIM7 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM7_Pos) 176 #define GTZC_PERIPH_WWDG (GTZC_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos) 177 #define GTZC_PERIPH_IWDG (GTZC_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos) 178 #define GTZC_PERIPH_SPI2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_SPI2_Pos) 179 #define GTZC_PERIPH_SPI3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_SPI3_Pos) 180 #define GTZC_PERIPH_USART2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos) 181 #define GTZC_PERIPH_USART3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_USART3_Pos) 182 #define GTZC_PERIPH_UART4 (GTZC_PERIPH_REG1 | GTZC_CFGR1_UART4_Pos) 183 #define GTZC_PERIPH_UART5 (GTZC_PERIPH_REG1 | GTZC_CFGR1_UART5_Pos) 184 #define GTZC_PERIPH_I2C1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I2C1_Pos) 185 #define GTZC_PERIPH_I2C2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I2C2_Pos) 186 #define GTZC_PERIPH_I2C3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I2C3_Pos) 187 #define GTZC_PERIPH_CRS (GTZC_PERIPH_REG1 | GTZC_CFGR1_CRS_Pos) 188 #define GTZC_PERIPH_DAC1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_DAC1_Pos) 189 #define GTZC_PERIPH_OPAMP (GTZC_PERIPH_REG1 | GTZC_CFGR1_OPAMP_Pos) 190 #define GTZC_PERIPH_LPTIM1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_LPTIM1_Pos) 191 #define GTZC_PERIPH_LPUART1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_LPUART1_Pos) 192 #define GTZC_PERIPH_I2C4 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I2C4_Pos) 193 #define GTZC_PERIPH_LPTIM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos) 194 #define GTZC_PERIPH_LPTIM3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_LPTIM3_Pos) 195 #define GTZC_PERIPH_FDCAN1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_FDCAN1_Pos) 196 #define GTZC_PERIPH_USBFS (GTZC_PERIPH_REG1 | GTZC_CFGR1_USBFS_Pos) 197 #define GTZC_PERIPH_UCPD1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_UCPD1_Pos) 198 #define GTZC_PERIPH_VREFBUF (GTZC_PERIPH_REG1 | GTZC_CFGR1_VREFBUF_Pos) 199 #define GTZC_PERIPH_COMP (GTZC_PERIPH_REG1 | GTZC_CFGR1_COMP_Pos) 200 #define GTZC_PERIPH_TIM1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM1_Pos) 201 #define GTZC_PERIPH_SPI1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_SPI1_Pos) 202 #define GTZC_PERIPH_TIM8 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM8_Pos) 203 #define GTZC_PERIPH_USART1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_USART1_Pos) 204 #define GTZC_PERIPH_TIM15 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM15_Pos) 205 #define GTZC_PERIPH_TIM16 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos) 206 #define GTZC_PERIPH_TIM17 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos) 207 #define GTZC_PERIPH_SAI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos) 208 #define GTZC_PERIPH_SAI2 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SAI2_Pos) 209 #define GTZC_PERIPH_DFSDM1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_DFSDM1_Pos) 210 #define GTZC_PERIPH_CRC (GTZC_PERIPH_REG2 | GTZC_CFGR2_CRC_Pos) 211 #define GTZC_PERIPH_TSC (GTZC_PERIPH_REG2 | GTZC_CFGR2_TSC_Pos) 212 #define GTZC_PERIPH_ICACHE_REG (GTZC_PERIPH_REG2 | GTZC_CFGR2_ICACHE_REG_Pos) 213 #define GTZC_PERIPH_ADC (GTZC_PERIPH_REG2 | GTZC_CFGR2_ADC_Pos) 214 #define GTZC_PERIPH_AES (GTZC_PERIPH_REG2 | GTZC_CFGR2_AES_Pos) 215 #define GTZC_PERIPH_HASH (GTZC_PERIPH_REG2 | GTZC_CFGR2_HASH_Pos) 216 #define GTZC_PERIPH_RNG (GTZC_PERIPH_REG2 | GTZC_CFGR2_RNG_Pos) 217 #define GTZC_PERIPH_PKA (GTZC_PERIPH_REG2 | GTZC_CFGR2_PKA_Pos) 218 #define GTZC_PERIPH_SDMMC1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SDMMC1_Pos) 219 #define GTZC_PERIPH_FMC_REG (GTZC_PERIPH_REG2 | GTZC_CFGR2_FMC_REG_Pos) 220 #define GTZC_PERIPH_OCTOSPI1_REG (GTZC_PERIPH_REG2 | GTZC_CFGR2_OCTOSPI1_REG_Pos) 221 #define GTZC_PERIPH_RTC (GTZC_PERIPH_REG2 | GTZC_CFGR2_RTC_Pos) 222 #define GTZC_PERIPH_PWR (GTZC_PERIPH_REG2 | GTZC_CFGR2_PWR_Pos) 223 #define GTZC_PERIPH_SYSCFG (GTZC_PERIPH_REG2 | GTZC_CFGR2_SYSCFG_Pos) 224 #define GTZC_PERIPH_DMA1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_DMA1_Pos) 225 #define GTZC_PERIPH_DMA2 (GTZC_PERIPH_REG2 | GTZC_CFGR2_DMA2_Pos) 226 #define GTZC_PERIPH_DMAMUX1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_DMAMUX1_Pos) 227 #define GTZC_PERIPH_RCC (GTZC_PERIPH_REG2 | GTZC_CFGR2_RCC_Pos) 228 #define GTZC_PERIPH_FLASH (GTZC_PERIPH_REG2 | GTZC_CFGR2_FLASH_Pos) 229 #define GTZC_PERIPH_FLASH_REG (GTZC_PERIPH_REG2 | GTZC_CFGR2_FLASH_REG_Pos) 230 #define GTZC_PERIPH_EXTI (GTZC_PERIPH_REG2 | GTZC_CFGR2_EXTI_Pos) 231 #define GTZC_PERIPH_OTFDEC1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_OTFDEC1_Pos) 232 #define GTZC_PERIPH_TZSC (GTZC_PERIPH_REG3 | GTZC_CFGR3_TZSC_Pos) 233 #define GTZC_PERIPH_TZIC (GTZC_PERIPH_REG3 | GTZC_CFGR3_TZIC_Pos) 234 #define GTZC_PERIPH_FMC_MEM (GTZC_PERIPH_REG3 | GTZC_CFGR3_FMC_MEM_Pos) 235 #define GTZC_PERIPH_OCTOSPI1_MEM (GTZC_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI1_MEM_Pos) 236 #define GTZC_PERIPH_SRAM1 (GTZC_PERIPH_REG3 | GTZC_CFGR3_SRAM1_Pos) 237 #define GTZC_PERIPH_MPCBB1_REG (GTZC_PERIPH_REG3 | GTZC_CFGR3_MPCBB1_REG_Pos) 238 #define GTZC_PERIPH_SRAM2 (GTZC_PERIPH_REG3 | GTZC_CFGR3_SRAM2_Pos) 239 #define GTZC_PERIPH_MPCBB2_REG (GTZC_PERIPH_REG3 | GTZC_CFGR3_MPCBB2_REG_Pos) 240 241 #define GTZC_PERIPH_ALL (0x00000020U) 242 243 /* Note that two maximum values are also defined here: 244 * - max number of securable AHB/APB peripherals or masters 245 * (used in TZSC sub-block) 246 * - max number of securable and TrustZone-aware AHB/APB peripherals or masters 247 * (used in TZIC sub-block) 248 */ 249 #define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_OCTOSPI1_REG + 1U)) 250 #define GTZC_TZIC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_MPCBB2_REG + 1U)) 251 252 /** 253 * @} 254 */ 255 256 /** @defgroup GTZC_TZSC_PeriphAttributes GTZC TZSC peripheral attribute values 257 * @note secure and non-secure attributes are only available from secure state when the system 258 * implement the security (TZEN=1) 259 * @{ 260 */ 261 262 /* user-oriented definitions for attribute parameter (PeriphAttributes) used in 263 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 264 * functions 265 */ 266 #define GTZC_TZSC_PERIPH_SEC (GTZC_ATTR_SEC_MASK | 0x00000001U) /*!< Secure attribute */ 267 #define GTZC_TZSC_PERIPH_NSEC (GTZC_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure attribute */ 268 #define GTZC_TZSC_PERIPH_PRIV (GTZC_ATTR_PRIV_MASK | 0x00000002U) /*!< Privilege attribute */ 269 #define GTZC_TZSC_PERIPH_NPRIV (GTZC_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privilege attribute */ 270 271 /** 272 * @} 273 */ 274 275 /** @defgroup GTZC_TZSC_Lock GTZC TZSC lock values 276 * @{ 277 */ 278 279 /* user-oriented definitions for HAL_GTZC_TZSC_GetLock() returned value */ 280 #define GTZC_TZSC_LOCK_OFF (0U) 281 #define GTZC_TZSC_LOCK_ON GTZC_TZSC_CR_LCK_Msk 282 283 /** 284 * @} 285 */ 286 287 /** @defgroup GTZC_MPCWM_Group GTZC MPCWM values 288 * @{ 289 */ 290 291 /* user-oriented definitions for TZSC_MPCWM */ 292 #define GTZC_TZSC_MPCWM_GRANULARITY 0x00020000U /* OCTOSPI & FMC granularity: 128 kbytes */ 293 294 /** 295 * @} 296 */ 297 298 /** @defgroup GTZC_MPCWM_Attribute GTZC MPCWM Attribute values 299 * @{ 300 */ 301 302 /* user-oriented definitions for TZSC_MPCWM */ 303 #define GTZC_TZSC_MPCWM_REGION_NSEC (0U) 304 #define GTZC_TZSC_MPCWM_REGION_SEC (1U) 305 306 /** 307 * @} 308 */ 309 310 /** @defgroup GTZC_MPCBB_Group GTZC MPCBB values 311 * @{ 312 */ 313 314 /* user-oriented definitions for MPCBB */ 315 #define GTZC_MPCBB_BLOCK_SIZE 0x100U /* 256 Bytes */ 316 #define GTZC_MPCBB_SUPERBLOCK_SIZE (GTZC_MPCBB_BLOCK_SIZE * 32U) /* 8 KBytes */ 317 #define GTZC_MCPBB_SUPERBLOCK_UNLOCKED (0U) 318 #define GTZC_MCPBB_SUPERBLOCK_LOCKED (1U) 319 320 #define GTZC_MCPBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U) 321 #define GTZC_MCPBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U) 322 323 /* user-oriented definitions for HAL_GTZC_MPCBB_GetLock() returned value */ 324 #define GTZC_MCPBB_LOCK_OFF (0U) 325 #define GTZC_MCPBB_LOCK_ON (1U) 326 327 /** 328 * @} 329 */ 330 331 /** @defgroup GTZC_TZIC_Flag GTZC TZIC flag values 332 * @{ 333 */ 334 335 /* user-oriented definitions for HAL_GTZC_TZIC_GetFlag() flag parameter */ 336 #define GTZC_TZIC_NO_ILA_EVENT (0U) 337 #define GTZC_TZIC_ILA_EVENT_PENDING (1U) 338 339 /** 340 * @} 341 */ 342 343 /** 344 * @} 345 */ 346 347 /* Private macros ------------------------------------------------------------*/ 348 349 /** @defgroup GTZC_Private_Macros GTZC Private Macros 350 * @{ 351 */ 352 353 /* retrieve information to access register for a specific PeriphId */ 354 #define GTZC_GET_REG_INDEX(periph_id)\ 355 (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) 356 #define GTZC_GET_PERIPH_POS(periph_id) ((periph_id) & GTZC_PERIPH_BIT_POSITION) 357 358 #define IS_GTZC_BASE_ADDRESS(mem, address)\ 359 ( ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) || \ 360 ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) ) 361 362 #define GTZC_MEM_SIZE(mem)\ 363 ( mem ## _SIZE ) 364 365 #define GTZC_BASE_ADDRESS_S(mem)\ 366 ( mem ## _BASE_S ) 367 368 #define GTZC_BASE_ADDRESS_NS(mem)\ 369 ( mem ## _BASE_NS ) 370 371 /** 372 * @} 373 */ 374 375 /* Exported macros -----------------------------------------------------------*/ 376 377 /** @defgroup GTZC_Exported_Macros GTZC Exported Macros 378 * @{ 379 */ 380 381 /* user-oriented macro to get array index of a specific PeriphId 382 * in case of GTZC_PERIPH_ALL usage in the two following functions: 383 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 384 */ 385 #define HAL_GTZC_GET_ARRAY_INDEX(periph_id)\ 386 ( (GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id)) ) 387 388 /** 389 * @} 390 */ 391 392 /* Exported functions --------------------------------------------------------*/ 393 394 /** @addtogroup GTZC_Exported_Functions 395 * @{ 396 */ 397 398 /** @addtogroup GTZC_Exported_Functions_Group1 399 * @brief TZSC Initialization and Configuration functions 400 * @{ 401 */ 402 403 HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, 404 uint32_t PeriphAttributes); 405 HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, 406 uint32_t *PeriphAttributes); 407 408 /** 409 * @} 410 */ 411 412 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 413 414 /** @addtogroup GTZC_Exported_Functions_Group2 415 * @brief MPCWM Initialization and Configuration functions 416 * @{ 417 */ 418 419 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, 420 const MPCWM_ConfigTypeDef *pMPCWM_Desc); 421 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, 422 MPCWM_ConfigTypeDef *pMPCWM_Desc); 423 /** 424 * @} 425 */ 426 427 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 428 429 /** @addtogroup GTZC_Exported_Functions_Group3 430 * @brief TZSC and TZSC-MPCWM Lock functions 431 * @{ 432 */ 433 434 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 435 void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance); 436 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 437 uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance); 438 439 /** 440 * @} 441 */ 442 443 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 444 445 /** @addtogroup GTZC_Exported_Functions_Group4 446 * @brief MPCBB Initialization and Configuration functions 447 * @{ 448 */ 449 450 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, 451 const MPCBB_ConfigTypeDef *pMPCBB_desc); 452 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, 453 MPCBB_ConfigTypeDef *pMPCBB_desc); 454 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, 455 uint32_t NbBlocks, 456 const uint32_t *pMemAttributes); 457 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, 458 uint32_t NbBlocks, 459 uint32_t *pMemAttributes); 460 HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, 461 uint32_t NbSuperBlocks, 462 const uint32_t *pLockAttributes); 463 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, 464 uint32_t NbSuperBlocks, 465 uint32_t *pLockAttributes); 466 HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress); 467 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, 468 uint32_t *pLockState); 469 470 /** 471 * @} 472 */ 473 474 /** @addtogroup GTZC_Exported_Functions_Group5 475 * @brief TZIC functions 476 * @{ 477 */ 478 479 HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId); 480 HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId); 481 HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag); 482 HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId); 483 484 /** 485 * @} 486 */ 487 488 /** @addtogroup GTZC_Exported_Functions_Group6 489 * @brief IRQ related Functions 490 * @{ 491 */ 492 493 void HAL_GTZC_IRQHandler(void); 494 void HAL_GTZC_TZIC_Callback(uint32_t PeriphId); 495 496 /** 497 * @} 498 */ 499 500 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 501 502 /** 503 * @} 504 */ 505 506 /** 507 * @} 508 */ 509 510 /** 511 * @} 512 */ 513 514 #ifdef __cplusplus 515 } 516 #endif 517 518 #endif /* STM32L5xx_HAL_GTZC_H */ 519
