1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_flash.h 4 * @author MCD Application Team 5 * @brief Header file of FLASH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32L5xx_HAL_FLASH_H 20 #define STM32L5xx_HAL_FLASH_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32l5xx_hal_def.h" 28 29 /** @addtogroup STM32L5xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup FLASH 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 /** @defgroup FLASH_Exported_Types FLASH Exported Types 39 * @{ 40 */ 41 42 /** 43 * @brief FLASH Erase structure definition 44 */ 45 typedef struct 46 { 47 uint32_t TypeErase; /*!< Mass erase or page erase. 48 This parameter can be a value of @ref FLASH_Type_Erase */ 49 uint32_t Banks; /*!< Select bank to erase. 50 This parameter must be a value of @ref FLASH_Banks 51 (FLASH_BANK_BOTH should be used only for mass erase) */ 52 uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled 53 This parameter must be a value between 0 and (max number of pages in the bank - 1) 54 (eg : 127 for 512kB dual bank) */ 55 uint32_t NbPages; /*!< Number of pages to be erased. 56 This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/ 57 } FLASH_EraseInitTypeDef; 58 59 /** 60 * @brief FLASH Option Bytes Program structure definition 61 */ 62 typedef struct 63 { 64 uint32_t OptionType; /*!< Option byte to be configured. 65 This parameter can be a combination of the values of @ref FLASH_OB_Type */ 66 uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). 67 Only one WRP area could be programmed at the same time. 68 This parameter can be value of @ref FLASH_OB_WRP_Area */ 69 uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). 70 This parameter must be a value between 0 and (max number of pages in the bank - 1) 71 (eg : 127 for 512kB dual bank) */ 72 uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). 73 This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */ 74 uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP). 75 This parameter can be a value of @ref FLASH_OB_Read_Protection */ 76 uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). 77 This parameter can be a combination of @ref FLASH_OB_USER_Type */ 78 uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). 79 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, 80 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, 81 @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, 82 @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, 83 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_SWAP_BANK, 84 @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_DBANK, 85 @ref FLASH_OB_USER_SRAM2_PAR, @ref FLASH_OB_USER_SRAM2_RST, 86 @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0, 87 @ref FLASH_OB_USER_PA15_PUPEN and @ref FLASH_OB_USER_TZEN */ 88 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 89 uint32_t WMSecConfig; /*!< Configuration of the Watermark-based Secure Area (used for OPTIONBYTE_WMSEC). 90 This parameter must be a value of @ref FLASH_OB_WMSEC */ 91 uint32_t WMSecStartPage; /*!< Start page of secure area (used for OPTIONBYTE_WMSEC). 92 This parameter must be a value between 0 and (max number of pages in the bank - 1) */ 93 uint32_t WMSecEndPage; /*!< End page of secure area (used for OPTIONBYTE_WMSEC). 94 This parameter must be a value between WMSecStartPage and (max number of pages in the bank - 1) */ 95 uint32_t WMHDPEndPage; /*!< End page of the secure hide protection (used for OPTIONBYTE_WMSEC). 96 This parameter must be a value between WMSecStartPage and WMPCROPStartPage 97 (if PCROP area activated) or WMSecEndPage */ 98 uint32_t BootLock; /*!< Configuration of the boot lock (used for OPTIONBYTE_BOOT_LOCK). 99 This parameter must be a value of @ref FLASH_OB_BOOT_LOCK */ 100 #endif 101 uint32_t BootAddrConfig; /*!< Configuration of the Boot address (used for OPTIONBYTE_BOOTADDR). 102 This parameter must be a value of @ref FLASH_OB_BOOTADDR */ 103 uint32_t BootAddr; /*!< Boot address (used for OPTIONBYTE_BOOTADDR). 104 This parameter must be a value between 0x0 and 0xFFFFFF00 */ 105 } FLASH_OBProgramInitTypeDef; 106 107 /** 108 * @brief FLASH handle Structure definition 109 */ 110 typedef struct 111 { 112 HAL_LockTypeDef Lock; /*!< FLASH locking object */ 113 uint32_t ErrorCode; /*!< FLASH error code */ 114 uint32_t ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ 115 uint32_t Address; /*!< Internal variable to save address selected for program in IT context */ 116 uint32_t Bank; /*!< Internal variable to save current bank selected during erase in IT context */ 117 uint32_t Page; /*!< Internal variable to define the current page which is being erased in IT context */ 118 uint32_t NbPagesToErase; /*!< Internal variable to save the remaining pages to erase in IT context */ 119 }FLASH_ProcessTypeDef; 120 121 /** 122 * @} 123 */ 124 125 /* Exported constants --------------------------------------------------------*/ 126 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 127 * @{ 128 */ 129 130 /** @defgroup FLASH_Flags FLASH Flags Definition 131 * @{ 132 */ 133 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 134 #define FLASH_FLAG_EOP FLASH_SECSR_SECEOP /*!< FLASH End of operation flag */ 135 #define FLASH_FLAG_OPERR FLASH_SECSR_SECOPERR /*!< FLASH Operation error flag */ 136 #define FLASH_FLAG_PROGERR FLASH_SECSR_SECPROGERR /*!< FLASH Programming error flag */ 137 #define FLASH_FLAG_WRPERR FLASH_SECSR_SECWRPERR /*!< FLASH Write protection error flag */ 138 #define FLASH_FLAG_PGAERR FLASH_SECSR_SECPGAERR /*!< FLASH Programming alignment error flag */ 139 #define FLASH_FLAG_SIZERR FLASH_SECSR_SECSIZERR /*!< FLASH Size error flag */ 140 #define FLASH_FLAG_PGSERR FLASH_SECSR_SECPGSERR /*!< FLASH Programming sequence error flag */ 141 #define FLASH_FLAG_OPTWERR FLASH_NSSR_OPTWERR /*!< FLASH Option modification error flag */ 142 #define FLASH_FLAG_BSY FLASH_SECSR_SECBSY /*!< FLASH Busy flag */ 143 #define FLASH_FLAG_ECCC (FLASH_ECCR_ECCC | FLASH_ECCR_ECCC2) /*!< FLASH ECC correction */ 144 #define FLASH_FLAG_ECCD (FLASH_ECCR_ECCD | FLASH_ECCR_ECCD2) /*!< FLASH ECC detection */ 145 146 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 147 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR) /*!< Flash all flags from Status Register */ 148 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCD | FLASH_FLAG_ECCC) /*!< Flash all flags from ECC Register */ 149 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_OPTWERR | FLASH_FLAG_ECCR_ERRORS) /*!< Flash all flags */ 150 #else 151 #define FLASH_FLAG_EOP FLASH_NSSR_NSEOP /*!< FLASH End of operation flag */ 152 #define FLASH_FLAG_OPERR FLASH_NSSR_NSOPERR /*!< FLASH Operation error flag */ 153 #define FLASH_FLAG_PROGERR FLASH_NSSR_NSPROGERR /*!< FLASH Programming error flag */ 154 #define FLASH_FLAG_WRPERR FLASH_NSSR_NSWRPERR /*!< FLASH Write protection error flag */ 155 #define FLASH_FLAG_PGAERR FLASH_NSSR_NSPGAERR /*!< FLASH Programming alignment error flag */ 156 #define FLASH_FLAG_SIZERR FLASH_NSSR_NSSIZERR /*!< FLASH Size error flag */ 157 #define FLASH_FLAG_PGSERR FLASH_NSSR_NSPGSERR /*!< FLASH Programming sequence error flag */ 158 #define FLASH_FLAG_OPTWERR FLASH_NSSR_OPTWERR /*!< FLASH Option modification error flag */ 159 #define FLASH_FLAG_BSY FLASH_NSSR_NSBSY /*!< FLASH Busy flag */ 160 #define FLASH_FLAG_ECCC (FLASH_ECCR_ECCC | FLASH_ECCR_ECCC2) /*!< FLASH ECC correction */ 161 #define FLASH_FLAG_ECCD (FLASH_ECCR_ECCD | FLASH_ECCR_ECCD2) /*!< FLASH ECC detection */ 162 163 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 164 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 165 FLASH_FLAG_OPTWERR) /*!< Flash all flags from Status Register */ 166 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCD | FLASH_FLAG_ECCC) /*!< Flash all flags from ECC Register */ 167 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS) /*!< Flash all flags */ 168 #endif 169 /** 170 * @} 171 */ 172 173 /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition 174 * @brief FLASH Interrupt definition 175 * @{ 176 */ 177 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 178 #define FLASH_IT_EOP FLASH_SECCR_SECEOPIE /*!< End of FLASH Operation Interrupt source */ 179 #define FLASH_IT_OPERR FLASH_SECCR_SECERRIE /*!< Error Interrupt source */ 180 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */ 181 #else 182 #define FLASH_IT_EOP FLASH_NSCR_NSEOPIE /*!< End of FLASH Operation Interrupt source */ 183 #define FLASH_IT_OPERR FLASH_NSCR_NSERRIE /*!< Error Interrupt source */ 184 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */ 185 #endif 186 /** 187 * @} 188 */ 189 190 /** @defgroup FLASH_Error FLASH Error 191 * @{ 192 */ 193 #define HAL_FLASH_ERROR_NONE 0x00000000U /*!< Flash no error */ 194 #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR /*!< Flash operation error */ 195 #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR /*!< Flash programming error */ 196 #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Flash write protection error */ 197 #define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR /*!< Flash programming alignment error */ 198 #define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR /*!< Flash size error */ 199 #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Flash programming sequence error */ 200 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 201 #else 202 #define HAL_FLASH_ERROR_OPTW FLASH_FLAG_OPTWERR /*!< Flash option modification error */ 203 #endif 204 #define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC /*!< Flash ECC correction error */ 205 #define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD /*!< Flash ECC detection error */ 206 /** 207 * @} 208 */ 209 210 /** @defgroup FLASH_Type_Erase FLASH Erase Type 211 * @{ 212 */ 213 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 214 #define FLASH_TYPEERASE_PAGES FLASH_SECCR_SECPER /*!<Secure pages erase only*/ 215 #define FLASH_TYPEERASE_PAGES_NS (FLASH_NSCR_NSPER | FLASH_NON_SECURE_MASK) /*!<Non-secure pages erase only*/ 216 #define FLASH_TYPEERASE_MASSERASE (FLASH_SECCR_SECMER1 | FLASH_SECCR_SECMER2) /*!<Secure flash mass erase activation*/ 217 #define FLASH_TYPEERASE_MASSERASE_NS (FLASH_NSCR_NSMER1 | FLASH_NSCR_NSMER2 | FLASH_NON_SECURE_MASK) /*!<Non-secure flash mass erase activation*/ 218 #else 219 #define FLASH_TYPEERASE_PAGES FLASH_NSCR_NSPER /*!<Pages erase only*/ 220 #define FLASH_TYPEERASE_MASSERASE (FLASH_NSCR_NSMER1 | FLASH_NSCR_NSMER2) /*!<Flash mass erase activation*/ 221 #endif 222 /** 223 * @} 224 */ 225 226 /** @defgroup FLASH_Banks FLASH Banks 227 * @{ 228 */ 229 #define FLASH_BANK_1 0x00000001U /*!< Bank 1 */ 230 #define FLASH_BANK_2 0x00000002U /*!< Bank 2 */ 231 #define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ 232 /** 233 * @} 234 */ 235 236 /** @defgroup FLASH_Type_Program FLASH Program Type 237 * @{ 238 */ 239 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 240 #define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_SECCR_SECPG /*!<Program a double-word (64-bit) at a specified secure address.*/ 241 #define FLASH_TYPEPROGRAM_DOUBLEWORD_NS (FLASH_NSCR_NSPG | FLASH_NON_SECURE_MASK) /*!<Program a double-word (64-bit) at a specified non-secure address.*/ 242 #else 243 #define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_NSCR_NSPG /*!<Program a double-word (64-bit) at a specified address.*/ 244 #endif 245 /** 246 * @} 247 */ 248 249 /** @defgroup FLASH_OB_Type FLASH Option Bytes Type 250 * @{ 251 */ 252 #define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */ 253 #define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */ 254 #define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */ 255 #define OPTIONBYTE_BOOTADDR 0x00000008U /*!< Boot address option byte configuration */ 256 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 257 #define OPTIONBYTE_WMSEC 0x00000010U /*!< Watermark-based secure area option byte configuration */ 258 #define OPTIONBYTE_BOOT_LOCK 0x00000020U /*!< Boot lock option byte configuration */ 259 #endif 260 /** 261 * @} 262 */ 263 264 /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area 265 * @{ 266 */ 267 #define OB_WRPAREA_BANK1_AREAA 0x00000001U /*!< Flash Bank 1 Area A */ 268 #define OB_WRPAREA_BANK1_AREAB 0x00000002U /*!< Flash Bank 1 Area B */ 269 #define OB_WRPAREA_BANK2_AREAA 0x00000004U /*!< Flash Bank 2 Area A */ 270 #define OB_WRPAREA_BANK2_AREAB 0x00000008U /*!< Flash Bank 2 Area B */ 271 /** 272 * @} 273 */ 274 275 /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection 276 * @{ 277 */ 278 #define OB_RDP_LEVEL_0 ((uint32_t)0xAA) /*!< RDP level 0 code */ 279 #define OB_RDP_LEVEL_0_5 ((uint32_t)0x55) /*!< RDP level 0.5 code */ 280 #define OB_RDP_LEVEL_1 ((uint32_t)0xBB) /*!< RDP level 1 code */ 281 #define OB_RDP_LEVEL_2 ((uint32_t)0xCC) /*!< RDP level 2 code. 282 Warning: When enabling read protection level 2 283 it's no more possible to go back to level 1 or 0. */ 284 /** 285 * @} 286 */ 287 288 /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type 289 * @{ 290 */ 291 #define OB_USER_BOR_LEV 0x00000001U /*!< BOR reset Level */ 292 #define OB_USER_nRST_STOP 0x00000002U /*!< Reset generated when entering the stop mode */ 293 #define OB_USER_nRST_STDBY 0x00000004U /*!< Reset generated when entering the standby mode */ 294 #define OB_USER_nRST_SHDW 0x00000008U /*!< Reset generated when entering the shutdown mode */ 295 #define OB_USER_IWDG_SW 0x00000010U /*!< Independent watchdog selection */ 296 #define OB_USER_IWDG_STOP 0x00000020U /*!< Independent watchdog counter freeze in stop mode */ 297 #define OB_USER_IWDG_STDBY 0x00000040U /*!< Independent watchdog counter freeze in standby mode */ 298 #define OB_USER_WWDG_SW 0x00000080U /*!< Window watchdog selection */ 299 #define OB_USER_SWAP_BANK 0x00000100U /*!< Swap banks */ 300 #define OB_USER_DUALBANK 0x00000200U /*!< Dual-Bank on 256kB Flash memory devices */ 301 #define OB_USER_DBANK 0x00000400U /*!< Single bank with 128-bits data or two banks with 64-bits data */ 302 #define OB_USER_SRAM2_PE 0x00000800U /*!< SRAM2 parity error enable */ 303 #define OB_USER_SRAM2_RST 0x00001000U /*!< SRAM2 Erase when system reset */ 304 #define OB_USER_nSWBOOT0 0x00002000U /*!< Software BOOT0 */ 305 #define OB_USER_nBOOT0 0x00004000U /*!< nBOOT0 option bit */ 306 #define OB_USER_PA15_PUPEN 0x00008000U /*!< PA15 pull-up enable option bit */ 307 #define OB_USER_TZEN 0x00010000U /*!< Global TrustZone enable */ 308 /** 309 * @} 310 */ 311 312 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level 313 * @{ 314 */ 315 #define OB_BOR_LEVEL_0 FLASH_OPTR_BOR_LEV_0 /*!< Reset level threshold is around 1.7V */ 316 #define OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_1 /*!< Reset level threshold is around 2.0V */ 317 #define OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_2 /*!< Reset level threshold is around 2.2V */ 318 #define OB_BOR_LEVEL_3 FLASH_OPTR_BOR_LEV_3 /*!< Reset level threshold is around 2.5V */ 319 #define OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_4 /*!< Reset level threshold is around 2.8V */ 320 /** 321 * @} 322 */ 323 324 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop 325 * @{ 326 */ 327 #define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */ 328 #define OB_STOP_NORST FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */ 329 /** 330 * @} 331 */ 332 333 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby 334 * @{ 335 */ 336 #define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */ 337 #define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */ 338 /** 339 * @} 340 */ 341 342 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown 343 * @{ 344 */ 345 #define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */ 346 #define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode */ 347 /** 348 * @} 349 */ 350 351 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type 352 * @{ 353 */ 354 #define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */ 355 #define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */ 356 /** 357 * @} 358 */ 359 360 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop 361 * @{ 362 */ 363 #define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */ 364 #define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop mode */ 365 /** 366 * @} 367 */ 368 369 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby 370 * @{ 371 */ 372 #define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */ 373 #define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in Standby mode */ 374 /** 375 * @} 376 */ 377 378 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type 379 * @{ 380 */ 381 #define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ 382 #define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */ 383 /** 384 * @} 385 */ 386 387 /** @defgroup FLASH_OB_USER_SWAP_BANK FLASH Option Bytes User Swap banks 388 * @{ 389 */ 390 #define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank 1 is located at AHB address 0x0, Bank 2 is located at 0x40000 */ 391 #define OB_SWAP_BANK_ENABLE FLASH_OPTR_SWAP_BANK /*!< Bank 1 is located at AHB address 0x40000, Bank 2 is located at 0x0 */ 392 /** 393 * @} 394 */ 395 396 /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type 397 * @{ 398 */ 399 #define OB_DUALBANK_SINGLE 0x00000000U /*!< 256 kB Single-bank Flash */ 400 #define OB_DUALBANK_DUAL FLASH_OPTR_DB256K /*!< 256 kB Dual-bank Flash */ 401 /** 402 * @} 403 */ 404 405 /** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type 406 * @{ 407 */ 408 #define OB_DBANK_128_BITS 0x00000000U /*!< Single-bank with 128-bits data */ 409 #define OB_DBANK_64_BITS FLASH_OPTR_DBANK /*!< Dual-bank with 64-bits data */ 410 /** 411 * @} 412 */ 413 414 /** @defgroup FLASH_OB_USER_SRAM2_PAR FLASH Option Bytes User SRAM2 Parity error enable 415 * @{ 416 */ 417 #define OB_SRAM2_PARITY_ENABLE 0x00000000U /*!< SRAM2 parity error generation enable */ 418 #define OB_SRAM2_PARITY_DISABLE FLASH_OPTR_SRAM2_PE /*!< SRAM2 parity check disable */ 419 /** 420 * @} 421 */ 422 423 /** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type 424 * @{ 425 */ 426 #define OB_SRAM2_RST_ERASE 0x00000000U /*!< SRAM2 erased when a system reset occurs */ 427 #define OB_SRAM2_RST_NOT_ERASE FLASH_OPTR_SRAM2_RST /*!< SRAM2 is not erased when a system reset occurs */ 428 /** 429 * @} 430 */ 431 432 /** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 433 * @{ 434 */ 435 #define OB_BOOT0_FROM_OB 0x00000000U /*!< BOOT0 taken from the option bit nBOOT0 */ 436 #define OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0 /*!< BOOT0 taken from BOOT0 pin */ 437 /** 438 * @} 439 */ 440 441 /** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit 442 * @{ 443 */ 444 #define OB_nBOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */ 445 #define OB_nBOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */ 446 /** 447 * @} 448 */ 449 450 /** @defgroup FLASH_OB_USER_PA15_PUPEN FLASH Option Bytes User PA15 pull-up enable option bit 451 * @{ 452 */ 453 #define OB_PA15_PUP_DISABLE 0x00000000U /*!< USB power delivery dead-battery enabled/ TDI pull-up deactivated */ 454 #define OB_PA15_PUP_ENABLE FLASH_OPTR_PA15_PUPEN /*!< USB power delivery dead-battery disabled/ TDI pull-up activated */ 455 /** 456 * @} 457 */ 458 459 /** @defgroup FLASH_OB_USER_TZEN FLASH Option Bytes User Global TrustZone 460 * @{ 461 */ 462 #define OB_TZEN_DISABLE 0x00000000U /*!< no TrustZone */ 463 #define OB_TZEN_ENABLE FLASH_OPTR_TZEN /*!< TrustZone */ 464 /** 465 * @} 466 */ 467 468 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 469 /** @defgroup FLASH_OB_BOOT_LOCK FLASH Option Bytes Boot Lock 470 * @{ 471 */ 472 #define OB_BOOT_LOCK_DISABLE 0x00000000U /*!< Boot lock disable */ 473 #define OB_BOOT_LOCK_ENABLE FLASH_SECBOOTADD0R_BOOT_LOCK /*!< Boot lock enable */ 474 /** 475 * @} 476 */ 477 478 /** @defgroup FLASH_OB_WMSEC FLASH Option Bytes Watermarked-based security configuration 479 * @{ 480 */ 481 #define OB_WMSEC_AREA1 FLASH_BANK_1 /*!< Watermarked-based security area for bank 1 */ 482 #define OB_WMSEC_AREA2 FLASH_BANK_2 /*!< Watermarked-based security area for bank 2 */ 483 484 #define OB_WMSEC_SECURE_AREA_CONFIG 0x00000010U /*!< Configure Watermarked-based security area */ 485 #define OB_WMSEC_HDP_AREA_CONFIG 0x00000020U /*!< Configure Watermarked-based secure hide area */ 486 #define OB_WMSEC_HDP_AREA_ENABLE 0x00000080U /*!< Enable Watermarked-based secure hide area */ 487 #define OB_WMSEC_HDP_AREA_DISABLE 0x00000100U /*!< Disable Watermarked-based secure hide area */ 488 /** 489 * @} 490 */ 491 #endif 492 493 /** @defgroup FLASH_OB_BOOTADDR FLASH Option Bytes Boot address 494 * @{ 495 */ 496 #define OB_BOOTADDR_NS0 0x00000001U /*!< Non-secure boot address 0 */ 497 #define OB_BOOTADDR_NS1 0x00000002U /*!< Non-secure boot address 1 */ 498 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 499 #define OB_BOOTADDR_SEC0 0x00000004U /*!< Secure boot address 0 */ 500 #endif 501 /** 502 * @} 503 */ 504 505 /** @defgroup FLASH_Latency FLASH Latency 506 * @{ 507 */ 508 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ 509 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ 510 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ 511 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ 512 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ 513 #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait state */ 514 #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait state */ 515 #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */ 516 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */ 517 #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait states */ 518 #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait state */ 519 #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait state */ 520 #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait states */ 521 #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait states */ 522 #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait states */ 523 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait states */ 524 /** 525 * @} 526 */ 527 528 /** @defgroup FLASH_Keys FLASH Keys 529 * @{ 530 */ 531 #define FLASH_KEY1 0x45670123U /*!< Flash key1 */ 532 #define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 533 to unlock the FLASH registers access */ 534 535 #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */ 536 #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 537 to unlock the RUN_PD bit in FLASH_ACR */ 538 539 #define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ 540 #define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 541 to allow option bytes operations */ 542 543 #define FLASH_LVEKEY1 0xF4F5F6F7U /*!< Flash LVE key1 */ 544 #define FLASH_LVEKEY2 0x0A1B2C3DU /*!< Flash LVE key2: used with FLASH_LVEKEY1 545 to unblock the LVEN bit in FLASH_ACR */ 546 /** 547 * @} 548 */ 549 550 /** 551 * @} 552 */ 553 554 /* Exported macros -----------------------------------------------------------*/ 555 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros 556 * @brief macros to control FLASH features 557 * @{ 558 */ 559 560 /** 561 * @brief Set the FLASH Latency. 562 * @param __LATENCY__ FLASH Latency. 563 * This parameter can be one of the following values : 564 * @arg FLASH_LATENCY_0: FLASH Zero wait state 565 * @arg FLASH_LATENCY_1: FLASH One wait state 566 * @arg FLASH_LATENCY_2: FLASH Two wait states 567 * @arg FLASH_LATENCY_3: FLASH Three wait states 568 * @arg FLASH_LATENCY_4: FLASH Four wait states 569 * @arg FLASH_LATENCY_5: FLASH Five wait states 570 * @arg FLASH_LATENCY_6: FLASH Six wait states 571 * @arg FLASH_LATENCY_7: FLASH Seven wait states 572 * @arg FLASH_LATENCY_8: FLASH Eight wait states 573 * @arg FLASH_LATENCY_9: FLASH Nine wait states 574 * @arg FLASH_LATENCY_10: FLASH Ten wait states 575 * @arg FLASH_LATENCY_11: FLASH Eleven wait states 576 * @arg FLASH_LATENCY_12: FLASH Twelve wait states 577 * @arg FLASH_LATENCY_13: FLASH Thirteen wait states 578 * @arg FLASH_LATENCY_14: FLASH Fourteen wait states 579 * @arg FLASH_LATENCY_15: FLASH Fifteen wait states 580 * @retval None 581 */ 582 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))) 583 584 /** 585 * @brief Get the FLASH Latency. 586 * @retval FLASH Latency 587 * This parameter can be one of the following values : 588 * @arg FLASH_LATENCY_0: FLASH Zero wait state 589 * @arg FLASH_LATENCY_1: FLASH One wait state 590 * @arg FLASH_LATENCY_2: FLASH Two wait states 591 * @arg FLASH_LATENCY_3: FLASH Three wait states 592 * @arg FLASH_LATENCY_4: FLASH Four wait states 593 * @arg FLASH_LATENCY_5: FLASH Five wait states 594 * @arg FLASH_LATENCY_6: FLASH Six wait states 595 * @arg FLASH_LATENCY_7: FLASH Seven wait states 596 * @arg FLASH_LATENCY_8: FLASH Eight wait states 597 * @arg FLASH_LATENCY_9: FLASH Nine wait states 598 * @arg FLASH_LATENCY_10: FLASH Ten wait states 599 * @arg FLASH_LATENCY_11: FLASH Eleven wait states 600 * @arg FLASH_LATENCY_12: FLASH Twelve wait states 601 * @arg FLASH_LATENCY_13: FLASH Thirteen wait states 602 * @arg FLASH_LATENCY_14: FLASH Fourteen wait states 603 * @arg FLASH_LATENCY_15: FLASH Fifteen wait states 604 */ 605 #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) 606 607 /** 608 * @brief Enable the FLASH power down during Low-power run mode. 609 * @retval None 610 * @note Writing this bit to 0, automatically the keys are 611 * lost and a new unlock sequence is necessary to re-write it to 1. 612 */ 613 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ 614 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ 615 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ 616 } while (0) 617 618 /** 619 * @brief Disable the FLASH power down during Low-power run mode. 620 * @retval None 621 * @note Writing this bit to 1, automatically the keys are 622 * loss and a new unlock sequence is necessary to re-write it to 0. 623 */ 624 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ 625 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ 626 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ 627 } while (0) 628 629 /** 630 * @brief Enable the FLASH power down during Low-Power sleep mode 631 * @retval None 632 */ 633 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 634 635 /** 636 * @brief Disable the FLASH power down during Low-Power sleep mode 637 * @retval None 638 */ 639 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 640 641 /** 642 * @} 643 */ 644 645 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros 646 * @brief macros to handle FLASH interrupts 647 * @{ 648 */ 649 650 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 651 /** 652 * @brief Enable secure FLASH interrupts from the secure world. 653 * @param __INTERRUPT__ FLASH interrupt. 654 * This parameter can be any combination of the following values: 655 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 656 * @arg FLASH_IT_OPERR: Error Interrupt 657 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 658 * @retval None 659 */ 660 /* Enable secure FLASH interrupts from the secure world */ 661 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 662 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 663 } while(0) 664 /** 665 * @brief Enable non-secure FLASH interrupts from the secure world. 666 * @param __INTERRUPT__ FLASH interrupt. 667 * This parameter can be any combination of the following values: 668 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 669 * @arg FLASH_IT_OPERR: Error Interrupt 670 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 671 * @retval None 672 */ 673 #define __HAL_FLASH_ENABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 674 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 675 } while(0) 676 #else 677 /** 678 * @brief Enable non-secure FLASH interrupts from the non-secure world. 679 * @param __INTERRUPT__ FLASH interrupt. 680 * This parameter can be any combination of the following values: 681 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 682 * @arg FLASH_IT_OPERR: Error Interrupt 683 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 684 * @retval None 685 */ 686 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 687 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 688 } while(0) 689 #endif /* __ARM_FEATURE_CMSE */ 690 691 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 692 /** 693 * @brief Disable secure FLASH interrupts from the secure world. 694 * @param __INTERRUPT__ FLASH interrupt. 695 * This parameter can be any combination of the following values: 696 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 697 * @arg FLASH_IT_OPERR: Error Interrupt 698 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 699 * @retval None 700 */ 701 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 702 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 703 } while(0) 704 /** 705 * @brief Disable non-secure FLASH interrupts from the secure world. 706 * @param __INTERRUPT__ FLASH interrupt. 707 * This parameter can be any combination of the following values: 708 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 709 * @arg FLASH_IT_OPERR: Error Interrupt 710 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 711 * @retval None 712 */ 713 #define __HAL_FLASH_DISABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 714 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 715 } while(0) 716 #else 717 /** 718 * @brief Disable non-secure FLASH interrupts from the non-secure world. 719 * @param __INTERRUPT__ FLASH interrupt. 720 * This parameter can be any combination of the following values: 721 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 722 * @arg FLASH_IT_OPERR: Error Interrupt 723 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 724 * @retval None 725 */ 726 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 727 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 728 } while(0) 729 #endif /* __ARM_FEATURE_CMSE */ 730 731 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 732 /** 733 * @brief Check whether the specified secure FLASH flags from the secure world is set or not. 734 * @param __FLAG__ specifies the FLASH flag to check. 735 * This parameter can be one of the following values: 736 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 737 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 738 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 739 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 740 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 741 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 742 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 743 * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag 744 * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 745 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 746 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 747 * @retval The new state of FLASH_FLAG (SET or RESET). 748 */ 749 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \ 750 (READ_BIT(FLASH->ECCR, (__FLAG__)) != 0U) : \ 751 ((((__FLAG__) & (FLASH_FLAG_OPTWERR)) != 0U) ? \ 752 (READ_BIT(FLASH->NSSR, (__FLAG__)) != 0U) : \ 753 (READ_BIT(FLASH->SECSR, (__FLAG__)) != 0U))) 754 /** 755 * @brief Check whether the specified non-secure FLASH flags from the secure world is set or not. 756 * @param __FLAG__ specifies the FLASH flag to check. 757 * This parameter can be one of the following values: 758 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 759 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 760 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 761 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 762 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 763 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 764 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 765 * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag 766 * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 767 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 768 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 769 * @retval The new state of FLASH_FLAG (SET or RESET). 770 */ 771 #define __HAL_FLASH_GET_FLAG_NS(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \ 772 (READ_BIT(FLASH->ECCR, (__FLAG__)) != 0U) : \ 773 (READ_BIT(FLASH->NSSR, (__FLAG__)) != 0U)) 774 #else 775 /** 776 * @brief Check whether the specified non-secure FLASH flags from the non-secure world is set or not. 777 * @param __FLAG__ specifies the FLASH flag to check. 778 * This parameter can be one of the following values: 779 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 780 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 781 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 782 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 783 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 784 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 785 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 786 * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag 787 * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 788 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 789 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 790 * @retval The new state of FLASH_FLAG (SET or RESET). 791 */ 792 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \ 793 (READ_BIT(FLASH->ECCR, (__FLAG__)) != 0U) : \ 794 (READ_BIT(FLASH->NSSR, (__FLAG__)) != 0U)) 795 #endif /* __ARM_FEATURE_CMSE */ 796 797 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 798 /** 799 * @brief Clear secure FLASH flags from the secure world. 800 * @param __FLAG__ specifies the FLASH flags to clear. 801 * This parameter can be any combination of the following values: 802 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 803 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 804 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 805 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 806 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 807 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 808 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 809 * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag (Only in non-secure) 810 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 811 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 812 * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags 813 * @retval None 814 */ 815 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ 816 if(((__FLAG__) & FLASH_FLAG_OPTWERR) != 0U) { SET_BIT(FLASH->NSSR, ((__FLAG__) & (FLASH_FLAG_OPTWERR))); }\ 817 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | FLASH_FLAG_OPTWERR)) != 0U) { WRITE_REG(FLASH->SECSR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | FLASH_FLAG_OPTWERR))); } \ 818 } while(0) 819 /** 820 * @brief Clear non-secure FLASH flags from the secure world. 821 * @param __FLAG__ specifies the FLASH flags to clear. 822 * This parameter can be any combination of the following values: 823 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 824 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 825 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 826 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 827 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 828 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 829 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 830 * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag (Only in non-secure) 831 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 832 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 833 * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags 834 * @retval None 835 */ 836 #define __HAL_FLASH_CLEAR_FLAG_NS(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ 837 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->NSSR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ 838 } while(0) 839 #else 840 /** 841 * @brief Clear non-secure FLASH flags from the non-secure world. 842 * @param __FLAG__ specifies the FLASH flags to clear. 843 * This parameter can be any combination of the following values: 844 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 845 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 846 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 847 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 848 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 849 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 850 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 851 * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag (Only in non-secure) 852 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 853 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 854 * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags 855 * @retval None 856 */ 857 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ 858 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->NSSR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ 859 } while(0) 860 #endif /* __ARM_FEATURE_CMSE */ 861 /** 862 * @} 863 */ 864 865 /* Include FLASH HAL Extended module */ 866 #include "stm32l5xx_hal_flash_ex.h" 867 #include "stm32l5xx_hal_flash_ramfunc.h" 868 869 /* Exported functions --------------------------------------------------------*/ 870 /** @addtogroup FLASH_Exported_Functions 871 * @{ 872 */ 873 874 /* Program operation functions ***********************************************/ 875 /** @addtogroup FLASH_Exported_Functions_Group1 876 * @{ 877 */ 878 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 879 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 880 /* FLASH IRQ handler method */ 881 void HAL_FLASH_IRQHandler(void); 882 /* Callbacks in non blocking modes */ 883 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 884 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 885 /** 886 * @} 887 */ 888 889 /* Peripheral Control functions **********************************************/ 890 /** @addtogroup FLASH_Exported_Functions_Group2 891 * @{ 892 */ 893 HAL_StatusTypeDef HAL_FLASH_Unlock(void); 894 HAL_StatusTypeDef HAL_FLASH_Lock(void); 895 /* Option bytes control */ 896 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 897 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 898 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); 899 /** 900 * @} 901 */ 902 903 /* Peripheral State functions ************************************************/ 904 /** @addtogroup FLASH_Exported_Functions_Group3 905 * @{ 906 */ 907 uint32_t HAL_FLASH_GetError(void); 908 /** 909 * @} 910 */ 911 912 /** 913 * @} 914 */ 915 916 /* Private variables ---------------------------------------------------------*/ 917 /** @addtogroup FLASH_Private_Variables FLASH Private Variables 918 * @{ 919 */ 920 extern FLASH_ProcessTypeDef pFlash; 921 /** 922 * @} 923 */ 924 925 /* Private function ----------------------------------------------------------*/ 926 /** @addtogroup FLASH_Private_Functions FLASH Private Functions 927 * @{ 928 */ 929 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 930 /** 931 * @} 932 */ 933 934 /* Private constants ---------------------------------------------------------*/ 935 /** @defgroup FLASH_Private_Constants FLASH Private Constants 936 * @{ 937 */ 938 #define FLASH_BANK_SIZE (FLASH_SIZE >> 1) 939 940 #define FLASH_PAGE_SIZE 0x00000800U 941 #define FLASH_PAGE_SIZE_128_BITS 0x00001000U 942 943 #define FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE) 944 #define FLASH_PAGE_NB_PER_BANK (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) 945 #define FLASH_PAGE_NB_128_BITS (FLASH_SIZE / FLASH_PAGE_SIZE_128_BITS) 946 947 #define FLASH_TIMEOUT_VALUE 1000u /* 1 s */ 948 949 #define FLASH_NON_SECURE_MASK 0x80000000U 950 /** 951 * @} 952 */ 953 954 /* Private macros ------------------------------------------------------------*/ 955 /** @defgroup FLASH_Private_Macros FLASH Private Macros 956 * @{ 957 */ 958 959 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 960 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ 961 ((VALUE) == FLASH_TYPEERASE_PAGES_NS) || \ 962 ((VALUE) == FLASH_TYPEERASE_MASSERASE) || \ 963 ((VALUE) == FLASH_TYPEERASE_MASSERASE_NS)) 964 #else 965 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ 966 ((VALUE) == FLASH_TYPEERASE_MASSERASE)) 967 #endif 968 969 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ 970 ((BANK) == FLASH_BANK_2) || \ 971 ((BANK) == FLASH_BANK_BOTH)) 972 973 #define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ 974 ((BANK) == FLASH_BANK_2)) 975 976 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 977 #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ 978 ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD_NS)) 979 #else 980 #define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) 981 #endif 982 983 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 984 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) || \ 985 (((ADDRESS) >= FLASH_BASE_NS) && ((ADDRESS) < (FLASH_BASE_NS+FLASH_SIZE)))) 986 #else 987 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) 988 #endif 989 990 #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= OTP_BASE) && ((ADDRESS) < (OTP_BASE+OTP_SIZE))) 991 992 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS))) 993 994 #define IS_FLASH_PAGE(PAGE) ((PAGE) < 128U) 995 996 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 997 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ 998 OPTIONBYTE_WMSEC | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_BOOTADDR))) 999 #else 1000 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ 1001 OPTIONBYTE_BOOTADDR))) 1002 #endif 1003 1004 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ 1005 ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) 1006 1007 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ 1008 ((LEVEL) == OB_RDP_LEVEL_0_5) ||\ 1009 ((LEVEL) == OB_RDP_LEVEL_1) ||\ 1010 ((LEVEL) == OB_RDP_LEVEL_2)) 1011 1012 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFFFU) && ((TYPE) != 0U)) 1013 1014 #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ 1015 ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ 1016 ((LEVEL) == OB_BOR_LEVEL_4)) 1017 1018 #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) 1019 1020 #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) 1021 1022 #define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) 1023 1024 #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) 1025 1026 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) 1027 1028 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) 1029 1030 #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) 1031 1032 #define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) 1033 1034 #define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL)) 1035 1036 #define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) 1037 1038 #define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE)) 1039 1040 #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) 1041 1042 #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) 1043 1044 #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET)) 1045 1046 #define IS_OB_USER_PA15_PUPEN(VALUE) (((VALUE) == OB_PA15_PUP_DISABLE) || ((VALUE) == OB_PA15_PUP_ENABLE)) 1047 1048 #define IS_OB_USER_TZEN(VALUE) (((VALUE) == OB_TZEN_DISABLE) || ((VALUE) == OB_TZEN_ENABLE)) 1049 1050 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1051 #define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_DISABLE) || ((VALUE) == OB_BOOT_LOCK_ENABLE)) 1052 1053 #define IS_OB_WMSEC_CONFIG(CFG) ((((CFG) & 0x1B3U) != 0U) && (((CFG) & 0x3U) != 0U) && (((CFG) & 0xFFFFFE4CU) == 0U)) 1054 1055 #define IS_OB_WMSEC_AREA_EXCLUSIVE(WMSEC) (((((WMSEC) & OB_WMSEC_AREA1) != 0U) && (((WMSEC) & OB_WMSEC_AREA2) == 0U)) || \ 1056 ((((WMSEC) & OB_WMSEC_AREA2) != 0U) && (((WMSEC) & OB_WMSEC_AREA1) == 0U))) 1057 #endif 1058 1059 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1060 #define IS_OB_BOOTADDR_CONFIG(CFG) (((CFG) == OB_BOOTADDR_NS0) || ((CFG) == OB_BOOTADDR_NS1) || \ 1061 ((CFG) == OB_BOOTADDR_SEC0)) 1062 #else 1063 #define IS_OB_BOOTADDR_CONFIG(CFG) (((CFG) == OB_BOOTADDR_NS0) || ((CFG) == OB_BOOTADDR_NS1)) 1064 #endif 1065 1066 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ 1067 ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ 1068 ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ 1069 ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ 1070 ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ 1071 ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ 1072 ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ 1073 ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) 1074 1075 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1076 #define IS_FLASH_SECURE_OPERATION() ((pFlash.ProcedureOnGoing & FLASH_NON_SECURE_MASK) == 0U) 1077 #else 1078 #define IS_FLASH_SECURE_OPERATION() (0U) 1079 #endif /* __ARM_FEATURE_CMSE */ 1080 /** 1081 * @} 1082 */ 1083 1084 /** 1085 * @} 1086 */ 1087 1088 /** 1089 * @} 1090 */ 1091 1092 #ifdef __cplusplus 1093 } 1094 #endif 1095 1096 #endif /* STM32L5xx_HAL_FLASH_H */ 1097 1098
