1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L5xx_HAL_DMA_H 21 #define STM32L5xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l5xx_hal_def.h" 29 30 /** @addtogroup STM32L5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup DMA_Exported_Types DMA Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief DMA Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Request; /*!< Specifies the request selected for the specified channel. 49 This parameter can be a value of @ref DMA_request */ 50 51 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 52 from memory to memory or from peripheral to memory. 53 This parameter can be a value of @ref DMA_Data_transfer_direction */ 54 55 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 56 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 57 58 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 59 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 60 61 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 62 This parameter can be a value of @ref DMA_Peripheral_data_size */ 63 64 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 65 This parameter can be a value of @ref DMA_Memory_data_size */ 66 67 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 68 This parameter can be a value of @ref DMA_mode 69 @note The circular buffer mode cannot be used if the memory-to-memory 70 data transfer is configured on the selected Channel */ 71 72 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 73 This parameter can be a value of @ref DMA_Priority_level */ 74 } DMA_InitTypeDef; 75 76 /** 77 * @brief HAL DMA State structures definition 78 */ 79 typedef enum 80 { 81 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 82 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 83 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 84 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 85 }HAL_DMA_StateTypeDef; 86 87 /** 88 * @brief HAL DMA Error Code structure definition 89 */ 90 typedef enum 91 { 92 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 93 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 94 }HAL_DMA_LevelCompleteTypeDef; 95 96 97 /** 98 * @brief HAL DMA Callback ID structure definition 99 */ 100 typedef enum 101 { 102 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 103 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 104 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ 105 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ 106 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ 107 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ 108 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ 109 110 }HAL_DMA_CallbackIDTypeDef; 111 112 /** 113 * @brief DMA handle Structure definition 114 */ 115 typedef struct __DMA_HandleTypeDef 116 { 117 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 118 119 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 120 121 HAL_LockTypeDef Lock; /*!< DMA locking object */ 122 123 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 124 125 void *Parent; /*!< Parent object state */ 126 127 void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 128 129 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 130 131 void (* XferM1CpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ 132 133 void (* XferM1HalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ 134 135 void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 136 137 void (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ 138 139 __IO uint32_t ErrorCode; /*!< DMA Error code */ 140 141 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 142 143 uint32_t ChannelIndex; /*!< DMA Channel Index */ 144 145 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ 146 147 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 148 149 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 150 151 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 152 153 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ 154 155 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 156 157 158 }DMA_HandleTypeDef; 159 /** 160 * @} 161 */ 162 163 /* Exported constants --------------------------------------------------------*/ 164 165 /** @defgroup DMA_Exported_Constants DMA Exported Constants 166 * @{ 167 */ 168 169 /** @defgroup DMA_Error_Code DMA Error Code 170 * @{ 171 */ 172 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 173 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 174 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 175 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 176 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 177 #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ 178 #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ 179 180 /** 181 * @} 182 */ 183 184 /** @defgroup DMA_request DMA request 185 * @{ 186 */ 187 #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ 188 189 #define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ 190 #define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ 191 #define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ 192 #define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ 193 194 #define DMA_REQUEST_ADC1 5U /*!< DMAMUX1 ADC1 request */ 195 #define DMA_REQUEST_ADC2 6U /*!< DMAMUX1 ADC2 request */ 196 197 #define DMA_REQUEST_DAC1_CH1 7U /*!< DMAMUX1 DAC1 CH1 request */ 198 #define DMA_REQUEST_DAC1_CH2 8U /*!< DMAMUX1 DAC1 CH2 request */ 199 200 #define DMA_REQUEST_TIM6_UP 9U /*!< DMAMUX1 TIM6 UP request */ 201 #define DMA_REQUEST_TIM7_UP 10U /*!< DMAMUX1 TIM7 UP request */ 202 203 #define DMA_REQUEST_SPI1_RX 11U /*!< DMAMUX1 SPI1 RX request */ 204 #define DMA_REQUEST_SPI1_TX 12U /*!< DMAMUX1 SPI1 TX request */ 205 #define DMA_REQUEST_SPI2_RX 13U /*!< DMAMUX1 SPI2 RX request */ 206 #define DMA_REQUEST_SPI2_TX 14U /*!< DMAMUX1 SPI2 TX request */ 207 #define DMA_REQUEST_SPI3_RX 15U /*!< DMAMUX1 SPI3 RX request */ 208 #define DMA_REQUEST_SPI3_TX 16U /*!< DMAMUX1 SPI3 TX request */ 209 210 #define DMA_REQUEST_I2C1_RX 17U /*!< DMAMUX1 I2C1 RX request */ 211 #define DMA_REQUEST_I2C1_TX 18U /*!< DMAMUX1 I2C1 TX request */ 212 #define DMA_REQUEST_I2C2_RX 19U /*!< DMAMUX1 I2C2 RX request */ 213 #define DMA_REQUEST_I2C2_TX 20U /*!< DMAMUX1 I2C2 TX request */ 214 #define DMA_REQUEST_I2C3_RX 21U /*!< DMAMUX1 I2C3 RX request */ 215 #define DMA_REQUEST_I2C3_TX 22U /*!< DMAMUX1 I2C3 TX request */ 216 #define DMA_REQUEST_I2C4_RX 23U /*!< DMAMUX1 I2C4 RX request */ 217 #define DMA_REQUEST_I2C4_TX 24U /*!< DMAMUX1 I2C4 TX request */ 218 219 #define DMA_REQUEST_USART1_RX 25U /*!< DMAMUX1 USART1 RX request */ 220 #define DMA_REQUEST_USART1_TX 26U /*!< DMAMUX1 USART1 TX request */ 221 #define DMA_REQUEST_USART2_RX 27U /*!< DMAMUX1 USART2 RX request */ 222 #define DMA_REQUEST_USART2_TX 28U /*!< DMAMUX1 USART2 TX request */ 223 #define DMA_REQUEST_USART3_RX 29U /*!< DMAMUX1 USART3 RX request */ 224 #define DMA_REQUEST_USART3_TX 30U /*!< DMAMUX1 USART3 TX request */ 225 226 #define DMA_REQUEST_UART4_RX 31U /*!< DMAMUX1 UART4 RX request */ 227 #define DMA_REQUEST_UART4_TX 32U /*!< DMAMUX1 UART4 TX request */ 228 #define DMA_REQUEST_UART5_RX 33U /*!< DMAMUX1 UART5 RX request */ 229 #define DMA_REQUEST_UART5_TX 34U /*!< DMAMUX1 UART5 TX request */ 230 231 #define DMA_REQUEST_LPUART1_RX 35U /*!< DMAMUX1 LP_UART1_RX request */ 232 #define DMA_REQUEST_LPUART1_TX 36U /*!< DMAMUX1 LP_UART1_RX request */ 233 234 #define DMA_REQUEST_SAI1_A 37U /*!< DMAMUX1 SAI1 A request */ 235 #define DMA_REQUEST_SAI1_B 38U /*!< DMAMUX1 SAI1 B request */ 236 #define DMA_REQUEST_SAI2_A 39U /*!< DMAMUX1 SAI2 A request */ 237 #define DMA_REQUEST_SAI2_B 40U /*!< DMAMUX1 SAI2 B request */ 238 239 #define DMA_REQUEST_OCTOSPI1 41U /*!< DMAMUX1 OCTOSPI1 request */ 240 241 #define DMA_REQUEST_TIM1_CH1 42U /*!< DMAMUX1 TIM1 CH1 request */ 242 #define DMA_REQUEST_TIM1_CH2 43U /*!< DMAMUX1 TIM1 CH2 request */ 243 #define DMA_REQUEST_TIM1_CH3 44U /*!< DMAMUX1 TIM1 CH3 request */ 244 #define DMA_REQUEST_TIM1_CH4 45U /*!< DMAMUX1 TIM1 CH4 request */ 245 #define DMA_REQUEST_TIM1_UP 46U /*!< DMAMUX1 TIM1 UP request */ 246 #define DMA_REQUEST_TIM1_TRIG 47U /*!< DMAMUX1 TIM1 TRIG request */ 247 #define DMA_REQUEST_TIM1_COM 48U /*!< DMAMUX1 TIM1 COM request */ 248 249 #define DMA_REQUEST_TIM8_CH1 49U /*!< DMAMUX1 TIM8 CH1 request */ 250 #define DMA_REQUEST_TIM8_CH2 50U /*!< DMAMUX1 TIM8 CH2 request */ 251 #define DMA_REQUEST_TIM8_CH3 51U /*!< DMAMUX1 TIM8 CH3 request */ 252 #define DMA_REQUEST_TIM8_CH4 52U /*!< DMAMUX1 TIM8 CH4 request */ 253 #define DMA_REQUEST_TIM8_UP 53U /*!< DMAMUX1 TIM8 UP request */ 254 #define DMA_REQUEST_TIM8_TRIG 54U /*!< DMAMUX1 TIM8 TRIG request */ 255 #define DMA_REQUEST_TIM8_COM 55U /*!< DMAMUX1 TIM8 COM request */ 256 257 #define DMA_REQUEST_TIM2_CH1 56U /*!< DMAMUX1 TIM2 CH1 request */ 258 #define DMA_REQUEST_TIM2_CH2 57U /*!< DMAMUX1 TIM2 CH2 request */ 259 #define DMA_REQUEST_TIM2_CH3 58U /*!< DMAMUX1 TIM2 CH3 request */ 260 #define DMA_REQUEST_TIM2_CH4 59U /*!< DMAMUX1 TIM2 CH4 request */ 261 #define DMA_REQUEST_TIM2_UP 60U /*!< DMAMUX1 TIM2 UP request */ 262 263 #define DMA_REQUEST_TIM3_CH1 61U /*!< DMAMUX1 TIM3 CH1 request */ 264 #define DMA_REQUEST_TIM3_CH2 62U /*!< DMAMUX1 TIM3 CH2 request */ 265 #define DMA_REQUEST_TIM3_CH3 63U /*!< DMAMUX1 TIM3 CH3 request */ 266 #define DMA_REQUEST_TIM3_CH4 64U /*!< DMAMUX1 TIM3 CH4 request */ 267 #define DMA_REQUEST_TIM3_UP 65U /*!< DMAMUX1 TIM3 UP request */ 268 #define DMA_REQUEST_TIM3_TRIG 66U /*!< DMAMUX1 TIM3 TRIG request */ 269 270 #define DMA_REQUEST_TIM4_CH1 67U /*!< DMAMUX1 TIM4 CH1 request */ 271 #define DMA_REQUEST_TIM4_CH2 68U /*!< DMAMUX1 TIM4 CH2 request */ 272 #define DMA_REQUEST_TIM4_CH3 69U /*!< DMAMUX1 TIM4 CH3 request */ 273 #define DMA_REQUEST_TIM4_CH4 70U /*!< DMAMUX1 TIM4 CH4 request */ 274 #define DMA_REQUEST_TIM4_UP 71U /*!< DMAMUX1 TIM4 UP request */ 275 276 #define DMA_REQUEST_TIM5_CH1 72U /*!< DMAMUX1 TIM5 CH1 request */ 277 #define DMA_REQUEST_TIM5_CH2 73U /*!< DMAMUX1 TIM5 CH2 request */ 278 #define DMA_REQUEST_TIM5_CH3 74U /*!< DMAMUX1 TIM5 CH3 request */ 279 #define DMA_REQUEST_TIM5_CH4 75U /*!< DMAMUX1 TIM5 CH4 request */ 280 #define DMA_REQUEST_TIM5_UP 76U /*!< DMAMUX1 TIM5 UP request */ 281 #define DMA_REQUEST_TIM5_TRIG 77U /*!< DMAMUX1 TIM5 TRIG request */ 282 283 #define DMA_REQUEST_TIM15_CH1 78U /*!< DMAMUX1 TIM15 CH1 request */ 284 #define DMA_REQUEST_TIM15_UP 79U /*!< DMAMUX1 TIM15 UP request */ 285 #define DMA_REQUEST_TIM15_TRIG 80U /*!< DMAMUX1 TIM15 TRIG request */ 286 #define DMA_REQUEST_TIM15_COM 81U /*!< DMAMUX1 TIM15 COM request */ 287 288 #define DMA_REQUEST_TIM16_CH1 82U /*!< DMAMUX1 TIM16 CH1 request */ 289 #define DMA_REQUEST_TIM16_UP 83U /*!< DMAMUX1 TIM16 UP request */ 290 #define DMA_REQUEST_TIM17_CH1 84U /*!< DMAMUX1 TIM17 CH1 request */ 291 #define DMA_REQUEST_TIM17_UP 85U /*!< DMAMUX1 TIM17 UP request */ 292 293 #define DMA_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX1 DFSDM1 Filter0 request */ 294 #define DMA_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX1 DFSDM1 Filter1 request */ 295 #define DMA_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX1 DFSDM1 Filter2 request */ 296 #define DMA_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX1 DFSDM1 Filter3 request */ 297 298 #define DMA_REQUEST_AES_IN 90U /*!< DMAMUX1 AES IN request */ 299 #define DMA_REQUEST_AES_OUT 91U /*!< DMAMUX1 AES OUT request */ 300 301 #define DMA_REQUEST_HASH_IN 92U /*!< DMAMUX1 HASH IN request */ 302 303 #define DMA_REQUEST_UCPD1_TX 93U /*!< DMAMUX1 UCPD1 TX request */ 304 #define DMA_REQUEST_UCPD1_RX 94U /*!< DMAMUX1 UCPD1 RX request */ 305 /** 306 * @} 307 */ 308 309 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 310 * @{ 311 */ 312 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 313 #define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ 314 #define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ 315 /** 316 * @} 317 */ 318 319 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 320 * @{ 321 */ 322 #define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ 323 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ 324 /** 325 * @} 326 */ 327 328 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 329 * @{ 330 */ 331 #define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ 332 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ 333 /** 334 * @} 335 */ 336 337 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 338 * @{ 339 */ 340 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 341 #define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 342 #define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 343 /** 344 * @} 345 */ 346 347 /** @defgroup DMA_Memory_data_size DMA Memory data size 348 * @{ 349 */ 350 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 351 #define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 352 #define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ 353 /** 354 * @} 355 */ 356 357 /** @defgroup DMA_mode DMA mode 358 * @{ 359 */ 360 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 361 #define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ 362 #define DMA_DOUBLE_BUFFER_M0 DMA_CCR_DBM /*!< Double buffer mode with first target memory M0 */ 363 #define DMA_DOUBLE_BUFFER_M1 (DMA_CCR_DBM | DMA_CCR_CT) /*!< Double buffer mode with first target memory M1 */ 364 /** 365 * @} 366 */ 367 368 /** @defgroup DMA_Priority_level DMA Priority level 369 * @{ 370 */ 371 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 372 #define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ 373 #define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ 374 #define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ 375 /** 376 * @} 377 */ 378 379 380 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 381 * @{ 382 */ 383 #define DMA_IT_TC DMA_CCR_TCIE 384 #define DMA_IT_HT DMA_CCR_HTIE 385 #define DMA_IT_TE DMA_CCR_TEIE 386 /** 387 * @} 388 */ 389 390 /** @defgroup DMA_flag_definitions DMA flag definitions 391 * @{ 392 */ 393 #define DMA_FLAG_GL1 DMA_ISR_GIF1 394 #define DMA_FLAG_TC1 DMA_ISR_TCIF1 395 #define DMA_FLAG_HT1 DMA_ISR_HTIF1 396 #define DMA_FLAG_TE1 DMA_ISR_TEIF1 397 #define DMA_FLAG_GL2 DMA_ISR_GIF2 398 #define DMA_FLAG_TC2 DMA_ISR_TCIF2 399 #define DMA_FLAG_HT2 DMA_ISR_HTIF2 400 #define DMA_FLAG_TE2 DMA_ISR_TEIF2 401 #define DMA_FLAG_GL3 DMA_ISR_GIF3 402 #define DMA_FLAG_TC3 DMA_ISR_TCIF3 403 #define DMA_FLAG_HT3 DMA_ISR_HTIF3 404 #define DMA_FLAG_TE3 DMA_ISR_TEIF3 405 #define DMA_FLAG_GL4 DMA_ISR_GIF4 406 #define DMA_FLAG_TC4 DMA_ISR_TCIF4 407 #define DMA_FLAG_HT4 DMA_ISR_HTIF4 408 #define DMA_FLAG_TE4 DMA_ISR_TEIF4 409 #define DMA_FLAG_GL5 DMA_ISR_GIF5 410 #define DMA_FLAG_TC5 DMA_ISR_TCIF5 411 #define DMA_FLAG_HT5 DMA_ISR_HTIF5 412 #define DMA_FLAG_TE5 DMA_ISR_TEIF5 413 #define DMA_FLAG_GL6 DMA_ISR_GIF6 414 #define DMA_FLAG_TC6 DMA_ISR_TCIF6 415 #define DMA_FLAG_HT6 DMA_ISR_HTIF6 416 #define DMA_FLAG_TE6 DMA_ISR_TEIF6 417 #define DMA_FLAG_GL7 DMA_ISR_GIF7 418 #define DMA_FLAG_TC7 DMA_ISR_TCIF7 419 #define DMA_FLAG_HT7 DMA_ISR_HTIF7 420 #define DMA_FLAG_TE7 DMA_ISR_TEIF7 421 #define DMA_FLAG_GL8 DMA_ISR_GIF8 422 #define DMA_FLAG_TC8 DMA_ISR_TCIF8 423 #define DMA_FLAG_HT8 DMA_ISR_HTIF8 424 #define DMA_FLAG_TE8 DMA_ISR_TEIF8 425 426 /** 427 * @} 428 */ 429 430 /** @defgroup DMA_Channel_Attributes DMA Channel Attributes 431 * @brief DMA channel secure or non-secure and privileged or non-privileged attributes 432 * @note Secure and non-secure attributes are only available from secure when the system 433 * implements the security (TZEN=1) 434 * @{ 435 */ 436 437 #define DMA_CHANNEL_ATTR_PRIV_MASK (DMA_CCR_PRIV >> 16U) 438 #define DMA_CHANNEL_ATTR_SEC_MASK (DMA_CCR_SECM >> 16U) 439 #define DMA_CHANNEL_ATTR_SEC_SRC_MASK (DMA_CCR_SSEC >> 16U) 440 #define DMA_CHANNEL_ATTR_SEC_DEST_MASK (DMA_CCR_DSEC >> 16U) 441 442 #define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | DMA_CCR_PRIV) /*!< Channel is privileged */ 443 #define DMA_CHANNEL_NPRIV (DMA_CHANNEL_ATTR_PRIV_MASK) /*!< Channel is unprivileged */ 444 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 445 #define DMA_CHANNEL_SEC (DMA_CHANNEL_ATTR_SEC_MASK | DMA_CCR_SECM) /*!< Channel is secure */ 446 #define DMA_CHANNEL_NSEC (DMA_CHANNEL_ATTR_SEC_MASK) /*!< Channel is non-secure */ 447 #define DMA_CHANNEL_SRC_SEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK | DMA_CCR_SSEC) /*!< Channel source is secure */ 448 #define DMA_CHANNEL_SRC_NSEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK) /*!< Channel source is non-secure */ 449 #define DMA_CHANNEL_DEST_SEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK | DMA_CCR_DSEC) /*!< Channel destination is secure */ 450 #define DMA_CHANNEL_DEST_NSEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK) /*!< Channel destination is non-secure */ 451 #endif /* __ARM_FEATURE_CMSE */ 452 453 /** 454 * @} 455 */ 456 457 /** 458 * @} 459 */ 460 461 /* Exported macros -----------------------------------------------------------*/ 462 /** @defgroup DMA_Exported_Macros DMA Exported Macros 463 * @{ 464 */ 465 466 /** @brief Reset DMA handle state. 467 * @param __HANDLE__ DMA handle 468 * @retval None 469 */ 470 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 471 472 /** 473 * @brief Enable the specified DMA Channel. 474 * @param __HANDLE__ DMA handle 475 * @retval None 476 */ 477 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 478 479 /** 480 * @brief Disable the specified DMA Channel. 481 * @param __HANDLE__ DMA handle 482 * @retval None 483 */ 484 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 485 486 487 /* Interrupt & Flag management */ 488 489 /** 490 * @brief Return the current DMA Channel transfer complete flag. 491 * @param __HANDLE__ DMA handle 492 * @retval The specified transfer complete flag index. 493 */ 494 495 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 496 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ 498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ 500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ 502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ 506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TC7 :\ 510 DMA_FLAG_TC8) 511 512 /** 513 * @brief Return the current DMA Channel half transfer complete flag. 514 * @param __HANDLE__ DMA handle 515 * @retval The specified half transfer complete flag index. 516 */ 517 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 518 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ 522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 523 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ 524 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 525 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ 526 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 527 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ 528 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 529 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ 530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ 531 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_HT7 :\ 532 DMA_FLAG_HT8) 533 534 /** 535 * @brief Return the current DMA Channel transfer error flag. 536 * @param __HANDLE__ DMA handle 537 * @retval The specified transfer error flag index. 538 */ 539 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 540 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ 542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 543 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ 544 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 545 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ 546 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 547 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ 548 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 549 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ 550 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 551 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ 552 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ 553 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TE7 :\ 554 DMA_FLAG_TE8) 555 556 /** 557 * @brief Return the current DMA Channel Global interrupt flag. 558 * @param __HANDLE__ DMA handle 559 * @retval The specified transfer error flag index. 560 */ 561 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 562 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 563 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ 564 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 565 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ 566 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 567 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ 568 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 569 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ 570 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ 571 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ 572 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ 573 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ 574 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_ISR_GIF7 :\ 575 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_ISR_GIF7 :\ 576 DMA_ISR_GIF8) 577 578 /** 579 * @brief Get the DMA Channel pending flags. 580 * @param __HANDLE__ DMA handle 581 * @param __FLAG__ Get the specified flag. 582 * This parameter can be any combination of the following values: 583 * @arg DMA_FLAG_TCx: Transfer complete flag 584 * @arg DMA_FLAG_HTx: Half transfer complete flag 585 * @arg DMA_FLAG_TEx: Transfer error flag 586 * @arg DMA_FLAG_GLx: Global interrupt flag 587 * Where x can be from 1 to 8 to select the DMA Channel x flag. 588 * @retval The state of FLAG (SET or RESET). 589 */ 590 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \ 591 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) 592 593 /** 594 * @brief Clear the DMA Channel pending flags. 595 * @param __HANDLE__ DMA handle 596 * @param __FLAG__ specifies the flag to clear. 597 * This parameter can be any combination of the following values: 598 * @arg DMA_FLAG_TCx: Transfer complete flag 599 * @arg DMA_FLAG_HTx: Half transfer complete flag 600 * @arg DMA_FLAG_TEx: Transfer error flag 601 * @arg DMA_FLAG_GLx: Global interrupt flag 602 * Where x can be from 1 to 8 to select the DMA Channel x flag. 603 * @retval None 604 */ 605 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \ 606 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) 607 608 /** 609 * @brief Enable the specified DMA Channel interrupts. 610 * @param __HANDLE__ DMA handle 611 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 612 * This parameter can be any combination of the following values: 613 * @arg DMA_IT_TC: Transfer complete interrupt mask 614 * @arg DMA_IT_HT: Half transfer complete interrupt mask 615 * @arg DMA_IT_TE: Transfer error interrupt mask 616 * @retval None 617 */ 618 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 619 620 /** 621 * @brief Disable the specified DMA Channel interrupts. 622 * @param __HANDLE__ DMA handle 623 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 624 * This parameter can be any combination of the following values: 625 * @arg DMA_IT_TC: Transfer complete interrupt mask 626 * @arg DMA_IT_HT: Half transfer complete interrupt mask 627 * @arg DMA_IT_TE: Transfer error interrupt mask 628 * @retval None 629 */ 630 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 631 632 /** 633 * @brief Check whether the specified DMA Channel interrupt is enabled or not. 634 * @param __HANDLE__ DMA handle 635 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 636 * This parameter can be one of the following values: 637 * @arg DMA_IT_TC: Transfer complete interrupt mask 638 * @arg DMA_IT_HT: Half transfer complete interrupt mask 639 * @arg DMA_IT_TE: Transfer error interrupt mask 640 * @retval The state of DMA_IT (SET or RESET). 641 */ 642 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 643 644 /** 645 * @brief Return the number of remaining data units in the current DMA Channel transfer. 646 * @param __HANDLE__ DMA handle 647 * @retval The number of remaining data units in the current DMA Channel transfer. 648 */ 649 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 650 651 /** 652 * @} 653 */ 654 655 /* Include DMA HAL Extension module */ 656 #include "stm32l5xx_hal_dma_ex.h" 657 658 /* Exported functions --------------------------------------------------------*/ 659 660 /** @addtogroup DMA_Exported_Functions 661 * @{ 662 */ 663 664 /** @addtogroup DMA_Exported_Functions_Group1 665 * @{ 666 */ 667 /* Initialization and de-initialization functions *****************************/ 668 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 669 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); 670 /** 671 * @} 672 */ 673 674 /** @addtogroup DMA_Exported_Functions_Group2 675 * @{ 676 */ 677 /* IO operation functions *****************************************************/ 678 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 679 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 680 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 681 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 682 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 683 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 684 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); 685 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 686 687 /** 688 * @} 689 */ 690 691 /** @addtogroup DMA_Exported_Functions_Group3 692 * @{ 693 */ 694 /* Peripheral State and Error functions ***************************************/ 695 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 696 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 697 /** 698 * @} 699 */ 700 701 /** @addtogroup DMA_Exported_Functions_Group4 702 * @{ 703 */ 704 /* DMA Attributes functions ********************************************/ 705 HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t ChannelAttributes); 706 HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t *ChannelAttributes); 707 /** 708 * @} 709 */ 710 711 /** 712 * @} 713 */ 714 715 /* Private macros ------------------------------------------------------------*/ 716 /** @defgroup DMA_Private_Macros DMA Private Macros 717 * @{ 718 */ 719 720 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 721 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 722 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 723 724 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x40000U)) 725 726 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 727 ((STATE) == DMA_PINC_DISABLE)) 728 729 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 730 ((STATE) == DMA_MINC_DISABLE)) 731 732 #define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_UCPD1_RX) 733 734 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 735 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 736 ((SIZE) == DMA_PDATAALIGN_WORD)) 737 738 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 739 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 740 ((SIZE) == DMA_MDATAALIGN_WORD )) 741 742 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 743 ((MODE) == DMA_CIRCULAR) || \ 744 ((MODE) == DMA_DOUBLE_BUFFER_M0) || \ 745 ((MODE) == DMA_DOUBLE_BUFFER_M1)) 746 747 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 748 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 749 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 750 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 751 752 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 753 #define IS_DMA_ATTRIBUTES(ATTRIBUTE) ((((ATTRIBUTE) & (~(0x001E001EU))) == 0U) && (((ATTRIBUTE) & 0x0000001EU) != 0U)) 754 #else 755 #define IS_DMA_ATTRIBUTES(ATTRIBUTE) (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ 756 ((ATTRIBUTE) == DMA_CHANNEL_NPRIV)) 757 #endif 758 759 /** 760 * @} 761 */ 762 763 /* Private functions ---------------------------------------------------------*/ 764 765 /** 766 * @} 767 */ 768 769 /** 770 * @} 771 */ 772 773 #ifdef __cplusplus 774 } 775 #endif 776 777 #endif /* STM32L5xx_HAL_DMA_H */ 778 779
