1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_dac.h 4 * @author MCD Application Team 5 * @brief Header file of DAC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L5xx_HAL_DAC_H 21 #define STM32L5xx_HAL_DAC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /** @addtogroup STM32L5xx_HAL_Driver 28 * @{ 29 */ 30 31 /* Includes ------------------------------------------------------------------*/ 32 #include "stm32l5xx_hal_def.h" 33 34 #if defined(DAC1) 35 36 /** @addtogroup DAC 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 42 /** @defgroup DAC_Exported_Types DAC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief HAL State structures definition 48 */ 49 typedef enum 50 { 51 HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ 52 HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ 53 HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ 54 HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ 55 HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ 56 57 } HAL_DAC_StateTypeDef; 58 59 /** 60 * @brief DAC handle Structure definition 61 */ 62 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 63 typedef struct __DAC_HandleTypeDef 64 #else 65 typedef struct 66 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 67 { 68 DAC_TypeDef *Instance; /*!< Register base address */ 69 70 __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ 71 72 HAL_LockTypeDef Lock; /*!< DAC locking object */ 73 74 DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ 75 76 DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ 77 78 __IO uint32_t ErrorCode; /*!< DAC Error code */ 79 80 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 81 void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); 82 void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); 83 void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac); 84 void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac); 85 86 void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); 87 void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); 88 void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac); 89 void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac); 90 91 92 void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac); 93 void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac); 94 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 95 96 } DAC_HandleTypeDef; 97 98 /** 99 * @brief DAC Configuration sample and hold Channel structure definition 100 */ 101 typedef struct 102 { 103 uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel. 104 This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 105 This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ 106 107 uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel 108 This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 109 This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ 110 111 uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel 112 This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 113 This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ 114 } DAC_SampleAndHoldConfTypeDef; 115 116 /** 117 * @brief DAC Configuration regular Channel structure definition 118 */ 119 typedef struct 120 { 121 uint32_t DAC_HighFrequency; /*!< Specifies the frequency interface mode 122 This parameter can be a value of @ref DAC_HighFrequency */ 123 124 uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode. 125 This parameter can be a value of @ref DAC_SampleAndHold */ 126 127 uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. 128 This parameter can be a value of @ref DAC_trigger_selection */ 129 130 uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. 131 This parameter can be a value of @ref DAC_output_buffer */ 132 133 uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral . 134 This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */ 135 136 uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode 137 This parameter must be a value of @ref DAC_UserTrimming 138 DAC_UserTrimming is either factory or user trimming */ 139 140 uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value 141 i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. 142 This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ 143 DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */ 144 } DAC_ChannelConfTypeDef; 145 146 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 147 /** 148 * @brief HAL DAC Callback ID enumeration definition 149 */ 150 typedef enum 151 { 152 HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */ 153 HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */ 154 HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */ 155 HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */ 156 157 HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */ 158 HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */ 159 HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */ 160 HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */ 161 162 HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */ 163 HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */ 164 HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */ 165 } HAL_DAC_CallbackIDTypeDef; 166 167 /** 168 * @brief HAL DAC Callback pointer definition 169 */ 170 typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); 171 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 172 173 /** 174 * @} 175 */ 176 177 /* Exported constants --------------------------------------------------------*/ 178 179 /** @defgroup DAC_Exported_Constants DAC Exported Constants 180 * @{ 181 */ 182 183 /** @defgroup DAC_Error_Code DAC Error Code 184 * @{ 185 */ 186 #define HAL_DAC_ERROR_NONE 0x00U /*!< No error */ 187 #define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */ 188 #define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */ 189 #define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */ 190 #define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */ 191 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 192 #define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */ 193 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 194 195 /** 196 * @} 197 */ 198 199 /** @defgroup DAC_trigger_selection DAC trigger selection 200 * @{ 201 */ 202 #define DAC_TRIGGER_NONE 0x00000000UL /*!< conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ 203 #define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1) /*!< conversion started by software trigger for DAC channel */ 204 #define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel. */ 205 #define DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ 206 #define DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ 207 #define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ 208 #define DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ 209 #define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ 210 #define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ 211 #define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ 212 #define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */ 213 #define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 |DAC_CR_TEN1) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */ 214 #define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ 215 216 /** 217 * @} 218 */ 219 220 /** @defgroup DAC_output_buffer DAC output buffer 221 * @{ 222 */ 223 #define DAC_OUTPUTBUFFER_ENABLE 0x00000000U 224 #define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1) 225 226 /** 227 * @} 228 */ 229 230 /** @defgroup DAC_Channel_selection DAC Channel selection 231 * @{ 232 */ 233 #define DAC_CHANNEL_1 0x00000000U 234 235 #define DAC_CHANNEL_2 0x00000010U 236 237 /** 238 * @} 239 */ 240 241 /** @defgroup DAC_data_alignment DAC data alignment 242 * @{ 243 */ 244 #define DAC_ALIGN_12B_R 0x00000000U 245 #define DAC_ALIGN_12B_L 0x00000004U 246 #define DAC_ALIGN_8B_R 0x00000008U 247 248 /** 249 * @} 250 */ 251 252 /** @defgroup DAC_flags_definition DAC flags definition 253 * @{ 254 */ 255 #define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) 256 257 #define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) 258 259 260 /** 261 * @} 262 */ 263 264 /** @defgroup DAC_IT_definition DAC IT definition 265 * @{ 266 */ 267 #define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1) 268 269 #define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2) 270 271 272 /** 273 * @} 274 */ 275 276 /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral 277 * @{ 278 */ 279 #define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) 280 #define DAC_CHIPCONNECT_INTERNAL (1UL << 1) 281 #define DAC_CHIPCONNECT_BOTH (1UL << 2) 282 283 /** 284 * @} 285 */ 286 287 /** @defgroup DAC_UserTrimming DAC User Trimming 288 * @{ 289 */ 290 #define DAC_TRIMMING_FACTORY (0x00000000UL) /*!< Factory trimming */ 291 #define DAC_TRIMMING_USER (0x00000001UL) /*!< User trimming */ 292 /** 293 * @} 294 */ 295 296 /** @defgroup DAC_SampleAndHold DAC power mode 297 * @{ 298 */ 299 #define DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL) 300 #define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2) 301 302 /** 303 * @} 304 */ 305 /** @defgroup DAC_HighFrequency DAC high frequency interface mode 306 * @{ 307 */ 308 #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */ 309 #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ (DAC_CR_HFSEL) /*!< High frequency interface mode compatible to AHB>80MHz enabled */ 310 #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC 0x00000002UL /*!< High frequency interface mode automatic */ 311 312 /** 313 * @} 314 */ 315 316 /** 317 * @} 318 */ 319 320 /* Exported macro ------------------------------------------------------------*/ 321 322 /** @defgroup DAC_Exported_Macros DAC Exported Macros 323 * @{ 324 */ 325 326 /** @brief Reset DAC handle state. 327 * @param __HANDLE__ specifies the DAC handle. 328 * @retval None 329 */ 330 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 331 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \ 332 (__HANDLE__)->State = HAL_DAC_STATE_RESET; \ 333 (__HANDLE__)->MspInitCallback = NULL; \ 334 (__HANDLE__)->MspDeInitCallback = NULL; \ 335 } while(0) 336 #else 337 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) 338 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 339 340 /** @brief Enable the DAC channel. 341 * @param __HANDLE__ specifies the DAC handle. 342 * @param __DAC_Channel__ specifies the DAC channel 343 * @retval None 344 */ 345 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ 346 ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) 347 348 /** @brief Disable the DAC channel. 349 * @param __HANDLE__ specifies the DAC handle 350 * @param __DAC_Channel__ specifies the DAC channel. 351 * @retval None 352 */ 353 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ 354 ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) 355 356 /** @brief Set DHR12R1 alignment. 357 * @param __ALIGNMENT__ specifies the DAC alignment 358 * @retval None 359 */ 360 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__)) 361 362 363 /** @brief Set DHR12R2 alignment. 364 * @param __ALIGNMENT__ specifies the DAC alignment 365 * @retval None 366 */ 367 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__)) 368 369 370 /** @brief Set DHR12RD alignment. 371 * @param __ALIGNMENT__ specifies the DAC alignment 372 * @retval None 373 */ 374 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__)) 375 376 /** @brief Enable the DAC interrupt. 377 * @param __HANDLE__ specifies the DAC handle 378 * @param __INTERRUPT__ specifies the DAC interrupt. 379 * This parameter can be any combination of the following values: 380 * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt 381 * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt 382 * @retval None 383 */ 384 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) 385 386 /** @brief Disable the DAC interrupt. 387 * @param __HANDLE__ specifies the DAC handle 388 * @param __INTERRUPT__ specifies the DAC interrupt. 389 * This parameter can be any combination of the following values: 390 * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt 391 * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt 392 * @retval None 393 */ 394 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) 395 396 /** @brief Check whether the specified DAC interrupt source is enabled or not. 397 * @param __HANDLE__ DAC handle 398 * @param __INTERRUPT__ DAC interrupt source to check 399 * This parameter can be any combination of the following values: 400 * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt 401 * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt 402 * @retval State of interruption (SET or RESET) 403 */ 404 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\ 405 & (__INTERRUPT__)) == (__INTERRUPT__)) 406 407 /** @brief Get the selected DAC's flag status. 408 * @param __HANDLE__ specifies the DAC handle. 409 * @param __FLAG__ specifies the DAC flag to get. 410 * This parameter can be any combination of the following values: 411 * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag 412 * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag 413 * @retval None 414 */ 415 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 416 417 /** @brief Clear the DAC's flag. 418 * @param __HANDLE__ specifies the DAC handle. 419 * @param __FLAG__ specifies the DAC flag to clear. 420 * This parameter can be any combination of the following values: 421 * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag 422 * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag 423 * @retval None 424 */ 425 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) 426 427 /** 428 * @} 429 */ 430 431 /* Private macro -------------------------------------------------------------*/ 432 433 /** @defgroup DAC_Private_Macros DAC Private Macros 434 * @{ 435 */ 436 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ 437 ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) 438 439 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ 440 ((CHANNEL) == DAC_CHANNEL_2)) 441 442 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ 443 ((ALIGN) == DAC_ALIGN_12B_L) || \ 444 ((ALIGN) == DAC_ALIGN_8B_R)) 445 446 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL) 447 448 #define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL) 449 450 /** 451 * @} 452 */ 453 454 /* Include DAC HAL Extended module */ 455 #include "stm32l5xx_hal_dac_ex.h" 456 457 /* Exported functions --------------------------------------------------------*/ 458 459 /** @addtogroup DAC_Exported_Functions 460 * @{ 461 */ 462 463 /** @addtogroup DAC_Exported_Functions_Group1 464 * @{ 465 */ 466 /* Initialization and de-initialization functions *****************************/ 467 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac); 468 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac); 469 void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac); 470 void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac); 471 472 /** 473 * @} 474 */ 475 476 /** @addtogroup DAC_Exported_Functions_Group2 477 * @{ 478 */ 479 /* IO operation functions *****************************************************/ 480 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); 481 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); 482 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, 483 uint32_t Alignment); 484 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); 485 void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); 486 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); 487 488 void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac); 489 void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac); 490 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); 491 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); 492 493 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 494 /* DAC callback registering/unregistering */ 495 HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, 496 pDAC_CallbackTypeDef pCallback); 497 HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID); 498 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 499 500 /** 501 * @} 502 */ 503 504 /** @addtogroup DAC_Exported_Functions_Group3 505 * @{ 506 */ 507 /* Peripheral Control functions ***********************************************/ 508 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel); 509 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); 510 /** 511 * @} 512 */ 513 514 /** @addtogroup DAC_Exported_Functions_Group4 515 * @{ 516 */ 517 /* Peripheral State and Error functions ***************************************/ 518 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac); 519 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); 520 521 /** 522 * @} 523 */ 524 525 /** 526 * @} 527 */ 528 529 /** @defgroup DAC_Private_Functions DAC Private Functions 530 * @{ 531 */ 532 void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); 533 void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); 534 void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); 535 /** 536 * @} 537 */ 538 539 /** 540 * @} 541 */ 542 543 #endif /* DAC1 */ 544 545 /** 546 * @} 547 */ 548 549 #ifdef __cplusplus 550 } 551 #endif 552 553 554 #endif /* STM32L5xx_HAL_DAC_H */ 555 556 557
