1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L5xx_HAL_CORTEX_H 21 #define STM32L5xx_HAL_CORTEX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l5xx_hal_def.h" 29 30 /** @addtogroup STM32L5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @defgroup CORTEX CORTEX 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 40 * @{ 41 */ 42 43 #if (__MPU_PRESENT == 1) 44 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 45 * @{ 46 */ 47 typedef struct 48 { 49 uint8_t Enable; /*!< Specifies the status of the region. 50 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 51 uint8_t Number; /*!< Specifies the number of the region to protect. 52 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 53 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 54 uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */ 55 uint8_t AttributesIndex; /*!< Specifies the memory attributes index. 56 This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ 57 uint8_t AccessPermission; /*!< Specifies the region access permission type. 58 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 59 uint8_t DisableExec; /*!< Specifies the instruction access status. 60 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 61 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 62 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 63 } MPU_Region_InitTypeDef; 64 /** 65 * @} 66 */ 67 68 /** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes Initialization Structure Definition 69 * @{ 70 */ 71 typedef struct 72 { 73 uint8_t Number; /*!< Specifies the number of the memory attributes to configure. 74 This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ 75 76 uint8_t Attributes; /*!< Specifies the memory attributes vue. 77 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ 78 79 } MPU_Attributes_InitTypeDef; 80 /** 81 * @} 82 */ 83 84 #endif /* __MPU_PRESENT */ 85 86 /** 87 * @} 88 */ 89 90 /* Exported constants --------------------------------------------------------*/ 91 92 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 93 * @{ 94 */ 95 96 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 97 * @{ 98 */ 99 #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority, 100 3 bits for subpriority */ 101 #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority, 102 2 bits for subpriority */ 103 #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority, 104 1 bits for subpriority */ 105 #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority, 106 0 bit for subpriority */ 107 /** 108 * @} 109 */ 110 111 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 112 * @{ 113 */ 114 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) 115 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) 116 /** 117 * @} 118 */ 119 120 #if (__MPU_PRESENT == 1) 121 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 122 * @{ 123 */ 124 #define MPU_HFNMI_PRIVDEF_NONE 0U 125 #define MPU_HARDFAULT_NMI 2U 126 #define MPU_PRIVILEGED_DEFAULT 4U 127 #define MPU_HFNMI_PRIVDEF 6U 128 /** 129 * @} 130 */ 131 132 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 133 * @{ 134 */ 135 #define MPU_REGION_ENABLE 1U 136 #define MPU_REGION_DISABLE 0U 137 /** 138 * @} 139 */ 140 141 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 142 * @{ 143 */ 144 #define MPU_INSTRUCTION_ACCESS_ENABLE 0U 145 #define MPU_INSTRUCTION_ACCESS_DISABLE 1U 146 /** 147 * @} 148 */ 149 150 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 151 * @{ 152 */ 153 #define MPU_ACCESS_NOT_SHAREABLE 0U 154 #define MPU_ACCESS_OUTER_SHAREABLE 2U 155 #define MPU_ACCESS_INNER_SHAREABLE 3U 156 /** 157 * @} 158 */ 159 160 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 161 * @{ 162 */ 163 #define MPU_REGION_PRIV_RW 0U 164 #define MPU_REGION_ALL_RW 1U 165 #define MPU_REGION_PRIV_RO 2U 166 #define MPU_REGION_ALL_RO 3U 167 /** 168 * @} 169 */ 170 171 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 172 * @{ 173 */ 174 #define MPU_REGION_NUMBER0 0U 175 #define MPU_REGION_NUMBER1 1U 176 #define MPU_REGION_NUMBER2 2U 177 #define MPU_REGION_NUMBER3 3U 178 #define MPU_REGION_NUMBER4 4U 179 #define MPU_REGION_NUMBER5 5U 180 #define MPU_REGION_NUMBER6 6U 181 #define MPU_REGION_NUMBER7 7U 182 /** 183 * @} 184 */ 185 186 /** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number 187 * @{ 188 */ 189 #define MPU_ATTRIBUTES_NUMBER0 0U 190 #define MPU_ATTRIBUTES_NUMBER1 1U 191 #define MPU_ATTRIBUTES_NUMBER2 2U 192 #define MPU_ATTRIBUTES_NUMBER3 3U 193 #define MPU_ATTRIBUTES_NUMBER4 4U 194 #define MPU_ATTRIBUTES_NUMBER5 5U 195 #define MPU_ATTRIBUTES_NUMBER6 6U 196 #define MPU_ATTRIBUTES_NUMBER7 7U 197 /** 198 * @} 199 */ 200 201 /** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes 202 * @{ 203 */ 204 #define MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ 205 #define MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ 206 #define MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ 207 #define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ 208 209 #define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ 210 #define MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ 211 #define MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ 212 213 #define MPU_TRANSIENT 0x0U /* Normal memory, transient. */ 214 #define MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ 215 216 #define MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ 217 #define MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ 218 #define MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ 219 #define MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ 220 221 #define OUTER(__ATTR__) ((__ATTR__) << 4U) 222 #define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U)) 223 /** 224 * @} 225 */ 226 227 #endif /* __MPU_PRESENT */ 228 229 /** 230 * @} 231 */ 232 233 /* Exported macros -----------------------------------------------------------*/ 234 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 235 * @{ 236 */ 237 238 /** 239 * @} 240 */ 241 242 /* Exported functions --------------------------------------------------------*/ 243 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 244 * @{ 245 */ 246 247 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 248 * @brief Initialization and Configuration functions 249 * @{ 250 */ 251 /* Initialization and Configuration functions *****************************/ 252 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 253 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 254 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 255 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 256 void HAL_NVIC_SystemReset(void); 257 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 258 /** 259 * @} 260 */ 261 262 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 263 * @brief Cortex control functions 264 * @{ 265 */ 266 /* Peripheral Control functions ***********************************************/ 267 uint32_t HAL_NVIC_GetPriorityGrouping(void); 268 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); 269 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 270 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 271 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 272 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 273 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 274 void HAL_SYSTICK_IRQHandler(void); 275 void HAL_SYSTICK_Callback(void); 276 277 #if (__MPU_PRESENT == 1) 278 void HAL_MPU_Enable(uint32_t MPU_Control); 279 void HAL_MPU_Disable(void); 280 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_RegionInit); 281 void HAL_MPU_ConfigMemoryAttributes(MPU_Attributes_InitTypeDef *MPU_AttributesInit); 282 #ifdef MPU_NS 283 void HAL_MPU_Enable_NS(uint32_t MPU_Control); 284 void HAL_MPU_Disable_NS(void); 285 void HAL_MPU_ConfigRegion_NS(MPU_Region_InitTypeDef *MPU_RegionInit); 286 void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_AttributesInit); 287 #endif /* MPU_NS */ 288 #endif /* __MPU_PRESENT */ 289 /** 290 * @} 291 */ 292 293 /** 294 * @} 295 */ 296 297 /* Private types -------------------------------------------------------------*/ 298 /* Private variables ---------------------------------------------------------*/ 299 /* Private constants ---------------------------------------------------------*/ 300 /* Private macros ------------------------------------------------------------*/ 301 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 302 * @{ 303 */ 304 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 305 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 306 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 307 ((GROUP) == NVIC_PRIORITYGROUP_3)) 308 309 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) 310 311 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) 312 313 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) 314 315 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ 316 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 317 318 #if (__MPU_PRESENT == 1) 319 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 320 ((STATE) == MPU_REGION_DISABLE)) 321 322 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 323 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 324 325 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \ 326 ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \ 327 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 328 329 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_PRIV_RW) || \ 330 ((TYPE) == MPU_REGION_ALL_RW) || \ 331 ((TYPE) == MPU_REGION_PRIV_RO) || \ 332 ((TYPE) == MPU_REGION_ALL_RO)) 333 334 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 335 ((NUMBER) == MPU_REGION_NUMBER1) || \ 336 ((NUMBER) == MPU_REGION_NUMBER2) || \ 337 ((NUMBER) == MPU_REGION_NUMBER3) || \ 338 ((NUMBER) == MPU_REGION_NUMBER4) || \ 339 ((NUMBER) == MPU_REGION_NUMBER5) || \ 340 ((NUMBER) == MPU_REGION_NUMBER6) || \ 341 ((NUMBER) == MPU_REGION_NUMBER7)) 342 343 #define IS_MPU_ATTRIBUTES_NUMBER(NUMBER) (((NUMBER) == MPU_ATTRIBUTES_NUMBER0) || \ 344 ((NUMBER) == MPU_ATTRIBUTES_NUMBER1) || \ 345 ((NUMBER) == MPU_ATTRIBUTES_NUMBER2) || \ 346 ((NUMBER) == MPU_ATTRIBUTES_NUMBER3) || \ 347 ((NUMBER) == MPU_ATTRIBUTES_NUMBER4) || \ 348 ((NUMBER) == MPU_ATTRIBUTES_NUMBER5) || \ 349 ((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \ 350 ((NUMBER) == MPU_ATTRIBUTES_NUMBER7)) 351 352 #endif /* __MPU_PRESENT */ 353 354 /** 355 * @} 356 */ 357 358 /* Private functions ---------------------------------------------------------*/ 359 360 /** 361 * @} 362 */ 363 364 /** 365 * @} 366 */ 367 368 #ifdef __cplusplus 369 } 370 #endif 371 372 #endif /* STM32L5xx_HAL_CORTEX_H */ 373 374 375
