1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_adc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L5xx_HAL_ADC_EX_H 21 #define STM32L5xx_HAL_ADC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l5xx_hal_def.h" 29 30 /** @addtogroup STM32L5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup ADCEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief ADC Injected Conversion Oversampling structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Ratio; /*!< Configures the oversampling ratio. 49 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 50 51 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 52 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 53 } ADC_InjOversamplingTypeDef; 54 55 /** 56 * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected 57 * @note Parameters of this structure are shared within 2 scopes: 58 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, 59 * InjectedOffsetNumber, InjectedOffset 60 * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, 61 * InjectedDiscontinuousConvMode, 62 * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, 63 * InjecOversamplingMode, InjecOversampling. 64 * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 65 * ADC state can be either: 66 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 67 * 'InjectedSingleDiff') 68 * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled 69 * without conversion on going on injected group. 70 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': 71 * ADC enabled without conversion on going on regular and injected groups. 72 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 73 * 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going 74 * on ADC groups regular and injected. 75 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 76 * without error reporting (as it can be the expected behavior in case of intended action to update another 77 * parameter (which fulfills the ADC state condition) on the fly). 78 */ 79 typedef struct 80 { 81 uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. 82 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 83 Note: Depending on devices and ADC instances, some channels may not be 84 available on device package pins. Refer to device datasheet for 85 channels availability. */ 86 87 uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. 88 This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. 89 Note: to disable a channel or change order of conversion sequencer, 90 rank containing a previous channel setting can be overwritten by 91 the new channel setting (or parameter number of conversions 92 adjusted) */ 93 94 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 95 Unit: ADC clock cycles. 96 Conversion time is the addition of sampling time and processing time 97 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 98 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 99 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. 100 Caution: This parameter applies to a channel that can be used in a 101 regular and/or injected group. It overwrites the last setting. 102 Note: In case of usage of internal measurement channels (VrefInt, ...), 103 sampling time constraints must be respected (sampling time can be 104 adjusted in function of ADC clock frequency and sampling time 105 setting). Refer to device datasheet for timings values. */ 106 107 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. 108 In differential mode: Differential measurement is between the selected 109 channel 'i' (positive input) and channel 'i+1' (negative input). 110 Only channel 'i' has to be configured, channel 'i+1' is configured 111 automatically. 112 This parameter must be a value of 113 @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. 114 Caution: This parameter applies to a channel that can be used in a 115 regular and/or injected group. It overwrites the last setting. 116 Note: Refer to Reference Manual to ensure the selected channel is 117 available in differential mode. 118 Note: When configuring a channel 'i' in differential mode, the channel 119 'i+1' is not usable separately. 120 Note: This parameter must be modified when ADC is disabled (before ADC 121 start conversion or after ADC stop conversion). 122 If ADC is enabled, this parameter setting is bypassed without error 123 reporting (as it can be the expected behavior in case of another 124 parameter update on the fly) */ 125 126 uint32_t InjectedOffsetNumber; /*!< Selects the offset number. 127 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. 128 Caution: Only one offset is allowed per channel. This parameter 129 overwrites the last setting. */ 130 131 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. 132 Offset value must be a positive number. 133 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this 134 parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 135 0x3FF, 0xFF or 0x3F respectively. 136 Note: This parameter must be modified when no conversion is on going 137 on both regular and injected groups (ADC disabled, or ADC enabled 138 without continuous mode or external trigger that could launch a 139 conversion). */ 140 141 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group 142 injected sequencer. 143 To use the injected group sequencer and convert several ranks, parameter 144 'ScanConvMode' must be enabled. 145 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 146 Caution: this setting impacts the entire injected group. Therefore, 147 call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on 148 injected group can impact the configuration of other channels previously 149 set. */ 150 151 FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected 152 is performed in Complete-sequence/Discontinuous-sequence 153 (main sequence subdivided in successive parts). 154 Discontinuous mode is used only if sequencer is enabled (parameter 155 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 156 Discontinuous mode can be enabled only if continuous mode is disabled. 157 This parameter can be set to ENABLE or DISABLE. 158 Note: This parameter must be modified when ADC is disabled (before ADC 159 start conversion or after ADC stop conversion). 160 Note: For injected group, discontinuous mode converts the sequence 161 channel by channel (discontinuous length fixed to 1 rank). 162 Caution: this setting impacts the entire injected group. Therefore, 163 call of HAL_ADCEx_InjectedConfigChannel() to 164 configure a channel on injected group can impact the 165 configuration of other channels previously set. */ 166 167 FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion 168 after regular one 169 This parameter can be set to ENABLE or DISABLE. 170 Note: To use Automatic injected conversion, discontinuous mode must 171 be disabled ('DiscontinuousConvMode' and 172 'InjectedDiscontinuousConvMode' set to DISABLE) 173 Note: To use Automatic injected conversion, injected group external 174 triggers must be disabled ('ExternalTrigInjecConv' set to 175 ADC_INJECTED_SOFTWARE_START) 176 Note: In case of DMA used with regular group: if DMA configured in 177 normal mode (single shot) JAUTO will be stopped upon DMA transfer 178 complete. 179 To maintain JAUTO always enabled, DMA must be configured in 180 circular mode. 181 Caution: this setting impacts the entire injected group. Therefore, 182 call of HAL_ADCEx_InjectedConfigChannel() to configure a channel 183 on injected group can impact the configuration of other channels 184 previously set. */ 185 186 FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. 187 This parameter can be set to ENABLE or DISABLE. 188 If context queue is enabled, injected sequencer&channels configurations 189 are queued on up to 2 contexts. If a 190 new injected context is set when queue is full, error is triggered by 191 interruption and through function 192 'HAL_ADCEx_InjectedQueueOverflowCallback'. 193 Caution: This feature request that the sequence is fully configured 194 before injected conversion start. 195 Therefore, configure channels with as many calls to 196 HAL_ADCEx_InjectedConfigChannel() as the 197 'InjectedNbrOfConversion' parameter. 198 Caution: this setting impacts the entire injected group. Therefore, 199 call of HAL_ADCEx_InjectedConfigChannel() to 200 configure a channel on injected group can impact the 201 configuration of other channels previously set. 202 Note: This parameter must be modified when ADC is disabled (before ADC 203 start conversion or after ADC stop conversion). */ 204 205 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of 206 injected group. 207 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled 208 and software trigger is used instead. 209 This parameter can be a value of 210 @ref ADC_injected_external_trigger_source. 211 Caution: this setting impacts the entire injected group. Therefore, 212 call of HAL_ADCEx_InjectedConfigChannel() to configure a channel 213 on injected group can impact the configuration of other channels 214 previously set. */ 215 216 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 217 This parameter can be a value of @ref ADC_injected_external_trigger_edge. 218 If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter 219 is discarded. 220 Caution: this setting impacts the entire injected group. Therefore, 221 call of HAL_ADCEx_InjectedConfigChannel() to 222 configure a channel on injected group can impact the 223 configuration of other channels previously set. */ 224 225 FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. 226 This parameter can be set to ENABLE or DISABLE. 227 Note: This parameter can be modified only if there is no 228 conversion is ongoing (both ADSTART and JADSTART cleared). */ 229 230 ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. 231 Caution: this setting overwrites the previous oversampling 232 configuration if oversampling already enabled. 233 Note: This parameter can be modified only if there is no 234 conversion is ongoing (both ADSTART and JADSTART cleared).*/ 235 } ADC_InjectionConfTypeDef; 236 237 #if defined(ADC_MULTIMODE_SUPPORT) 238 /** 239 * @brief Structure definition of ADC multimode 240 * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state 241 * (both Master and Slave ADCs). 242 * Both Master and Slave ADCs must be disabled. 243 */ 244 typedef struct 245 { 246 uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. 247 This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ 248 249 uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC: 250 selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel 251 (one DMA channel for both ADC, DMA of ADC master). 252 This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */ 253 254 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. 255 This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. 256 Delay range depends on selected resolution: 257 from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits, 258 from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */ 259 } ADC_MultiModeTypeDef; 260 #endif /* ADC_MULTIMODE_SUPPORT */ 261 262 /** 263 * @} 264 */ 265 266 /* Exported constants --------------------------------------------------------*/ 267 268 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants 269 * @{ 270 */ 271 272 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source 273 * @{ 274 */ 275 /* ADC group regular trigger sources for all ADC instances */ 276 #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< ADC group injected conversion 277 trigger software start */ 278 #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion 279 trigger from external peripheral: TIM1 TRGO. */ 280 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion 281 trigger from external peripheral: TIM1 TRGO2. */ 282 #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion 283 trigger from external peripheral: TIM1 channel 4 event (capture compare). */ 284 #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion 285 trigger from external peripheral: TIM2 TRGO. */ 286 #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion 287 trigger from external peripheral: TIM2 channel 1 event (capture compare). */ 288 #define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion 289 trigger from external peripheral: TIM3 TRGO. */ 290 #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion 291 trigger from external peripheral: TIM3 channel 1 event (capture compare). */ 292 #define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion 293 trigger from external peripheral: TIM3 channel 3 event (capture compare). */ 294 #define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion 295 trigger from external peripheral: TIM3 channel 4 event (capture compare). */ 296 #define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion 297 trigger from external peripheral: TIM4 TRGO. */ 298 #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion 299 trigger from external peripheral: TIM6 TRGO. */ 300 #define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion 301 trigger from external peripheral: TIM8 channel 4 event (capture compare). */ 302 #define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion 303 trigger from external peripheral: TIM8 TRGO. */ 304 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion 305 trigger from external peripheral: TIM8 TRGO2. */ 306 #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion 307 trigger from external peripheral: TIM15 TRGO. */ 308 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion 309 trigger from external peripheral: external interrupt line 15. */ 310 /** 311 * @} 312 */ 313 314 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) 315 * @{ 316 */ 317 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions trigger 318 disabled (SW start)*/ 319 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions trigger 320 polarity set to rising edge */ 321 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions trigger 322 polarity set to falling edge */ 323 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions trigger 324 polarity set to both rising and falling edges */ 325 /** 326 * @} 327 */ 328 329 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending 330 * @{ 331 */ 332 #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended */ 333 #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential */ 334 /** 335 * @} 336 */ 337 338 /** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number 339 * @{ 340 */ 341 #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected 342 ADC channel */ 343 #define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which 344 the offset programmed will be applied (independently of channel mapped 345 on ADC group regular or group injected) */ 346 #define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which 347 the offset programmed will be applied (independently of channel mapped 348 on ADC group regular or group injected) */ 349 #define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which 350 the offset programmed will be applied (independently of channel mapped 351 on ADC group regular or group injected) */ 352 #define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which 353 the offset programmed will be applied (independently of channel mapped 354 on ADC group regular or group injected) */ 355 /** 356 * @} 357 */ 358 359 /** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 360 * @{ 361 */ 362 #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ 363 #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ 364 #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ 365 #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ 366 /** 367 * @} 368 */ 369 370 #if defined(ADC_MULTIMODE_SUPPORT) 371 /** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode 372 * @{ 373 */ 374 #define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled 375 (ADC independent mode) */ 376 #define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular 377 simultaneous */ 378 #define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined 379 group regular interleaved */ 380 #define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group 381 injected simultaneous */ 382 #define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group 383 injected alternate trigger. Works only with external triggers (not internal 384 SW start) */ 385 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined 386 group regular simultaneous + group injected simultaneous */ 387 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined 388 group regular simultaneous + group injected alternate trigger */ 389 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined 390 group regular interleaved + group injected simultaneous */ 391 392 /** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution 393 * @{ 394 */ 395 #define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own 396 DMA channel */ 397 #define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, 398 DMA of ADC master) for 12 and 10 bits resolution */ 399 #define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, 400 DMA of ADC master) for 8 and 6 bits resolution */ 401 /** 402 * @} 403 */ 404 405 /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 406 * @{ 407 */ 408 #define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two 409 sampling phases: 1 ADC clock cycle */ 410 #define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two 411 sampling phases: 2 ADC clock cycles */ 412 #define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two 413 sampling phases: 3 ADC clock cycles */ 414 #define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two 415 sampling phases: 4 ADC clock cycles */ 416 #define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two 417 sampling phases: 5 ADC clock cycles */ 418 #define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two 419 sampling phases: 6 ADC clock cycles */ 420 #define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two 421 sampling phases: 7 ADC clock cycles */ 422 #define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two 423 sampling phases: 8 ADC clock cycles */ 424 #define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two 425 sampling phases: 9 ADC clock cycles */ 426 #define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two 427 sampling phases: 10 ADC clock cycles */ 428 #define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two 429 sampling phases: 11 ADC clock cycles */ 430 #define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two 431 sampling phases: 12 ADC clock cycles */ 432 /** 433 * @} 434 */ 435 436 /** 437 * @} 438 */ 439 #endif /* ADC_MULTIMODE_SUPPORT */ 440 441 /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups 442 * @{ 443 */ 444 #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on 445 all STM32 devices) */ 446 #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on 447 all STM32 devices) */ 448 #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ 449 /** 450 * @} 451 */ 452 453 /** @defgroup ADC_CFGR_fields ADCx CFGR fields 454 * @{ 455 */ 456 #if defined(DFSDM1_Channel0) 457 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 458 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 459 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 460 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 461 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 462 ADC_CFGR_RES | ADC_CFGR_DFSDMCFG | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) 463 #else 464 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 465 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 466 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 467 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 468 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 469 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) 470 #endif /* ADC_CFGR_DFSDMCFG */ 471 /** 472 * @} 473 */ 474 475 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields 476 * @{ 477 */ 478 #if defined(ADC_SMPR1_SMPPLUS) 479 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 480 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 481 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 482 ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS) 483 #else 484 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 485 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 486 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 487 ADC_SMPR1_SMP0) 488 #endif /* ADC_SMPR1_SMPPLUS */ 489 /** 490 * @} 491 */ 492 493 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 494 * @{ 495 */ 496 /* ADC_CFGR fields of parameters that can be updated when no conversion 497 (neither regular nor injected) is on-going */ 498 #if defined(DFSDM1_Channel0) 499 #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY | ADC_CFGR_DFSDMCFG)) 500 #else 501 #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY)) 502 #endif /* ADC_CFGR_DFSDMCFG */ 503 /** 504 * @} 505 */ 506 507 #if defined(DFSDM1_Channel0) 508 /** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data 509 * @{ 510 */ 511 #define ADC_DFSDM_MODE_DISABLE (0x00000000UL) /*!< ADC conversions are not transferred 512 by DFSDM. */ 513 #define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transferred 514 to DFSDM for post processing. The ADC conversion data format must be 16-bit 515 signed and right aligned, refer to reference manual. 516 DFSDM transfer cannot be used if DMA transfer is enabled. */ 517 /** 518 * @} 519 */ 520 #endif /* ADC_CFGR_DFSDMCFG */ 521 522 /** 523 * @} 524 */ 525 526 /* Exported macros -----------------------------------------------------------*/ 527 528 #if defined(ADC_MULTIMODE_SUPPORT) 529 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros 530 * @{ 531 */ 532 533 /** @brief Force ADC instance in multimode mode independent (multimode disable). 534 * @note This macro must be used only in case of transition from multimode 535 * to mode independent and in case of unknown previous state, 536 * to ensure ADC configuration is in mode independent. 537 * @note Standard way of multimode configuration change is done from 538 * HAL ADC handle of ADC master using function 539 * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". 540 * Usage of this macro is not the Standard way of multimode 541 * configuration and can lead to have HAL ADC handles status 542 * misaligned. Usage of this macro must be limited to cases 543 * mentioned above. 544 * @param __HANDLE__ ADC handle. 545 * @retval None 546 */ 547 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ 548 LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) 549 550 /** 551 * @} 552 */ 553 #endif /* ADC_MULTIMODE_SUPPORT */ 554 555 /* Private macros ------------------------------------------------------------*/ 556 557 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros 558 * @{ 559 */ 560 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 561 /* code of final user. */ 562 563 /** 564 * @brief Test if conversion trigger of injected group is software start 565 * or external trigger. 566 * @param __HANDLE__ ADC handle. 567 * @retval SET (software start) or RESET (external trigger). 568 */ 569 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 570 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) 571 572 /** 573 * @brief Check whether or not ADC is independent. 574 * @param __HANDLE__ ADC handle. 575 * @note When multimode feature is not available, the macro always returns SET. 576 * @retval SET (ADC is independent) or RESET (ADC is not). 577 */ 578 #define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) 579 580 /** 581 * @brief Set the selected injected Channel rank. 582 * @param __CHANNELNB__ Channel number. 583 * @param __RANKNB__ Rank number. 584 * @retval None 585 */ 586 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) \ 587 ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \ 588 << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) 589 590 /** 591 * @brief Configure ADC injected context queue 592 * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. 593 * @retval None 594 */ 595 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) \ 596 ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) 597 598 /** 599 * @brief Configure ADC discontinuous conversion mode for injected group 600 * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. 601 * @retval None 602 */ 603 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) \ 604 ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) 605 606 /** 607 * @brief Configure ADC discontinuous conversion mode for regular group 608 * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. 609 * @retval None 610 */ 611 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) \ 612 ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) 613 614 /** 615 * @brief Configure the number of discontinuous conversions for regular group. 616 * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. 617 * @retval None 618 */ 619 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) \ 620 (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) 621 622 /** 623 * @brief Configure the ADC auto delay mode. 624 * @param __AUTOWAIT__ Auto delay bit enable or disable. 625 * @retval None 626 */ 627 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) 628 629 /** 630 * @brief Configure ADC continuous conversion mode. 631 * @param __CONTINUOUS_MODE__ Continuous mode. 632 * @retval None 633 */ 634 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) 635 636 /** 637 * @brief Configure the ADC DMA continuous request. 638 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 639 * @retval None 640 */ 641 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos) 642 643 #if defined(ADC_MULTIMODE_SUPPORT) 644 /** 645 * @brief Configure the ADC DMA continuous request for ADC multimode. 646 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 647 * @retval None 648 */ 649 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) 650 #endif /* ADC_MULTIMODE_SUPPORT */ 651 652 /** 653 * @brief Shift the offset with respect to the selected ADC resolution. 654 * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. 655 * If resolution 12 bits, no shift. 656 * If resolution 10 bits, shift of 2 ranks on the left. 657 * If resolution 8 bits, shift of 4 ranks on the left. 658 * If resolution 6 bits, shift of 6 ranks on the left. 659 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 660 * @param __HANDLE__ ADC handle 661 * @param __OFFSET__ Value to be shifted 662 * @retval None 663 */ 664 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 665 ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) 666 667 /** 668 * @brief Shift the AWD1 threshold with respect to the selected ADC resolution. 669 * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. 670 * If resolution 12 bits, no shift. 671 * If resolution 10 bits, shift of 2 ranks on the left. 672 * If resolution 8 bits, shift of 4 ranks on the left. 673 * If resolution 6 bits, shift of 6 ranks on the left. 674 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 675 * @param __HANDLE__ ADC handle 676 * @param __THRESHOLD__ Value to be shifted 677 * @retval None 678 */ 679 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 680 ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) 681 682 /** 683 * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution. 684 * @note Thresholds have to be left-aligned on bit 7. 685 * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded). 686 * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded). 687 * If resolution 8 bits, no shift. 688 * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0). 689 * @param __HANDLE__ ADC handle 690 * @param __THRESHOLD__ Value to be shifted 691 * @retval None 692 */ 693 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 694 ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \ 695 ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ 696 ((__THRESHOLD__) << 2UL) \ 697 ) 698 699 /** 700 * @brief Clear Common Control Register. 701 * @param __HANDLE__ ADC handle. 702 * @retval None 703 */ 704 #if defined(ADC_MULTIMODE_SUPPORT) 705 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ 706 ADC_CCR_CKMODE | \ 707 ADC_CCR_PRESC | \ 708 ADC_CCR_VBATEN | \ 709 ADC_CCR_TSEN | \ 710 ADC_CCR_VREFEN | \ 711 ADC_CCR_MDMA | \ 712 ADC_CCR_DMACFG | \ 713 ADC_CCR_DELAY | \ 714 ADC_CCR_DUAL) 715 #else 716 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ 717 ADC_CCR_CKMODE | \ 718 ADC_CCR_PRESC | \ 719 ADC_CCR_VBATEN | \ 720 ADC_CCR_TSEN | \ 721 ADC_CCR_VREFEN) 722 723 #endif /* ADC_MULTIMODE_SUPPORT */ 724 725 /** 726 * @brief Set handle instance of the ADC slave associated to the ADC master. 727 * @param __HANDLE_MASTER__ ADC master handle. 728 * @param __HANDLE_SLAVE__ ADC slave handle. 729 * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set 730 * to NULL. 731 * @retval None 732 */ 733 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ 734 ( ((__HANDLE_MASTER__)->Instance == ADC1) ? \ 735 ((__HANDLE_SLAVE__)->Instance = ADC2) \ 736 : \ 737 ((__HANDLE_SLAVE__)->Instance = NULL) \ 738 ) 739 740 741 /** 742 * @brief Verify the ADC instance connected to the temperature sensor. 743 * @param __HANDLE__ ADC handle. 744 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 745 */ 746 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 747 748 /** 749 * @brief Verify the ADC instance connected to the battery voltage VBAT. 750 * @param __HANDLE__ ADC handle. 751 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 752 */ 753 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 754 755 /** 756 * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. 757 * @param __HANDLE__ ADC handle. 758 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 759 */ 760 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 761 762 /** 763 * @brief Verify the length of scheduled injected conversions group. 764 * @param __LENGTH__ number of programmed conversions. 765 * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) 766 * or RESET (__LENGTH__ is null or too large) 767 */ 768 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) 769 770 /** 771 * @brief Calibration factor size verification (7 bits maximum). 772 * @param __CALIBRATION_FACTOR__ Calibration factor value. 773 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) 774 */ 775 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) 776 777 778 /** 779 * @brief Verify the ADC channel setting. 780 * @param __HANDLE__ ADC handle. 781 * @param __CHANNEL__ programmed ADC channel. 782 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 783 */ 784 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ 785 (((__CHANNEL__) == ADC_CHANNEL_0) || \ 786 ((__CHANNEL__) == ADC_CHANNEL_1) || \ 787 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 788 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 789 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 790 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 791 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 792 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 793 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 794 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 795 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 796 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 797 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 798 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 799 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 800 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 801 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 802 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 803 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 804 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 805 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 806 ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \ 807 ((((__HANDLE__)->Instance) == ADC2) && \ 808 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 809 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 810 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 811 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 812 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 813 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 814 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 815 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 816 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 817 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 818 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 819 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 820 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 821 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 822 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 823 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 824 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 825 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 826 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2) || \ 827 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2)))) 828 829 /** 830 * @brief Verify the ADC channel setting in differential mode. 831 * @param __HANDLE__ ADC handle. 832 * @param __CHANNEL__ programmed ADC channel. 833 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 834 */ 835 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 836 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 837 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 838 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 839 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 840 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 841 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 842 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 843 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 844 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 845 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 846 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 847 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 848 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 849 ((__CHANNEL__) == ADC_CHANNEL_15) ) 850 851 /** 852 * @brief Verify the ADC single-ended input or differential mode setting. 853 * @param __SING_DIFF__ programmed channel setting. 854 * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) 855 */ 856 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ 857 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) 858 859 /** 860 * @brief Verify the ADC offset management setting. 861 * @param __OFFSET_NUMBER__ ADC offset management. 862 * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) 863 */ 864 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ 865 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ 866 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ 867 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ 868 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) 869 870 /** 871 * @brief Verify the ADC injected channel setting. 872 * @param __CHANNEL__ programmed ADC injected channel. 873 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 874 */ 875 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ 876 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ 877 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ 878 ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) 879 880 /** 881 * @brief Verify the ADC injected conversions external trigger. 882 * @param __HANDLE__ ADC handle. 883 * @param __INJTRIG__ programmed ADC injected conversions external trigger. 884 * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) 885 */ 886 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 887 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 888 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 889 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 890 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 891 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 892 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 893 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 894 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 895 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 896 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 897 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 898 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 899 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 900 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 901 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 902 ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) 903 904 /** 905 * @brief Verify the ADC edge trigger setting for injected group. 906 * @param __EDGE__ programmed ADC edge trigger setting. 907 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 908 */ 909 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 910 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 911 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 912 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 913 914 #if defined(ADC_MULTIMODE_SUPPORT) 915 /** 916 * @brief Verify the ADC multimode setting. 917 * @param __MODE__ programmed ADC multimode setting. 918 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 919 */ 920 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ 921 ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ 922 ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ 923 ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ 924 ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ 925 ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ 926 ((__MODE__) == ADC_DUALMODE_INTERL) || \ 927 ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) 928 929 /** 930 * @brief Verify the ADC multimode DMA access setting. 931 * @param __MODE__ programmed ADC multimode DMA access setting. 932 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 933 */ 934 #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \ 935 ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \ 936 ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) ) 937 938 /** 939 * @brief Verify the ADC multimode delay setting. 940 * @param __DELAY__ programmed ADC multimode delay setting. 941 * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) 942 */ 943 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ 944 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ 945 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ 946 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ 947 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 948 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 949 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 950 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ 951 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ 952 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ 953 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ 954 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) ) 955 #endif /* ADC_MULTIMODE_SUPPORT */ 956 957 /** 958 * @brief Verify the ADC analog watchdog setting. 959 * @param __WATCHDOG__ programmed ADC analog watchdog setting. 960 * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) 961 */ 962 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ 963 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ 964 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) 965 966 /** 967 * @brief Verify the ADC analog watchdog mode setting. 968 * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. 969 * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) 970 */ 971 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ 972 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 973 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 974 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 975 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 976 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 977 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 978 979 /** 980 * @brief Verify the ADC conversion (regular or injected or both). 981 * @param __CONVERSION__ ADC conversion group. 982 * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) 983 */ 984 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ 985 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ 986 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) 987 988 /** 989 * @brief Verify the ADC event type. 990 * @param __EVENT__ ADC event. 991 * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) 992 */ 993 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ 994 ((__EVENT__) == ADC_AWD_EVENT) || \ 995 ((__EVENT__) == ADC_AWD2_EVENT) || \ 996 ((__EVENT__) == ADC_AWD3_EVENT) || \ 997 ((__EVENT__) == ADC_OVR_EVENT) || \ 998 ((__EVENT__) == ADC_JQOVF_EVENT) ) 999 1000 /** 1001 * @brief Verify the ADC oversampling ratio. 1002 * @param __RATIO__ programmed ADC oversampling ratio. 1003 * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) 1004 */ 1005 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ 1006 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ 1007 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ 1008 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ 1009 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ 1010 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ 1011 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ 1012 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) 1013 1014 /** 1015 * @brief Verify the ADC oversampling shift. 1016 * @param __SHIFT__ programmed ADC oversampling shift. 1017 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) 1018 */ 1019 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ 1020 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ 1021 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ 1022 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ 1023 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ 1024 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ 1025 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ 1026 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ 1027 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) 1028 1029 /** 1030 * @brief Verify the ADC oversampling triggered mode. 1031 * @param __MODE__ programmed ADC oversampling triggered mode. 1032 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1033 */ 1034 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 1035 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 1036 1037 /** 1038 * @brief Verify the ADC oversampling regular conversion resumed or continued mode. 1039 * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. 1040 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1041 */ 1042 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ 1043 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) 1044 1045 /** 1046 * @brief Verify the DFSDM mode configuration. 1047 * @param __HANDLE__ ADC handle. 1048 * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For 1049 * this reason, the input parameter is the ADC handle and not the configuration parameter 1050 * directly. 1051 * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) 1052 */ 1053 #if defined(DFSDM1_Channel0) 1054 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \ 1055 ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) ) 1056 #else 1057 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) 1058 #endif /* ADC_CFGR_DFSDMCFG */ 1059 1060 /** 1061 * @brief Return the DFSDM configuration mode. 1062 * @param __HANDLE__ ADC handle. 1063 * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). 1064 * For this reason, the input parameter is the ADC handle and not the configuration parameter 1065 * directly. 1066 * @retval DFSDM configuration mode 1067 */ 1068 #if defined(DFSDM1_Channel0) 1069 #define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig) 1070 #else 1071 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) 1072 #endif /* ADC_CFGR_DFSDMCFG */ 1073 1074 /** 1075 * @} 1076 */ 1077 1078 1079 /* Exported functions --------------------------------------------------------*/ 1080 /** @addtogroup ADCEx_Exported_Functions 1081 * @{ 1082 */ 1083 1084 /** @addtogroup ADCEx_Exported_Functions_Group1 1085 * @{ 1086 */ 1087 /* IO operation functions *****************************************************/ 1088 1089 /* ADC calibration */ 1090 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 1091 uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 1092 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, 1093 uint32_t CalibrationFactor); 1094 1095 /* Blocking mode: Polling */ 1096 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); 1097 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); 1098 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1099 1100 /* Non-blocking mode: Interruption */ 1101 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); 1102 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); 1103 1104 #if defined(ADC_MULTIMODE_SUPPORT) 1105 /* ADC multimode */ 1106 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1107 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1108 uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc); 1109 #endif /* ADC_MULTIMODE_SUPPORT */ 1110 1111 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1112 uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank); 1113 1114 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 1115 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); 1116 void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); 1117 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); 1118 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); 1119 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); 1120 1121 /* ADC group regular conversions stop */ 1122 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); 1123 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); 1124 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); 1125 #if defined(ADC_MULTIMODE_SUPPORT) 1126 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1127 #endif /* ADC_MULTIMODE_SUPPORT */ 1128 1129 /** 1130 * @} 1131 */ 1132 1133 /** @addtogroup ADCEx_Exported_Functions_Group2 1134 * @{ 1135 */ 1136 /* Peripheral Control functions ***********************************************/ 1137 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, 1138 const ADC_InjectionConfTypeDef *pConfigInjected); 1139 #if defined(ADC_MULTIMODE_SUPPORT) 1140 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, 1141 const ADC_MultiModeTypeDef *pMultimode); 1142 #endif /* ADC_MULTIMODE_SUPPORT */ 1143 1144 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); 1145 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); 1146 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); 1147 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); 1148 1149 /** 1150 * @} 1151 */ 1152 1153 /** 1154 * @} 1155 */ 1156 1157 /** 1158 * @} 1159 */ 1160 1161 /** 1162 * @} 1163 */ 1164 1165 #ifdef __cplusplus 1166 } 1167 #endif 1168 1169 #endif /* STM32L5xx_HAL_ADC_EX_H */ 1170
