1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L5xx_HAL_ADC_H 21 #define STM32L5xx_HAL_ADC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l5xx_hal_def.h" 29 30 /* Include low level driver */ 31 #include "stm32l5xx_ll_adc.h" 32 33 /** @addtogroup STM32L5xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup ADC 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup ADC_Exported_Types ADC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief ADC group regular oversampling structure definition 48 */ 49 typedef struct 50 { 51 uint32_t Ratio; /*!< Configures the oversampling ratio. 52 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 53 54 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 55 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 56 57 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 58 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ 59 60 uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. 61 The oversampling is either temporary stopped or reset upon an injected 62 sequence interruption. 63 If oversampling is enabled on both regular and injected groups, this 64 parameter is discarded and forced to setting 65 "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed 66 during injection sequence). 67 This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ 68 69 } ADC_OversamplingTypeDef; 70 71 /** 72 * @brief Structure definition of ADC instance and ADC group regular. 73 * @note Parameters of this structure are shared within 2 scopes: 74 * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, 75 * ScanConvMode, EOCSelection, LowPowerAutoWait. 76 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, 77 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. 78 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 79 * ADC state can be either: 80 * - For all parameters: ADC disabled 81 * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled 82 * without conversion on going on group regular. 83 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going 84 * on groups regular and injected. 85 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 86 * without error reporting (as it can be the expected behavior in case of intended action to update another 87 * parameter (which fulfills the ADC state condition) on the fly). 88 */ 89 typedef struct 90 { 91 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous 92 clock derived from system clock or PLL (Refer to reference manual for list of 93 clocks available)) and clock prescaler. 94 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. 95 Note: The ADC clock configuration is common to all ADC instances. 96 Note: In case of usage of channels on injected group, ADC frequency should be 97 lower than AHB clock frequency /4 for resolution 12 or 10 bits, 98 AHB clock frequency /3 for resolution 8 bits, 99 AHB clock frequency /2 for resolution 6 bits. 100 Note: In case of synchronous clock mode based on HCLK/1, the configuration must 101 be enabled only if the system clock has a 50% duty clock cycle (APB 102 prescaler configured inside RCC must be bypassed and PCLK clock must have 103 50% duty cycle). Refer to reference manual for details. 104 Note: In case of usage of asynchronous clock, the selected clock must be 105 preliminarily enabled at RCC top level. 106 Note: This parameter can be modified only if all ADC instances are disabled. */ 107 108 uint32_t Resolution; /*!< Configure the ADC resolution. 109 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ 110 111 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). 112 Refer to reference manual for alignments formats versus resolutions. 113 This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ 114 115 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. 116 This parameter can be associated to parameter 'DiscontinuousConvMode' to have 117 main sequence subdivided in successive parts. 118 If disabled: Conversion is performed in single mode (one channel converted, the 119 one defined in rank 1). Parameters 'NbrOfConversion' and 120 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 121 If enabled: Conversions are performed in sequence mode (multiple ranks defined 122 by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each 123 channel in sequencer). Scan direction is upward: from rank 1 to 124 rank 'n'. 125 This parameter can be a value of @ref ADC_Scan_mode */ 126 127 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and 128 interruption: end of unitary conversion or end of sequence conversions. 129 This parameter can be a value of @ref ADC_EOCSelection. */ 130 131 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the 132 previous conversion (for ADC group regular) or previous sequence (for ADC group 133 injected) has been retrieved by user software, using function HAL_ADC_GetValue() 134 or HAL_ADCEx_InjectedGetValue(). 135 This feature automatically adapts the frequency of ADC conversions triggers to 136 the speed of the system that reads the data. Moreover, this avoids risk of 137 overrun for low frequency applications. 138 This parameter can be set to ENABLE or DISABLE. 139 Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), 140 HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC 141 flag (by CPU to free the IRQ pending event or by DMA). 142 Auto wait will work but fort a very short time, discarding its intended 143 benefit (except specific case of high load of CPU or DMA transfers which 144 can justify usage of auto wait). 145 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, 146 when ADC conversion data is needed: 147 use HAL_ADC_PollForConversion() to ensure that conversion is completed and 148 HAL_ADC_GetValue() to retrieve conversion result and trig another 149 conversion start. (in case of usage of ADC group injected, use the 150 equivalent functions HAL_ADCExInjected_Start(), 151 HAL_ADCEx_InjectedGetValue(), ...). */ 152 153 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) 154 or continuous mode for ADC group regular, after the first ADC conversion 155 start trigger occurred (software start or external trigger). This parameter 156 can be set to ENABLE or DISABLE. */ 157 158 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group 159 sequencer. 160 This parameter is dependent on ScanConvMode: 161 - sequencer configured to fully configurable: 162 Number of ranks in the scan sequence is configurable using this parameter. 163 Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to 164 parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'. 165 Afterwards, when all needed sequencer ranks are set, parameter 166 'NbrOfConversion' can be updated without modifying configuration of 167 sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded). 168 - sequencer configured to not fully configurable: 169 Number of ranks in the scan sequence is defined by number of channels set in 170 the sequence. This parameter is discarded. 171 This parameter must be a number between Min_Data = 1 and Max_Data = 8. 172 Note: This parameter must be modified when no conversion is on going on regular 173 group (ADC disabled, or ADC enabled without continuous mode or external 174 trigger that could launch a conversion). */ 175 176 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed 177 in Complete-sequence/Discontinuous-sequence (main sequence subdivided in 178 successive parts). 179 Discontinuous mode is used only if sequencer is enabled (parameter 180 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 181 Discontinuous mode can be enabled only if continuous mode is disabled. 182 If continuous mode is enabled, this parameter setting is discarded. 183 This parameter can be set to ENABLE or DISABLE. 184 Note: On this STM32 series, ADC group regular number of discontinuous 185 ranks increment is fixed to one-by-one. */ 186 187 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence 188 of ADC group regular (parameter NbrOfConversion) will be subdivided. 189 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 190 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 191 192 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion 193 start. 194 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger 195 is used instead. 196 This parameter can be a value of @ref ADC_regular_external_trigger_source. 197 Caution: external trigger source is common to all ADC instances. */ 198 199 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start 200 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 201 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 202 203 FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA 204 transfer stops when number of conversions is reached) or in continuous 205 mode (DMA transfer unlimited, whatever number of conversions). 206 This parameter can be set to ENABLE or DISABLE. 207 Note: In continuous mode, DMA must be configured in circular mode. 208 Otherwise an overrun will be triggered when DMA buffer maximum 209 pointer is reached. */ 210 211 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 212 This parameter applies to ADC group regular only. 213 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. 214 Note: In case of overrun set to data preserved and usage with programming model 215 with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of 216 conversion flags, this induces the release of the preserved data. If 217 needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), 218 placed in user program code (called before end of conversion flags clear) 219 Note: Error reporting with respect to the conversion mode: 220 - Usage with ADC conversion by polling for event or interruption: Error is 221 reported only if overrun is set to data preserved. If overrun is set to 222 data overwritten, user can willingly not read all the converted data, 223 this is not considered as an erroneous case. 224 - Usage with ADC conversion by DMA: Error is reported whatever overrun 225 setting (DMA is expected to process all data from data register). */ 226 227 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 228 This parameter can be set to ENABLE or DISABLE. 229 Note: This parameter can be modified only if there is no conversion is 230 ongoing on ADC groups regular and injected */ 231 232 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. 233 Caution: this setting overwrites the previous oversampling configuration 234 if oversampling is already enabled. */ 235 236 #if defined(DFSDM1_Channel0) 237 uint32_t DFSDMConfig; /*!< Specify whether ADC conversion data is sent directly to DFSDM. 238 This parameter can be a value of @ref ADC_HAL_EC_REG_DFSDM_TRANSFER. 239 Note: This parameter can be modified only if there is no conversion is ongoing 240 (both ADSTART and JADSTART cleared). */ 241 242 #endif /* ADC_CFGR_DFSDMCFG */ 243 } ADC_InitTypeDef; 244 245 /** 246 * @brief Structure definition of ADC channel for regular group 247 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 248 * ADC state can be either: 249 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') 250 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion 251 * on going on regular group. 252 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on 253 * regular and injected groups. 254 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 255 * without error reporting (as it can be the expected behavior in case of intended action to update another 256 * parameter (which fulfills the ADC state condition) on the fly). 257 */ 258 typedef struct 259 { 260 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 261 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 262 Note: Depending on devices and ADC instances, some channels may not be available 263 on device package pins. Refer to device datasheet for channels 264 availability. */ 265 266 uint32_t Rank; /*!< Specify the rank in the regular group sequencer. 267 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS 268 Note: to disable a channel or change order of conversion sequencer, rank 269 containing a previous channel setting can be overwritten by the new channel 270 setting (or parameter number of conversions adjusted) */ 271 272 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 273 Unit: ADC clock cycles 274 Conversion time is the addition of sampling time and processing time 275 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 276 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 277 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 278 Caution: This parameter applies to a channel that can be used into regular 279 and/or injected group. It overwrites the last setting. 280 Note: In case of usage of internal measurement channels (VrefInt, Vbat, ...), 281 sampling time constraints must be respected (sampling time can be adjusted 282 in function of ADC clock frequency and sampling time setting). 283 Refer to device datasheet for timings values. */ 284 285 uint32_t SingleDiff; /*!< Select single-ended or differential input. 286 In differential mode: Differential measurement is carried out between the 287 selected channel 'i' (positive input) and channel 'i+1' (negative input). 288 Only channel 'i' has to be configured, channel 'i+1' is configured automatically 289 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING 290 Caution: This parameter applies to a channel that can be used in a regular 291 and/or injected group. 292 It overwrites the last setting. 293 Note: Refer to Reference Manual to ensure the selected channel is available in 294 differential mode. 295 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is 296 not usable separately. 297 Note: This parameter must be modified when ADC is disabled (before ADC start 298 conversion or after ADC stop conversion). 299 If ADC is enabled, this parameter setting is bypassed without error 300 reporting (as it can be the expected behavior in case of another parameter 301 update on the fly) */ 302 303 uint32_t OffsetNumber; /*!< Select the offset number 304 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB 305 Caution: Only one offset is allowed per channel. This parameter overwrites the 306 last setting. */ 307 308 uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data. 309 Offset value must be a positive number. 310 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter 311 must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 312 0x3FF, 0xFF or 0x3F respectively. 313 Note: This parameter must be modified when no conversion is on going on both 314 regular and injected groups (ADC disabled, or ADC enabled without 315 continuous mode or external trigger that could launch a conversion). */ 316 317 } ADC_ChannelConfTypeDef; 318 319 /** 320 * @brief Structure definition of ADC analog watchdog 321 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 322 * ADC state can be either: 323 * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and 324 injected. 325 */ 326 typedef struct 327 { 328 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. 329 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels 330 by setting parameter 'WatchdogMode') 331 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls 332 of 'HAL_ADC_AnalogWDGConfig()' for each channel) 333 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ 334 335 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. 336 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all 337 channels, ADC groups regular and-or injected. 338 For Analog Watchdog 2 and 3: Several channels can be monitored by applying 339 successively the AWD init structure. Channels on ADC 340 group regular and injected are not differentiated: Set 341 value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 342 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor 343 all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no 344 channel. 345 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 346 347 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 348 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' 349 is configured on single channel (only 1 channel can be 350 monitored). 351 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, 352 call successively the function HAL_ADC_AnalogWDGConfig() 353 for each channel to be added (or removed with value 354 'ADC_ANALOGWATCHDOG_NONE'). 355 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ 356 357 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 358 This parameter can be set to ENABLE or DISABLE */ 359 360 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. 361 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a 362 number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F 363 respectively. 364 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC 365 resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 366 LSB are ignored. 367 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 368 impacted: the comparison of analog watchdog thresholds is done on 369 oversampling final computation (after ratio and shift application): 370 ADC data register bitfield [15:4] (12 most significant bits). */ 371 372 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 373 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a 374 number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F 375 respectively. 376 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC 377 resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 378 LSB are ignored. 379 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 380 impacted: the comparison of analog watchdog thresholds is done on 381 oversampling final computation (after ratio and shift application): 382 ADC data register bitfield [15:4] (12 most significant bits).*/ 383 } ADC_AnalogWDGConfTypeDef; 384 385 /** 386 * @brief ADC group injected contexts queue configuration 387 * @note Structure intended to be used only through structure "ADC_HandleTypeDef" 388 */ 389 typedef struct 390 { 391 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each 392 HAL_ADCEx_InjectedConfigChannel() call to finally initialize 393 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ 394 395 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ 396 } ADC_InjectionConfigTypeDef; 397 398 /** @defgroup ADC_States ADC States 399 * @{ 400 */ 401 402 /** 403 * @brief HAL ADC state machine: ADC states definition (bitfields) 404 * @note ADC state machine is managed by bitfields, state must be compared 405 * with bit by bit. 406 * For example: 407 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " 408 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " 409 */ 410 /* States of ADC global scope */ 411 #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ 412 #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ 413 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, 414 calibration, ...) */ 415 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ 416 417 /* States of ADC errors */ 418 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ 419 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ 420 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ 421 422 /* States of ADC group regular */ 423 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur 424 (either by continuous mode, external trigger, low power 425 auto power-on (if feature available), multimode ADC master 426 control (if feature available)) */ 427 #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ 428 #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ 429 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag 430 raised */ 431 432 /* States of ADC group injected */ 433 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur 434 (either by auto-injection mode, external trigger, low 435 power auto power-on (if feature available), multimode 436 ADC master control (if feature available)) */ 437 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ 438 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ 439 440 /* States of ADC analog watchdogs */ 441 #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 442 #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ 443 #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ 444 445 /* States of ADC multi-mode */ 446 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC 447 master (when feature available) */ 448 449 /** 450 * @} 451 */ 452 453 /** 454 * @brief ADC handle Structure definition 455 */ 456 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 457 typedef struct __ADC_HandleTypeDef 458 #else 459 typedef struct 460 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 461 { 462 ADC_TypeDef *Instance; /*!< Register base address */ 463 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular 464 conversions setting */ 465 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 466 HAL_LockTypeDef Lock; /*!< ADC locking object */ 467 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 468 __IO uint32_t ErrorCode; /*!< ADC Error code */ 469 ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up 470 structure */ 471 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 472 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 473 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer 474 callback */ 475 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 476 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 477 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete 478 callback */ 479 void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue 480 overflow callback */ 481 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ 482 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ 483 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ 484 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 485 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 486 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 487 } ADC_HandleTypeDef; 488 489 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 490 /** 491 * @brief HAL ADC Callback ID enumeration definition 492 */ 493 typedef enum 494 { 495 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 496 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 497 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 498 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 499 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 500 HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ 501 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ 502 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ 503 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ 504 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 505 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 506 } HAL_ADC_CallbackIDTypeDef; 507 508 /** 509 * @brief HAL ADC Callback pointer definition 510 */ 511 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 512 513 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 514 515 /** 516 * @} 517 */ 518 519 520 /* Exported constants --------------------------------------------------------*/ 521 522 /** @defgroup ADC_Exported_Constants ADC Exported Constants 523 * @{ 524 */ 525 526 /** @defgroup ADC_Error_Code ADC Error Code 527 * @{ 528 */ 529 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 530 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, 531 enable/disable, erroneous state, ...) */ 532 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 533 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 534 #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ 535 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 536 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 537 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 538 /** 539 * @} 540 */ 541 542 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 543 * @{ 544 */ 545 546 #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock 547 without prescaler */ 548 #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock 549 with prescaler division by 2 */ 550 #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock 551 with prescaler division by 4 */ 552 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without 553 prescaler */ 554 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler 555 division by 2 */ 556 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler 557 division by 4 */ 558 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler 559 division by 6 */ 560 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler 561 division by 8 */ 562 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler 563 division by 10 */ 564 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler 565 division by 12 */ 566 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler 567 division by 16 */ 568 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler 569 division by 32 */ 570 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler 571 division by 64 */ 572 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler 573 division by 128 */ 574 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler 575 division by 256 */ 576 /** 577 * @} 578 */ 579 580 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution 581 * @{ 582 */ 583 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ 584 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ 585 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ 586 #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ 587 /** 588 * @} 589 */ 590 591 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment 592 * @{ 593 */ 594 #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned 595 (alignment on data register LSB bit 0)*/ 596 #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned 597 (alignment on data register MSB bit 15)*/ 598 /** 599 * @} 600 */ 601 602 /** @defgroup ADC_Scan_mode ADC sequencer scan mode 603 * @{ 604 */ 605 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ 606 #define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ 607 /** 608 * @} 609 */ 610 611 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source 612 * @{ 613 */ 614 /* ADC group regular trigger sources for all ADC instances */ 615 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion 616 trigger software start */ 617 #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion 618 trigger from external peripheral: TIM1 TRGO. */ 619 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion 620 trigger from external peripheral: TIM1 TRGO2. */ 621 #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion 622 trigger from external peripheral: TIM1 channel 1 event (capture compare). */ 623 #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion 624 trigger from external peripheral: TIM1 channel 2 event (capture compare). */ 625 #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion 626 trigger from external peripheral: TIM1 channel 3 event (capture compare). */ 627 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion 628 trigger from external peripheral: TIM2 TRGO. */ 629 #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion 630 trigger from external peripheral: TIM2 channel 2 event (capture compare). */ 631 #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion 632 trigger from external peripheral: TIM3 TRGO. */ 633 #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion 634 trigger from external peripheral: TIM3 channel 4 event (capture compare). */ 635 #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion 636 trigger from external peripheral: TIM4 TRGO. */ 637 #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion 638 trigger from external peripheral: TIM4 channel 4 event (capture compare). */ 639 #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion 640 trigger from external peripheral: TIM6 TRGO. */ 641 #define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion 642 trigger from external peripheral: TIM8 TRGO. */ 643 #define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion 644 trigger from external peripheral: TIM8 TRGO2. */ 645 #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion 646 trigger from external peripheral: TIM15 TRGO. */ 647 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion 648 trigger from external peripheral: external interrupt line 11. */ 649 /** 650 * @} 651 */ 652 653 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) 654 * @{ 655 */ 656 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger 657 disabled (SW start)*/ 658 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion 659 trigger polarity set to rising edge */ 660 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion 661 trigger polarity set to falling edge */ 662 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion 663 trigger polarity set to both rising and falling edges */ 664 /** 665 * @} 666 */ 667 668 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions 669 * @{ 670 */ 671 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ 672 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ 673 /** 674 * @} 675 */ 676 677 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 678 * @{ 679 */ 680 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case 681 of overrun: data preserved */ 682 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case 683 of overrun: data overwritten */ 684 /** 685 * @} 686 */ 687 688 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 689 * @{ 690 */ 691 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 692 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 693 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 694 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 695 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 696 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 697 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 698 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 699 #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ 700 #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ 701 #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ 702 #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ 703 #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ 704 #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ 705 #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ 706 #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ 707 /** 708 * @} 709 */ 710 711 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 712 * @{ 713 */ 714 #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */ 715 #define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */ 716 #define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ 717 #define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */ 718 #define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */ 719 #define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */ 720 #define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */ 721 #define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */ 722 #define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 723 ADC clock cycles. If selected, this sampling time replaces sampling time 724 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */ 725 /** 726 * @} 727 */ 728 729 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number 730 * @{ 731 */ 732 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ 733 /* all ADC instances (refer to Reference Manual). */ 734 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */ 735 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */ 736 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */ 737 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */ 738 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */ 739 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */ 740 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */ 741 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */ 742 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */ 743 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */ 744 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */ 745 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */ 746 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */ 747 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */ 748 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */ 749 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */ 750 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */ 751 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */ 752 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< External channel (GPIO pin) ADCx_IN18 */ 753 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: Internal 754 voltage reference, channel specific to ADC1. */ 755 #define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor, 756 channel specific to ADC1. */ 757 #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/3: Vbat voltage 758 through a divider ladder of factor 1/3 to have channel voltage always below 759 Vdda, channel specific to ADC1. */ 760 #define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< Internal channel DAC1 channel 1, 761 channel specific to ADC2. */ 762 #define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< Internal channel DAC1 channel 2, 763 channel specific to ADC2. */ 764 /** 765 * @} 766 */ 767 768 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number 769 * @{ 770 */ 771 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ 772 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ 773 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ 774 /** 775 * @} 776 */ 777 778 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode 779 * @{ 780 */ 781 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */ 782 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< ADC AWD applied to a regular 783 group single channel */ 784 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to an 785 injected group single channel */ 786 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN\ 787 | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to a regular 788 and injected groups single channel */ 789 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< ADC AWD applied to regular 790 group all channels */ 791 #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to injected 792 group all channels */ 793 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to regular 794 and injected groups all channels */ 795 /** 796 * @} 797 */ 798 799 /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio 800 * @{ 801 */ 802 /** 803 * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed 804 * to result as the ADC oversampling conversion data (before potential shift) 805 */ 806 #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */ 807 #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */ 808 #define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio 8 */ 809 #define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio 16 */ 810 #define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio 32 */ 811 #define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio 64 */ 812 #define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio 128 */ 813 #define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio 256 */ 814 /** 815 * @} 816 */ 817 818 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift 819 * @{ 820 */ 821 /** 822 * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling 823 * conversion data) 824 */ 825 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */ 826 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */ 827 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */ 828 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */ 829 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */ 830 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */ 831 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */ 832 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */ 833 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */ 834 /** 835 * @} 836 */ 837 838 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 839 * @{ 840 */ 841 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: 842 continuous mode (all conversions of OVS ratio are done from 1 trigger) */ 843 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: 844 discontinuous mode (each conversion of OVS ratio needs a trigger) */ 845 /** 846 * @} 847 */ 848 849 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular 850 * @{ 851 */ 852 #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained 853 during injection sequence */ 854 #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during 855 injection sequence */ 856 /** 857 * @} 858 */ 859 860 /** @defgroup ADC_Event_type ADC Event type 861 * @{ 862 */ 863 /** 864 * @note Analog watchdog 1 is available on all stm32 series 865 * Analog watchdog 2 and 3 are not available on all series 866 */ 867 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 868 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */ 869 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */ 870 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */ 871 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ 872 #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ 873 /** 874 * @} 875 */ 876 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility 877 with other STM32 devices having only one analog watchdog */ 878 879 /** @defgroup ADC_interrupts_definition ADC interrupts definition 880 * @{ 881 */ 882 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 883 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ 884 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ 885 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ 886 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 887 #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ 888 #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ 889 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 890 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog 891 watchdog) */ 892 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog 893 watchdog) */ 894 #define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ 895 896 #define ADC_IT_AWD ADC_IT_AWD1 /*!< Analog watchdog 1 interrupt source: naming for compatibility 897 with other STM32 series having only one analog watchdog */ 898 899 /** 900 * @} 901 */ 902 903 /** @defgroup ADC_flags_definition ADC flags definition 904 * @{ 905 */ 906 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 907 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 908 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 909 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 910 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 911 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ 912 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ 913 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ 914 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ 915 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ 916 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ 917 918 /** 919 * @} 920 */ 921 922 /** 923 * @} 924 */ 925 926 /* Private macro -------------------------------------------------------------*/ 927 928 /** @defgroup ADC_Private_Macros ADC Private Macros 929 * @{ 930 */ 931 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 932 /* code of final user. */ 933 934 /** 935 * @brief Return resolution bits in CFGR register RES[1:0] field. 936 * @param __HANDLE__ ADC handle 937 * @retval Value of bitfield RES in CFGR register. 938 */ 939 #define ADC_GET_RESOLUTION(__HANDLE__) \ 940 (LL_ADC_GetResolution((__HANDLE__)->Instance)) 941 942 /** 943 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 944 * @param __HANDLE__ ADC handle 945 * @retval None 946 */ 947 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 948 949 /** 950 * @brief Simultaneously clear and set specific bits of the handle State. 951 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 952 * the first parameter is the ADC handle State, the second parameter is the 953 * bit field to clear, the third and last parameter is the bit field to set. 954 * @retval None 955 */ 956 #define ADC_STATE_CLR_SET MODIFY_REG 957 958 /** 959 * @brief Verify that a given value is aligned with the ADC resolution range. 960 * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). 961 * @param __ADC_VALUE__ value checked against the resolution. 962 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 963 */ 964 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 965 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) 966 967 /** 968 * @brief Verify the length of the scheduled regular conversions group. 969 * @param __LENGTH__ number of programmed conversions. 970 * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) 971 * or RESET (__LENGTH__ is null or too large) 972 */ 973 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) 974 975 976 /** 977 * @brief Verify the number of scheduled regular conversions in discontinuous mode. 978 * @param NUMBER number of scheduled regular conversions in discontinuous mode. 979 * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) 980 * or RESET (NUMBER is null or too large) 981 */ 982 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) 983 984 985 /** 986 * @brief Verify the ADC clock setting. 987 * @param __ADC_CLOCK__ programmed ADC clock. 988 * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) 989 */ 990 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ 991 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 992 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ 993 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ 994 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ 995 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ 996 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ 997 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ 998 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ 999 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ 1000 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ 1001 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ 1002 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ 1003 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ 1004 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) 1005 1006 /** 1007 * @brief Verify the ADC resolution setting. 1008 * @param __RESOLUTION__ programmed ADC resolution. 1009 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 1010 */ 1011 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 1012 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 1013 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 1014 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 1015 1016 /** 1017 * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. 1018 * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. 1019 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 1020 */ 1021 #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 1022 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 1023 1024 /** 1025 * @brief Verify the ADC converted data alignment. 1026 * @param __ALIGN__ programmed ADC converted data alignment. 1027 * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) 1028 */ 1029 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ 1030 ((__ALIGN__) == ADC_DATAALIGN_LEFT) ) 1031 1032 /** 1033 * @brief Verify the ADC scan mode. 1034 * @param __SCAN_MODE__ programmed ADC scan mode. 1035 * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) 1036 */ 1037 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ 1038 ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) 1039 1040 /** 1041 * @brief Verify the ADC edge trigger setting for regular group. 1042 * @param __EDGE__ programmed ADC edge trigger setting. 1043 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 1044 */ 1045 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 1046 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 1047 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 1048 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 1049 1050 /** 1051 * @brief Verify the ADC regular conversions external trigger. 1052 * @param __HANDLE__ ADC handle 1053 * @param __REGTRIG__ programmed ADC regular conversions external trigger. 1054 * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) 1055 */ 1056 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 1057 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 1058 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 1059 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 1060 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 1061 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 1062 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 1063 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 1064 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 1065 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 1066 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1067 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1068 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 1069 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 1070 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 1071 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 1072 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 1073 1074 /** 1075 * @brief Verify the ADC regular conversions check for converted data availability. 1076 * @param __EOC_SELECTION__ converted data availability check. 1077 * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) 1078 */ 1079 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ 1080 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) 1081 1082 /** 1083 * @brief Verify the ADC regular conversions overrun handling. 1084 * @param __OVR__ ADC regular conversions overrun handling. 1085 * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) 1086 */ 1087 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ 1088 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) 1089 1090 /** 1091 * @brief Verify the ADC conversions sampling time. 1092 * @param __TIME__ ADC conversions sampling time. 1093 * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) 1094 */ 1095 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 1096 ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \ 1097 ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ 1098 ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ 1099 ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ 1100 ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ 1101 ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ 1102 ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ 1103 ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) 1104 1105 /** 1106 * @brief Verify the ADC regular channel setting. 1107 * @param __CHANNEL__ programmed ADC regular channel. 1108 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 1109 */ 1110 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ 1111 ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ 1112 ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ 1113 ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ 1114 ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ 1115 ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ 1116 ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ 1117 ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ 1118 ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ 1119 ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ 1120 ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ 1121 ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ 1122 ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ 1123 ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ 1124 ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ 1125 ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) 1126 1127 /** 1128 * @} 1129 */ 1130 1131 1132 /* Private constants ---------------------------------------------------------*/ 1133 1134 /** @defgroup ADC_Private_Constants ADC Private Constants 1135 * @{ 1136 */ 1137 1138 /* Fixed timeout values for ADC conversion (including sampling time) */ 1139 /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */ 1140 /* Maximum conversion time is 12.5 + Maximum sampling time */ 1141 /* or 12.5 + 640.5 = 653 ADC clock cycles */ 1142 /* Minimum ADC Clock frequency is 0.14 MHz */ 1143 /* Maximum conversion time is */ 1144 /* 653 / 0.14 MHz = 4.66 ms */ 1145 #define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ 1146 1147 /* Delay for temperature sensor stabilization time. */ 1148 /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ 1149 /* Unit: us */ 1150 #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) 1151 1152 /** 1153 * @} 1154 */ 1155 1156 /* Exported macro ------------------------------------------------------------*/ 1157 1158 /** @defgroup ADC_Exported_Macros ADC Exported Macros 1159 * @{ 1160 */ 1161 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 1162 /* final user. */ 1163 1164 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. 1165 * @{ 1166 */ 1167 1168 /** @brief Reset ADC handle state. 1169 * @param __HANDLE__ ADC handle 1170 * @retval None 1171 */ 1172 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1173 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1174 do{ \ 1175 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 1176 (__HANDLE__)->MspInitCallback = NULL; \ 1177 (__HANDLE__)->MspDeInitCallback = NULL; \ 1178 } while(0) 1179 #else 1180 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1181 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 1182 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1183 1184 /** 1185 * @brief Enable ADC interrupt. 1186 * @param __HANDLE__ ADC handle 1187 * @param __INTERRUPT__ ADC Interrupt 1188 * This parameter can be one of the following values: 1189 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1190 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1191 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1192 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1193 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1194 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1195 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1196 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1197 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1198 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1199 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1200 * @retval None 1201 */ 1202 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1203 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 1204 1205 /** 1206 * @brief Disable ADC interrupt. 1207 * @param __HANDLE__ ADC handle 1208 * @param __INTERRUPT__ ADC Interrupt 1209 * This parameter can be one of the following values: 1210 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1211 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1212 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1213 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1214 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1215 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1216 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1217 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1218 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1219 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1220 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1221 * @retval None 1222 */ 1223 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1224 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 1225 1226 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 1227 * @param __HANDLE__ ADC handle 1228 * @param __INTERRUPT__ ADC interrupt source to check 1229 * This parameter can be one of the following values: 1230 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1231 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1232 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1233 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1234 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1235 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1236 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1237 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1238 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1239 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1240 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1241 * @retval State of interruption (SET or RESET) 1242 */ 1243 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 1244 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 1245 1246 /** 1247 * @brief Check whether the specified ADC flag is set or not. 1248 * @param __HANDLE__ ADC handle 1249 * @param __FLAG__ ADC flag 1250 * This parameter can be one of the following values: 1251 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1252 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1253 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1254 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1255 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1256 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1257 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1258 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1259 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1260 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1261 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 1262 * @retval State of flag (TRUE or FALSE). 1263 */ 1264 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 1265 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 1266 1267 /** 1268 * @brief Clear the specified ADC flag. 1269 * @param __HANDLE__ ADC handle 1270 * @param __FLAG__ ADC flag 1271 * This parameter can be one of the following values: 1272 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1273 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1274 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1275 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1276 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1277 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1278 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1279 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1280 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1281 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1282 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 1283 * @retval None 1284 */ 1285 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 1286 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1287 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 1288 1289 /** 1290 * @} 1291 */ 1292 1293 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro 1294 * @{ 1295 */ 1296 1297 /** 1298 * @brief Helper macro to get ADC channel number in decimal format 1299 * from literals ADC_CHANNEL_x. 1300 * @note Example: 1301 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) 1302 * will return decimal number "4". 1303 * @note The input can be a value from functions where a channel 1304 * number is returned, either defined with number 1305 * or with bitfield (only one bit must be set). 1306 * @param __CHANNEL__ This parameter can be one of the following values: 1307 * @arg @ref ADC_CHANNEL_0 (7) 1308 * @arg @ref ADC_CHANNEL_1 (7) 1309 * @arg @ref ADC_CHANNEL_2 (7) 1310 * @arg @ref ADC_CHANNEL_3 (7) 1311 * @arg @ref ADC_CHANNEL_4 (7) 1312 * @arg @ref ADC_CHANNEL_5 (7) 1313 * @arg @ref ADC_CHANNEL_6 1314 * @arg @ref ADC_CHANNEL_7 1315 * @arg @ref ADC_CHANNEL_8 1316 * @arg @ref ADC_CHANNEL_9 1317 * @arg @ref ADC_CHANNEL_10 1318 * @arg @ref ADC_CHANNEL_11 1319 * @arg @ref ADC_CHANNEL_12 1320 * @arg @ref ADC_CHANNEL_13 1321 * @arg @ref ADC_CHANNEL_14 1322 * @arg @ref ADC_CHANNEL_15 1323 * @arg @ref ADC_CHANNEL_16 1324 * @arg @ref ADC_CHANNEL_17 1325 * @arg @ref ADC_CHANNEL_18 1326 * @arg @ref ADC_CHANNEL_VREFINT 1327 * @arg @ref ADC_CHANNEL_TEMPSENSOR 1328 * @arg @ref ADC_CHANNEL_VBAT 1329 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 1330 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 1331 * 1332 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n 1333 * (6) On STM32L5, parameter available on devices with several ADC instances.\n 1334 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 1335 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 1336 * @retval Value between Min_Data=0 and Max_Data=18 1337 */ 1338 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 1339 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) 1340 1341 /** 1342 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x 1343 * from number in decimal format. 1344 * @note Example: 1345 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) 1346 * will return a data equivalent to "ADC_CHANNEL_4". 1347 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 1348 * @retval Returned value can be one of the following values: 1349 * @arg @ref ADC_CHANNEL_0 (7) 1350 * @arg @ref ADC_CHANNEL_1 (7) 1351 * @arg @ref ADC_CHANNEL_2 (7) 1352 * @arg @ref ADC_CHANNEL_3 (7) 1353 * @arg @ref ADC_CHANNEL_4 (7) 1354 * @arg @ref ADC_CHANNEL_5 (7) 1355 * @arg @ref ADC_CHANNEL_6 1356 * @arg @ref ADC_CHANNEL_7 1357 * @arg @ref ADC_CHANNEL_8 1358 * @arg @ref ADC_CHANNEL_9 1359 * @arg @ref ADC_CHANNEL_10 1360 * @arg @ref ADC_CHANNEL_11 1361 * @arg @ref ADC_CHANNEL_12 1362 * @arg @ref ADC_CHANNEL_13 1363 * @arg @ref ADC_CHANNEL_14 1364 * @arg @ref ADC_CHANNEL_15 1365 * @arg @ref ADC_CHANNEL_16 1366 * @arg @ref ADC_CHANNEL_17 1367 * @arg @ref ADC_CHANNEL_18 1368 * @arg @ref ADC_CHANNEL_VREFINT (1) 1369 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 1370 * @arg @ref ADC_CHANNEL_VBAT (4) 1371 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 1372 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 1373 * 1374 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n 1375 * (6) On STM32L5, parameter available on devices with several ADC instances.\n 1376 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 1377 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 1378 * 4.21 Ms/s)).\n 1379 * (1, 2, 3, 4) For ADC channel read back from ADC register, 1380 * comparison with internal channel parameter to be done 1381 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1382 */ 1383 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 1384 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) 1385 1386 /** 1387 * @brief Helper macro to determine whether the selected channel 1388 * corresponds to literal definitions of driver. 1389 * @note The different literal definitions of ADC channels are: 1390 * - ADC internal channel: 1391 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... 1392 * - ADC external channel (channel connected to a GPIO pin): 1393 * ADC_CHANNEL_1, ADC_CHANNEL_2, ... 1394 * @note The channel parameter must be a value defined from literal 1395 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1396 * ADC_CHANNEL_TEMPSENSOR, ...), 1397 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), 1398 * must not be a value from functions where a channel number is 1399 * returned from ADC registers, 1400 * because internal and external channels share the same channel 1401 * number in ADC registers. The differentiation is made only with 1402 * parameters definitions of driver. 1403 * @param __CHANNEL__ This parameter can be one of the following values: 1404 * @arg @ref ADC_CHANNEL_0 (7) 1405 * @arg @ref ADC_CHANNEL_1 (7) 1406 * @arg @ref ADC_CHANNEL_2 (7) 1407 * @arg @ref ADC_CHANNEL_3 (7) 1408 * @arg @ref ADC_CHANNEL_4 (7) 1409 * @arg @ref ADC_CHANNEL_5 (7) 1410 * @arg @ref ADC_CHANNEL_6 1411 * @arg @ref ADC_CHANNEL_7 1412 * @arg @ref ADC_CHANNEL_8 1413 * @arg @ref ADC_CHANNEL_9 1414 * @arg @ref ADC_CHANNEL_10 1415 * @arg @ref ADC_CHANNEL_11 1416 * @arg @ref ADC_CHANNEL_12 1417 * @arg @ref ADC_CHANNEL_13 1418 * @arg @ref ADC_CHANNEL_14 1419 * @arg @ref ADC_CHANNEL_15 1420 * @arg @ref ADC_CHANNEL_16 1421 * @arg @ref ADC_CHANNEL_17 1422 * @arg @ref ADC_CHANNEL_18 1423 * @arg @ref ADC_CHANNEL_VREFINT 1424 * @arg @ref ADC_CHANNEL_TEMPSENSOR 1425 * @arg @ref ADC_CHANNEL_VBAT 1426 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 1427 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 1428 * 1429 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n 1430 * (6) On STM32L5, parameter available on devices with several ADC instances.\n 1431 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 1432 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 1433 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel 1434 * connected to a GPIO pin). 1435 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 1436 */ 1437 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 1438 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) 1439 1440 /** 1441 * @brief Helper macro to convert a channel defined from parameter 1442 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1443 * ADC_CHANNEL_TEMPSENSOR, ...), 1444 * to its equivalent parameter definition of a ADC external channel 1445 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). 1446 * @note The channel parameter can be, additionally to a value 1447 * defined from parameter definition of a ADC internal channel 1448 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), 1449 * a value defined from parameter definition of 1450 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1451 * or a value from functions where a channel number is returned 1452 * from ADC registers. 1453 * @param __CHANNEL__ This parameter can be one of the following values: 1454 * @arg @ref ADC_CHANNEL_0 (7) 1455 * @arg @ref ADC_CHANNEL_1 (7) 1456 * @arg @ref ADC_CHANNEL_2 (7) 1457 * @arg @ref ADC_CHANNEL_3 (7) 1458 * @arg @ref ADC_CHANNEL_4 (7) 1459 * @arg @ref ADC_CHANNEL_5 (7) 1460 * @arg @ref ADC_CHANNEL_6 1461 * @arg @ref ADC_CHANNEL_7 1462 * @arg @ref ADC_CHANNEL_8 1463 * @arg @ref ADC_CHANNEL_9 1464 * @arg @ref ADC_CHANNEL_10 1465 * @arg @ref ADC_CHANNEL_11 1466 * @arg @ref ADC_CHANNEL_12 1467 * @arg @ref ADC_CHANNEL_13 1468 * @arg @ref ADC_CHANNEL_14 1469 * @arg @ref ADC_CHANNEL_15 1470 * @arg @ref ADC_CHANNEL_16 1471 * @arg @ref ADC_CHANNEL_17 1472 * @arg @ref ADC_CHANNEL_18 1473 * @arg @ref ADC_CHANNEL_VREFINT 1474 * @arg @ref ADC_CHANNEL_TEMPSENSOR 1475 * @arg @ref ADC_CHANNEL_VBAT 1476 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 1477 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 1478 * 1479 * (2) On STM32L5, parameter available only on ADC instance: ADC2.\n 1480 * (6) On STM32L5, parameter available on devices with several ADC instances.\n 1481 * (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 1482 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 1483 * @retval Returned value can be one of the following values: 1484 * @arg @ref ADC_CHANNEL_0 1485 * @arg @ref ADC_CHANNEL_1 1486 * @arg @ref ADC_CHANNEL_2 1487 * @arg @ref ADC_CHANNEL_3 1488 * @arg @ref ADC_CHANNEL_4 1489 * @arg @ref ADC_CHANNEL_5 1490 * @arg @ref ADC_CHANNEL_6 1491 * @arg @ref ADC_CHANNEL_7 1492 * @arg @ref ADC_CHANNEL_8 1493 * @arg @ref ADC_CHANNEL_9 1494 * @arg @ref ADC_CHANNEL_10 1495 * @arg @ref ADC_CHANNEL_11 1496 * @arg @ref ADC_CHANNEL_12 1497 * @arg @ref ADC_CHANNEL_13 1498 * @arg @ref ADC_CHANNEL_14 1499 * @arg @ref ADC_CHANNEL_15 1500 * @arg @ref ADC_CHANNEL_16 1501 * @arg @ref ADC_CHANNEL_17 1502 * @arg @ref ADC_CHANNEL_18 1503 */ 1504 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 1505 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) 1506 1507 /** 1508 * @brief Helper macro to determine whether the internal channel 1509 * selected is available on the ADC instance selected. 1510 * @note The channel parameter must be a value defined from parameter 1511 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1512 * ADC_CHANNEL_TEMPSENSOR, ...), 1513 * must not be a value defined from parameter definition of 1514 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1515 * or a value from functions where a channel number is 1516 * returned from ADC registers, 1517 * because internal and external channels share the same channel 1518 * number in ADC registers. The differentiation is made only with 1519 * parameters definitions of driver. 1520 * @param __ADC_INSTANCE__ ADC instance 1521 * @param __CHANNEL__ This parameter can be one of the following values: 1522 * @arg @ref ADC_CHANNEL_VREFINT 1523 * @arg @ref ADC_CHANNEL_TEMPSENSOR 1524 * @arg @ref ADC_CHANNEL_VBAT 1525 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 1526 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 1527 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 1528 * Value "1" if the internal channel selected is available on the ADC instance selected. 1529 */ 1530 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 1531 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) 1532 1533 #if defined(ADC_MULTIMODE_SUPPORT) 1534 /** 1535 * @brief Helper macro to get the ADC multimode conversion data of ADC master 1536 * or ADC slave from raw value with both ADC conversion data concatenated. 1537 * @note This macro is intended to be used when multimode transfer by DMA 1538 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). 1539 * In this case the transferred data need to processed with this macro 1540 * to separate the conversion data of ADC master and ADC slave. 1541 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 1542 * @arg @ref LL_ADC_MULTI_MASTER 1543 * @arg @ref LL_ADC_MULTI_SLAVE 1544 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 1545 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 1546 */ 1547 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 1548 __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) 1549 #endif /* ADC_MULTIMODE_SUPPORT */ 1550 1551 /** 1552 * @brief Helper macro to select the ADC common instance 1553 * to which is belonging the selected ADC instance. 1554 * @note ADC common register instance can be used for: 1555 * - Set parameters common to several ADC instances 1556 * - Multimode (for devices with several ADC instances) 1557 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1558 * @param __ADCx__ ADC instance 1559 * @retval ADC common register instance 1560 */ 1561 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ 1562 __LL_ADC_COMMON_INSTANCE((__ADCx__)) 1563 1564 /** 1565 * @brief Helper macro to check if all ADC instances sharing the same 1566 * ADC common instance are disabled. 1567 * @note This check is required by functions with setting conditioned to 1568 * ADC state: 1569 * All ADC instances of the ADC common group must be disabled. 1570 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1571 * @note On devices with only 1 ADC common instance, parameter of this macro 1572 * is useless and can be ignored (parameter kept for compatibility 1573 * with devices featuring several ADC common instances). 1574 * @param __ADCXY_COMMON__ ADC common instance 1575 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1576 * @retval Value "0" if all ADC instances sharing the same ADC common instance 1577 * are disabled. 1578 * Value "1" if at least one ADC instance sharing the same ADC common instance 1579 * is enabled. 1580 */ 1581 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1582 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) 1583 1584 /** 1585 * @brief Helper macro to define the ADC conversion data full-scale digital 1586 * value corresponding to the selected ADC resolution. 1587 * @note ADC conversion data full-scale corresponds to voltage range 1588 * determined by analog voltage references Vref+ and Vref- 1589 * (refer to reference manual). 1590 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1591 * @arg @ref ADC_RESOLUTION_12B 1592 * @arg @ref ADC_RESOLUTION_10B 1593 * @arg @ref ADC_RESOLUTION_8B 1594 * @arg @ref ADC_RESOLUTION_6B 1595 * @retval ADC conversion data full-scale digital value 1596 */ 1597 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 1598 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) 1599 1600 /** 1601 * @brief Helper macro to convert the ADC conversion data from 1602 * a resolution to another resolution. 1603 * @param __DATA__ ADC conversion data to be converted 1604 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 1605 * This parameter can be one of the following values: 1606 * @arg @ref ADC_RESOLUTION_12B 1607 * @arg @ref ADC_RESOLUTION_10B 1608 * @arg @ref ADC_RESOLUTION_8B 1609 * @arg @ref ADC_RESOLUTION_6B 1610 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 1611 * This parameter can be one of the following values: 1612 * @arg @ref ADC_RESOLUTION_12B 1613 * @arg @ref ADC_RESOLUTION_10B 1614 * @arg @ref ADC_RESOLUTION_8B 1615 * @arg @ref ADC_RESOLUTION_6B 1616 * @retval ADC conversion data to the requested resolution 1617 */ 1618 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 1619 __ADC_RESOLUTION_CURRENT__,\ 1620 __ADC_RESOLUTION_TARGET__) \ 1621 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ 1622 (__ADC_RESOLUTION_CURRENT__),\ 1623 (__ADC_RESOLUTION_TARGET__)) 1624 1625 /** 1626 * @brief Helper macro to calculate the voltage (unit: mVolt) 1627 * corresponding to a ADC conversion data (unit: digital value). 1628 * @note Analog reference voltage (Vref+) must be either known from 1629 * user board environment or can be calculated using ADC measurement 1630 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1631 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1632 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 1633 * (unit: digital value). 1634 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1635 * @arg @ref ADC_RESOLUTION_12B 1636 * @arg @ref ADC_RESOLUTION_10B 1637 * @arg @ref ADC_RESOLUTION_8B 1638 * @arg @ref ADC_RESOLUTION_6B 1639 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1640 */ 1641 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 1642 __ADC_DATA__,\ 1643 __ADC_RESOLUTION__) \ 1644 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 1645 (__ADC_DATA__),\ 1646 (__ADC_RESOLUTION__)) 1647 1648 /** 1649 * @brief Helper macro to calculate analog reference voltage (Vref+) 1650 * (unit: mVolt) from ADC conversion data of internal voltage 1651 * reference VrefInt. 1652 * @note Computation is using VrefInt calibration value 1653 * stored in system memory for each device during production. 1654 * @note This voltage depends on user board environment: voltage level 1655 * connected to pin Vref+. 1656 * On devices with small package, the pin Vref+ is not present 1657 * and internally bonded to pin Vdda. 1658 * @note On this STM32 series, calibration data of internal voltage reference 1659 * VrefInt corresponds to a resolution of 12 bits, 1660 * this is the recommended ADC resolution to convert voltage of 1661 * internal voltage reference VrefInt. 1662 * Otherwise, this macro performs the processing to scale 1663 * ADC conversion data to 12 bits. 1664 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 1665 * of internal voltage reference VrefInt (unit: digital value). 1666 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1667 * @arg @ref ADC_RESOLUTION_12B 1668 * @arg @ref ADC_RESOLUTION_10B 1669 * @arg @ref ADC_RESOLUTION_8B 1670 * @arg @ref ADC_RESOLUTION_6B 1671 * @retval Analog reference voltage (unit: mV) 1672 */ 1673 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 1674 __ADC_RESOLUTION__) \ 1675 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ 1676 (__ADC_RESOLUTION__)) 1677 1678 /** 1679 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1680 * from ADC conversion data of internal temperature sensor. 1681 * @note Computation is using temperature sensor calibration values 1682 * stored in system memory for each device during production. 1683 * @note Calculation formula: 1684 * Temperature = ((TS_ADC_DATA - TS_CAL1) 1685 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 1686 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 1687 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1688 * Avg_Slope = (TS_CAL2 - TS_CAL1) 1689 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 1690 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 1691 * TEMP_DEGC_CAL1 (calibrated in factory) 1692 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 1693 * TEMP_DEGC_CAL2 (calibrated in factory) 1694 * Caution: Calculation relevancy under reserve that calibration 1695 * parameters are correct (address and data). 1696 * To calculate temperature using temperature sensor 1697 * datasheet typical values (generic values less, therefore 1698 * less accurate than calibrated values), 1699 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 1700 * @note As calculation input, the analog reference voltage (Vref+) must be 1701 * defined as it impacts the ADC LSB equivalent voltage. 1702 * @note Analog reference voltage (Vref+) must be either known from 1703 * user board environment or can be calculated using ADC measurement 1704 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1705 * @note On this STM32 series, calibration data of temperature sensor 1706 * corresponds to a resolution of 12 bits, 1707 * this is the recommended ADC resolution to convert voltage of 1708 * temperature sensor. 1709 * Otherwise, this macro performs the processing to scale 1710 * ADC conversion data to 12 bits. 1711 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1712 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 1713 * temperature sensor (unit: digital value). 1714 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 1715 * sensor voltage has been measured. 1716 * This parameter can be one of the following values: 1717 * @arg @ref ADC_RESOLUTION_12B 1718 * @arg @ref ADC_RESOLUTION_10B 1719 * @arg @ref ADC_RESOLUTION_8B 1720 * @arg @ref ADC_RESOLUTION_6B 1721 * @retval Temperature (unit: degree Celsius) 1722 */ 1723 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ 1724 __TEMPSENSOR_ADC_DATA__,\ 1725 __ADC_RESOLUTION__) \ 1726 __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ 1727 (__TEMPSENSOR_ADC_DATA__),\ 1728 (__ADC_RESOLUTION__)) 1729 1730 /** 1731 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1732 * from ADC conversion data of internal temperature sensor. 1733 * @note Computation is using temperature sensor typical values 1734 * (refer to device datasheet). 1735 * @note Calculation formula: 1736 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 1737 * / Avg_Slope + CALx_TEMP 1738 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1739 * (unit: digital value) 1740 * Avg_Slope = temperature sensor slope 1741 * (unit: uV/Degree Celsius) 1742 * TS_TYP_CALx_VOLT = temperature sensor digital value at 1743 * temperature CALx_TEMP (unit: mV) 1744 * Caution: Calculation relevancy under reserve the temperature sensor 1745 * of the current device has characteristics in line with 1746 * datasheet typical values. 1747 * If temperature sensor calibration values are available on 1748 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 1749 * temperature calculation will be more accurate using 1750 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 1751 * @note As calculation input, the analog reference voltage (Vref+) must be 1752 * defined as it impacts the ADC LSB equivalent voltage. 1753 * @note Analog reference voltage (Vref+) must be either known from 1754 * user board environment or can be calculated using ADC measurement 1755 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1756 * @note ADC measurement data must correspond to a resolution of 12bits 1757 * (full scale digital value 4095). If not the case, the data must be 1758 * preliminarily rescaled to an equivalent resolution of 12 bits. 1759 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value 1760 (unit: uV/DegCelsius). 1761 * On STM32WB, refer to device datasheet parameter "Avg_Slope". 1762 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at 1763 temperature and Vref+ defined in parameters below) (unit: mV). 1764 * On STM32WB, refer to device datasheet parameter "V30" 1765 (corresponding to TS_CAL1). 1766 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see 1767 parameter above) is corresponding (unit: mV) 1768 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 1769 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 1770 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 1771 * This parameter can be one of the following values: 1772 * @arg @ref ADC_RESOLUTION_12B 1773 * @arg @ref ADC_RESOLUTION_10B 1774 * @arg @ref ADC_RESOLUTION_8B 1775 * @arg @ref ADC_RESOLUTION_6B 1776 * @retval Temperature (unit: degree Celsius) 1777 */ 1778 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 1779 __TEMPSENSOR_TYP_CALX_V__,\ 1780 __TEMPSENSOR_CALX_TEMP__,\ 1781 __VREFANALOG_VOLTAGE__,\ 1782 __TEMPSENSOR_ADC_DATA__,\ 1783 __ADC_RESOLUTION__) \ 1784 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ 1785 (__TEMPSENSOR_TYP_CALX_V__),\ 1786 (__TEMPSENSOR_CALX_TEMP__),\ 1787 (__VREFANALOG_VOLTAGE__),\ 1788 (__TEMPSENSOR_ADC_DATA__),\ 1789 (__ADC_RESOLUTION__)) 1790 1791 /** 1792 * @} 1793 */ 1794 1795 /** 1796 * @} 1797 */ 1798 1799 /* Include ADC HAL Extended module */ 1800 #include "stm32l5xx_hal_adc_ex.h" 1801 1802 /* Exported functions --------------------------------------------------------*/ 1803 /** @addtogroup ADC_Exported_Functions 1804 * @{ 1805 */ 1806 1807 /** @addtogroup ADC_Exported_Functions_Group1 1808 * @brief Initialization and Configuration functions 1809 * @{ 1810 */ 1811 /* Initialization and de-initialization functions ****************************/ 1812 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); 1813 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 1814 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); 1815 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); 1816 1817 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1818 /* Callbacks Register/UnRegister functions ***********************************/ 1819 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, 1820 pADC_CallbackTypeDef pCallback); 1821 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 1822 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1823 /** 1824 * @} 1825 */ 1826 1827 /** @addtogroup ADC_Exported_Functions_Group2 1828 * @brief IO operation functions 1829 * @{ 1830 */ 1831 /* IO operation functions *****************************************************/ 1832 1833 /* Blocking mode: Polling */ 1834 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); 1835 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); 1836 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1837 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); 1838 1839 /* Non-blocking mode: Interruption */ 1840 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); 1841 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); 1842 1843 /* Non-blocking mode: DMA */ 1844 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1845 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); 1846 1847 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1848 uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); 1849 1850 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 1851 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); 1852 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); 1853 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); 1854 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); 1855 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 1856 /** 1857 * @} 1858 */ 1859 1860 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 1861 * @brief Peripheral Control functions 1862 * @{ 1863 */ 1864 /* Peripheral Control functions ***********************************************/ 1865 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig); 1866 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, 1867 const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig); 1868 1869 /** 1870 * @} 1871 */ 1872 1873 /* Peripheral State functions *************************************************/ 1874 /** @addtogroup ADC_Exported_Functions_Group4 1875 * @{ 1876 */ 1877 uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); 1878 uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); 1879 1880 /** 1881 * @} 1882 */ 1883 1884 /** 1885 * @} 1886 */ 1887 1888 /* Private functions ---------------------------------------------------------*/ 1889 /** @addtogroup ADC_Private_Functions ADC Private Functions 1890 * @{ 1891 */ 1892 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); 1893 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); 1894 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); 1895 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 1896 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 1897 void ADC_DMAError(DMA_HandleTypeDef *hdma); 1898 1899 /** 1900 * @} 1901 */ 1902 1903 /** 1904 * @} 1905 */ 1906 1907 /** 1908 * @} 1909 */ 1910 1911 #ifdef __cplusplus 1912 } 1913 #endif 1914 1915 1916 #endif /* STM32L5xx_HAL_ADC_H */ 1917
