1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32l4xx_ll_adc.h"
22 #include "stm32l4xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32L4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup ADC_LL_Private_Constants
44 * @{
45 */
46
47 /* Definitions of ADC hardware constraints delays */
48 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
49 /* not timeout values: */
50 /* Timeout values for ADC operations are dependent to device clock */
51 /* configuration (system clock versus ADC clock), */
52 /* and therefore must be defined in user application. */
53 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
54 /* values definition. */
55 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
56 /* of device clock setting. */
57 /* In user application, ADC timeout values should be defined with */
58 /* temporal values, in function of device clock settings. */
59 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
60 /* - ADC clock from synchronous clock with AHB prescaler 512, */
61 /* APB prescaler 16, ADC prescaler 4. */
62 /* - ADC clock from asynchronous clock (PLLSAI) with prescaler 1, */
63 /* with highest ratio CPU clock frequency vs HSI clock frequency: */
64 /* CPU clock frequency max 72MHz, PLLSAI freq min 26MHz: ratio 4. */
65 /* Unit: CPU cycles. */
66 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
67 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
68 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
69
70 /**
71 * @}
72 */
73
74 /* Private macros ------------------------------------------------------------*/
75
76 /** @addtogroup ADC_LL_Private_Macros
77 * @{
78 */
79
80 /* Check of parameters for configuration of ADC hierarchical scope: */
81 /* common to several ADC instances. */
82 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
83 (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
84 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
85 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
86 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
87 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
89 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
90 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
93 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
94 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
95 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
96 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
97 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
98 )
99
100 /* Check of parameters for configuration of ADC hierarchical scope: */
101 /* ADC instance. */
102 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
103 (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
104 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
105 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
106 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
107 )
108
109 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
110 (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
111 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
112 )
113
114 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
115 (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
116 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
117 )
118
119 /* Check of parameters for configuration of ADC hierarchical scope: */
120 /* ADC group regular */
121 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
122 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
123 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
124 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
125 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
126 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
127 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
128 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
129 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
130 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
131 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
132 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
133 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
134 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
135 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
136 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
137 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
139 )
140
141 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
142 (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
143 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
144 )
145
146 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
147 (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
148 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
149 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
150 )
151
152 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
153 (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
154 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
155 )
156
157 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
158 (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
159 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
160 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
161 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
162 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
163 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
164 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
165 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
166 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
167 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
168 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
169 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
170 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
171 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
172 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
173 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
174 )
175
176 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
177 (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
178 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
179 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
180 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
181 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
182 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
183 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
184 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
185 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
186 )
187
188 /* Check of parameters for configuration of ADC hierarchical scope: */
189 /* ADC group injected */
190 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
191 (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
192 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
193 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
194 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
195 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
196 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
197 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
198 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
199 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
200 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
201 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
202 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
203 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
204 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
205 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
206 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
207 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
208 )
209
210 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
211 (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
212 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
213 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
214 )
215
216 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
217 (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
218 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
219 )
220
221 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
222 (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
223 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
224 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
225 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
226 )
227
228 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
229 (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
230 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
231 )
232
233 #if defined(ADC_MULTIMODE_SUPPORT)
234 /* Check of parameters for configuration of ADC hierarchical scope: */
235 /* multimode. */
236 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
237 (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
238 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
239 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
240 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
241 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
242 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
243 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
244 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
245 )
246
247 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
248 (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
249 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \
250 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \
251 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \
252 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \
253 )
254
255 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
256 (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
257 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \
258 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \
259 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \
260 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
261 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
262 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
263 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
264 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
265 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
266 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
267 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
268 )
269
270 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
271 (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
272 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
273 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
274 )
275
276 #endif /* ADC_MULTIMODE_SUPPORT */
277 /**
278 * @}
279 */
280
281
282 /* Private function prototypes -----------------------------------------------*/
283
284 /* Exported functions --------------------------------------------------------*/
285 /** @addtogroup ADC_LL_Exported_Functions
286 * @{
287 */
288
289 /** @addtogroup ADC_LL_EF_Init
290 * @{
291 */
292
293 /**
294 * @brief De-initialize registers of all ADC instances belonging to
295 * the same ADC common instance to their default reset values.
296 * @note This function is performing a hard reset, using high level
297 * clock source RCC ADC reset.
298 * Caution: On this STM32 series, if several ADC instances are available
299 * on the selected device, RCC ADC reset will reset
300 * all ADC instances belonging to the common ADC instance.
301 * To de-initialize only 1 ADC instance, use
302 * function @ref LL_ADC_DeInit().
303 * @param ADCxy_COMMON ADC common instance
304 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
305 * @retval An ErrorStatus enumeration value:
306 * - SUCCESS: ADC common registers are de-initialized
307 * - ERROR: not applicable
308 */
LL_ADC_CommonDeInit(ADC_Common_TypeDef * ADCxy_COMMON)309 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
310 {
311 /* Check the parameters */
312 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
313
314 /* Prevent unused argument compilation warning */
315 (void)(ADCxy_COMMON);
316
317 /* Force reset of ADC clock (core clock) */
318 LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC);
319
320 /* Release reset of ADC clock (core clock) */
321 LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC);
322
323 return SUCCESS;
324 }
325
326 /**
327 * @brief Initialize some features of ADC common parameters
328 * (all ADC instances belonging to the same ADC common instance)
329 * and multimode (for devices with several ADC instances available).
330 * @note The setting of ADC common parameters is conditioned to
331 * ADC instances state:
332 * All ADC instances belonging to the same ADC common instance
333 * must be disabled.
334 * @param ADCxy_COMMON ADC common instance
335 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
336 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
337 * @retval An ErrorStatus enumeration value:
338 * - SUCCESS: ADC common registers are initialized
339 * - ERROR: ADC common registers are not initialized
340 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)341 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
342 {
343 ErrorStatus status = SUCCESS;
344
345 /* Check the parameters */
346 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
347 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
348
349 #if defined(ADC_MULTIMODE_SUPPORT)
350 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
351 if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
352 {
353 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
354 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
355 }
356 #endif /* ADC_MULTIMODE_SUPPORT */
357
358 /* Note: Hardware constraint (refer to description of functions */
359 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
360 /* On this STM32 series, setting of these features is conditioned to */
361 /* ADC state: */
362 /* All ADC instances of the ADC common group must be disabled. */
363 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
364 {
365 /* Configuration of ADC hierarchical scope: */
366 /* - common to several ADC */
367 /* (all ADC instances belonging to the same ADC common instance) */
368 /* - Set ADC clock (conversion clock) */
369 /* - multimode (if several ADC instances available on the */
370 /* selected device) */
371 /* - Set ADC multimode configuration */
372 /* - Set ADC multimode DMA transfer */
373 /* - Set ADC multimode: delay between 2 sampling phases */
374 #if defined(ADC_MULTIMODE_SUPPORT)
375 if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
376 {
377 MODIFY_REG(ADCxy_COMMON->CCR,
378 ADC_CCR_CKMODE
379 | ADC_CCR_PRESC
380 | ADC_CCR_DUAL
381 | ADC_CCR_MDMA
382 | ADC_CCR_DELAY
383 ,
384 ADC_CommonInitStruct->CommonClock
385 | ADC_CommonInitStruct->Multimode
386 | ADC_CommonInitStruct->MultiDMATransfer
387 | ADC_CommonInitStruct->MultiTwoSamplingDelay
388 );
389 }
390 else
391 {
392 MODIFY_REG(ADCxy_COMMON->CCR,
393 ADC_CCR_CKMODE
394 | ADC_CCR_PRESC
395 | ADC_CCR_DUAL
396 | ADC_CCR_MDMA
397 | ADC_CCR_DELAY
398 ,
399 ADC_CommonInitStruct->CommonClock
400 | LL_ADC_MULTI_INDEPENDENT
401 );
402 }
403 #else
404 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
405 #endif
406 }
407 else
408 {
409 /* Initialization error: One or several ADC instances belonging to */
410 /* the same ADC common instance are not disabled. */
411 status = ERROR;
412 }
413
414 return status;
415 }
416
417 /**
418 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
419 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
420 * whose fields will be set to default values.
421 * @retval None
422 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)423 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
424 {
425 /* Set ADC_CommonInitStruct fields to default values */
426 /* Set fields of ADC common */
427 /* (all ADC instances belonging to the same ADC common instance) */
428 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
429
430 #if defined(ADC_MULTIMODE_SUPPORT)
431 /* Set fields of ADC multimode */
432 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
433 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
434 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
435 #endif /* ADC_MULTIMODE_SUPPORT */
436 }
437
438 /**
439 * @brief De-initialize registers of the selected ADC instance
440 * to their default reset values.
441 * @note To reset all ADC instances quickly (perform a hard reset),
442 * use function @ref LL_ADC_CommonDeInit().
443 * @note If this functions returns error status, it means that ADC instance
444 * is in an unknown state.
445 * In this case, perform a hard reset using high level
446 * clock source RCC ADC reset.
447 * Caution: On this STM32 series, if several ADC instances are available
448 * on the selected device, RCC ADC reset will reset
449 * all ADC instances belonging to the common ADC instance.
450 * Refer to function @ref LL_ADC_CommonDeInit().
451 * @param ADCx ADC instance
452 * @retval An ErrorStatus enumeration value:
453 * - SUCCESS: ADC registers are de-initialized
454 * - ERROR: ADC registers are not de-initialized
455 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)456 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
457 {
458 ErrorStatus status = SUCCESS;
459
460 __IO uint32_t timeout_cpu_cycles = 0UL;
461
462 /* Check the parameters */
463 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
464
465 /* Disable ADC instance if not already disabled. */
466 if (LL_ADC_IsEnabled(ADCx) == 1UL)
467 {
468 /* Set ADC group regular trigger source to SW start to ensure to not */
469 /* have an external trigger event occurring during the conversion stop */
470 /* ADC disable process. */
471 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
472
473 /* Stop potential ADC conversion on going on ADC group regular. */
474 if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
475 {
476 if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
477 {
478 LL_ADC_REG_StopConversion(ADCx);
479 }
480 }
481
482 /* Set ADC group injected trigger source to SW start to ensure to not */
483 /* have an external trigger event occurring during the conversion stop */
484 /* ADC disable process. */
485 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
486
487 /* Stop potential ADC conversion on going on ADC group injected. */
488 if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
489 {
490 if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
491 {
492 LL_ADC_INJ_StopConversion(ADCx);
493 }
494 }
495
496 /* Wait for ADC conversions are effectively stopped */
497 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
498 while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
499 | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
500 {
501 timeout_cpu_cycles--;
502 if (timeout_cpu_cycles == 0UL)
503 {
504 /* Time-out error */
505 status = ERROR;
506 break;
507 }
508 }
509
510 /* Flush group injected contexts queue (register JSQR): */
511 /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
512 /* contexts queue is maintained with the last active context). */
513 LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
514
515 /* Disable the ADC instance */
516 LL_ADC_Disable(ADCx);
517
518 /* Wait for ADC instance is effectively disabled */
519 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
520 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
521 {
522 timeout_cpu_cycles--;
523 if (timeout_cpu_cycles == 0UL)
524 {
525 /* Time-out error */
526 status = ERROR;
527 break;
528 }
529 }
530 }
531
532 /* Check whether ADC state is compliant with expected state */
533 if (READ_BIT(ADCx->CR,
534 (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
535 | ADC_CR_ADDIS | ADC_CR_ADEN)
536 )
537 == 0UL)
538 {
539 /* ========== Reset ADC registers ========== */
540 /* Reset register IER */
541 CLEAR_BIT(ADCx->IER,
542 (LL_ADC_IT_ADRDY
543 | LL_ADC_IT_EOC
544 | LL_ADC_IT_EOS
545 | LL_ADC_IT_OVR
546 | LL_ADC_IT_EOSMP
547 | LL_ADC_IT_JEOC
548 | LL_ADC_IT_JEOS
549 | LL_ADC_IT_JQOVF
550 | LL_ADC_IT_AWD1
551 | LL_ADC_IT_AWD2
552 | LL_ADC_IT_AWD3
553 )
554 );
555
556 /* Reset register ISR */
557 SET_BIT(ADCx->ISR,
558 (LL_ADC_FLAG_ADRDY
559 | LL_ADC_FLAG_EOC
560 | LL_ADC_FLAG_EOS
561 | LL_ADC_FLAG_OVR
562 | LL_ADC_FLAG_EOSMP
563 | LL_ADC_FLAG_JEOC
564 | LL_ADC_FLAG_JEOS
565 | LL_ADC_FLAG_JQOVF
566 | LL_ADC_FLAG_AWD1
567 | LL_ADC_FLAG_AWD2
568 | LL_ADC_FLAG_AWD3
569 )
570 );
571
572 /* Reset register CR */
573 /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
574 /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
575 /* access mode "read-set": no direct reset applicable. */
576 /* - Reset Calibration mode to default setting (single ended). */
577 /* - Disable ADC internal voltage regulator. */
578 /* - Enable ADC deep power down. */
579 /* Note: ADC internal voltage regulator disable and ADC deep power */
580 /* down enable are conditioned to ADC state disabled: */
581 /* already done above. */
582 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
583 SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
584
585 /* Reset register CFGR */
586 MODIFY_REG(ADCx->CFGR,
587 (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
588 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
589 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
590 | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
591 | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN
592 | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN),
593 ADC_CFGR_JQDIS
594 );
595
596 /* Reset register CFGR2 */
597 CLEAR_BIT(ADCx->CFGR2,
598 (ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
599 | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
600 );
601
602 /* Reset register SMPR1 */
603 CLEAR_BIT(ADCx->SMPR1,
604 (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
605 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
606 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
607 );
608
609 /* Reset register SMPR2 */
610 CLEAR_BIT(ADCx->SMPR2,
611 (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
612 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
613 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
614 );
615
616 /* Reset register TR1 */
617 MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
618
619 /* Reset register TR2 */
620 MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
621
622 /* Reset register TR3 */
623 MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
624
625 /* Reset register SQR1 */
626 CLEAR_BIT(ADCx->SQR1,
627 (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
628 | ADC_SQR1_SQ1 | ADC_SQR1_L)
629 );
630
631 /* Reset register SQR2 */
632 CLEAR_BIT(ADCx->SQR2,
633 (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
634 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
635 );
636
637 /* Reset register SQR3 */
638 CLEAR_BIT(ADCx->SQR3,
639 (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
640 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
641 );
642
643 /* Reset register SQR4 */
644 CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
645
646 /* Reset register JSQR */
647 CLEAR_BIT(ADCx->JSQR,
648 (ADC_JSQR_JL
649 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
650 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
651 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1)
652 );
653
654 /* Reset register DR */
655 /* Note: bits in access mode read only, no direct reset applicable */
656
657 /* Reset register OFR1 */
658 CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
659 /* Reset register OFR2 */
660 CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
661 /* Reset register OFR3 */
662 CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
663 /* Reset register OFR4 */
664 CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
665
666 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
667 /* Note: bits in access mode read only, no direct reset applicable */
668
669 /* Reset register AWD2CR */
670 CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
671
672 /* Reset register AWD3CR */
673 CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
674
675 /* Reset register DIFSEL */
676 CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
677
678 /* Reset register CALFACT */
679 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
680 }
681 else
682 {
683 /* ADC instance is in an unknown state */
684 /* Need to performing a hard reset of ADC instance, using high level */
685 /* clock source RCC ADC reset. */
686 /* Caution: On this STM32 series, if several ADC instances are available */
687 /* on the selected device, RCC ADC reset will reset */
688 /* all ADC instances belonging to the common ADC instance. */
689 /* Caution: On this STM32 series, if several ADC instances are available */
690 /* on the selected device, RCC ADC reset will reset */
691 /* all ADC instances belonging to the common ADC instance. */
692 status = ERROR;
693 }
694
695 return status;
696 }
697
698 /**
699 * @brief Initialize some features of ADC instance.
700 * @note These parameters have an impact on ADC scope: ADC instance.
701 * Affects both group regular and group injected (availability
702 * of ADC group injected depends on STM32 families).
703 * Refer to corresponding unitary functions into
704 * @ref ADC_LL_EF_Configuration_ADC_Instance .
705 * @note The setting of these parameters by function @ref LL_ADC_Init()
706 * is conditioned to ADC state:
707 * ADC instance must be disabled.
708 * This condition is applied to all ADC features, for efficiency
709 * and compatibility over all STM32 families. However, the different
710 * features can be set under different ADC state conditions
711 * (setting possible with ADC enabled without conversion on going,
712 * ADC enabled with conversion on going, ...)
713 * Each feature can be updated afterwards with a unitary function
714 * and potentially with ADC in a different state than disabled,
715 * refer to description of each function for setting
716 * conditioned to ADC state.
717 * @note After using this function, some other features must be configured
718 * using LL unitary functions.
719 * The minimum configuration remaining to be done is:
720 * - Set ADC group regular or group injected sequencer:
721 * map channel on the selected sequencer rank.
722 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
723 * - Set ADC channel sampling time
724 * Refer to function LL_ADC_SetChannelSamplingTime();
725 * @param ADCx ADC instance
726 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
727 * @retval An ErrorStatus enumeration value:
728 * - SUCCESS: ADC registers are initialized
729 * - ERROR: ADC registers are not initialized
730 */
LL_ADC_Init(ADC_TypeDef * ADCx,LL_ADC_InitTypeDef * ADC_InitStruct)731 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
732 {
733 ErrorStatus status = SUCCESS;
734
735 /* Check the parameters */
736 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
737
738 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
739 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
740 assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
741
742 /* Note: Hardware constraint (refer to description of this function): */
743 /* ADC instance must be disabled. */
744 if (LL_ADC_IsEnabled(ADCx) == 0UL)
745 {
746 /* Configuration of ADC hierarchical scope: */
747 /* - ADC instance */
748 /* - Set ADC data resolution */
749 /* - Set ADC conversion data alignment */
750 /* - Set ADC low power mode */
751 MODIFY_REG(ADCx->CFGR,
752 ADC_CFGR_RES
753 | ADC_CFGR_ALIGN
754 | ADC_CFGR_AUTDLY
755 ,
756 ADC_InitStruct->Resolution
757 | ADC_InitStruct->DataAlignment
758 | ADC_InitStruct->LowPowerMode
759 );
760
761 }
762 else
763 {
764 /* Initialization error: ADC instance is not disabled. */
765 status = ERROR;
766 }
767
768 return status;
769 }
770
771 /**
772 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
773 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
774 * whose fields will be set to default values.
775 * @retval None
776 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * ADC_InitStruct)777 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
778 {
779 /* Set ADC_InitStruct fields to default values */
780 /* Set fields of ADC instance */
781 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
782 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
783 ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
784
785 }
786
787 /**
788 * @brief Initialize some features of ADC group regular.
789 * @note These parameters have an impact on ADC scope: ADC group regular.
790 * Refer to corresponding unitary functions into
791 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
792 * (functions with prefix "REG").
793 * @note The setting of these parameters by function @ref LL_ADC_Init()
794 * is conditioned to ADC state:
795 * ADC instance must be disabled.
796 * This condition is applied to all ADC features, for efficiency
797 * and compatibility over all STM32 families. However, the different
798 * features can be set under different ADC state conditions
799 * (setting possible with ADC enabled without conversion on going,
800 * ADC enabled with conversion on going, ...)
801 * Each feature can be updated afterwards with a unitary function
802 * and potentially with ADC in a different state than disabled,
803 * refer to description of each function for setting
804 * conditioned to ADC state.
805 * @note After using this function, other features must be configured
806 * using LL unitary functions.
807 * The minimum configuration remaining to be done is:
808 * - Set ADC group regular or group injected sequencer:
809 * map channel on the selected sequencer rank.
810 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
811 * - Set ADC channel sampling time
812 * Refer to function LL_ADC_SetChannelSamplingTime();
813 * @param ADCx ADC instance
814 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
815 * @retval An ErrorStatus enumeration value:
816 * - SUCCESS: ADC registers are initialized
817 * - ERROR: ADC registers are not initialized
818 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)819 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
820 {
821 ErrorStatus status = SUCCESS;
822
823 /* Check the parameters */
824 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
825 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
826 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
827 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
828 {
829 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
830
831 /* ADC group regular continuous mode and discontinuous mode */
832 /* can not be enabled simultenaeously */
833 assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
834 || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
835 }
836 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
837 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
838 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
839
840 /* Note: Hardware constraint (refer to description of this function): */
841 /* ADC instance must be disabled. */
842 if (LL_ADC_IsEnabled(ADCx) == 0UL)
843 {
844 /* Configuration of ADC hierarchical scope: */
845 /* - ADC group regular */
846 /* - Set ADC group regular trigger source */
847 /* - Set ADC group regular sequencer length */
848 /* - Set ADC group regular sequencer discontinuous mode */
849 /* - Set ADC group regular continuous mode */
850 /* - Set ADC group regular conversion data transfer: no transfer or */
851 /* transfer by DMA, and DMA requests mode */
852 /* - Set ADC group regular overrun behavior */
853 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
854 /* setting of trigger source to SW start. */
855 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
856 {
857 MODIFY_REG(ADCx->CFGR,
858 ADC_CFGR_EXTSEL
859 | ADC_CFGR_EXTEN
860 | ADC_CFGR_DISCEN
861 | ADC_CFGR_DISCNUM
862 | ADC_CFGR_CONT
863 | ADC_CFGR_DMAEN
864 | ADC_CFGR_DMACFG
865 | ADC_CFGR_OVRMOD
866 ,
867 ADC_REG_InitStruct->TriggerSource
868 | ADC_REG_InitStruct->SequencerDiscont
869 | ADC_REG_InitStruct->ContinuousMode
870 | ADC_REG_InitStruct->DMATransfer
871 | ADC_REG_InitStruct->Overrun
872 );
873 }
874 else
875 {
876 MODIFY_REG(ADCx->CFGR,
877 ADC_CFGR_EXTSEL
878 | ADC_CFGR_EXTEN
879 | ADC_CFGR_DISCEN
880 | ADC_CFGR_DISCNUM
881 | ADC_CFGR_CONT
882 | ADC_CFGR_DMAEN
883 | ADC_CFGR_DMACFG
884 | ADC_CFGR_OVRMOD
885 ,
886 ADC_REG_InitStruct->TriggerSource
887 | LL_ADC_REG_SEQ_DISCONT_DISABLE
888 | ADC_REG_InitStruct->ContinuousMode
889 | ADC_REG_InitStruct->DMATransfer
890 | ADC_REG_InitStruct->Overrun
891 );
892 }
893
894 /* Set ADC group regular sequencer length and scan direction */
895 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
896 }
897 else
898 {
899 /* Initialization error: ADC instance is not disabled. */
900 status = ERROR;
901 }
902 return status;
903 }
904
905 /**
906 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
907 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
908 * whose fields will be set to default values.
909 * @retval None
910 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)911 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
912 {
913 /* Set ADC_REG_InitStruct fields to default values */
914 /* Set fields of ADC group regular */
915 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
916 /* setting of trigger source to SW start. */
917 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
918 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
919 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
920 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
921 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
922 ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
923 }
924
925 /**
926 * @brief Initialize some features of ADC group injected.
927 * @note These parameters have an impact on ADC scope: ADC group injected.
928 * Refer to corresponding unitary functions into
929 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
930 * (functions with prefix "INJ").
931 * @note The setting of these parameters by function @ref LL_ADC_Init()
932 * is conditioned to ADC state:
933 * ADC instance must be disabled.
934 * This condition is applied to all ADC features, for efficiency
935 * and compatibility over all STM32 families. However, the different
936 * features can be set under different ADC state conditions
937 * (setting possible with ADC enabled without conversion on going,
938 * ADC enabled with conversion on going, ...)
939 * Each feature can be updated afterwards with a unitary function
940 * and potentially with ADC in a different state than disabled,
941 * refer to description of each function for setting
942 * conditioned to ADC state.
943 * @note After using this function, other features must be configured
944 * using LL unitary functions.
945 * The minimum configuration remaining to be done is:
946 * - Set ADC group injected sequencer:
947 * map channel on the selected sequencer rank.
948 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
949 * - Set ADC channel sampling time
950 * Refer to function LL_ADC_SetChannelSamplingTime();
951 * @note Caution if feature ADC group injected contexts queue is enabled
952 * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
953 * using successively several times this function will appear as
954 * having no effect.
955 * To set several features of ADC group injected, use
956 * function @ref LL_ADC_INJ_ConfigQueueContext().
957 * @param ADCx ADC instance
958 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
959 * @retval An ErrorStatus enumeration value:
960 * - SUCCESS: ADC registers are initialized
961 * - ERROR: ADC registers are not initialized
962 */
LL_ADC_INJ_Init(ADC_TypeDef * ADCx,LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)963 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
964 {
965 ErrorStatus status = SUCCESS;
966
967 /* Check the parameters */
968 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
969 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
970 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
971 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
972 {
973 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
974 }
975 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
976
977 /* Note: Hardware constraint (refer to description of this function): */
978 /* ADC instance must be disabled. */
979 if (LL_ADC_IsEnabled(ADCx) == 0UL)
980 {
981 /* Configuration of ADC hierarchical scope: */
982 /* - ADC group injected */
983 /* - Set ADC group injected trigger source */
984 /* - Set ADC group injected sequencer length */
985 /* - Set ADC group injected sequencer discontinuous mode */
986 /* - Set ADC group injected conversion trigger: independent or */
987 /* from ADC group regular */
988 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
989 /* setting of trigger source to SW start. */
990 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
991 {
992 MODIFY_REG(ADCx->CFGR,
993 ADC_CFGR_JDISCEN
994 | ADC_CFGR_JAUTO
995 ,
996 ADC_INJ_InitStruct->SequencerDiscont
997 | ADC_INJ_InitStruct->TrigAuto
998 );
999 }
1000 else
1001 {
1002 MODIFY_REG(ADCx->CFGR,
1003 ADC_CFGR_JDISCEN
1004 | ADC_CFGR_JAUTO
1005 ,
1006 LL_ADC_REG_SEQ_DISCONT_DISABLE
1007 | ADC_INJ_InitStruct->TrigAuto
1008 );
1009 }
1010
1011 MODIFY_REG(ADCx->JSQR,
1012 ADC_JSQR_JEXTSEL
1013 | ADC_JSQR_JEXTEN
1014 | ADC_JSQR_JL
1015 ,
1016 ADC_INJ_InitStruct->TriggerSource
1017 | ADC_INJ_InitStruct->SequencerLength
1018 );
1019 }
1020 else
1021 {
1022 /* Initialization error: ADC instance is not disabled. */
1023 status = ERROR;
1024 }
1025 return status;
1026 }
1027
1028 /**
1029 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
1030 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1031 * whose fields will be set to default values.
1032 * @retval None
1033 */
LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)1034 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1035 {
1036 /* Set ADC_INJ_InitStruct fields to default values */
1037 /* Set fields of ADC group injected */
1038 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
1039 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
1040 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
1041 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
1042 }
1043
1044 /**
1045 * @}
1046 */
1047
1048 /**
1049 * @}
1050 */
1051
1052 /**
1053 * @}
1054 */
1055
1056 #endif /* ADC1 || ADC2 || ADC3 */
1057
1058 /**
1059 * @}
1060 */
1061
1062 #endif /* USE_FULL_LL_DRIVER */
1063
