1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_pwr_ex.c
4 * @author MCD Application Team
5 * @brief Extended PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Extended Initialization and de-initialization functions
9 * + Extended Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2017 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 */
23
24 /* Includes ------------------------------------------------------------------*/
25 #include "stm32l4xx_hal.h"
26
27 /** @addtogroup STM32L4xx_HAL_Driver
28 * @{
29 */
30
31 /** @defgroup PWREx PWREx
32 * @brief PWR Extended HAL module driver
33 * @{
34 */
35
36 #ifdef HAL_PWR_MODULE_ENABLED
37
38 /* Private typedef -----------------------------------------------------------*/
39 /* Private define ------------------------------------------------------------*/
40
41 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
42 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */
43 #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
44 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */
45 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
46 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x00000003) /* PH0/PH1 */
47 #elif defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
48 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000FFFF) /* PH0..PH15 */
49 #endif
50
51 #if defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
52 #define PWR_PORTI_AVAILABLE_PINS ((uint32_t)0x00000FFF) /* PI0..PI11 */
53 #endif
54
55 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
56 * @{
57 */
58
59 /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
60 * @{
61 */
62 #define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */
63 #define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */
64 #define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */
65 #define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */
66 /**
67 * @}
68 */
69
70 /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
71 * @{
72 */
73 #define PWR_FLAG_SETTING_DELAY_US 50UL /*!< Time out value for REGLPF and VOSF flags setting */
74 /**
75 * @}
76 */
77
78
79
80 /**
81 * @}
82 */
83
84
85
86 /* Private macro -------------------------------------------------------------*/
87 /* Private variables ---------------------------------------------------------*/
88 /* Private function prototypes -----------------------------------------------*/
89 /* Exported functions --------------------------------------------------------*/
90
91 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
92 * @{
93 */
94
95 /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
96 * @brief Extended Peripheral Control functions
97 *
98 @verbatim
99 ===============================================================================
100 ##### Extended Peripheral Initialization and de-initialization functions #####
101 ===============================================================================
102 [..]
103
104 @endverbatim
105 * @{
106 */
107
108
109 /**
110 * @brief Return Voltage Scaling Range.
111 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
112 * or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
113 */
HAL_PWREx_GetVoltageRange(void)114 uint32_t HAL_PWREx_GetVoltageRange(void)
115 {
116 #if defined(PWR_CR5_R1MODE)
117 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
118 {
119 return PWR_REGULATOR_VOLTAGE_SCALE2;
120 }
121 else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE)
122 {
123 /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */
124 return PWR_REGULATOR_VOLTAGE_SCALE1;
125 }
126 else
127 {
128 return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
129 }
130 #else
131 return (PWR->CR1 & PWR_CR1_VOS);
132 #endif
133 }
134
135
136
137 /**
138 * @brief Configure the main internal regulator output voltage.
139 * @param VoltageScaling specifies the regulator output voltage to achieve
140 * a tradeoff between performance and power consumption.
141 * This parameter can be one of the following values:
142 @if STM32L4S9xx
143 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode,
144 * typical output voltage at 1.2 V,
145 * system frequency up to 120 MHz.
146 @endif
147 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
148 * typical output voltage at 1.2 V,
149 * system frequency up to 80 MHz.
150 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
151 * typical output voltage at 1.0 V,
152 * system frequency up to 26 MHz.
153 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
154 * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
155 * When moving from Range 2 to Range 1, the system frequency can be increased to
156 * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API. For
157 * some devices, the system frequency can be increased up to 120 MHz.
158 * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be
159 * cleared before returning the status. If the flag is not cleared within
160 * 50 microseconds, HAL_TIMEOUT status is reported.
161 * @retval HAL Status
162 */
HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)163 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
164 {
165 uint32_t wait_loop_index;
166
167 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
168
169 #if defined(PWR_CR5_R1MODE)
170 if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)
171 {
172 /* If current range is range 2 */
173 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
174 {
175 /* Make sure Range 1 Boost is enabled */
176 CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
177
178 /* Set Range 1 */
179 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
180
181 /* Wait until VOSF is cleared */
182 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1;
183 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
184 {
185 wait_loop_index--;
186 }
187 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
188 {
189 return HAL_TIMEOUT;
190 }
191 }
192 /* If current range is range 1 normal or boost mode */
193 else
194 {
195 /* Enable Range 1 Boost (no issue if bit already reset) */
196 CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
197 }
198 }
199 else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
200 {
201 /* If current range is range 2 */
202 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
203 {
204 /* Make sure Range 1 Boost is disabled */
205 SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
206
207 /* Set Range 1 */
208 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
209
210 /* Wait until VOSF is cleared */
211 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1;
212 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
213 {
214 wait_loop_index--;
215 }
216 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
217 {
218 return HAL_TIMEOUT;
219 }
220 }
221 /* If current range is range 1 normal or boost mode */
222 else
223 {
224 /* Disable Range 1 Boost (no issue if bit already set) */
225 SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
226 }
227 }
228 else
229 {
230 /* Set Range 2 */
231 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
232 /* No need to wait for VOSF to be cleared for this transition */
233 /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */
234 }
235
236 #else
237
238 /* If Set Range 1 */
239 if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
240 {
241 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
242 {
243 /* Set Range 1 */
244 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
245
246 /* Wait until VOSF is cleared */
247 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
248 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
249 {
250 wait_loop_index--;
251 }
252 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
253 {
254 return HAL_TIMEOUT;
255 }
256 }
257 }
258 else
259 {
260 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
261 {
262 /* Set Range 2 */
263 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
264 /* No need to wait for VOSF to be cleared for this transition */
265 }
266 }
267 #endif
268
269 return HAL_OK;
270 }
271
272
273 /**
274 * @brief Enable battery charging.
275 * When VDD is present, charge the external battery on VBAT thru an internal resistor.
276 * @param ResistorSelection specifies the resistor impedance.
277 * This parameter can be one of the following values:
278 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
279 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
280 * @retval None
281 */
HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)282 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
283 {
284 assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
285
286 /* Specify resistor selection */
287 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
288
289 /* Enable battery charging */
290 SET_BIT(PWR->CR4, PWR_CR4_VBE);
291 }
292
293
294 /**
295 * @brief Disable battery charging.
296 * @retval None
297 */
HAL_PWREx_DisableBatteryCharging(void)298 void HAL_PWREx_DisableBatteryCharging(void)
299 {
300 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
301 }
302
303
304 #if defined(PWR_CR2_USV)
305 /**
306 * @brief Enable VDDUSB supply.
307 * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
308 * @retval None
309 */
HAL_PWREx_EnableVddUSB(void)310 void HAL_PWREx_EnableVddUSB(void)
311 {
312 SET_BIT(PWR->CR2, PWR_CR2_USV);
313 }
314
315
316 /**
317 * @brief Disable VDDUSB supply.
318 * @retval None
319 */
HAL_PWREx_DisableVddUSB(void)320 void HAL_PWREx_DisableVddUSB(void)
321 {
322 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
323 }
324 #endif /* PWR_CR2_USV */
325
326 #if defined(PWR_CR2_IOSV)
327 /**
328 * @brief Enable VDDIO2 supply.
329 * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present.
330 * @retval None
331 */
HAL_PWREx_EnableVddIO2(void)332 void HAL_PWREx_EnableVddIO2(void)
333 {
334 SET_BIT(PWR->CR2, PWR_CR2_IOSV);
335 }
336
337
338 /**
339 * @brief Disable VDDIO2 supply.
340 * @retval None
341 */
HAL_PWREx_DisableVddIO2(void)342 void HAL_PWREx_DisableVddIO2(void)
343 {
344 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
345 }
346 #endif /* PWR_CR2_IOSV */
347
348
349 /**
350 * @brief Enable Internal Wake-up Line.
351 * @retval None
352 */
HAL_PWREx_EnableInternalWakeUpLine(void)353 void HAL_PWREx_EnableInternalWakeUpLine(void)
354 {
355 SET_BIT(PWR->CR3, PWR_CR3_EIWF);
356 }
357
358
359 /**
360 * @brief Disable Internal Wake-up Line.
361 * @retval None
362 */
HAL_PWREx_DisableInternalWakeUpLine(void)363 void HAL_PWREx_DisableInternalWakeUpLine(void)
364 {
365 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
366 }
367
368
369
370 /**
371 * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
372 * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in
373 * pull-up state in Standby and Shutdown modes.
374 * @note This state is effective in Standby and Shutdown modes only if APC bit
375 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
376 * @note The configuration is lost when exiting the Shutdown mode due to the
377 * power-on reset, maintained when exiting the Standby mode.
378 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
379 * PDy bit of PWR_PDCRx register is cleared unless it is reserved.
380 * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input
381 * parameter at the same time are set.
382 * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
383 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
384 * @param GPIONumber Specify the I/O pins numbers.
385 * This parameter can be one of the following values:
386 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
387 * I/O pins are available) or the logical OR of several of them to set
388 * several bits for a given port in a single API call.
389 * @retval HAL Status
390 */
HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)391 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
392 {
393 HAL_StatusTypeDef status = HAL_OK;
394
395 assert_param(IS_PWR_GPIO(GPIO));
396 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
397
398 switch (GPIO)
399 {
400 case PWR_GPIO_A:
401 SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
402 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
403 break;
404 case PWR_GPIO_B:
405 SET_BIT(PWR->PUCRB, GPIONumber);
406 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
407 break;
408 case PWR_GPIO_C:
409 SET_BIT(PWR->PUCRC, GPIONumber);
410 CLEAR_BIT(PWR->PDCRC, GPIONumber);
411 break;
412 #if defined(GPIOD)
413 case PWR_GPIO_D:
414 SET_BIT(PWR->PUCRD, GPIONumber);
415 CLEAR_BIT(PWR->PDCRD, GPIONumber);
416 break;
417 #endif
418 #if defined(GPIOE)
419 case PWR_GPIO_E:
420 SET_BIT(PWR->PUCRE, GPIONumber);
421 CLEAR_BIT(PWR->PDCRE, GPIONumber);
422 break;
423 #endif
424 #if defined(GPIOF)
425 case PWR_GPIO_F:
426 SET_BIT(PWR->PUCRF, GPIONumber);
427 CLEAR_BIT(PWR->PDCRF, GPIONumber);
428 break;
429 #endif
430 #if defined(GPIOG)
431 case PWR_GPIO_G:
432 SET_BIT(PWR->PUCRG, GPIONumber);
433 CLEAR_BIT(PWR->PDCRG, GPIONumber);
434 break;
435 #endif
436 case PWR_GPIO_H:
437 SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
438 #if defined (STM32L496xx) || defined (STM32L4A6xx)
439 CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));
440 #else
441 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
442 #endif
443 break;
444 #if defined(GPIOI)
445 case PWR_GPIO_I:
446 SET_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
447 CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
448 break;
449 #endif
450 default:
451 status = HAL_ERROR;
452 break;
453 }
454
455 return status;
456 }
457
458
459 /**
460 * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
461 * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
462 * in pull-up state in Standby and Shutdown modes.
463 * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input
464 * parameter at the same time are reset.
465 * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
466 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
467 * @param GPIONumber Specify the I/O pins numbers.
468 * This parameter can be one of the following values:
469 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
470 * I/O pins are available) or the logical OR of several of them to reset
471 * several bits for a given port in a single API call.
472 * @retval HAL Status
473 */
HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)474 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
475 {
476 HAL_StatusTypeDef status = HAL_OK;
477
478 assert_param(IS_PWR_GPIO(GPIO));
479 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
480
481 switch (GPIO)
482 {
483 case PWR_GPIO_A:
484 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
485 break;
486 case PWR_GPIO_B:
487 CLEAR_BIT(PWR->PUCRB, GPIONumber);
488 break;
489 case PWR_GPIO_C:
490 CLEAR_BIT(PWR->PUCRC, GPIONumber);
491 break;
492 #if defined(GPIOD)
493 case PWR_GPIO_D:
494 CLEAR_BIT(PWR->PUCRD, GPIONumber);
495 break;
496 #endif
497 #if defined(GPIOE)
498 case PWR_GPIO_E:
499 CLEAR_BIT(PWR->PUCRE, GPIONumber);
500 break;
501 #endif
502 #if defined(GPIOF)
503 case PWR_GPIO_F:
504 CLEAR_BIT(PWR->PUCRF, GPIONumber);
505 break;
506 #endif
507 #if defined(GPIOG)
508 case PWR_GPIO_G:
509 CLEAR_BIT(PWR->PUCRG, GPIONumber);
510 break;
511 #endif
512 case PWR_GPIO_H:
513 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
514 break;
515 #if defined(GPIOI)
516 case PWR_GPIO_I:
517 CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
518 break;
519 #endif
520 default:
521 status = HAL_ERROR;
522 break;
523 }
524
525 return status;
526 }
527
528
529
530 /**
531 * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
532 * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in
533 * pull-down state in Standby and Shutdown modes.
534 * @note This state is effective in Standby and Shutdown modes only if APC bit
535 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
536 * @note The configuration is lost when exiting the Shutdown mode due to the
537 * power-on reset, maintained when exiting the Standby mode.
538 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
539 * PUy bit of PWR_PUCRx register is cleared unless it is reserved.
540 * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input
541 * parameter at the same time are set.
542 * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
543 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
544 * @param GPIONumber Specify the I/O pins numbers.
545 * This parameter can be one of the following values:
546 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
547 * I/O pins are available) or the logical OR of several of them to set
548 * several bits for a given port in a single API call.
549 * @retval HAL Status
550 */
HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)551 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
552 {
553 HAL_StatusTypeDef status = HAL_OK;
554
555 assert_param(IS_PWR_GPIO(GPIO));
556 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
557
558 switch (GPIO)
559 {
560 case PWR_GPIO_A:
561 SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
562 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
563 break;
564 case PWR_GPIO_B:
565 SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
566 CLEAR_BIT(PWR->PUCRB, GPIONumber);
567 break;
568 case PWR_GPIO_C:
569 SET_BIT(PWR->PDCRC, GPIONumber);
570 CLEAR_BIT(PWR->PUCRC, GPIONumber);
571 break;
572 #if defined(GPIOD)
573 case PWR_GPIO_D:
574 SET_BIT(PWR->PDCRD, GPIONumber);
575 CLEAR_BIT(PWR->PUCRD, GPIONumber);
576 break;
577 #endif
578 #if defined(GPIOE)
579 case PWR_GPIO_E:
580 SET_BIT(PWR->PDCRE, GPIONumber);
581 CLEAR_BIT(PWR->PUCRE, GPIONumber);
582 break;
583 #endif
584 #if defined(GPIOF)
585 case PWR_GPIO_F:
586 SET_BIT(PWR->PDCRF, GPIONumber);
587 CLEAR_BIT(PWR->PUCRF, GPIONumber);
588 break;
589 #endif
590 #if defined(GPIOG)
591 case PWR_GPIO_G:
592 SET_BIT(PWR->PDCRG, GPIONumber);
593 CLEAR_BIT(PWR->PUCRG, GPIONumber);
594 break;
595 #endif
596 case PWR_GPIO_H:
597 #if defined (STM32L496xx) || defined (STM32L4A6xx)
598 SET_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));
599 #else
600 SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
601 #endif
602 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
603 break;
604 #if defined(GPIOI)
605 case PWR_GPIO_I:
606 SET_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
607 CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
608 break;
609 #endif
610 default:
611 status = HAL_ERROR;
612 break;
613 }
614
615 return status;
616 }
617
618
619 /**
620 * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
621 * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
622 * in pull-down state in Standby and Shutdown modes.
623 * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input
624 * parameter at the same time are reset.
625 * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
626 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral.
627 * @param GPIONumber Specify the I/O pins numbers.
628 * This parameter can be one of the following values:
629 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less
630 * I/O pins are available) or the logical OR of several of them to reset
631 * several bits for a given port in a single API call.
632 * @retval HAL Status
633 */
HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)634 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
635 {
636 HAL_StatusTypeDef status = HAL_OK;
637
638 assert_param(IS_PWR_GPIO(GPIO));
639 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
640
641 switch (GPIO)
642 {
643 case PWR_GPIO_A:
644 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
645 break;
646 case PWR_GPIO_B:
647 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
648 break;
649 case PWR_GPIO_C:
650 CLEAR_BIT(PWR->PDCRC, GPIONumber);
651 break;
652 #if defined(GPIOD)
653 case PWR_GPIO_D:
654 CLEAR_BIT(PWR->PDCRD, GPIONumber);
655 break;
656 #endif
657 #if defined(GPIOE)
658 case PWR_GPIO_E:
659 CLEAR_BIT(PWR->PDCRE, GPIONumber);
660 break;
661 #endif
662 #if defined(GPIOF)
663 case PWR_GPIO_F:
664 CLEAR_BIT(PWR->PDCRF, GPIONumber);
665 break;
666 #endif
667 #if defined(GPIOG)
668 case PWR_GPIO_G:
669 CLEAR_BIT(PWR->PDCRG, GPIONumber);
670 break;
671 #endif
672 case PWR_GPIO_H:
673 #if defined (STM32L496xx) || defined (STM32L4A6xx)
674 CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3))));
675 #else
676 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
677 #endif
678 break;
679 #if defined(GPIOI)
680 case PWR_GPIO_I:
681 CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS));
682 break;
683 #endif
684 default:
685 status = HAL_ERROR;
686 break;
687 }
688
689 return status;
690 }
691
692
693
694 /**
695 * @brief Enable pull-up and pull-down configuration.
696 * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in
697 * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
698 * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
699 * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
700 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there
701 * is no conflict when setting PUy or PDy bit.
702 * @retval None
703 */
HAL_PWREx_EnablePullUpPullDownConfig(void)704 void HAL_PWREx_EnablePullUpPullDownConfig(void)
705 {
706 SET_BIT(PWR->CR3, PWR_CR3_APC);
707 }
708
709
710 /**
711 * @brief Disable pull-up and pull-down configuration.
712 * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
713 * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
714 * @retval None
715 */
HAL_PWREx_DisablePullUpPullDownConfig(void)716 void HAL_PWREx_DisablePullUpPullDownConfig(void)
717 {
718 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
719 }
720
721
722
723 /**
724 * @brief Enable Full SRAM2 content retention in Standby mode.
725 * @retval None
726 */
HAL_PWREx_EnableSRAM2ContentRetention(void)727 void HAL_PWREx_EnableSRAM2ContentRetention(void)
728 {
729 (void) HAL_PWREx_SetSRAM2ContentRetention(PWR_FULL_SRAM2_RETENTION);
730 }
731
732 /**
733 * @brief Disable SRAM2 content retention in Standby mode.
734 * @retval None
735 */
HAL_PWREx_DisableSRAM2ContentRetention(void)736 void HAL_PWREx_DisableSRAM2ContentRetention(void)
737 {
738 (void) HAL_PWREx_SetSRAM2ContentRetention(PWR_NO_SRAM2_RETENTION);
739 }
740
741 /**
742 * @brief Enable SRAM2 content retention in Standby mode.
743 * @param SRAM2Size: specifies the SRAM2 size kept in Standby mode
744 * This parameter can be one of the following values:
745 * @arg @ref PWR_NO_SRAM2_RETENTION SRAM2 is powered off in Standby mode (SRAM2 content is lost)
746 * @arg @ref PWR_FULL_SRAM2_RETENTION Full SRAM2 is powered by the low-power regulator in Standby mode
747 * @arg @ref PWR_4KBYTES_SRAM2_RETENTION Only 4 Kbytes of SRAM2 is powered by the low-power regulator in Standby mode
748 * @note PWR_4KBYTES_SRAM2_RETENTION parameter is not available on all devices
749 * @retval HAL Status
750 */
HAL_PWREx_SetSRAM2ContentRetention(uint32_t SRAM2Size)751 HAL_StatusTypeDef HAL_PWREx_SetSRAM2ContentRetention(uint32_t SRAM2Size)
752 {
753 assert_param(IS_PWR_SRAM2_RETENTION(SRAM2Size));
754
755 if (SRAM2Size == PWR_NO_SRAM2_RETENTION)
756 {
757 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
758 }
759 else if (SRAM2Size == PWR_FULL_SRAM2_RETENTION)
760 {
761 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, PWR_FULL_SRAM2_RETENTION);
762 }
763 #if defined(PWR_CR3_RRS_1)
764 else if (SRAM2Size == PWR_4KBYTES_SRAM2_RETENTION)
765 {
766 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, PWR_4KBYTES_SRAM2_RETENTION);
767 }
768 #endif /* PWR_CR3_RRS_1 */
769 else {
770 return HAL_ERROR;
771 }
772
773 return HAL_OK;
774 }
775
776
777 #if defined(PWR_CR3_ENULP)
778 /**
779 * @brief Enable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes.
780 * @note All the other modes are not affected by this bit.
781 * @retval None
782 */
HAL_PWREx_EnableBORPVD_ULP(void)783 void HAL_PWREx_EnableBORPVD_ULP(void)
784 {
785 SET_BIT(PWR->CR3, PWR_CR3_ENULP);
786 }
787
788
789 /**
790 * @brief Disable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes.
791 * @note All the other modes are not affected by this bit
792 * @retval None
793 */
HAL_PWREx_DisableBORPVD_ULP(void)794 void HAL_PWREx_DisableBORPVD_ULP(void)
795 {
796 CLEAR_BIT(PWR->CR3, PWR_CR3_ENULP);
797 }
798 #endif /* PWR_CR3_ENULP */
799
800
801 #if defined(PWR_CR4_EXT_SMPS_ON)
802 /**
803 * @brief Enable the CFLDO working @ 0.95V.
804 * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the
805 * internal CFLDO can be reduced to 0.95V.
806 * @retval None
807 */
HAL_PWREx_EnableExtSMPS_0V95(void)808 void HAL_PWREx_EnableExtSMPS_0V95(void)
809 {
810 SET_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);
811 }
812
813 /**
814 * @brief Disable the CFLDO working @ 0.95V
815 * @note Before SMPS is switched off, the regulated voltage of the
816 * internal CFLDO shall be set to 1.00V.
817 * 1.00V. is also default operating Range 2 voltage.
818 * @retval None
819 */
HAL_PWREx_DisableExtSMPS_0V95(void)820 void HAL_PWREx_DisableExtSMPS_0V95(void)
821 {
822 CLEAR_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);
823 }
824 #endif /* PWR_CR4_EXT_SMPS_ON */
825
826
827 #if defined(PWR_CR1_RRSTP)
828 /**
829 * @brief Enable SRAM3 content retention in Stop 2 mode.
830 * @note When RRSTP bit is set, SRAM3 is powered by the low-power regulator in
831 * Stop 2 mode and its content is kept.
832 * @retval None
833 */
HAL_PWREx_EnableSRAM3ContentRetention(void)834 void HAL_PWREx_EnableSRAM3ContentRetention(void)
835 {
836 SET_BIT(PWR->CR1, PWR_CR1_RRSTP);
837 }
838
839
840 /**
841 * @brief Disable SRAM3 content retention in Stop 2 mode.
842 * @note When RRSTP bit is reset, SRAM3 is powered off in Stop 2 mode
843 * and its content is lost.
844 * @retval None
845 */
HAL_PWREx_DisableSRAM3ContentRetention(void)846 void HAL_PWREx_DisableSRAM3ContentRetention(void)
847 {
848 CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP);
849 }
850 #endif /* PWR_CR1_RRSTP */
851
852 #if defined(PWR_CR3_DSIPDEN)
853 /**
854 * @brief Enable pull-down activation on DSI pins.
855 * @retval None
856 */
HAL_PWREx_EnableDSIPinsPDActivation(void)857 void HAL_PWREx_EnableDSIPinsPDActivation(void)
858 {
859 SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN);
860 }
861
862
863 /**
864 * @brief Disable pull-down activation on DSI pins.
865 * @retval None
866 */
HAL_PWREx_DisableDSIPinsPDActivation(void)867 void HAL_PWREx_DisableDSIPinsPDActivation(void)
868 {
869 CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN);
870 }
871 #endif /* PWR_CR3_DSIPDEN */
872
873 #if defined(PWR_CR2_PVME1)
874 /**
875 * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
876 * @retval None
877 */
HAL_PWREx_EnablePVM1(void)878 void HAL_PWREx_EnablePVM1(void)
879 {
880 SET_BIT(PWR->CR2, PWR_PVM_1);
881 }
882
883 /**
884 * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
885 * @retval None
886 */
HAL_PWREx_DisablePVM1(void)887 void HAL_PWREx_DisablePVM1(void)
888 {
889 CLEAR_BIT(PWR->CR2, PWR_PVM_1);
890 }
891 #endif /* PWR_CR2_PVME1 */
892
893
894 #if defined(PWR_CR2_PVME2)
895 /**
896 * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
897 * @retval None
898 */
HAL_PWREx_EnablePVM2(void)899 void HAL_PWREx_EnablePVM2(void)
900 {
901 SET_BIT(PWR->CR2, PWR_PVM_2);
902 }
903
904 /**
905 * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
906 * @retval None
907 */
HAL_PWREx_DisablePVM2(void)908 void HAL_PWREx_DisablePVM2(void)
909 {
910 CLEAR_BIT(PWR->CR2, PWR_PVM_2);
911 }
912 #endif /* PWR_CR2_PVME2 */
913
914
915 /**
916 * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
917 * @retval None
918 */
HAL_PWREx_EnablePVM3(void)919 void HAL_PWREx_EnablePVM3(void)
920 {
921 SET_BIT(PWR->CR2, PWR_PVM_3);
922 }
923
924 /**
925 * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
926 * @retval None
927 */
HAL_PWREx_DisablePVM3(void)928 void HAL_PWREx_DisablePVM3(void)
929 {
930 CLEAR_BIT(PWR->CR2, PWR_PVM_3);
931 }
932
933
934 /**
935 * @brief Enable the Power Voltage Monitoring 4: VDDA versus 2.2V.
936 * @retval None
937 */
HAL_PWREx_EnablePVM4(void)938 void HAL_PWREx_EnablePVM4(void)
939 {
940 SET_BIT(PWR->CR2, PWR_PVM_4);
941 }
942
943 /**
944 * @brief Disable the Power Voltage Monitoring 4: VDDA versus 2.2V.
945 * @retval None
946 */
HAL_PWREx_DisablePVM4(void)947 void HAL_PWREx_DisablePVM4(void)
948 {
949 CLEAR_BIT(PWR->CR2, PWR_PVM_4);
950 }
951
952
953
954
955 /**
956 * @brief Configure the Peripheral Voltage Monitoring (PVM).
957 * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
958 * PVM configuration information.
959 * @note The API configures a single PVM according to the information contained
960 * in the input structure. To configure several PVMs, the API must be singly
961 * called for each PVM used.
962 * @note Refer to the electrical characteristics of your device datasheet for
963 * more details about the voltage thresholds corresponding to each
964 * detection level and to each monitored supply.
965 * @retval HAL status
966 */
HAL_PWREx_ConfigPVM(PWR_PVMTypeDef * sConfigPVM)967 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
968 {
969 HAL_StatusTypeDef status = HAL_OK;
970
971 /* Check the parameters */
972 assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
973 assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
974
975
976 /* Configure EXTI 35 to 38 interrupts if so required:
977 scan thru PVMType to detect which PVMx is set and
978 configure the corresponding EXTI line accordingly. */
979 switch (sConfigPVM->PVMType)
980 {
981 #if defined(PWR_CR2_PVME1)
982 case PWR_PVM_1:
983 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
984 __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
985 __HAL_PWR_PVM1_EXTI_DISABLE_IT();
986 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
987 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
988
989 /* Configure interrupt mode */
990 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
991 {
992 __HAL_PWR_PVM1_EXTI_ENABLE_IT();
993 }
994
995 /* Configure event mode */
996 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
997 {
998 __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
999 }
1000
1001 /* Configure the edge */
1002 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1003 {
1004 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
1005 }
1006
1007 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1008 {
1009 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
1010 }
1011 break;
1012 #endif /* PWR_CR2_PVME1 */
1013
1014 #if defined(PWR_CR2_PVME2)
1015 case PWR_PVM_2:
1016 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
1017 __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
1018 __HAL_PWR_PVM2_EXTI_DISABLE_IT();
1019 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();
1020 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
1021
1022 /* Configure interrupt mode */
1023 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1024 {
1025 __HAL_PWR_PVM2_EXTI_ENABLE_IT();
1026 }
1027
1028 /* Configure event mode */
1029 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1030 {
1031 __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
1032 }
1033
1034 /* Configure the edge */
1035 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1036 {
1037 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
1038 }
1039
1040 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1041 {
1042 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
1043 }
1044 break;
1045 #endif /* PWR_CR2_PVME2 */
1046
1047 case PWR_PVM_3:
1048 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
1049 __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
1050 __HAL_PWR_PVM3_EXTI_DISABLE_IT();
1051 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
1052 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
1053
1054 /* Configure interrupt mode */
1055 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1056 {
1057 __HAL_PWR_PVM3_EXTI_ENABLE_IT();
1058 }
1059
1060 /* Configure event mode */
1061 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1062 {
1063 __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
1064 }
1065
1066 /* Configure the edge */
1067 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1068 {
1069 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
1070 }
1071
1072 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1073 {
1074 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
1075 }
1076 break;
1077
1078 case PWR_PVM_4:
1079 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
1080 __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
1081 __HAL_PWR_PVM4_EXTI_DISABLE_IT();
1082 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();
1083 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
1084
1085 /* Configure interrupt mode */
1086 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
1087 {
1088 __HAL_PWR_PVM4_EXTI_ENABLE_IT();
1089 }
1090
1091 /* Configure event mode */
1092 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
1093 {
1094 __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
1095 }
1096
1097 /* Configure the edge */
1098 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
1099 {
1100 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
1101 }
1102
1103 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
1104 {
1105 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
1106 }
1107 break;
1108
1109 default:
1110 status = HAL_ERROR;
1111 break;
1112 }
1113
1114 return status;
1115 }
1116
1117
1118
1119 /**
1120 * @brief Enter Low-power Run mode
1121 * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode.
1122 * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
1123 * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.
1124 * Additionally, the clock frequency must be reduced below 2 MHz.
1125 * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must
1126 * be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
1127 * @retval None
1128 */
HAL_PWREx_EnableLowPowerRunMode(void)1129 void HAL_PWREx_EnableLowPowerRunMode(void)
1130 {
1131 /* Set Regulator parameter */
1132 SET_BIT(PWR->CR1, PWR_CR1_LPR);
1133 }
1134
1135
1136 /**
1137 * @brief Exit Low-power Run mode.
1138 * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
1139 * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
1140 * returns HAL_TIMEOUT status). The system clock frequency can then be
1141 * increased above 2 MHz.
1142 * @retval HAL Status
1143 */
HAL_PWREx_DisableLowPowerRunMode(void)1144 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
1145 {
1146 uint32_t wait_loop_index;
1147
1148 /* Clear LPR bit */
1149 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
1150
1151 /* Wait until REGLPF is reset */
1152 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
1153 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))
1154 {
1155 wait_loop_index--;
1156 }
1157 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
1158 {
1159 return HAL_TIMEOUT;
1160 }
1161
1162 return HAL_OK;
1163 }
1164
1165
1166 /**
1167 * @brief Enter Stop 0 mode.
1168 * @note In Stop 0 mode, main and low voltage regulators are ON.
1169 * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode.
1170 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
1171 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
1172 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
1173 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
1174 * only to the peripheral requesting it.
1175 * SRAM1, SRAM2 and register contents are preserved.
1176 * The BOR is available.
1177 * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
1178 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
1179 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
1180 * @note By keeping the internal regulator ON during Stop 0 mode, the consumption
1181 * is higher although the startup time is reduced.
1182 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
1183 * This parameter can be one of the following values:
1184 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
1185 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
1186 * @retval None
1187 */
HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)1188 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
1189 {
1190 /* Check the parameters */
1191 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
1192
1193 /* Stop 0 mode with Main Regulator */
1194 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);
1195
1196 /* Set SLEEPDEEP bit of Cortex System Control Register */
1197 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1198
1199 /* Select Stop mode entry --------------------------------------------------*/
1200 if(STOPEntry == PWR_STOPENTRY_WFI)
1201 {
1202 /* Request Wait For Interrupt */
1203 __WFI();
1204 }
1205 else
1206 {
1207 /* Request Wait For Event */
1208 __SEV();
1209 __WFE();
1210 __WFE();
1211 }
1212
1213 /* Reset SLEEPDEEP bit of Cortex System Control Register */
1214 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1215 }
1216
1217
1218 /**
1219 * @brief Enter Stop 1 mode.
1220 * @note In Stop 1 mode, only low power voltage regulator is ON.
1221 * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode.
1222 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
1223 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
1224 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
1225 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
1226 * only to the peripheral requesting it.
1227 * SRAM1, SRAM2 and register contents are preserved.
1228 * The BOR is available.
1229 * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
1230 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
1231 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
1232 * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
1233 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
1234 * This parameter can be one of the following values:
1235 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
1236 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
1237 * @retval None
1238 */
HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)1239 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
1240 {
1241 /* Check the parameters */
1242 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
1243
1244 /* Stop 1 mode with Low-Power Regulator */
1245 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);
1246
1247 /* Set SLEEPDEEP bit of Cortex System Control Register */
1248 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1249
1250 /* Select Stop mode entry --------------------------------------------------*/
1251 if(STOPEntry == PWR_STOPENTRY_WFI)
1252 {
1253 /* Request Wait For Interrupt */
1254 __WFI();
1255 }
1256 else
1257 {
1258 /* Request Wait For Event */
1259 __SEV();
1260 __WFE();
1261 __WFE();
1262 }
1263
1264 /* Reset SLEEPDEEP bit of Cortex System Control Register */
1265 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1266 }
1267
1268
1269 /**
1270 * @brief Enter Stop 2 mode.
1271 * @note In Stop 2 mode, only low power voltage regulator is ON.
1272 * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode.
1273 * @note All clocks in the VCORE domain are stopped, the PLL, the MSI,
1274 * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability
1275 * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after
1276 * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only
1277 * to the peripheral requesting it.
1278 * SRAM1, SRAM2 and register contents are preserved.
1279 * SRAM3 content is preserved depending on RRSTP bit setting (not available on all devices).
1280 * The BOR is available.
1281 * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.
1282 * Otherwise, Stop 1 mode is entered.
1283 * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event,
1284 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
1285 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
1286 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
1287 * This parameter can be one of the following values:
1288 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
1289 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
1290 * @retval None
1291 */
HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)1292 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
1293 {
1294 /* Check the parameter */
1295 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
1296
1297 /* Set Stop mode 2 */
1298 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2);
1299
1300 /* Set SLEEPDEEP bit of Cortex System Control Register */
1301 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1302
1303 /* Select Stop mode entry --------------------------------------------------*/
1304 if(STOPEntry == PWR_STOPENTRY_WFI)
1305 {
1306 /* Request Wait For Interrupt */
1307 __WFI();
1308 }
1309 else
1310 {
1311 /* Request Wait For Event */
1312 __SEV();
1313 __WFE();
1314 __WFE();
1315 }
1316
1317 /* Reset SLEEPDEEP bit of Cortex System Control Register */
1318 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1319 }
1320
1321
1322
1323
1324
1325 /**
1326 * @brief Enter Shutdown mode.
1327 * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched
1328 * off. The voltage regulator is disabled and Vcore domain is powered off.
1329 * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
1330 * The BOR is not available.
1331 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
1332 * @retval None
1333 */
HAL_PWREx_EnterSHUTDOWNMode(void)1334 void HAL_PWREx_EnterSHUTDOWNMode(void)
1335 {
1336
1337 /* Set Shutdown mode */
1338 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
1339
1340 /* Set SLEEPDEEP bit of Cortex System Control Register */
1341 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1342
1343 /* This option is used to ensure that store operations are completed */
1344 #if defined ( __CC_ARM)
1345 __force_stores();
1346 #endif
1347 /* Request Wait For Interrupt */
1348 __WFI();
1349 }
1350
1351
1352
1353
1354 /**
1355 * @brief This function handles the PWR PVD/PVMx interrupt request.
1356 * @note This API should be called under the PVD_PVM_IRQHandler().
1357 * @retval None
1358 */
HAL_PWREx_PVD_PVM_IRQHandler(void)1359 void HAL_PWREx_PVD_PVM_IRQHandler(void)
1360 {
1361 /* Check PWR exti flag */
1362 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != 0x0U)
1363 {
1364 /* PWR PVD interrupt user callback */
1365 HAL_PWR_PVDCallback();
1366
1367 /* Clear PVD exti pending bit */
1368 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
1369 }
1370 /* Next, successively check PVMx exti flags */
1371 #if defined(PWR_CR2_PVME1)
1372 if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0x0U)
1373 {
1374 /* PWR PVM1 interrupt user callback */
1375 HAL_PWREx_PVM1Callback();
1376
1377 /* Clear PVM1 exti pending bit */
1378 __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
1379 }
1380 #endif /* PWR_CR2_PVME1 */
1381 #if defined(PWR_CR2_PVME2)
1382 if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != 0x0U)
1383 {
1384 /* PWR PVM2 interrupt user callback */
1385 HAL_PWREx_PVM2Callback();
1386
1387 /* Clear PVM2 exti pending bit */
1388 __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();
1389 }
1390 #endif /* PWR_CR2_PVME2 */
1391 if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0x0U)
1392 {
1393 /* PWR PVM3 interrupt user callback */
1394 HAL_PWREx_PVM3Callback();
1395
1396 /* Clear PVM3 exti pending bit */
1397 __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
1398 }
1399 if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != 0x0U)
1400 {
1401 /* PWR PVM4 interrupt user callback */
1402 HAL_PWREx_PVM4Callback();
1403
1404 /* Clear PVM4 exti pending bit */
1405 __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
1406 }
1407 }
1408
1409
1410 #if defined(PWR_CR2_PVME1)
1411 /**
1412 * @brief PWR PVM1 interrupt callback
1413 * @retval None
1414 */
HAL_PWREx_PVM1Callback(void)1415 __weak void HAL_PWREx_PVM1Callback(void)
1416 {
1417 /* NOTE : This function should not be modified; when the callback is needed,
1418 HAL_PWREx_PVM1Callback() API can be implemented in the user file
1419 */
1420 }
1421 #endif /* PWR_CR2_PVME1 */
1422
1423 #if defined(PWR_CR2_PVME2)
1424 /**
1425 * @brief PWR PVM2 interrupt callback
1426 * @retval None
1427 */
HAL_PWREx_PVM2Callback(void)1428 __weak void HAL_PWREx_PVM2Callback(void)
1429 {
1430 /* NOTE : This function should not be modified; when the callback is needed,
1431 HAL_PWREx_PVM2Callback() API can be implemented in the user file
1432 */
1433 }
1434 #endif /* PWR_CR2_PVME2 */
1435
1436 /**
1437 * @brief PWR PVM3 interrupt callback
1438 * @retval None
1439 */
HAL_PWREx_PVM3Callback(void)1440 __weak void HAL_PWREx_PVM3Callback(void)
1441 {
1442 /* NOTE : This function should not be modified; when the callback is needed,
1443 HAL_PWREx_PVM3Callback() API can be implemented in the user file
1444 */
1445 }
1446
1447 /**
1448 * @brief PWR PVM4 interrupt callback
1449 * @retval None
1450 */
HAL_PWREx_PVM4Callback(void)1451 __weak void HAL_PWREx_PVM4Callback(void)
1452 {
1453 /* NOTE : This function should not be modified; when the callback is needed,
1454 HAL_PWREx_PVM4Callback() API can be implemented in the user file
1455 */
1456 }
1457
1458
1459 /**
1460 * @}
1461 */
1462
1463 /**
1464 * @}
1465 */
1466
1467 #endif /* HAL_PWR_MODULE_ENABLED */
1468 /**
1469 * @}
1470 */
1471
1472 /**
1473 * @}
1474 */
1475
