1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Initialization/de-initialization functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2019 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 */
23
24 /* Includes ------------------------------------------------------------------*/
25 #include "stm32l4xx_hal.h"
26
27 /** @addtogroup STM32L4xx_HAL_Driver
28 * @{
29 */
30
31 /** @defgroup PWR PWR
32 * @brief PWR HAL module driver
33 * @{
34 */
35
36 #ifdef HAL_PWR_MODULE_ENABLED
37
38 /* Private typedef -----------------------------------------------------------*/
39 /* Private define ------------------------------------------------------------*/
40
41 /** @defgroup PWR_Private_Defines PWR Private Defines
42 * @{
43 */
44
45 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
46 * @{
47 */
48 #define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */
49 #define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */
50 #define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */
51 #define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */
52 /**
53 * @}
54 */
55
56 /**
57 * @}
58 */
59
60 /* Private macro -------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62 /* Private function prototypes -----------------------------------------------*/
63 /* Exported functions --------------------------------------------------------*/
64
65 /** @defgroup PWR_Exported_Functions PWR Exported Functions
66 * @{
67 */
68
69 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
70 * @brief Initialization and de-initialization functions
71 *
72 @verbatim
73 ===============================================================================
74 ##### Initialization and de-initialization functions #####
75 ===============================================================================
76 [..]
77
78 @endverbatim
79 * @{
80 */
81
82 /**
83 * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
84 * @retval None
85 */
HAL_PWR_DeInit(void)86 void HAL_PWR_DeInit(void)
87 {
88 __HAL_RCC_PWR_FORCE_RESET();
89 __HAL_RCC_PWR_RELEASE_RESET();
90 }
91
92 /**
93 * @brief Enable access to the backup domain
94 * (RTC registers, RTC backup data registers).
95 * @note After reset, the backup domain is protected against
96 * possible unwanted write accesses.
97 * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
98 * In order to set or modify the RTC clock, the backup domain access must be
99 * disabled.
100 * @note LSEON bit that switches on and off the LSE crystal belongs as well to the
101 * back-up domain.
102 * @retval None
103 */
HAL_PWR_EnableBkUpAccess(void)104 void HAL_PWR_EnableBkUpAccess(void)
105 {
106 SET_BIT(PWR->CR1, PWR_CR1_DBP);
107 }
108
109 /**
110 * @brief Disable access to the backup domain
111 * (RTC registers, RTC backup data registers).
112 * @retval None
113 */
HAL_PWR_DisableBkUpAccess(void)114 void HAL_PWR_DisableBkUpAccess(void)
115 {
116 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
117 }
118
119
120
121
122 /**
123 * @}
124 */
125
126
127
128 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
129 * @brief Low Power modes configuration functions
130 *
131 @verbatim
132
133 ===============================================================================
134 ##### Peripheral Control functions #####
135 ===============================================================================
136
137 [..]
138 *** PVD configuration ***
139 =========================
140 [..]
141 (+) The PVD is used to monitor the VDD power supply by comparing it to a
142 threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
143
144 (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
145 than the PVD threshold. This event is internally connected to the EXTI
146 line16 and can generate an interrupt if enabled. This is done through
147 __HAL_PVD_EXTI_ENABLE_IT() macro.
148 (+) The PVD is stopped in Standby mode.
149
150
151 *** WakeUp pin configuration ***
152 ================================
153 [..]
154 (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
155 The polarity of these pins can be set to configure event detection on high
156 level (rising edge) or low level (falling edge).
157
158
159
160 *** Low Power modes configuration ***
161 =====================================
162 [..]
163 The devices feature 8 low-power modes:
164 (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
165 (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
166 (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
167 (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
168 (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
169 (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
170 (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
171 (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
172 (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
173
174
175 *** Low-power run mode ***
176 ==========================
177 [..]
178 (+) Entry: (from main run mode)
179 (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
180
181 (+) Exit:
182 (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
183 then can the system clock frequency be increased above 2 MHz.
184
185
186 *** Sleep mode / Low-power sleep mode ***
187 =========================================
188 [..]
189 (+) Entry:
190 The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
191 in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
192 (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
193 (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
194 In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
195 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
196 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
197
198 (+) WFI Exit:
199 (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
200 controller (NVIC) or any wake-up event.
201
202 (+) WFE Exit:
203 (++) Any wake-up event such as an EXTI line configured in event mode.
204
205 [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
206 the MCU is in Low-power Run mode.
207
208 *** Stop 0, Stop 1 and Stop 2 modes ***
209 ===============================
210 [..]
211 (+) Entry:
212 The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
213 (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
214 (++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
215 (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
216 (++) PWR_MAINREGULATOR_ON
217 (++) PWR_LOWPOWERREGULATOR_ON
218 (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
219 (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
220 (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
221
222 (+) WFI Exit:
223 (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
224 (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
225 when programmed in wakeup mode.
226 (+) WFE Exit:
227 (++) Any EXTI Line (Internal or External) configured in Event mode.
228
229 [..]
230 When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
231 depending on the LPR bit setting.
232 When exiting Stop 2 mode, the MCU is in Run mode.
233
234 *** Standby mode ***
235 ====================
236 [..]
237 The Standby mode offers two options:
238 (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
239 SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
240 and Standby circuitry.
241 (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
242 SRAM and register contents are lost except for the RTC registers, RTC backup registers
243 and Standby circuitry.
244
245 (++) Entry:
246 (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.
247 SRAM1 and register contents are lost except for registers in the Backup domain and
248 Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
249 To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
250 to set RRS bit.
251
252 (++) Exit:
253 (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
254 external reset in NRST pin, IWDG reset.
255
256 [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset.
257
258
259 *** Shutdown mode ***
260 ======================
261 [..]
262 In Shutdown mode,
263 voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
264 SRAM and registers contents are lost except for backup domain registers.
265
266 (+) Entry:
267 The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
268
269 (+) Exit:
270 (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
271 external reset in NRST pin.
272
273 [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
274
275
276 *** Auto-wakeup (AWU) from low-power mode ***
277 =============================================
278 [..]
279 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
280 Wakeup event, a tamper event or a time-stamp event, without depending on
281 an external interrupt (Auto-wakeup mode).
282
283 (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
284
285
286 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
287 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
288
289 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
290 is necessary to configure the RTC to detect the tamper or time stamp event using the
291 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
292
293 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
294 configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
295
296 @endverbatim
297 * @{
298 */
299
300
301
302 /**
303 * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
304 * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD
305 * configuration information.
306 * @note Refer to the electrical characteristics of your device datasheet for
307 * more details about the voltage thresholds corresponding to each
308 * detection level.
309 * @retval None
310 */
HAL_PWR_ConfigPVD(PWR_PVDTypeDef * sConfigPVD)311 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
312 {
313 /* Check the parameters */
314 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
315 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
316
317 /* Set PLS bits according to PVDLevel value */
318 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
319
320 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
321 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
322 __HAL_PWR_PVD_EXTI_DISABLE_IT();
323 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
324 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
325
326 /* Configure interrupt mode */
327 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
328 {
329 __HAL_PWR_PVD_EXTI_ENABLE_IT();
330 }
331
332 /* Configure event mode */
333 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
334 {
335 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
336 }
337
338 /* Configure the edge */
339 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
340 {
341 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
342 }
343
344 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
345 {
346 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
347 }
348
349 return HAL_OK;
350 }
351
352
353 /**
354 * @brief Enable the Power Voltage Detector (PVD).
355 * @retval None
356 */
HAL_PWR_EnablePVD(void)357 void HAL_PWR_EnablePVD(void)
358 {
359 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
360 }
361
362 /**
363 * @brief Disable the Power Voltage Detector (PVD).
364 * @retval None
365 */
HAL_PWR_DisablePVD(void)366 void HAL_PWR_DisablePVD(void)
367 {
368 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
369 }
370
371
372
373
374 /**
375 * @brief Enable the WakeUp PINx functionality.
376 * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
377 * This parameter can be one of the following legacy values which set the default polarity
378 * i.e. detection on high level (rising edge):
379 * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
380 *
381 * or one of the following value where the user can explicitly specify the enabled pin and
382 * the chosen polarity:
383 * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
384 * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
385 * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
386 * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
387 * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
388 * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
389 * @retval None
390 */
HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)391 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
392 {
393 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
394
395 /* Specifies the Wake-Up pin polarity for the event detection
396 (rising or falling edge) */
397 MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
398
399 /* Enable wake-up pin */
400 SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
401
402
403 }
404
405 /**
406 * @brief Disable the WakeUp PINx functionality.
407 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
408 * This parameter can be one of the following values:
409 * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
410 * @retval None
411 */
HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)412 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
413 {
414 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
415
416 CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
417 }
418
419
420 /**
421 * @brief Enter Sleep or Low-power Sleep mode.
422 * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
423 * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
424 * This parameter can be one of the following values:
425 * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
426 * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
427 * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
428 * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
429 * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
430 * Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
431 * Additionally, the clock frequency must be reduced below 2 MHz.
432 * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
433 * be done before calling HAL_PWR_EnterSLEEPMode() API.
434 * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
435 * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
436 * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
437 * This parameter can be one of the following values:
438 * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
439 * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
440 * @note When WFI entry is used, tick interrupt have to be disabled if not desired as
441 * the interrupt wake up source.
442 * @retval None
443 */
HAL_PWR_EnterSLEEPMode(uint32_t Regulator,uint8_t SLEEPEntry)444 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
445 {
446 /* Check the parameters */
447 assert_param(IS_PWR_REGULATOR(Regulator));
448 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
449
450 /* Set Regulator parameter */
451 if (Regulator == PWR_MAINREGULATOR_ON)
452 {
453 /* If in low-power run mode at this point, exit it */
454 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
455 {
456 if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
457 {
458 return ;
459 }
460 }
461 /* Regulator now in main mode. */
462 }
463 else
464 {
465 /* If in run mode, first move to low-power run mode.
466 The system clock frequency must be below 2 MHz at this point. */
467 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
468 {
469 HAL_PWREx_EnableLowPowerRunMode();
470 }
471 }
472
473 /* Clear SLEEPDEEP bit of Cortex System Control Register */
474 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
475
476 /* Select SLEEP mode entry -------------------------------------------------*/
477 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
478 {
479 /* Request Wait For Interrupt */
480 __WFI();
481 }
482 else
483 {
484 /* Request Wait For Event */
485 __SEV();
486 __WFE();
487 __WFE();
488 }
489
490 }
491
492
493 /**
494 * @brief Enter Stop mode
495 * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
496 * on devices where only "Stop mode" is mentioned with main or low power regulator ON.
497 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
498 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
499 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
500 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
501 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
502 * only to the peripheral requesting it.
503 * SRAM1, SRAM2 and register contents are preserved.
504 * The BOR is available.
505 * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
506 * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
507 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
508 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
509 * @note When the voltage regulator operates in low power mode (Stop 1), an additional
510 * startup delay is incurred when waking up.
511 * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
512 * is higher although the startup time is reduced.
513 * @param Regulator: Specifies the regulator state in Stop mode.
514 * This parameter can be one of the following values:
515 * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
516 * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
517 * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
518 * This parameter can be one of the following values:
519 * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
520 * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
521 * @retval None
522 */
HAL_PWR_EnterSTOPMode(uint32_t Regulator,uint8_t STOPEntry)523 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
524 {
525 /* Check the parameters */
526 assert_param(IS_PWR_REGULATOR(Regulator));
527
528 if(Regulator == PWR_LOWPOWERREGULATOR_ON)
529 {
530 HAL_PWREx_EnterSTOP1Mode(STOPEntry);
531 }
532 else
533 {
534 HAL_PWREx_EnterSTOP0Mode(STOPEntry);
535 }
536 }
537
538 /**
539 * @brief Enter Standby mode.
540 * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched
541 * off. The voltage regulator is disabled, except when SRAM2 content is preserved
542 * in which case the regulator is in low-power mode.
543 * SRAM1 and register contents are lost except for registers in the Backup domain and
544 * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
545 * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
546 * to set RRS bit.
547 * The BOR is available.
548 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
549 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
550 * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
551 * same.
552 * These states are effective in Standby mode only if APC bit is set through
553 * HAL_PWREx_EnablePullUpPullDownConfig() API.
554 * @retval None
555 */
HAL_PWR_EnterSTANDBYMode(void)556 void HAL_PWR_EnterSTANDBYMode(void)
557 {
558 /* Set Stand-by mode */
559 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
560
561 /* Set SLEEPDEEP bit of Cortex System Control Register */
562 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
563
564 /* This option is used to ensure that store operations are completed */
565 #if defined ( __CC_ARM)
566 __force_stores();
567 #endif
568 /* Request Wait For Interrupt */
569 __WFI();
570 }
571
572
573
574 /**
575 * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
576 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
577 * re-enters SLEEP mode when an interruption handling is over.
578 * Setting this bit is useful when the processor is expected to run only on
579 * interruptions handling.
580 * @retval None
581 */
HAL_PWR_EnableSleepOnExit(void)582 void HAL_PWR_EnableSleepOnExit(void)
583 {
584 /* Set SLEEPONEXIT bit of Cortex System Control Register */
585 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
586 }
587
588
589 /**
590 * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
591 * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
592 * re-enters SLEEP mode when an interruption handling is over.
593 * @retval None
594 */
HAL_PWR_DisableSleepOnExit(void)595 void HAL_PWR_DisableSleepOnExit(void)
596 {
597 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
598 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
599 }
600
601
602
603 /**
604 * @brief Enable CORTEX M4 SEVONPEND bit.
605 * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
606 * WFE to wake up when an interrupt moves from inactive to pended.
607 * @retval None
608 */
HAL_PWR_EnableSEVOnPend(void)609 void HAL_PWR_EnableSEVOnPend(void)
610 {
611 /* Set SEVONPEND bit of Cortex System Control Register */
612 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
613 }
614
615
616 /**
617 * @brief Disable CORTEX M4 SEVONPEND bit.
618 * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
619 * WFE to wake up when an interrupt moves from inactive to pended.
620 * @retval None
621 */
HAL_PWR_DisableSEVOnPend(void)622 void HAL_PWR_DisableSEVOnPend(void)
623 {
624 /* Clear SEVONPEND bit of Cortex System Control Register */
625 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
626 }
627
628
629
630
631
632 /**
633 * @brief PWR PVD interrupt callback
634 * @retval None
635 */
HAL_PWR_PVDCallback(void)636 __weak void HAL_PWR_PVDCallback(void)
637 {
638 /* NOTE : This function should not be modified; when the callback is needed,
639 the HAL_PWR_PVDCallback can be implemented in the user file
640 */
641 }
642
643 /**
644 * @}
645 */
646
647 /**
648 * @}
649 */
650
651 #endif /* HAL_PWR_MODULE_ENABLED */
652 /**
653 * @}
654 */
655
656 /**
657 * @}
658 */
659
