1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_dma2d.c
4 * @author MCD Application Team
5 * @brief DMA2D HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the DMA2D peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State and Errors functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2017 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### How to use this driver #####
27 ==============================================================================
28 [..]
29 (#) Program the required configuration through the following parameters:
30 the transfer mode, the output color mode and the output offset using
31 HAL_DMA2D_Init() function.
32
33 (#) Program the required configuration through the following parameters:
34 the input color mode, the input color, the input alpha value, the alpha mode,
35 the red/blue swap mode, the inverted alpha mode and the input offset using
36 HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
37
38 *** Polling mode IO operation ***
39 =================================
40 [..]
41 (#) Configure pdata parameter (explained hereafter), destination and data length
42 and enable the transfer using HAL_DMA2D_Start().
43 (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
44 user can specify the value of timeout according to his end application.
45
46 *** Interrupt mode IO operation ***
47 ===================================
48 [..]
49 (#) Configure pdata parameter, destination and data length and enable
50 the transfer using HAL_DMA2D_Start_IT().
51 (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
52 (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
53 add his own function by customization of function pointer XferCpltCallback (member
54 of DMA2D handle structure).
55 (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback
56 XferErrorCallback.
57
58 -@- In Register-to-Memory transfer mode, pdata parameter is the register
59 color, in Memory-to-memory or Memory-to-Memory with pixel format
60 conversion pdata is the source address.
61
62 -@- Configure the foreground source address, the background source address,
63 the destination and data length then Enable the transfer using
64 HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
65 in interrupt mode.
66
67 -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
68 are used if the memory to memory with blending transfer mode is selected.
69
70 (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
71 mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
72
73 (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent().
74
75 (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
76 consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
77 and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or
78 HAL_DMA2D_DisableDeadTime().
79
80 (#) The transfer can be suspended, resumed and aborted using the following
81 functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
82
83 (#) The CLUT loading can be suspended, resumed and aborted using the following
84 functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
85 HAL_DMA2D_CLUTLoading_Abort().
86
87 (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
88
89 (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
90
91 *** DMA2D HAL driver macros list ***
92 =============================================
93 [..]
94 Below the list of most used macros in DMA2D HAL driver :
95
96 (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
97 (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
98 (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
99 (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
100 (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
101 (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
102
103 *** Callback registration ***
104 ===================================
105 [..]
106 (#) The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1
107 allows the user to configure dynamically the driver callbacks.
108 Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback.
109
110 (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks:
111 (+) XferCpltCallback : callback for transfer complete.
112 (+) XferErrorCallback : callback for transfer error.
113 (+) LineEventCallback : callback for line event.
114 (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
115 (+) MspInitCallback : DMA2D MspInit.
116 (+) MspDeInitCallback : DMA2D MspDeInit.
117 This function takes as parameters the HAL peripheral handle, the Callback ID
118 and a pointer to the user callback function.
119
120 (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
121 weak (surcharged) function.
122 @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
123 and the Callback ID.
124 This function allows to reset following callbacks:
125 (+) XferCpltCallback : callback for transfer complete.
126 (+) XferErrorCallback : callback for transfer error.
127 (+) LineEventCallback : callback for line event.
128 (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
129 (+) MspInitCallback : DMA2D MspInit.
130 (+) MspDeInitCallback : DMA2D MspDeInit.
131
132 (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
133 all callbacks are reset to the corresponding legacy weak (surcharged) functions:
134 examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
135 Exception done for MspInit and MspDeInit callbacks that are respectively
136 reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
137 and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
138 If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
139 keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
140
141 Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
142 as weak (surcharged) functions. They must be defined by the user to be resorted to.
143
144 Callbacks can be registered/unregistered in READY state only.
145 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
146 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
147 during the Init/DeInit.
148 In that case first register the MspInit/MspDeInit user callbacks
149 using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit
150 or @ref HAL_DMA2D_Init function.
151
152 When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
153 not defined, the callback registering feature is not available
154 and weak (surcharged) callbacks are used.
155
156 [..]
157 (@) You can refer to the DMA2D HAL driver header file for more useful macros
158
159 @endverbatim
160 ******************************************************************************
161 */
162
163 /* Includes ------------------------------------------------------------------*/
164 #include "stm32l4xx_hal.h"
165
166 #ifdef HAL_DMA2D_MODULE_ENABLED
167 #if defined (DMA2D)
168
169 /** @addtogroup STM32L4xx_HAL_Driver
170 * @{
171 */
172
173 /** @defgroup DMA2D DMA2D
174 * @brief DMA2D HAL module driver
175 * @{
176 */
177
178 /* Private types -------------------------------------------------------------*/
179 /* Private define ------------------------------------------------------------*/
180 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
181 * @{
182 */
183
184 /** @defgroup DMA2D_TimeOut DMA2D Time Out
185 * @{
186 */
187 #define DMA2D_TIMEOUT_ABORT (1000U) /*!< 1s */
188 #define DMA2D_TIMEOUT_SUSPEND (1000U) /*!< 1s */
189 /**
190 * @}
191 */
192
193 /**
194 * @}
195 */
196
197 /* Private variables ---------------------------------------------------------*/
198 /* Private constants ---------------------------------------------------------*/
199 /* Private macro -------------------------------------------------------------*/
200 /* Private function prototypes -----------------------------------------------*/
201 /** @addtogroup DMA2D_Private_Functions DMA2D Private Functions
202 * @{
203 */
204 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
205 uint32_t Height);
206 /**
207 * @}
208 */
209
210 /* Private functions ---------------------------------------------------------*/
211 /* Exported functions --------------------------------------------------------*/
212 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
213 * @{
214 */
215
216 /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
217 * @brief Initialization and Configuration functions
218 *
219 @verbatim
220 ===============================================================================
221 ##### Initialization and Configuration functions #####
222 ===============================================================================
223 [..] This section provides functions allowing to:
224 (+) Initialize and configure the DMA2D
225 (+) De-initialize the DMA2D
226
227 @endverbatim
228 * @{
229 */
230
231 /**
232 * @brief Initialize the DMA2D according to the specified
233 * parameters in the DMA2D_InitTypeDef and create the associated handle.
234 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
235 * the configuration information for the DMA2D.
236 * @retval HAL status
237 */
HAL_DMA2D_Init(DMA2D_HandleTypeDef * hdma2d)238 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
239 {
240 /* Check the DMA2D peripheral state */
241 if (hdma2d == NULL)
242 {
243 return HAL_ERROR;
244 }
245
246 /* Check the parameters */
247 assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
248 assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
249 assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
250 assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
251 assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->Init.AlphaInverted));
252 assert_param(IS_DMA2D_RB_SWAP(hdma2d->Init.RedBlueSwap));
253 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
254 assert_param(IS_DMA2D_LOM_MODE(hdma2d->Init.LineOffsetMode));
255 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
256 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
257 assert_param(IS_DMA2D_BYTES_SWAP(hdma2d->Init.BytesSwap));
258 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
259
260 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
261 if (hdma2d->State == HAL_DMA2D_STATE_RESET)
262 {
263 /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */
264 hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
265 hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
266 if (hdma2d->MspInitCallback == NULL)
267 {
268 hdma2d->MspInitCallback = HAL_DMA2D_MspInit;
269 }
270
271 /* Init the low level hardware */
272 hdma2d->MspInitCallback(hdma2d);
273 }
274 #else
275 if (hdma2d->State == HAL_DMA2D_STATE_RESET)
276 {
277 /* Allocate lock resource and initialize it */
278 hdma2d->Lock = HAL_UNLOCKED;
279 /* Init the low level hardware */
280 HAL_DMA2D_MspInit(hdma2d);
281 }
282 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
283
284 /* Change DMA2D peripheral state */
285 hdma2d->State = HAL_DMA2D_STATE_BUSY;
286
287 /* DMA2D CR register configuration -------------------------------------------*/
288 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
289 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE | DMA2D_CR_LOM, hdma2d->Init.Mode | hdma2d->Init.LineOffsetMode);
290 #else
291 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
292 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
293
294 /* DMA2D OPFCCR register configuration ---------------------------------------*/
295 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
296 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB,
297 hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap);
298 #else
299 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
300 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
301
302 /* DMA2D OOR register configuration ------------------------------------------*/
303 MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
304 /* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/
305 MODIFY_REG(hdma2d->Instance->OPFCCR, (DMA2D_OPFCCR_AI | DMA2D_OPFCCR_RBS),
306 ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | \
307 (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
308
309
310 /* Update error code */
311 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
312
313 /* Initialize the DMA2D state*/
314 hdma2d->State = HAL_DMA2D_STATE_READY;
315
316 return HAL_OK;
317 }
318
319 /**
320 * @brief Deinitializes the DMA2D peripheral registers to their default reset
321 * values.
322 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
323 * the configuration information for the DMA2D.
324 * @retval None
325 */
326
HAL_DMA2D_DeInit(DMA2D_HandleTypeDef * hdma2d)327 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
328 {
329
330 /* Check the DMA2D peripheral state */
331 if (hdma2d == NULL)
332 {
333 return HAL_ERROR;
334 }
335
336 /* Before aborting any DMA2D transfer or CLUT loading, check
337 first whether or not DMA2D clock is enabled */
338 if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
339 {
340 /* Abort DMA2D transfer if any */
341 if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
342 {
343 if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
344 {
345 /* Issue when aborting DMA2D transfer */
346 return HAL_ERROR;
347 }
348 }
349 else
350 {
351 /* Abort background CLUT loading if any */
352 if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
353 {
354 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
355 {
356 /* Issue when aborting background CLUT loading */
357 return HAL_ERROR;
358 }
359 }
360 else
361 {
362 /* Abort foreground CLUT loading if any */
363 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
364 {
365 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
366 {
367 /* Issue when aborting foreground CLUT loading */
368 return HAL_ERROR;
369 }
370 }
371 }
372 }
373 }
374
375 /* Reset DMA2D control registers*/
376 hdma2d->Instance->CR = 0U;
377 hdma2d->Instance->IFCR = 0x3FU;
378 hdma2d->Instance->FGOR = 0U;
379 hdma2d->Instance->BGOR = 0U;
380 hdma2d->Instance->FGPFCCR = 0U;
381 hdma2d->Instance->BGPFCCR = 0U;
382 hdma2d->Instance->OPFCCR = 0U;
383
384 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
385
386 if (hdma2d->MspDeInitCallback == NULL)
387 {
388 hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
389 }
390
391 /* DeInit the low level hardware */
392 hdma2d->MspDeInitCallback(hdma2d);
393
394 #else
395 /* Carry on with de-initialization of low level hardware */
396 HAL_DMA2D_MspDeInit(hdma2d);
397 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
398
399 /* Update error code */
400 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
401
402 /* Initialize the DMA2D state*/
403 hdma2d->State = HAL_DMA2D_STATE_RESET;
404
405 /* Release Lock */
406 __HAL_UNLOCK(hdma2d);
407
408 return HAL_OK;
409 }
410
411 /**
412 * @brief Initializes the DMA2D MSP.
413 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
414 * the configuration information for the DMA2D.
415 * @retval None
416 */
HAL_DMA2D_MspInit(DMA2D_HandleTypeDef * hdma2d)417 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d)
418 {
419 /* Prevent unused argument(s) compilation warning */
420 UNUSED(hdma2d);
421
422 /* NOTE : This function should not be modified; when the callback is needed,
423 the HAL_DMA2D_MspInit can be implemented in the user file.
424 */
425 }
426
427 /**
428 * @brief DeInitializes the DMA2D MSP.
429 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
430 * the configuration information for the DMA2D.
431 * @retval None
432 */
HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef * hdma2d)433 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d)
434 {
435 /* Prevent unused argument(s) compilation warning */
436 UNUSED(hdma2d);
437
438 /* NOTE : This function should not be modified; when the callback is needed,
439 the HAL_DMA2D_MspDeInit can be implemented in the user file.
440 */
441 }
442
443 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
444 /**
445 * @brief Register a User DMA2D Callback
446 * To be used instead of the weak (surcharged) predefined callback
447 * @param hdma2d DMA2D handle
448 * @param CallbackID ID of the callback to be registered
449 * This parameter can be one of the following values:
450 * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
451 * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
452 * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
453 * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
454 * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
455 * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
456 * @param pCallback pointer to the Callback function
457 * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
458 * @retval status
459 */
HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef * hdma2d,HAL_DMA2D_CallbackIDTypeDef CallbackID,pDMA2D_CallbackTypeDef pCallback)460 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
461 pDMA2D_CallbackTypeDef pCallback)
462 {
463 HAL_StatusTypeDef status = HAL_OK;
464
465 if (pCallback == NULL)
466 {
467 /* Update the error code */
468 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
469 return HAL_ERROR;
470 }
471 /* Process locked */
472 __HAL_LOCK(hdma2d);
473
474 if (HAL_DMA2D_STATE_READY == hdma2d->State)
475 {
476 switch (CallbackID)
477 {
478 case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
479 hdma2d->XferCpltCallback = pCallback;
480 break;
481
482 case HAL_DMA2D_TRANSFERERROR_CB_ID :
483 hdma2d->XferErrorCallback = pCallback;
484 break;
485
486 case HAL_DMA2D_LINEEVENT_CB_ID :
487 hdma2d->LineEventCallback = pCallback;
488 break;
489
490 case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
491 hdma2d->CLUTLoadingCpltCallback = pCallback;
492 break;
493
494 case HAL_DMA2D_MSPINIT_CB_ID :
495 hdma2d->MspInitCallback = pCallback;
496 break;
497
498 case HAL_DMA2D_MSPDEINIT_CB_ID :
499 hdma2d->MspDeInitCallback = pCallback;
500 break;
501
502 default :
503 /* Update the error code */
504 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
505 /* update return status */
506 status = HAL_ERROR;
507 break;
508 }
509 }
510 else if (HAL_DMA2D_STATE_RESET == hdma2d->State)
511 {
512 switch (CallbackID)
513 {
514 case HAL_DMA2D_MSPINIT_CB_ID :
515 hdma2d->MspInitCallback = pCallback;
516 break;
517
518 case HAL_DMA2D_MSPDEINIT_CB_ID :
519 hdma2d->MspDeInitCallback = pCallback;
520 break;
521
522 default :
523 /* Update the error code */
524 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
525 /* update return status */
526 status = HAL_ERROR;
527 break;
528 }
529 }
530 else
531 {
532 /* Update the error code */
533 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
534 /* update return status */
535 status = HAL_ERROR;
536 }
537
538 /* Release Lock */
539 __HAL_UNLOCK(hdma2d);
540 return status;
541 }
542
543 /**
544 * @brief Unregister a DMA2D Callback
545 * DMA2D Callback is redirected to the weak (surcharged) predefined callback
546 * @param hdma2d DMA2D handle
547 * @param CallbackID ID of the callback to be unregistered
548 * This parameter can be one of the following values:
549 * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
550 * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
551 * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
552 * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
553 * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
554 * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
555 * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
556 * @retval status
557 */
HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef * hdma2d,HAL_DMA2D_CallbackIDTypeDef CallbackID)558 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
559 {
560 HAL_StatusTypeDef status = HAL_OK;
561
562 /* Process locked */
563 __HAL_LOCK(hdma2d);
564
565 if (HAL_DMA2D_STATE_READY == hdma2d->State)
566 {
567 switch (CallbackID)
568 {
569 case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
570 hdma2d->XferCpltCallback = NULL;
571 break;
572
573 case HAL_DMA2D_TRANSFERERROR_CB_ID :
574 hdma2d->XferErrorCallback = NULL;
575 break;
576
577 case HAL_DMA2D_LINEEVENT_CB_ID :
578 hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
579 break;
580
581 case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
582 hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
583 break;
584
585 case HAL_DMA2D_MSPINIT_CB_ID :
586 hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
587 break;
588
589 case HAL_DMA2D_MSPDEINIT_CB_ID :
590 hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
591 break;
592
593 default :
594 /* Update the error code */
595 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
596 /* update return status */
597 status = HAL_ERROR;
598 break;
599 }
600 }
601 else if (HAL_DMA2D_STATE_RESET == hdma2d->State)
602 {
603 switch (CallbackID)
604 {
605 case HAL_DMA2D_MSPINIT_CB_ID :
606 hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
607 break;
608
609 case HAL_DMA2D_MSPDEINIT_CB_ID :
610 hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
611 break;
612
613 default :
614 /* Update the error code */
615 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
616 /* update return status */
617 status = HAL_ERROR;
618 break;
619 }
620 }
621 else
622 {
623 /* Update the error code */
624 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
625 /* update return status */
626 status = HAL_ERROR;
627 }
628
629 /* Release Lock */
630 __HAL_UNLOCK(hdma2d);
631 return status;
632 }
633 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
634
635 /**
636 * @}
637 */
638
639
640 /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
641 * @brief IO operation functions
642 *
643 @verbatim
644 ===============================================================================
645 ##### IO operation functions #####
646 ===============================================================================
647 [..] This section provides functions allowing to:
648 (+) Configure the pdata, destination address and data size then
649 start the DMA2D transfer.
650 (+) Configure the source for foreground and background, destination address
651 and data size then start a MultiBuffer DMA2D transfer.
652 (+) Configure the pdata, destination address and data size then
653 start the DMA2D transfer with interrupt.
654 (+) Configure the source for foreground and background, destination address
655 and data size then start a MultiBuffer DMA2D transfer with interrupt.
656 (+) Abort DMA2D transfer.
657 (+) Suspend DMA2D transfer.
658 (+) Resume DMA2D transfer.
659 (+) Enable CLUT transfer.
660 (+) Configure CLUT loading then start transfer in polling mode.
661 (+) Configure CLUT loading then start transfer in interrupt mode.
662 (+) Abort DMA2D CLUT loading.
663 (+) Suspend DMA2D CLUT loading.
664 (+) Resume DMA2D CLUT loading.
665 (+) Poll for transfer complete.
666 (+) handle DMA2D interrupt request.
667 (+) Transfer watermark callback.
668 (+) CLUT Transfer Complete callback.
669
670
671 @endverbatim
672 * @{
673 */
674
675 /**
676 * @brief Start the DMA2D Transfer.
677 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
678 * the configuration information for the DMA2D.
679 * @param pdata Configure the source memory Buffer address if
680 * Memory-to-Memory or Memory-to-Memory with pixel format
681 * conversion mode is selected, or configure
682 * the color value if Register-to-Memory mode is selected.
683 * @param DstAddress The destination memory Buffer address.
684 * @param Width The width of data to be transferred from source
685 * to destination (expressed in number of pixels per line).
686 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
687 * @retval HAL status
688 */
HAL_DMA2D_Start(DMA2D_HandleTypeDef * hdma2d,uint32_t pdata,uint32_t DstAddress,uint32_t Width,uint32_t Height)689 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
690 uint32_t Height)
691 {
692 /* Check the parameters */
693 assert_param(IS_DMA2D_LINE(Height));
694 assert_param(IS_DMA2D_PIXEL(Width));
695
696 /* Process locked */
697 __HAL_LOCK(hdma2d);
698
699 /* Change DMA2D peripheral state */
700 hdma2d->State = HAL_DMA2D_STATE_BUSY;
701
702 /* Configure the source, destination address and the data size */
703 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
704
705 /* Enable the Peripheral */
706 __HAL_DMA2D_ENABLE(hdma2d);
707
708 return HAL_OK;
709 }
710
711 /**
712 * @brief Start the DMA2D Transfer with interrupt enabled.
713 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
714 * the configuration information for the DMA2D.
715 * @param pdata Configure the source memory Buffer address if
716 * the Memory-to-Memory or Memory-to-Memory with pixel format
717 * conversion mode is selected, or configure
718 * the color value if Register-to-Memory mode is selected.
719 * @param DstAddress The destination memory Buffer address.
720 * @param Width The width of data to be transferred from source
721 * to destination (expressed in number of pixels per line).
722 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
723 * @retval HAL status
724 */
HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef * hdma2d,uint32_t pdata,uint32_t DstAddress,uint32_t Width,uint32_t Height)725 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
726 uint32_t Height)
727 {
728 /* Check the parameters */
729 assert_param(IS_DMA2D_LINE(Height));
730 assert_param(IS_DMA2D_PIXEL(Width));
731
732 /* Process locked */
733 __HAL_LOCK(hdma2d);
734
735 /* Change DMA2D peripheral state */
736 hdma2d->State = HAL_DMA2D_STATE_BUSY;
737
738 /* Configure the source, destination address and the data size */
739 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
740
741 /* Enable the transfer complete, transfer error and configuration error interrupts */
742 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
743
744 /* Enable the Peripheral */
745 __HAL_DMA2D_ENABLE(hdma2d);
746
747 return HAL_OK;
748 }
749
750 /**
751 * @brief Start the multi-source DMA2D Transfer.
752 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
753 * the configuration information for the DMA2D.
754 * @param SrcAddress1 The source memory Buffer address for the foreground layer.
755 * @param SrcAddress2 The source memory Buffer address for the background layer.
756 * @param DstAddress The destination memory Buffer address.
757 * @param Width The width of data to be transferred from source
758 * to destination (expressed in number of pixels per line).
759 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
760 * @retval HAL status
761 */
HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef * hdma2d,uint32_t SrcAddress1,uint32_t SrcAddress2,uint32_t DstAddress,uint32_t Width,uint32_t Height)762 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
763 uint32_t DstAddress, uint32_t Width, uint32_t Height)
764 {
765 /* Check the parameters */
766 assert_param(IS_DMA2D_LINE(Height));
767 assert_param(IS_DMA2D_PIXEL(Width));
768
769 /* Process locked */
770 __HAL_LOCK(hdma2d);
771
772 /* Change DMA2D peripheral state */
773 hdma2d->State = HAL_DMA2D_STATE_BUSY;
774
775 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
776 if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
777 {
778 /*blending & fixed FG*/
779 WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
780 /* Configure the source, destination address and the data size */
781 DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height);
782 }
783 else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG)
784 {
785 /*blending & fixed BG*/
786 WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2);
787 /* Configure the source, destination address and the data size */
788 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
789 }
790 else
791 {
792 /* Configure DMA2D Stream source2 address */
793 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
794
795 /* Configure the source, destination address and the data size */
796 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
797 }
798
799 #else
800 /* Configure DMA2D Stream source2 address */
801 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
802
803 /* Configure the source, destination address and the data size */
804 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
805
806 #endif /*DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT*/
807 /* Enable the Peripheral */
808 __HAL_DMA2D_ENABLE(hdma2d);
809
810 return HAL_OK;
811 }
812
813 /**
814 * @brief Start the multi-source DMA2D Transfer with interrupt enabled.
815 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
816 * the configuration information for the DMA2D.
817 * @param SrcAddress1 The source memory Buffer address for the foreground layer.
818 * @param SrcAddress2 The source memory Buffer address for the background layer.
819 * @param DstAddress The destination memory Buffer address.
820 * @param Width The width of data to be transferred from source
821 * to destination (expressed in number of pixels per line).
822 * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
823 * @retval HAL status
824 */
HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef * hdma2d,uint32_t SrcAddress1,uint32_t SrcAddress2,uint32_t DstAddress,uint32_t Width,uint32_t Height)825 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
826 uint32_t DstAddress, uint32_t Width, uint32_t Height)
827 {
828 /* Check the parameters */
829 assert_param(IS_DMA2D_LINE(Height));
830 assert_param(IS_DMA2D_PIXEL(Width));
831
832 /* Process locked */
833 __HAL_LOCK(hdma2d);
834
835 /* Change DMA2D peripheral state */
836 hdma2d->State = HAL_DMA2D_STATE_BUSY;
837
838 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
839 if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
840 {
841 /*blending & fixed FG*/
842 WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
843 /* Configure the source, destination address and the data size */
844 DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height);
845 }
846 else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG)
847 {
848 /*blending & fixed BG*/
849 WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2);
850 /* Configure the source, destination address and the data size */
851 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
852 }
853 else
854 {
855 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
856
857 /* Configure the source, destination address and the data size */
858 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
859 }
860
861 #else
862 /* Configure DMA2D Stream source2 address */
863 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
864
865 /* Configure the source, destination address and the data size */
866 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
867
868 #endif /*DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT*/
869 /* Enable the transfer complete, transfer error and configuration error interrupts */
870 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
871
872 /* Enable the Peripheral */
873 __HAL_DMA2D_ENABLE(hdma2d);
874
875 return HAL_OK;
876 }
877
878 /**
879 * @brief Abort the DMA2D Transfer.
880 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
881 * the configuration information for the DMA2D.
882 * @retval HAL status
883 */
HAL_DMA2D_Abort(DMA2D_HandleTypeDef * hdma2d)884 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
885 {
886 uint32_t tickstart;
887
888 /* Abort the DMA2D transfer */
889 /* START bit is reset to make sure not to set it again, in the event the HW clears it
890 between the register read and the register write by the CPU (writing 0 has no
891 effect on START bitvalue) */
892 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
893
894 /* Get tick */
895 tickstart = HAL_GetTick();
896
897 /* Check if the DMA2D is effectively disabled */
898 while ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
899 {
900 if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT)
901 {
902 /* Update error code */
903 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
904
905 /* Change the DMA2D state */
906 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
907
908 /* Process Unlocked */
909 __HAL_UNLOCK(hdma2d);
910
911 return HAL_TIMEOUT;
912 }
913 }
914
915 /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
916 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
917
918 /* Change the DMA2D state*/
919 hdma2d->State = HAL_DMA2D_STATE_READY;
920
921 /* Process Unlocked */
922 __HAL_UNLOCK(hdma2d);
923
924 return HAL_OK;
925 }
926
927 /**
928 * @brief Suspend the DMA2D Transfer.
929 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
930 * the configuration information for the DMA2D.
931 * @retval HAL status
932 */
HAL_DMA2D_Suspend(DMA2D_HandleTypeDef * hdma2d)933 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
934 {
935 uint32_t tickstart;
936
937 /* Suspend the DMA2D transfer */
938 /* START bit is reset to make sure not to set it again, in the event the HW clears it
939 between the register read and the register write by the CPU (writing 0 has no
940 effect on START bitvalue). */
941 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
942
943 /* Get tick */
944 tickstart = HAL_GetTick();
945
946 /* Check if the DMA2D is effectively suspended */
947 while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START)
948 {
949 if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND)
950 {
951 /* Update error code */
952 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
953
954 /* Change the DMA2D state */
955 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
956
957 return HAL_TIMEOUT;
958 }
959 }
960
961 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
962 if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
963 {
964 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
965 }
966 else
967 {
968 /* Make sure SUSP bit is cleared since it is meaningless
969 when no transfer is on-going */
970 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
971 }
972
973 return HAL_OK;
974 }
975
976 /**
977 * @brief Resume the DMA2D Transfer.
978 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
979 * the configuration information for the DMA2D.
980 * @retval HAL status
981 */
HAL_DMA2D_Resume(DMA2D_HandleTypeDef * hdma2d)982 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
983 {
984 /* Check the SUSP and START bits */
985 if ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
986 {
987 /* Ongoing transfer is suspended: change the DMA2D state before resuming */
988 hdma2d->State = HAL_DMA2D_STATE_BUSY;
989 }
990
991 /* Resume the DMA2D transfer */
992 /* START bit is reset to make sure not to set it again, in the event the HW clears it
993 between the register read and the register write by the CPU (writing 0 has no
994 effect on START bitvalue). */
995 CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP | DMA2D_CR_START));
996
997 return HAL_OK;
998 }
999
1000
1001 /**
1002 * @brief Enable the DMA2D CLUT Transfer.
1003 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1004 * the configuration information for the DMA2D.
1005 * @param LayerIdx DMA2D Layer index.
1006 * This parameter can be one of the following values:
1007 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1008 * @retval HAL status
1009 */
HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)1010 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1011 {
1012 /* Check the parameters */
1013 assert_param(IS_DMA2D_LAYER(LayerIdx));
1014
1015 /* Process locked */
1016 __HAL_LOCK(hdma2d);
1017
1018 /* Change DMA2D peripheral state */
1019 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1020
1021 if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1022 {
1023 /* Enable the background CLUT loading */
1024 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1025 }
1026 else
1027 {
1028 /* Enable the foreground CLUT loading */
1029 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1030 }
1031
1032 return HAL_OK;
1033 }
1034
1035 /**
1036 * @brief Start DMA2D CLUT Loading.
1037 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1038 * the configuration information for the DMA2D.
1039 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1040 * the configuration information for the color look up table.
1041 * @param LayerIdx DMA2D Layer index.
1042 * This parameter can be one of the following values:
1043 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1044 * @retval HAL status
1045 */
HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef * hdma2d,DMA2D_CLUTCfgTypeDef * CLUTCfg,uint32_t LayerIdx)1046 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx)
1047 {
1048 /* Check the parameters */
1049 assert_param(IS_DMA2D_LAYER(LayerIdx));
1050 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
1051 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
1052
1053 /* Process locked */
1054 __HAL_LOCK(hdma2d);
1055
1056 /* Change DMA2D peripheral state */
1057 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1058
1059 /* Configure the CLUT of the background DMA2D layer */
1060 if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1061 {
1062 /* Write background CLUT memory address */
1063 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
1064
1065 /* Write background CLUT size and CLUT color mode */
1066 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1067 ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1068
1069 /* Enable the CLUT loading for the background */
1070 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1071 }
1072 /* Configure the CLUT of the foreground DMA2D layer */
1073 else
1074 {
1075 /* Write foreground CLUT memory address */
1076 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
1077
1078 /* Write foreground CLUT size and CLUT color mode */
1079 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1080 ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1081
1082 /* Enable the CLUT loading for the foreground */
1083 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1084 }
1085
1086 return HAL_OK;
1087 }
1088
1089 /**
1090 * @brief Start DMA2D CLUT Loading with interrupt enabled.
1091 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1092 * the configuration information for the DMA2D.
1093 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1094 * the configuration information for the color look up table.
1095 * @param LayerIdx DMA2D Layer index.
1096 * This parameter can be one of the following values:
1097 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1098 * @retval HAL status
1099 */
HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef * hdma2d,DMA2D_CLUTCfgTypeDef * CLUTCfg,uint32_t LayerIdx)1100 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
1101 uint32_t LayerIdx)
1102 {
1103 /* Check the parameters */
1104 assert_param(IS_DMA2D_LAYER(LayerIdx));
1105 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
1106 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
1107
1108 /* Process locked */
1109 __HAL_LOCK(hdma2d);
1110
1111 /* Change DMA2D peripheral state */
1112 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1113
1114 /* Configure the CLUT of the background DMA2D layer */
1115 if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1116 {
1117 /* Write background CLUT memory address */
1118 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
1119
1120 /* Write background CLUT size and CLUT color mode */
1121 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1122 ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1123
1124 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1125 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
1126
1127 /* Enable the CLUT loading for the background */
1128 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1129 }
1130 /* Configure the CLUT of the foreground DMA2D layer */
1131 else
1132 {
1133 /* Write foreground CLUT memory address */
1134 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
1135
1136 /* Write foreground CLUT size and CLUT color mode */
1137 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1138 ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1139
1140 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1141 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
1142
1143 /* Enable the CLUT loading for the foreground */
1144 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1145 }
1146
1147 return HAL_OK;
1148 }
1149
1150 /**
1151 * @brief Start DMA2D CLUT Loading.
1152 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1153 * the configuration information for the DMA2D.
1154 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1155 * the configuration information for the color look up table.
1156 * @param LayerIdx DMA2D Layer index.
1157 * This parameter can be one of the following values:
1158 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1159 * @note API obsolete and maintained for compatibility with legacy. User is
1160 * invited to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from
1161 * code compactness, code size and improved heap usage.
1162 * @retval HAL status
1163 */
HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef * hdma2d,DMA2D_CLUTCfgTypeDef CLUTCfg,uint32_t LayerIdx)1164 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1165 {
1166 /* Check the parameters */
1167 assert_param(IS_DMA2D_LAYER(LayerIdx));
1168 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1169 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1170
1171 /* Process locked */
1172 __HAL_LOCK(hdma2d);
1173
1174 /* Change DMA2D peripheral state */
1175 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1176
1177 /* Configure the CLUT of the background DMA2D layer */
1178 if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1179 {
1180 /* Write background CLUT memory address */
1181 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1182
1183 /* Write background CLUT size and CLUT color mode */
1184 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1185 ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1186
1187 /* Enable the CLUT loading for the background */
1188 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1189 }
1190 /* Configure the CLUT of the foreground DMA2D layer */
1191 else
1192 {
1193 /* Write foreground CLUT memory address */
1194 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1195
1196 /* Write foreground CLUT size and CLUT color mode */
1197 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1198 ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1199
1200 /* Enable the CLUT loading for the foreground */
1201 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1202 }
1203
1204 return HAL_OK;
1205 }
1206
1207 /**
1208 * @brief Start DMA2D CLUT Loading with interrupt enabled.
1209 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1210 * the configuration information for the DMA2D.
1211 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1212 * the configuration information for the color look up table.
1213 * @param LayerIdx DMA2D Layer index.
1214 * This parameter can be one of the following values:
1215 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1216 * @note API obsolete and maintained for compatibility with legacy. User is
1217 * invited to resort to HAL_DMA2D_CLUTStartLoad_IT() instead to benefit
1218 * from code compactness, code size and improved heap usage.
1219 * @retval HAL status
1220 */
HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef * hdma2d,DMA2D_CLUTCfgTypeDef CLUTCfg,uint32_t LayerIdx)1221 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1222 {
1223 /* Check the parameters */
1224 assert_param(IS_DMA2D_LAYER(LayerIdx));
1225 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1226 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1227
1228 /* Process locked */
1229 __HAL_LOCK(hdma2d);
1230
1231 /* Change DMA2D peripheral state */
1232 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1233
1234 /* Configure the CLUT of the background DMA2D layer */
1235 if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1236 {
1237 /* Write background CLUT memory address */
1238 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1239
1240 /* Write background CLUT size and CLUT color mode */
1241 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1242 ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1243
1244 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1245 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
1246
1247 /* Enable the CLUT loading for the background */
1248 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1249 }
1250 /* Configure the CLUT of the foreground DMA2D layer */
1251 else
1252 {
1253 /* Write foreground CLUT memory address */
1254 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1255
1256 /* Write foreground CLUT size and CLUT color mode */
1257 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1258 ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1259
1260 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1261 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
1262
1263 /* Enable the CLUT loading for the foreground */
1264 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1265 }
1266
1267 return HAL_OK;
1268 }
1269
1270 /**
1271 * @brief Abort the DMA2D CLUT loading.
1272 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1273 * the configuration information for the DMA2D.
1274 * @param LayerIdx DMA2D Layer index.
1275 * This parameter can be one of the following values:
1276 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1277 * @retval HAL status
1278 */
HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)1279 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1280 {
1281 uint32_t tickstart;
1282 const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
1283
1284 /* Abort the CLUT loading */
1285 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
1286
1287 /* If foreground CLUT loading is considered, update local variables */
1288 if (LayerIdx == DMA2D_FOREGROUND_LAYER)
1289 {
1290 reg = &(hdma2d->Instance->FGPFCCR);
1291 }
1292
1293
1294 /* Get tick */
1295 tickstart = HAL_GetTick();
1296
1297 /* Check if the CLUT loading is aborted */
1298 while ((*reg & DMA2D_BGPFCCR_START) != 0U)
1299 {
1300 if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT)
1301 {
1302 /* Update error code */
1303 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1304
1305 /* Change the DMA2D state */
1306 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1307
1308 /* Process Unlocked */
1309 __HAL_UNLOCK(hdma2d);
1310
1311 return HAL_TIMEOUT;
1312 }
1313 }
1314
1315 /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
1316 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
1317
1318 /* Change the DMA2D state*/
1319 hdma2d->State = HAL_DMA2D_STATE_READY;
1320
1321 /* Process Unlocked */
1322 __HAL_UNLOCK(hdma2d);
1323
1324 return HAL_OK;
1325 }
1326
1327 /**
1328 * @brief Suspend the DMA2D CLUT loading.
1329 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1330 * the configuration information for the DMA2D.
1331 * @param LayerIdx DMA2D Layer index.
1332 * This parameter can be one of the following values:
1333 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1334 * @retval HAL status
1335 */
HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)1336 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1337 {
1338 uint32_t tickstart;
1339 uint32_t loadsuspended;
1340 const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
1341
1342 /* Suspend the CLUT loading */
1343 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1344
1345 /* If foreground CLUT loading is considered, update local variables */
1346 if (LayerIdx == DMA2D_FOREGROUND_LAYER)
1347 {
1348 reg = &(hdma2d->Instance->FGPFCCR);
1349 }
1350
1351 /* Get tick */
1352 tickstart = HAL_GetTick();
1353
1354 /* Check if the CLUT loading is suspended */
1355 /* 1st condition: Suspend Check */
1356 loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;
1357 /* 2nd condition: Not Start Check */
1358 loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL;
1359 while (loadsuspended == 0UL)
1360 {
1361 if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND)
1362 {
1363 /* Update error code */
1364 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1365
1366 /* Change the DMA2D state */
1367 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1368
1369 return HAL_TIMEOUT;
1370 }
1371 /* 1st condition: Suspend Check */
1372 loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;
1373 /* 2nd condition: Not Start Check */
1374 loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL;
1375 }
1376
1377 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
1378 if ((*reg & DMA2D_BGPFCCR_START) != 0U)
1379 {
1380 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
1381 }
1382 else
1383 {
1384 /* Make sure SUSP bit is cleared since it is meaningless
1385 when no transfer is on-going */
1386 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1387 }
1388
1389 return HAL_OK;
1390 }
1391
1392 /**
1393 * @brief Resume the DMA2D CLUT loading.
1394 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1395 * the configuration information for the DMA2D.
1396 * @param LayerIdx DMA2D Layer index.
1397 * This parameter can be one of the following values:
1398 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1399 * @retval HAL status
1400 */
HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)1401 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1402 {
1403 /* Check the SUSP and START bits for background or foreground CLUT loading */
1404 if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1405 {
1406 /* Background CLUT loading suspension check */
1407 if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
1408 {
1409 if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
1410 {
1411 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
1412 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1413 }
1414 }
1415 }
1416 else
1417 {
1418 /* Foreground CLUT loading suspension check */
1419 if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
1420 {
1421 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
1422 {
1423 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
1424 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1425 }
1426 }
1427 }
1428
1429 /* Resume the CLUT loading */
1430 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1431
1432 return HAL_OK;
1433 }
1434
1435
1436 /**
1437
1438 * @brief Polling for transfer complete or CLUT loading.
1439 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1440 * the configuration information for the DMA2D.
1441 * @param Timeout Timeout duration
1442 * @retval HAL status
1443 */
HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef * hdma2d,uint32_t Timeout)1444 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
1445 {
1446 uint32_t tickstart;
1447 uint32_t layer_start;
1448 __IO uint32_t isrflags = 0x0U;
1449
1450 /* Polling for DMA2D transfer */
1451 if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
1452 {
1453 /* Get tick */
1454 tickstart = HAL_GetTick();
1455
1456 while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
1457 {
1458 isrflags = READ_REG(hdma2d->Instance->ISR);
1459 if ((isrflags & (DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
1460 {
1461 if ((isrflags & DMA2D_FLAG_CE) != 0U)
1462 {
1463 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1464 }
1465 if ((isrflags & DMA2D_FLAG_TE) != 0U)
1466 {
1467 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1468 }
1469 /* Clear the transfer and configuration error flags */
1470 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1471
1472 /* Change DMA2D state */
1473 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1474
1475 /* Process unlocked */
1476 __HAL_UNLOCK(hdma2d);
1477
1478 return HAL_ERROR;
1479 }
1480 /* Check for the Timeout */
1481 if (Timeout != HAL_MAX_DELAY)
1482 {
1483 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
1484 {
1485 /* Update error code */
1486 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1487
1488 /* Change the DMA2D state */
1489 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1490
1491 /* Process unlocked */
1492 __HAL_UNLOCK(hdma2d);
1493
1494 return HAL_TIMEOUT;
1495 }
1496 }
1497 }
1498 }
1499 /* Polling for CLUT loading (foreground or background) */
1500 layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
1501 layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
1502 if (layer_start != 0U)
1503 {
1504 /* Get tick */
1505 tickstart = HAL_GetTick();
1506
1507 while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
1508 {
1509 isrflags = READ_REG(hdma2d->Instance->ISR);
1510 if ((isrflags & (DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
1511 {
1512 if ((isrflags & DMA2D_FLAG_CAE) != 0U)
1513 {
1514 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1515 }
1516 if ((isrflags & DMA2D_FLAG_CE) != 0U)
1517 {
1518 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1519 }
1520 if ((isrflags & DMA2D_FLAG_TE) != 0U)
1521 {
1522 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1523 }
1524 /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
1525 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1526
1527 /* Change DMA2D state */
1528 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1529
1530 /* Process unlocked */
1531 __HAL_UNLOCK(hdma2d);
1532
1533 return HAL_ERROR;
1534 }
1535 /* Check for the Timeout */
1536 if (Timeout != HAL_MAX_DELAY)
1537 {
1538 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
1539 {
1540 /* Update error code */
1541 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1542
1543 /* Change the DMA2D state */
1544 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1545
1546 /* Process unlocked */
1547 __HAL_UNLOCK(hdma2d);
1548
1549 return HAL_TIMEOUT;
1550 }
1551 }
1552 }
1553 }
1554
1555 /* Clear the transfer complete and CLUT loading flags */
1556 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC | DMA2D_FLAG_CTC);
1557
1558 /* Change DMA2D state */
1559 hdma2d->State = HAL_DMA2D_STATE_READY;
1560
1561 /* Process unlocked */
1562 __HAL_UNLOCK(hdma2d);
1563
1564 return HAL_OK;
1565 }
1566 /**
1567 * @brief Handle DMA2D interrupt request.
1568 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1569 * the configuration information for the DMA2D.
1570 * @retval HAL status
1571 */
HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef * hdma2d)1572 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
1573 {
1574 uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
1575 uint32_t crflags = READ_REG(hdma2d->Instance->CR);
1576
1577 /* Transfer Error Interrupt management ***************************************/
1578 if ((isrflags & DMA2D_FLAG_TE) != 0U)
1579 {
1580 if ((crflags & DMA2D_IT_TE) != 0U)
1581 {
1582 /* Disable the transfer Error interrupt */
1583 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
1584
1585 /* Update error code */
1586 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1587
1588 /* Clear the transfer error flag */
1589 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
1590
1591 /* Change DMA2D state */
1592 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1593
1594 /* Process Unlocked */
1595 __HAL_UNLOCK(hdma2d);
1596
1597 if (hdma2d->XferErrorCallback != NULL)
1598 {
1599 /* Transfer error Callback */
1600 hdma2d->XferErrorCallback(hdma2d);
1601 }
1602 }
1603 }
1604 /* Configuration Error Interrupt management **********************************/
1605 if ((isrflags & DMA2D_FLAG_CE) != 0U)
1606 {
1607 if ((crflags & DMA2D_IT_CE) != 0U)
1608 {
1609 /* Disable the Configuration Error interrupt */
1610 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
1611
1612 /* Clear the Configuration error flag */
1613 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
1614
1615 /* Update error code */
1616 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1617
1618 /* Change DMA2D state */
1619 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1620
1621 /* Process Unlocked */
1622 __HAL_UNLOCK(hdma2d);
1623
1624 if (hdma2d->XferErrorCallback != NULL)
1625 {
1626 /* Transfer error Callback */
1627 hdma2d->XferErrorCallback(hdma2d);
1628 }
1629 }
1630 }
1631 /* CLUT access Error Interrupt management ***********************************/
1632 if ((isrflags & DMA2D_FLAG_CAE) != 0U)
1633 {
1634 if ((crflags & DMA2D_IT_CAE) != 0U)
1635 {
1636 /* Disable the CLUT access error interrupt */
1637 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
1638
1639 /* Clear the CLUT access error flag */
1640 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
1641
1642 /* Update error code */
1643 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1644
1645 /* Change DMA2D state */
1646 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1647
1648 /* Process Unlocked */
1649 __HAL_UNLOCK(hdma2d);
1650
1651 if (hdma2d->XferErrorCallback != NULL)
1652 {
1653 /* Transfer error Callback */
1654 hdma2d->XferErrorCallback(hdma2d);
1655 }
1656 }
1657 }
1658 /* Transfer watermark Interrupt management **********************************/
1659 if ((isrflags & DMA2D_FLAG_TW) != 0U)
1660 {
1661 if ((crflags & DMA2D_IT_TW) != 0U)
1662 {
1663 /* Disable the transfer watermark interrupt */
1664 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
1665
1666 /* Clear the transfer watermark flag */
1667 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
1668
1669 /* Transfer watermark Callback */
1670 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
1671 hdma2d->LineEventCallback(hdma2d);
1672 #else
1673 HAL_DMA2D_LineEventCallback(hdma2d);
1674 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
1675
1676 }
1677 }
1678 /* Transfer Complete Interrupt management ************************************/
1679 if ((isrflags & DMA2D_FLAG_TC) != 0U)
1680 {
1681 if ((crflags & DMA2D_IT_TC) != 0U)
1682 {
1683 /* Disable the transfer complete interrupt */
1684 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
1685
1686 /* Clear the transfer complete flag */
1687 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
1688
1689 /* Update error code */
1690 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1691
1692 /* Change DMA2D state */
1693 hdma2d->State = HAL_DMA2D_STATE_READY;
1694
1695 /* Process Unlocked */
1696 __HAL_UNLOCK(hdma2d);
1697
1698 if (hdma2d->XferCpltCallback != NULL)
1699 {
1700 /* Transfer complete Callback */
1701 hdma2d->XferCpltCallback(hdma2d);
1702 }
1703 }
1704 }
1705 /* CLUT Transfer Complete Interrupt management ******************************/
1706 if ((isrflags & DMA2D_FLAG_CTC) != 0U)
1707 {
1708 if ((crflags & DMA2D_IT_CTC) != 0U)
1709 {
1710 /* Disable the CLUT transfer complete interrupt */
1711 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
1712
1713 /* Clear the CLUT transfer complete flag */
1714 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
1715
1716 /* Update error code */
1717 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1718
1719 /* Change DMA2D state */
1720 hdma2d->State = HAL_DMA2D_STATE_READY;
1721
1722 /* Process Unlocked */
1723 __HAL_UNLOCK(hdma2d);
1724
1725 /* CLUT Transfer complete Callback */
1726 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
1727 hdma2d->CLUTLoadingCpltCallback(hdma2d);
1728 #else
1729 HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
1730 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
1731 }
1732 }
1733
1734 }
1735
1736 /**
1737 * @brief Transfer watermark callback.
1738 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1739 * the configuration information for the DMA2D.
1740 * @retval None
1741 */
HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef * hdma2d)1742 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
1743 {
1744 /* Prevent unused argument(s) compilation warning */
1745 UNUSED(hdma2d);
1746
1747 /* NOTE : This function should not be modified; when the callback is needed,
1748 the HAL_DMA2D_LineEventCallback can be implemented in the user file.
1749 */
1750 }
1751
1752 /**
1753 * @brief CLUT Transfer Complete callback.
1754 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
1755 * the configuration information for the DMA2D.
1756 * @retval None
1757 */
HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef * hdma2d)1758 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
1759 {
1760 /* Prevent unused argument(s) compilation warning */
1761 UNUSED(hdma2d);
1762
1763 /* NOTE : This function should not be modified; when the callback is needed,
1764 the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
1765 */
1766 }
1767
1768 /**
1769 * @}
1770 */
1771
1772 /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
1773 * @brief Peripheral Control functions
1774 *
1775 @verbatim
1776 ===============================================================================
1777 ##### Peripheral Control functions #####
1778 ===============================================================================
1779 [..] This section provides functions allowing to:
1780 (+) Configure the DMA2D foreground or background layer parameters.
1781 (+) Configure the DMA2D CLUT transfer.
1782 (+) Configure the line watermark
1783 (+) Configure the dead time value.
1784 (+) Enable or disable the dead time value functionality.
1785
1786
1787 @endverbatim
1788 * @{
1789 */
1790
1791 /**
1792 * @brief Configure the DMA2D Layer according to the specified
1793 * parameters in the DMA2D_HandleTypeDef.
1794 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1795 * the configuration information for the DMA2D.
1796 * @param LayerIdx DMA2D Layer index.
1797 * This parameter can be one of the following values:
1798 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1799 * @retval HAL status
1800 */
HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef * hdma2d,uint32_t LayerIdx)1801 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1802 {
1803 DMA2D_LayerCfgTypeDef *pLayerCfg;
1804 uint32_t regMask;
1805 uint32_t regValue;
1806
1807 /* Check the parameters */
1808 assert_param(IS_DMA2D_LAYER(LayerIdx));
1809 assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
1810 if (hdma2d->Init.Mode != DMA2D_R2M)
1811 {
1812 assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode));
1813 if (hdma2d->Init.Mode != DMA2D_M2M)
1814 {
1815 assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
1816 }
1817 }
1818 assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted));
1819 assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap));
1820
1821 /* Process locked */
1822 __HAL_LOCK(hdma2d);
1823
1824 /* Change DMA2D peripheral state */
1825 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1826
1827 pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
1828
1829 /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
1830 regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) | \
1831 (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
1832 regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS);
1833
1834
1835 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1836 {
1837 regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
1838 }
1839 else
1840 {
1841 regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
1842 }
1843
1844 /* Configure the background DMA2D layer */
1845 if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1846 {
1847 /* Write DMA2D BGPFCCR register */
1848 MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
1849
1850 /* DMA2D BGOR register configuration -------------------------------------*/
1851 WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
1852
1853 /* DMA2D BGCOLR register configuration -------------------------------------*/
1854 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1855 {
1856 WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \
1857 DMA2D_BGCOLR_RED));
1858 }
1859 }
1860 /* Configure the foreground DMA2D layer */
1861 else
1862 {
1863
1864
1865 /* Write DMA2D FGPFCCR register */
1866 MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
1867
1868 /* DMA2D FGOR register configuration -------------------------------------*/
1869 WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
1870
1871 /* DMA2D FGCOLR register configuration -------------------------------------*/
1872 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1873 {
1874 WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \
1875 DMA2D_FGCOLR_RED));
1876 }
1877 }
1878 /* Initialize the DMA2D state*/
1879 hdma2d->State = HAL_DMA2D_STATE_READY;
1880
1881 /* Process unlocked */
1882 __HAL_UNLOCK(hdma2d);
1883
1884 return HAL_OK;
1885 }
1886
1887 /**
1888 * @brief Configure the DMA2D CLUT Transfer.
1889 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1890 * the configuration information for the DMA2D.
1891 * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1892 * the configuration information for the color look up table.
1893 * @param LayerIdx DMA2D Layer index.
1894 * This parameter can be one of the following values:
1895 * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
1896 * @note API obsolete and maintained for compatibility with legacy. User is invited
1897 * to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from code compactness,
1898 * code size and improved heap usage.
1899 * @retval HAL status
1900 */
HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef * hdma2d,DMA2D_CLUTCfgTypeDef CLUTCfg,uint32_t LayerIdx)1901 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1902 {
1903 /* Check the parameters */
1904 assert_param(IS_DMA2D_LAYER(LayerIdx));
1905 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1906 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1907
1908 /* Process locked */
1909 __HAL_LOCK(hdma2d);
1910
1911 /* Change DMA2D peripheral state */
1912 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1913
1914 /* Configure the CLUT of the background DMA2D layer */
1915 if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1916 {
1917 /* Write background CLUT memory address */
1918 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1919
1920 /* Write background CLUT size and CLUT color mode */
1921 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1922 ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1923 }
1924 /* Configure the CLUT of the foreground DMA2D layer */
1925 else
1926 {
1927 /* Write foreground CLUT memory address */
1928 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1929
1930 /* Write foreground CLUT size and CLUT color mode */
1931 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1932 ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1933 }
1934
1935 /* Set the DMA2D state to Ready*/
1936 hdma2d->State = HAL_DMA2D_STATE_READY;
1937
1938 /* Process unlocked */
1939 __HAL_UNLOCK(hdma2d);
1940
1941 return HAL_OK;
1942 }
1943
1944
1945 /**
1946 * @brief Configure the line watermark.
1947 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
1948 * the configuration information for the DMA2D.
1949 * @param Line Line Watermark configuration (maximum 16-bit long value expected).
1950 * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
1951 * @note The transfer watermark interrupt is disabled once it has occurred.
1952 * @retval HAL status
1953 */
1954
HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef * hdma2d,uint32_t Line)1955 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
1956 {
1957 /* Check the parameters */
1958 if (Line > DMA2D_LWR_LW)
1959 {
1960 return HAL_ERROR;
1961 }
1962 else
1963 {
1964 /* Process locked */
1965 __HAL_LOCK(hdma2d);
1966
1967 /* Change DMA2D peripheral state */
1968 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1969
1970 /* Sets the Line watermark configuration */
1971 WRITE_REG(hdma2d->Instance->LWR, Line);
1972
1973 /* Enable the Line interrupt */
1974 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
1975
1976 /* Initialize the DMA2D state*/
1977 hdma2d->State = HAL_DMA2D_STATE_READY;
1978
1979 /* Process unlocked */
1980 __HAL_UNLOCK(hdma2d);
1981
1982 return HAL_OK;
1983 }
1984 }
1985
1986 /**
1987 * @brief Enable DMA2D dead time feature.
1988 * @param hdma2d DMA2D handle.
1989 * @retval HAL status
1990 */
HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef * hdma2d)1991 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1992 {
1993 /* Process Locked */
1994 __HAL_LOCK(hdma2d);
1995
1996 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1997
1998 /* Set DMA2D_AMTCR EN bit */
1999 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
2000
2001 hdma2d->State = HAL_DMA2D_STATE_READY;
2002
2003 /* Process Unlocked */
2004 __HAL_UNLOCK(hdma2d);
2005
2006 return HAL_OK;
2007 }
2008
2009 /**
2010 * @brief Disable DMA2D dead time feature.
2011 * @param hdma2d DMA2D handle.
2012 * @retval HAL status
2013 */
HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef * hdma2d)2014 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
2015 {
2016 /* Process Locked */
2017 __HAL_LOCK(hdma2d);
2018
2019 hdma2d->State = HAL_DMA2D_STATE_BUSY;
2020
2021 /* Clear DMA2D_AMTCR EN bit */
2022 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
2023
2024 hdma2d->State = HAL_DMA2D_STATE_READY;
2025
2026 /* Process Unlocked */
2027 __HAL_UNLOCK(hdma2d);
2028
2029 return HAL_OK;
2030 }
2031
2032 /**
2033 * @brief Configure dead time.
2034 * @note The dead time value represents the guaranteed minimum number of cycles between
2035 * two consecutive transactions on the AHB bus.
2036 * @param hdma2d DMA2D handle.
2037 * @param DeadTime dead time value.
2038 * @retval HAL status
2039 */
HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef * hdma2d,uint8_t DeadTime)2040 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
2041 {
2042 /* Process Locked */
2043 __HAL_LOCK(hdma2d);
2044
2045 hdma2d->State = HAL_DMA2D_STATE_BUSY;
2046
2047 /* Set DMA2D_AMTCR DT field */
2048 MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos));
2049
2050 hdma2d->State = HAL_DMA2D_STATE_READY;
2051
2052 /* Process Unlocked */
2053 __HAL_UNLOCK(hdma2d);
2054
2055 return HAL_OK;
2056 }
2057
2058 /**
2059 * @}
2060 */
2061
2062
2063 /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
2064 * @brief Peripheral State functions
2065 *
2066 @verbatim
2067 ===============================================================================
2068 ##### Peripheral State and Errors functions #####
2069 ===============================================================================
2070 [..]
2071 This subsection provides functions allowing to:
2072 (+) Get the DMA2D state
2073 (+) Get the DMA2D error code
2074
2075 @endverbatim
2076 * @{
2077 */
2078
2079 /**
2080 * @brief Return the DMA2D state
2081 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
2082 * the configuration information for the DMA2D.
2083 * @retval HAL state
2084 */
HAL_DMA2D_GetState(DMA2D_HandleTypeDef * hdma2d)2085 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
2086 {
2087 return hdma2d->State;
2088 }
2089
2090 /**
2091 * @brief Return the DMA2D error code
2092 * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
2093 * the configuration information for DMA2D.
2094 * @retval DMA2D Error Code
2095 */
HAL_DMA2D_GetError(DMA2D_HandleTypeDef * hdma2d)2096 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
2097 {
2098 return hdma2d->ErrorCode;
2099 }
2100
2101 /**
2102 * @}
2103 */
2104
2105 /**
2106 * @}
2107 */
2108
2109
2110 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
2111 * @{
2112 */
2113
2114 /**
2115 * @brief Set the DMA2D transfer parameters.
2116 * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
2117 * the configuration information for the specified DMA2D.
2118 * @param pdata The source memory Buffer address
2119 * @param DstAddress The destination memory Buffer address
2120 * @param Width The width of data to be transferred from source to destination.
2121 * @param Height The height of data to be transferred from source to destination.
2122 * @retval HAL status
2123 */
DMA2D_SetConfig(DMA2D_HandleTypeDef * hdma2d,uint32_t pdata,uint32_t DstAddress,uint32_t Width,uint32_t Height)2124 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
2125 uint32_t Height)
2126 {
2127 uint32_t tmp;
2128 uint32_t tmp1;
2129 uint32_t tmp2;
2130 uint32_t tmp3;
2131 uint32_t tmp4;
2132
2133 /* Configure DMA2D data size */
2134 MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL | DMA2D_NLR_PL), (Height | (Width << DMA2D_NLR_PL_Pos)));
2135
2136 /* Configure DMA2D destination address */
2137 WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
2138
2139 /* Register to memory DMA2D mode selected */
2140 if (hdma2d->Init.Mode == DMA2D_R2M)
2141 {
2142 tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
2143 tmp2 = pdata & DMA2D_OCOLR_RED_1;
2144 tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
2145 tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
2146
2147 /* Prepare the value to be written to the OCOLR register according to the color mode */
2148 if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
2149 {
2150 tmp = (tmp3 | tmp2 | tmp1 | tmp4);
2151 }
2152 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
2153 {
2154 tmp = (tmp3 | tmp2 | tmp4);
2155 }
2156 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
2157 {
2158 tmp2 = (tmp2 >> 19U);
2159 tmp3 = (tmp3 >> 10U);
2160 tmp4 = (tmp4 >> 3U);
2161 tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
2162 }
2163 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
2164 {
2165 tmp1 = (tmp1 >> 31U);
2166 tmp2 = (tmp2 >> 19U);
2167 tmp3 = (tmp3 >> 11U);
2168 tmp4 = (tmp4 >> 3U);
2169 tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
2170 }
2171 else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
2172 {
2173 tmp1 = (tmp1 >> 28U);
2174 tmp2 = (tmp2 >> 20U);
2175 tmp3 = (tmp3 >> 12U);
2176 tmp4 = (tmp4 >> 4U);
2177 tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
2178 }
2179 /* Write to DMA2D OCOLR register */
2180 WRITE_REG(hdma2d->Instance->OCOLR, tmp);
2181 }
2182 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
2183 else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) /*M2M_blending with fixed color FG DMA2D Mode selected*/
2184 {
2185 WRITE_REG(hdma2d->Instance->BGMAR, pdata);
2186 }
2187 else /* M2M, M2M_PFC,M2M_Blending or M2M_blending with fixed color BG DMA2D Mode */
2188 #else
2189 else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
2190 #endif /*DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT*/
2191 {
2192 /* Configure DMA2D source address */
2193 WRITE_REG(hdma2d->Instance->FGMAR, pdata);
2194 }
2195 }
2196
2197 /**
2198 * @}
2199 */
2200
2201 /**
2202 * @}
2203 */
2204
2205 /**
2206 * @}
2207 */
2208 #endif /* DMA2D */
2209 #endif /* HAL_DMA2D_MODULE_ENABLED */
2210
