1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32L4xx_LL_TIM_H
21 #define __STM32L4xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l4xx.h"
29
30 /** @addtogroup STM32L4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x3CU, /* 7: TIMx_CH5 */
55 0x3CU /* 8: TIMx_CH6 */
56 };
57
58 static const uint8_t SHIFT_TAB_OCxx[] =
59 {
60 0U, /* 0: OC1M, OC1FE, OC1PE */
61 0U, /* 1: - NA */
62 8U, /* 2: OC2M, OC2FE, OC2PE */
63 0U, /* 3: - NA */
64 0U, /* 4: OC3M, OC3FE, OC3PE */
65 0U, /* 5: - NA */
66 8U, /* 6: OC4M, OC4FE, OC4PE */
67 0U, /* 7: OC5M, OC5FE, OC5PE */
68 8U /* 8: OC6M, OC6FE, OC6PE */
69 };
70
71 static const uint8_t SHIFT_TAB_ICxx[] =
72 {
73 0U, /* 0: CC1S, IC1PSC, IC1F */
74 0U, /* 1: - NA */
75 8U, /* 2: CC2S, IC2PSC, IC2F */
76 0U, /* 3: - NA */
77 0U, /* 4: CC3S, IC3PSC, IC3F */
78 0U, /* 5: - NA */
79 8U, /* 6: CC4S, IC4PSC, IC4F */
80 0U, /* 7: - NA */
81 0U /* 8: - NA */
82 };
83
84 static const uint8_t SHIFT_TAB_CCxP[] =
85 {
86 0U, /* 0: CC1P */
87 2U, /* 1: CC1NP */
88 4U, /* 2: CC2P */
89 6U, /* 3: CC2NP */
90 8U, /* 4: CC3P */
91 10U, /* 5: CC3NP */
92 12U, /* 6: CC4P */
93 16U, /* 7: CC5P */
94 20U /* 8: CC6P */
95 };
96
97 static const uint8_t SHIFT_TAB_OISx[] =
98 {
99 0U, /* 0: OIS1 */
100 1U, /* 1: OIS1N */
101 2U, /* 2: OIS2 */
102 3U, /* 3: OIS2N */
103 4U, /* 4: OIS3 */
104 5U, /* 5: OIS3N */
105 6U, /* 6: OIS4 */
106 8U, /* 7: OIS5 */
107 10U /* 8: OIS6 */
108 };
109 /**
110 * @}
111 */
112
113 /* Private constants ---------------------------------------------------------*/
114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
115 * @{
116 */
117
118 /* Defines used for the bit position in the register and perform offsets */
119 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
120
121 /* Generic bit definitions for TIMx_OR2 register */
122 #define TIMx_OR2_BKINP TIM1_OR2_BKINP /*!< BRK BKIN input polarity */
123 #define TIMx_OR2_ETRSEL TIM1_OR2_ETRSEL /*!< TIMx ETR source selection */
124
125 /* Remap mask definitions */
126 #define TIMx_OR1_RMP_SHIFT 16U
127 #define TIMx_OR1_RMP_MASK 0x0000FFFFU
128 #if defined(ADC3)
129 #define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
130 #else
131 #define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
132 #endif /* ADC3 */
133 #define TIM2_OR1_RMP_MASK ((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR1_RMP | TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT)
134 #define TIM3_OR1_RMP_MASK (TIM3_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
135 #if defined(ADC2) && defined(ADC3)
136 #define TIM8_OR1_RMP_MASK ((TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
137 #else
138 #define TIM8_OR1_RMP_MASK (TIM8_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
139 #endif /* ADC2 & ADC3 */
140 #define TIM15_OR1_RMP_MASK (TIM15_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
141 #define TIM16_OR1_RMP_MASK (TIM16_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
142 #define TIM17_OR1_RMP_MASK (TIM17_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
143
144 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
145 #define DT_DELAY_1 ((uint8_t)0x7F)
146 #define DT_DELAY_2 ((uint8_t)0x3F)
147 #define DT_DELAY_3 ((uint8_t)0x1F)
148 #define DT_DELAY_4 ((uint8_t)0x1F)
149
150 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
151 #define DT_RANGE_1 ((uint8_t)0x00)
152 #define DT_RANGE_2 ((uint8_t)0x80)
153 #define DT_RANGE_3 ((uint8_t)0xC0)
154 #define DT_RANGE_4 ((uint8_t)0xE0)
155
156 /** Legacy definitions for compatibility purpose
157 @cond 0
158 */
159 #if defined(DFSDM1_Channel0)
160 #define TIMx_OR2_BKDFBK0E TIMx_OR2_BKDF1BK0E
161 #define TIMx_OR3_BK2DFBK1E TIMx_OR3_BK2DF1BK1E
162 #endif /* DFSDM1_Channel0 */
163 /**
164 @endcond
165 */
166
167 /**
168 * @}
169 */
170
171 /* Private macros ------------------------------------------------------------*/
172 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
173 * @{
174 */
175 /** @brief Convert channel id into channel index.
176 * @param __CHANNEL__ This parameter can be one of the following values:
177 * @arg @ref LL_TIM_CHANNEL_CH1
178 * @arg @ref LL_TIM_CHANNEL_CH1N
179 * @arg @ref LL_TIM_CHANNEL_CH2
180 * @arg @ref LL_TIM_CHANNEL_CH2N
181 * @arg @ref LL_TIM_CHANNEL_CH3
182 * @arg @ref LL_TIM_CHANNEL_CH3N
183 * @arg @ref LL_TIM_CHANNEL_CH4
184 * @arg @ref LL_TIM_CHANNEL_CH5
185 * @arg @ref LL_TIM_CHANNEL_CH6
186 * @retval none
187 */
188 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
189 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
190 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
191 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
192 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
193 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
194 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
195 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
196 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
197
198 /** @brief Calculate the deadtime sampling period(in ps).
199 * @param __TIMCLK__ timer input clock frequency (in Hz).
200 * @param __CKD__ This parameter can be one of the following values:
201 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
202 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
203 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
204 * @retval none
205 */
206 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
207 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
208 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
209 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
210 /**
211 * @}
212 */
213
214
215 /* Exported types ------------------------------------------------------------*/
216 #if defined(USE_FULL_LL_DRIVER)
217 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
218 * @{
219 */
220
221 /**
222 * @brief TIM Time Base configuration structure definition.
223 */
224 typedef struct
225 {
226 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
227 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
228
229 This feature can be modified afterwards using unitary function
230 @ref LL_TIM_SetPrescaler().*/
231
232 uint32_t CounterMode; /*!< Specifies the counter mode.
233 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
234
235 This feature can be modified afterwards using unitary function
236 @ref LL_TIM_SetCounterMode().*/
237
238 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
239 Auto-Reload Register at the next update event.
240 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
241 Some timer instances may support 32 bits counters. In that case this parameter must
242 be a number between 0x0000 and 0xFFFFFFFF.
243
244 This feature can be modified afterwards using unitary function
245 @ref LL_TIM_SetAutoReload().*/
246
247 uint32_t ClockDivision; /*!< Specifies the clock division.
248 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
249
250 This feature can be modified afterwards using unitary function
251 @ref LL_TIM_SetClockDivision().*/
252
253 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
254 reaches zero, an update event is generated and counting restarts
255 from the RCR value (N).
256 This means in PWM mode that (N+1) corresponds to:
257 - the number of PWM periods in edge-aligned mode
258 - the number of half PWM period in center-aligned mode
259 GP timers: this parameter must be a number between Min_Data = 0x00 and
260 Max_Data = 0xFF.
261 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
262 Max_Data = 0xFFFF.
263
264 This feature can be modified afterwards using unitary function
265 @ref LL_TIM_SetRepetitionCounter().*/
266 } LL_TIM_InitTypeDef;
267
268 /**
269 * @brief TIM Output Compare configuration structure definition.
270 */
271 typedef struct
272 {
273 uint32_t OCMode; /*!< Specifies the output mode.
274 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
275
276 This feature can be modified afterwards using unitary function
277 @ref LL_TIM_OC_SetMode().*/
278
279 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
280 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
281
282 This feature can be modified afterwards using unitary functions
283 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
284
285 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
286 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
287
288 This feature can be modified afterwards using unitary functions
289 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
290
291 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
292 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
293
294 This feature can be modified afterwards using unitary function
295 LL_TIM_OC_SetCompareCHx (x=1..6).*/
296
297 uint32_t OCPolarity; /*!< Specifies the output polarity.
298 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
299
300 This feature can be modified afterwards using unitary function
301 @ref LL_TIM_OC_SetPolarity().*/
302
303 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
304 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
305
306 This feature can be modified afterwards using unitary function
307 @ref LL_TIM_OC_SetPolarity().*/
308
309
310 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
311 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
312
313 This feature can be modified afterwards using unitary function
314 @ref LL_TIM_OC_SetIdleState().*/
315
316 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
317 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
318
319 This feature can be modified afterwards using unitary function
320 @ref LL_TIM_OC_SetIdleState().*/
321 } LL_TIM_OC_InitTypeDef;
322
323 /**
324 * @brief TIM Input Capture configuration structure definition.
325 */
326
327 typedef struct
328 {
329
330 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
331 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
332
333 This feature can be modified afterwards using unitary function
334 @ref LL_TIM_IC_SetPolarity().*/
335
336 uint32_t ICActiveInput; /*!< Specifies the input.
337 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
338
339 This feature can be modified afterwards using unitary function
340 @ref LL_TIM_IC_SetActiveInput().*/
341
342 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
343 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
344
345 This feature can be modified afterwards using unitary function
346 @ref LL_TIM_IC_SetPrescaler().*/
347
348 uint32_t ICFilter; /*!< Specifies the input capture filter.
349 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
350
351 This feature can be modified afterwards using unitary function
352 @ref LL_TIM_IC_SetFilter().*/
353 } LL_TIM_IC_InitTypeDef;
354
355
356 /**
357 * @brief TIM Encoder interface configuration structure definition.
358 */
359 typedef struct
360 {
361 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
362 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
363
364 This feature can be modified afterwards using unitary function
365 @ref LL_TIM_SetEncoderMode().*/
366
367 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
368 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
369
370 This feature can be modified afterwards using unitary function
371 @ref LL_TIM_IC_SetPolarity().*/
372
373 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
374 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
375
376 This feature can be modified afterwards using unitary function
377 @ref LL_TIM_IC_SetActiveInput().*/
378
379 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
380 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
381
382 This feature can be modified afterwards using unitary function
383 @ref LL_TIM_IC_SetPrescaler().*/
384
385 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
386 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
387
388 This feature can be modified afterwards using unitary function
389 @ref LL_TIM_IC_SetFilter().*/
390
391 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
392 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
393
394 This feature can be modified afterwards using unitary function
395 @ref LL_TIM_IC_SetPolarity().*/
396
397 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
398 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
399
400 This feature can be modified afterwards using unitary function
401 @ref LL_TIM_IC_SetActiveInput().*/
402
403 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
404 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
405
406 This feature can be modified afterwards using unitary function
407 @ref LL_TIM_IC_SetPrescaler().*/
408
409 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
410 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
411
412 This feature can be modified afterwards using unitary function
413 @ref LL_TIM_IC_SetFilter().*/
414
415 } LL_TIM_ENCODER_InitTypeDef;
416
417 /**
418 * @brief TIM Hall sensor interface configuration structure definition.
419 */
420 typedef struct
421 {
422
423 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
424 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
425
426 This feature can be modified afterwards using unitary function
427 @ref LL_TIM_IC_SetPolarity().*/
428
429 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
430 Prescaler must be set to get a maximum counter period longer than the
431 time interval between 2 consecutive changes on the Hall inputs.
432 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
433
434 This feature can be modified afterwards using unitary function
435 @ref LL_TIM_IC_SetPrescaler().*/
436
437 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
438 This parameter can be a value of
439 @ref TIM_LL_EC_IC_FILTER.
440
441 This feature can be modified afterwards using unitary function
442 @ref LL_TIM_IC_SetFilter().*/
443
444 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
445 A positive pulse (TRGO event) is generated with a programmable delay every time
446 a change occurs on the Hall inputs.
447 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
448
449 This feature can be modified afterwards using unitary function
450 @ref LL_TIM_OC_SetCompareCH2().*/
451 } LL_TIM_HALLSENSOR_InitTypeDef;
452
453 /**
454 * @brief BDTR (Break and Dead Time) structure definition
455 */
456 typedef struct
457 {
458 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
459 This parameter can be a value of @ref TIM_LL_EC_OSSR
460
461 This feature can be modified afterwards using unitary function
462 @ref LL_TIM_SetOffStates()
463
464 @note This bit-field cannot be modified as long as LOCK level 2 has been
465 programmed. */
466
467 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
468 This parameter can be a value of @ref TIM_LL_EC_OSSI
469
470 This feature can be modified afterwards using unitary function
471 @ref LL_TIM_SetOffStates()
472
473 @note This bit-field cannot be modified as long as LOCK level 2 has been
474 programmed. */
475
476 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
477 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
478
479 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
480 register has been written, their content is frozen until the next reset.*/
481
482 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
483 switching-on of the outputs.
484 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
485
486 This feature can be modified afterwards using unitary function
487 @ref LL_TIM_OC_SetDeadTime()
488
489 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
490 programmed. */
491
492 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
493 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
494
495 This feature can be modified afterwards using unitary functions
496 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
497
498 @note This bit-field can not be modified as long as LOCK level 1 has been
499 programmed. */
500
501 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
502 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
503
504 This feature can be modified afterwards using unitary function
505 @ref LL_TIM_ConfigBRK()
506
507 @note This bit-field can not be modified as long as LOCK level 1 has been
508 programmed. */
509
510 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
511 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
512
513 This feature can be modified afterwards using unitary function
514 @ref LL_TIM_ConfigBRK()
515
516 @note This bit-field can not be modified as long as LOCK level 1 has been
517 programmed. */
518
519 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
520 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
521
522 This feature can be modified afterwards using unitary functions
523 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
524
525 @note This bit-field can not be modified as long as LOCK level 1 has been
526 programmed. */
527
528 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
529 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
530
531 This feature can be modified afterwards using unitary function
532 @ref LL_TIM_ConfigBRK2()
533
534 @note This bit-field can not be modified as long as LOCK level 1 has been
535 programmed. */
536
537 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
538 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
539
540 This feature can be modified afterwards using unitary function
541 @ref LL_TIM_ConfigBRK2()
542
543 @note This bit-field can not be modified as long as LOCK level 1 has been
544 programmed. */
545
546 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
547 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
548
549 This feature can be modified afterwards using unitary functions
550 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
551
552 @note This bit-field can not be modified as long as LOCK level 1 has been
553 programmed. */
554 } LL_TIM_BDTR_InitTypeDef;
555
556 /**
557 * @}
558 */
559 #endif /* USE_FULL_LL_DRIVER */
560
561 /* Exported constants --------------------------------------------------------*/
562 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
563 * @{
564 */
565
566 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
567 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
568 * @{
569 */
570 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
571 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
572 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
573 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
574 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
575 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
576 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
577 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
578 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
579 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
580 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
581 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
582 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
583 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
584 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
585 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
586 /**
587 * @}
588 */
589
590 #if defined(USE_FULL_LL_DRIVER)
591 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
592 * @{
593 */
594 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
595 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
596 /**
597 * @}
598 */
599
600 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
601 * @{
602 */
603 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
604 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
605 /**
606 * @}
607 */
608
609 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
610 * @{
611 */
612 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
613 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
614 /**
615 * @}
616 */
617 #endif /* USE_FULL_LL_DRIVER */
618
619 /** @defgroup TIM_LL_EC_IT IT Defines
620 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
621 * @{
622 */
623 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
624 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
625 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
626 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
627 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
628 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
629 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
630 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
631 /**
632 * @}
633 */
634
635 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
636 * @{
637 */
638 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
639 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
640 /**
641 * @}
642 */
643
644 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
645 * @{
646 */
647 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
648 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
649 /**
650 * @}
651 */
652
653 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
654 * @{
655 */
656 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
657 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
658 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
659 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
660 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
661 /**
662 * @}
663 */
664
665 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
666 * @{
667 */
668 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
669 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
670 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
671 /**
672 * @}
673 */
674
675 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
676 * @{
677 */
678 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
679 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
680 /**
681 * @}
682 */
683
684 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
685 * @{
686 */
687 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
688 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
689 /**
690 * @}
691 */
692
693 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
694 * @{
695 */
696 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
697 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
698 /**
699 * @}
700 */
701
702 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
703 * @{
704 */
705 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
706 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
707 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
708 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
709 /**
710 * @}
711 */
712
713 /** @defgroup TIM_LL_EC_CHANNEL Channel
714 * @{
715 */
716 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
717 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
718 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
719 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
720 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
721 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
722 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
723 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
724 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
725 /**
726 * @}
727 */
728
729 #if defined(USE_FULL_LL_DRIVER)
730 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
731 * @{
732 */
733 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
734 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
735 /**
736 * @}
737 */
738 #endif /* USE_FULL_LL_DRIVER */
739
740 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
741 * @{
742 */
743 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
744 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
745 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
746 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
747 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
748 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
749 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
750 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
751 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
752 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
753 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
754 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
755 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
756 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
757 /**
758 * @}
759 */
760
761 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
762 * @{
763 */
764 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
765 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
766 /**
767 * @}
768 */
769
770 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
771 * @{
772 */
773 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
774 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
775 /**
776 * @}
777 */
778
779 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
780 * @{
781 */
782 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
783 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
784 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
785 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
786 /**
787 * @}
788 */
789
790 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
791 * @{
792 */
793 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
794 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
795 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
796 /**
797 * @}
798 */
799
800 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
801 * @{
802 */
803 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
804 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
805 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
806 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
807 /**
808 * @}
809 */
810
811 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
812 * @{
813 */
814 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
815 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
816 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
817 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
818 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
819 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
820 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
821 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
822 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
823 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
824 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
825 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
826 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
827 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
828 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
829 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
830 /**
831 * @}
832 */
833
834 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
835 * @{
836 */
837 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
838 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
839 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
840 /**
841 * @}
842 */
843
844 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
845 * @{
846 */
847 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
848 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
849 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
850 /**
851 * @}
852 */
853
854 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
855 * @{
856 */
857 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
858 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
859 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
860 /**
861 * @}
862 */
863
864 /** @defgroup TIM_LL_EC_TRGO Trigger Output
865 * @{
866 */
867 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
868 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
869 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
870 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
871 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
872 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
873 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
874 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
875 /**
876 * @}
877 */
878
879 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
880 * @{
881 */
882 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
883 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
884 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
885 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
886 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
887 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
888 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
889 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
890 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
891 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
892 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
893 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
894 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
895 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
896 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
897 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
898 /**
899 * @}
900 */
901
902 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
903 * @{
904 */
905 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
906 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
907 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
908 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
909 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
910 /**
911 * @}
912 */
913
914 /** @defgroup TIM_LL_EC_TS Trigger Selection
915 * @{
916 */
917 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
918 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
919 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
920 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
921 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
922 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
923 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
924 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
925 /**
926 * @}
927 */
928
929 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
930 * @{
931 */
932 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
933 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
934 /**
935 * @}
936 */
937
938 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
939 * @{
940 */
941 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
942 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
943 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
944 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
945 /**
946 * @}
947 */
948
949 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
950 * @{
951 */
952 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
953 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
954 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
955 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
956 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
957 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
958 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
959 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
960 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
961 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
962 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
963 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
964 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
965 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
966 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
967 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
968 /**
969 * @}
970 */
971
972 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
973 * @{
974 */
975 #define LL_TIM_ETRSOURCE_LEGACY 0x00000000U /*!< ETR legacy mode */
976 #define LL_TIM_ETRSOURCE_COMP1 TIM1_OR2_ETRSEL_0 /*!< COMP1 output connected to ETR input */
977 #define LL_TIM_ETRSOURCE_COMP2 TIM1_OR2_ETRSEL_1 /*!< COMP2 output connected to ETR input */
978 /**
979 * @}
980 */
981
982 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
983 * @{
984 */
985 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
986 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
987 /**
988 * @}
989 */
990
991 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
992 * @{
993 */
994 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
995 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
996 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
997 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
998 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
999 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1000 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1001 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1002 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1003 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1004 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1005 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1006 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1007 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1008 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1009 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1010 /**
1011 * @}
1012 */
1013
1014 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1015 * @{
1016 */
1017 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1018 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1019 /**
1020 * @}
1021 */
1022
1023 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1024 * @{
1025 */
1026 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1027 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1028 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1029 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1030 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1031 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1032 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1033 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1034 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1035 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1036 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1037 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1038 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1039 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1040 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1041 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1042 /**
1043 * @}
1044 */
1045
1046 /** @defgroup TIM_LL_EC_OSSI OSSI
1047 * @{
1048 */
1049 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1050 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1051 /**
1052 * @}
1053 */
1054
1055 /** @defgroup TIM_LL_EC_OSSR OSSR
1056 * @{
1057 */
1058 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1059 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1060 /**
1061 * @}
1062 */
1063
1064 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1065 * @{
1066 */
1067 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1068 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1069 /**
1070 * @}
1071 */
1072
1073 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1074 * @{
1075 */
1076 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE /*!< BKIN input from AF controller */
1077 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E /*!< internal signal: COMP1 output */
1078 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E /*!< internal signal: COMP2 output */
1079 #if defined(DFSDM1_Channel0)
1080 #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_OR2_BKDF1BK0E /*!< internal signal: DFSDM1 break output */
1081 #endif /* DFSDM1_Channel0 */
1082 /**
1083 * @}
1084 */
1085
1086 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1087 * @{
1088 */
1089 #define LL_TIM_BKIN_POLARITY_LOW TIM1_OR2_BKINP /*!< BRK BKIN input is active low */
1090 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1091 /**
1092 * @}
1093 */
1094
1095 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1096 * @{
1097 */
1098 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1099 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1100 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1101 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1102 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1103 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1104 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1105 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1106 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1107 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1108 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1109 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1110 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1111 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1112 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1113 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1114 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1115 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1116 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR1 register is the DMA base address for DMA burst */
1117 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1118 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1119 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1120 #define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_OR2 register is the DMA base address for DMA burst */
1121 #define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_OR3 register is the DMA base address for DMA burst */
1122 /**
1123 * @}
1124 */
1125
1126 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1127 * @{
1128 */
1129 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1130 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1131 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1132 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1133 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1134 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1135 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1136 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1137 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1138 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1139 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1140 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1141 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1142 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1143 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1144 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1145 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1146 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1147 /**
1148 * @}
1149 */
1150
1151 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap
1152 * @{
1153 */
1154 #define LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR1_RMP_MASK /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */
1155 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */
1156 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */
1157 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */
1158 /**
1159 * @}
1160 */
1161
1162 #if defined(ADC3)
1163 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC3_RMP TIM1 External Trigger ADC3 Remap
1164 * @{
1165 */
1166 #define LL_TIM_TIM1_ETR_ADC3_RMP_NC TIM1_OR1_RMP_MASK /*!< TIM1_ETR is not connected to ADC3 analog watchdog x*/
1167 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 1 */
1168 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 2 */
1169 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 3 */
1170 /**
1171 * @}
1172 */
1173 #endif /* ADC3 */
1174
1175 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap
1176 * @{
1177 */
1178 #define LL_TIM_TIM1_TI1_RMP_GPIO TIM1_OR1_RMP_MASK /*!< TIM1 input capture 1 is connected to GPIO */
1179 #define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1 input capture 1 is connected to COMP1 output */
1180 /**
1181 * @}
1182 */
1183
1184 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 Internal Trigger1 Remap
1185 * @{
1186 */
1187 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
1188 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR1_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */
1189 #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR1_ITR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */
1190 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
1191 /* STM32L496xx || STM32L4A6xx || */
1192 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
1193 #if defined (STM32L412xx) || defined (STM32L422xx) ||defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
1194 #define LL_TIM_TIM2_ITR1_RMP_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */
1195 #define LL_TIM_TIM2_ITR1_RMP_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */
1196 #endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */
1197 /* STM32L451xx || STM32L452xx || STM32L462xx */
1198 #define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2_ETR is connected to GPIO */
1199 #define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR1_ETR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ETR is connected to LSE */
1200 /**
1201 * @}
1202 */
1203
1204 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap
1205 * @{
1206 */
1207 #define LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2 input capture 4 is connected to GPIO */
1208 #define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP1_OUT */
1209 #if defined (STM32L412xx) || defined (STM32L422xx)
1210 #else
1211 #define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR1_TI4_RMP_1 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP2_OUT */
1212 #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT */
1213 #endif
1214 /**
1215 * @}
1216 */
1217
1218 #if defined(TIM3)
1219 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap
1220 * @{
1221 */
1222 #define LL_TIM_TIM3_TI1_RMP_GPIO TIM3_OR1_RMP_MASK /*!< TIM3 input capture 1 is connected to GPIO */
1223 #define LL_TIM_TIM3_TI1_RMP_COMP1 (TIM3_OR1_TI1_RMP_0 | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to COMP1_OUT */
1224 #define LL_TIM_TIM3_TI1_RMP_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to COMP2_OUT */
1225 #define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM3_OR1_TI1_RMP | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to logical OR between COMP1_OUT and COMP2_OUT */
1226 /**
1227 * @}
1228 */
1229 #endif /* TIM3 */
1230
1231 #if defined(TIM8)
1232 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP TIM8 External Trigger ADC2 Remap
1233 * @{
1234 */
1235 #define LL_TIM_TIM8_ETR_ADC2_RMP_NC TIM8_OR1_RMP_MASK /*!< TIM8_ETR is not connected to ADC2 analog watchdog x */
1236 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog */
1237 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 2 */
1238 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 3 */
1239 /**
1240 * @}
1241 */
1242
1243 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP TIM8 External Trigger ADC3 Remap
1244 * @{
1245 */
1246 #define LL_TIM_TIM8_ETR_ADC3_RMP_NC TIM8_OR1_RMP_MASK /*!< TIM8_ETR is not connected to ADC3 analog watchdog x */
1247 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 1 */
1248 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 2 */
1249 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 3 */
1250 /**
1251 * @}
1252 */
1253
1254 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 External Input Ch1 Remap
1255 * @{
1256 */
1257 #define LL_TIM_TIM8_TI1_RMP_GPIO TIM8_OR1_RMP_MASK /*!< TIM8 input capture 1 is connected to GPIO */
1258 #define LL_TIM_TIM8_TI1_RMP_COMP2 (TIM8_OR1_TI1_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8 input capture 1 is connected to COMP2 output */
1259 /**
1260 * @}
1261 */
1262 #endif /* TIM8 */
1263
1264 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap
1265 * @{
1266 */
1267 #define LL_TIM_TIM15_TI1_RMP_GPIO TIM15_OR1_RMP_MASK /*!< TIM15 input capture 1 is connected to GPIO */
1268 #define LL_TIM_TIM15_TI1_RMP_LSE (TIM15_OR1_TI1_RMP | TIM15_OR1_RMP_MASK) /*!< TIM15 input capture 1 is connected to LSE */
1269 /**
1270 * @}
1271 */
1272
1273 /** @defgroup TIM_LL_EC_TIM15_ENCODERMODE TIM15 ENCODERMODE
1274 * @{
1275 */
1276 #define LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION TIM15_OR1_RMP_MASK /*!< No redirection*/
1277 #define LL_TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0 | TIM15_OR1_RMP_MASK) /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
1278 #define LL_TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_RMP_MASK) /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectivel y*/
1279 #define LL_TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE | TIM15_OR1_RMP_MASK) /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
1280 /**
1281 * @}
1282 */
1283
1284 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
1285 * @{
1286 */
1287 #define LL_TIM_TIM16_TI1_RMP_GPIO TIM16_OR1_RMP_MASK /*!< TIM16 input capture 1 is connected to GPIO */
1288 #define LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSI */
1289 #define LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSE */
1290 #define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */
1291 #if defined TIM16_OR1_TI1_RMP_2
1292 #define LL_TIM_TIM16_TI1_RMP_MSI (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to MSI */
1293 #define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to HSE/32 */
1294 #define LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to MCO */
1295 #endif
1296 /**
1297 * @}
1298 */
1299
1300 #if defined(TIM17)
1301 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1302 * @{
1303 */
1304 #define LL_TIM_TIM17_TI1_RMP_GPIO TIM17_OR1_RMP_MASK /*!< TIM17 input capture 1 is connected to GPIO */
1305 #define LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MSI */
1306 #define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to HSE/32 */
1307 #define LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR1_TI1_RMP | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MCO */
1308 /**
1309 * @}
1310 */
1311 #endif /* TIM17 */
1312
1313 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1314 * @{
1315 */
1316 #define LL_TIM_OCREF_CLR_INT_NC 0x00000000U /*!< OCREF_CLR_INT is not connected */
1317 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
1318 /**
1319 * @}
1320 */
1321
1322 /** Legacy definitions for compatibility purpose
1323 @cond 0
1324 */
1325 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1326 /**
1327 @endcond
1328 */
1329 /**
1330 * @}
1331 */
1332
1333 /* Exported macro ------------------------------------------------------------*/
1334 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1335 * @{
1336 */
1337
1338 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1339 * @{
1340 */
1341 /**
1342 * @brief Write a value in TIM register.
1343 * @param __INSTANCE__ TIM Instance
1344 * @param __REG__ Register to be written
1345 * @param __VALUE__ Value to be written in the register
1346 * @retval None
1347 */
1348 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1349
1350 /**
1351 * @brief Read a value in TIM register.
1352 * @param __INSTANCE__ TIM Instance
1353 * @param __REG__ Register to be read
1354 * @retval Register value
1355 */
1356 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1357 /**
1358 * @}
1359 */
1360
1361 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
1362 * @{
1363 */
1364
1365 /**
1366 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1367 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1368 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1369 * to TIMx_CNT register bit 31)
1370 * @param __CNT__ Counter value
1371 * @retval UIF status bit
1372 */
1373 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1374 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1375
1376 /**
1377 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1378 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1379 * @param __TIMCLK__ timer input clock frequency (in Hz)
1380 * @param __CKD__ This parameter can be one of the following values:
1381 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1382 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1383 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1384 * @param __DT__ deadtime duration (in ns)
1385 * @retval DTG[0:7]
1386 */
1387 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1388 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1389 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1390 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1391 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1392 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1393 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1394 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1395 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1396 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1397 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1398 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1399 0U)
1400
1401 /**
1402 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1403 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1404 * @param __TIMCLK__ timer input clock frequency (in Hz)
1405 * @param __CNTCLK__ counter clock frequency (in Hz)
1406 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1407 */
1408 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1409 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1410
1411 /**
1412 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1413 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1414 * @param __TIMCLK__ timer input clock frequency (in Hz)
1415 * @param __PSC__ prescaler
1416 * @param __FREQ__ output signal frequency (in Hz)
1417 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1418 */
1419 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1420 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1421
1422 /**
1423 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1424 * active/inactive delay.
1425 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1426 * @param __TIMCLK__ timer input clock frequency (in Hz)
1427 * @param __PSC__ prescaler
1428 * @param __DELAY__ timer output compare active/inactive delay (in us)
1429 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1430 */
1431 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1432 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1433 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1434
1435 /**
1436 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1437 * (when the timer operates in one pulse mode).
1438 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1439 * @param __TIMCLK__ timer input clock frequency (in Hz)
1440 * @param __PSC__ prescaler
1441 * @param __DELAY__ timer output compare active/inactive delay (in us)
1442 * @param __PULSE__ pulse duration (in us)
1443 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1444 */
1445 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1446 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1447 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1448
1449 /**
1450 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1451 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1452 * @param __ICPSC__ This parameter can be one of the following values:
1453 * @arg @ref LL_TIM_ICPSC_DIV1
1454 * @arg @ref LL_TIM_ICPSC_DIV2
1455 * @arg @ref LL_TIM_ICPSC_DIV4
1456 * @arg @ref LL_TIM_ICPSC_DIV8
1457 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1458 */
1459 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1460 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1461
1462
1463 /**
1464 * @}
1465 */
1466
1467
1468 /**
1469 * @}
1470 */
1471
1472 /* Exported functions --------------------------------------------------------*/
1473 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1474 * @{
1475 */
1476
1477 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1478 * @{
1479 */
1480 /**
1481 * @brief Enable timer counter.
1482 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1483 * @param TIMx Timer instance
1484 * @retval None
1485 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1486 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1487 {
1488 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1489 }
1490
1491 /**
1492 * @brief Disable timer counter.
1493 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1494 * @param TIMx Timer instance
1495 * @retval None
1496 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1497 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1498 {
1499 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1500 }
1501
1502 /**
1503 * @brief Indicates whether the timer counter is enabled.
1504 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1505 * @param TIMx Timer instance
1506 * @retval State of bit (1 or 0).
1507 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1508 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1509 {
1510 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1511 }
1512
1513 /**
1514 * @brief Enable update event generation.
1515 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1516 * @param TIMx Timer instance
1517 * @retval None
1518 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1519 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1520 {
1521 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1522 }
1523
1524 /**
1525 * @brief Disable update event generation.
1526 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1527 * @param TIMx Timer instance
1528 * @retval None
1529 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1530 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1531 {
1532 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1533 }
1534
1535 /**
1536 * @brief Indicates whether update event generation is enabled.
1537 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1538 * @param TIMx Timer instance
1539 * @retval Inverted state of bit (0 or 1).
1540 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1541 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1542 {
1543 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1544 }
1545
1546 /**
1547 * @brief Set update event source
1548 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1549 * generate an update interrupt or DMA request if enabled:
1550 * - Counter overflow/underflow
1551 * - Setting the UG bit
1552 * - Update generation through the slave mode controller
1553 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1554 * overflow/underflow generates an update interrupt or DMA request if enabled.
1555 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1556 * @param TIMx Timer instance
1557 * @param UpdateSource This parameter can be one of the following values:
1558 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1559 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1560 * @retval None
1561 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1562 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1563 {
1564 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1565 }
1566
1567 /**
1568 * @brief Get actual event update source
1569 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1570 * @param TIMx Timer instance
1571 * @retval Returned value can be one of the following values:
1572 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1573 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1574 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1575 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1576 {
1577 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1578 }
1579
1580 /**
1581 * @brief Set one pulse mode (one shot v.s. repetitive).
1582 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1583 * @param TIMx Timer instance
1584 * @param OnePulseMode This parameter can be one of the following values:
1585 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1586 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1587 * @retval None
1588 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1589 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1590 {
1591 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1592 }
1593
1594 /**
1595 * @brief Get actual one pulse mode.
1596 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1597 * @param TIMx Timer instance
1598 * @retval Returned value can be one of the following values:
1599 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1600 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1601 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1602 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1603 {
1604 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1605 }
1606
1607 /**
1608 * @brief Set the timer counter counting mode.
1609 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1610 * check whether or not the counter mode selection feature is supported
1611 * by a timer instance.
1612 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1613 * requires a timer reset to avoid unexpected direction
1614 * due to DIR bit readonly in center aligned mode.
1615 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1616 * CR1 CMS LL_TIM_SetCounterMode
1617 * @param TIMx Timer instance
1618 * @param CounterMode This parameter can be one of the following values:
1619 * @arg @ref LL_TIM_COUNTERMODE_UP
1620 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1621 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1622 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1623 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1624 * @retval None
1625 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1626 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1627 {
1628 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1629 }
1630
1631 /**
1632 * @brief Get actual counter mode.
1633 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1634 * check whether or not the counter mode selection feature is supported
1635 * by a timer instance.
1636 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1637 * CR1 CMS LL_TIM_GetCounterMode
1638 * @param TIMx Timer instance
1639 * @retval Returned value can be one of the following values:
1640 * @arg @ref LL_TIM_COUNTERMODE_UP
1641 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1642 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1643 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1644 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1645 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1646 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1647 {
1648 uint32_t counter_mode;
1649
1650 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1651
1652 if (counter_mode == 0U)
1653 {
1654 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1655 }
1656
1657 return counter_mode;
1658 }
1659
1660 /**
1661 * @brief Enable auto-reload (ARR) preload.
1662 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1663 * @param TIMx Timer instance
1664 * @retval None
1665 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1666 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1667 {
1668 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1669 }
1670
1671 /**
1672 * @brief Disable auto-reload (ARR) preload.
1673 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1674 * @param TIMx Timer instance
1675 * @retval None
1676 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1677 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1678 {
1679 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1680 }
1681
1682 /**
1683 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1684 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1685 * @param TIMx Timer instance
1686 * @retval State of bit (1 or 0).
1687 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1688 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1689 {
1690 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1691 }
1692
1693 /**
1694 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1695 * (when supported) and the digital filters.
1696 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1697 * whether or not the clock division feature is supported by the timer
1698 * instance.
1699 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1700 * @param TIMx Timer instance
1701 * @param ClockDivision This parameter can be one of the following values:
1702 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1703 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1704 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1705 * @retval None
1706 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1707 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1708 {
1709 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1710 }
1711
1712 /**
1713 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1714 * generators (when supported) and the digital filters.
1715 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1716 * whether or not the clock division feature is supported by the timer
1717 * instance.
1718 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1719 * @param TIMx Timer instance
1720 * @retval Returned value can be one of the following values:
1721 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1722 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1723 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1724 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1725 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1726 {
1727 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1728 }
1729
1730 /**
1731 * @brief Set the counter value.
1732 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1733 * whether or not a timer instance supports a 32 bits counter.
1734 * @rmtoll CNT CNT LL_TIM_SetCounter
1735 * @param TIMx Timer instance
1736 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1737 * @retval None
1738 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1739 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1740 {
1741 WRITE_REG(TIMx->CNT, Counter);
1742 }
1743
1744 /**
1745 * @brief Get the counter value.
1746 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1747 * whether or not a timer instance supports a 32 bits counter.
1748 * @rmtoll CNT CNT LL_TIM_GetCounter
1749 * @param TIMx Timer instance
1750 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1751 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1752 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1753 {
1754 return (uint32_t)(READ_REG(TIMx->CNT));
1755 }
1756
1757 /**
1758 * @brief Get the current direction of the counter
1759 * @rmtoll CR1 DIR LL_TIM_GetDirection
1760 * @param TIMx Timer instance
1761 * @retval Returned value can be one of the following values:
1762 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1763 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1764 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1765 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1766 {
1767 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1768 }
1769
1770 /**
1771 * @brief Set the prescaler value.
1772 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1773 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1774 * prescaler ratio is taken into account at the next update event.
1775 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1776 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1777 * @param TIMx Timer instance
1778 * @param Prescaler between Min_Data=0 and Max_Data=65535
1779 * @retval None
1780 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1781 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1782 {
1783 WRITE_REG(TIMx->PSC, Prescaler);
1784 }
1785
1786 /**
1787 * @brief Get the prescaler value.
1788 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1789 * @param TIMx Timer instance
1790 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1791 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1792 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1793 {
1794 return (uint32_t)(READ_REG(TIMx->PSC));
1795 }
1796
1797 /**
1798 * @brief Set the auto-reload value.
1799 * @note The counter is blocked while the auto-reload value is null.
1800 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1801 * whether or not a timer instance supports a 32 bits counter.
1802 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1803 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1804 * @param TIMx Timer instance
1805 * @param AutoReload between Min_Data=0 and Max_Data=65535
1806 * @retval None
1807 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1808 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1809 {
1810 WRITE_REG(TIMx->ARR, AutoReload);
1811 }
1812
1813 /**
1814 * @brief Get the auto-reload value.
1815 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1816 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1817 * whether or not a timer instance supports a 32 bits counter.
1818 * @param TIMx Timer instance
1819 * @retval Auto-reload value
1820 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1821 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1822 {
1823 return (uint32_t)(READ_REG(TIMx->ARR));
1824 }
1825
1826 /**
1827 * @brief Set the repetition counter value.
1828 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1829 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1830 * whether or not a timer instance supports a repetition counter.
1831 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1832 * @param TIMx Timer instance
1833 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1834 * @retval None
1835 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1836 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1837 {
1838 WRITE_REG(TIMx->RCR, RepetitionCounter);
1839 }
1840
1841 /**
1842 * @brief Get the repetition counter value.
1843 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1844 * whether or not a timer instance supports a repetition counter.
1845 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1846 * @param TIMx Timer instance
1847 * @retval Repetition counter value
1848 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1849 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1850 {
1851 return (uint32_t)(READ_REG(TIMx->RCR));
1852 }
1853
1854 /**
1855 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1856 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1857 * in an atomic way.
1858 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1859 * @param TIMx Timer instance
1860 * @retval None
1861 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1862 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1863 {
1864 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1865 }
1866
1867 /**
1868 * @brief Disable update interrupt flag (UIF) remapping.
1869 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1870 * @param TIMx Timer instance
1871 * @retval None
1872 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1873 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1874 {
1875 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1876 }
1877
1878 /**
1879 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1880 * @param Counter Counter value
1881 * @retval State of bit (1 or 0).
1882 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)1883 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
1884 {
1885 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1886 }
1887
1888 /**
1889 * @}
1890 */
1891
1892 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1893 * @{
1894 */
1895 /**
1896 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1897 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1898 * they are updated only when a commutation event (COM) occurs.
1899 * @note Only on channels that have a complementary output.
1900 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1901 * whether or not a timer instance is able to generate a commutation event.
1902 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1903 * @param TIMx Timer instance
1904 * @retval None
1905 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1906 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1907 {
1908 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1909 }
1910
1911 /**
1912 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1913 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1914 * whether or not a timer instance is able to generate a commutation event.
1915 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1916 * @param TIMx Timer instance
1917 * @retval None
1918 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1919 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1920 {
1921 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1922 }
1923
1924 /**
1925 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1926 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1927 * whether or not a timer instance is able to generate a commutation event.
1928 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1929 * @param TIMx Timer instance
1930 * @param CCUpdateSource This parameter can be one of the following values:
1931 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1932 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1933 * @retval None
1934 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1935 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1936 {
1937 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1938 }
1939
1940 /**
1941 * @brief Set the trigger of the capture/compare DMA request.
1942 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1943 * @param TIMx Timer instance
1944 * @param DMAReqTrigger This parameter can be one of the following values:
1945 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1946 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1947 * @retval None
1948 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1949 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1950 {
1951 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1952 }
1953
1954 /**
1955 * @brief Get actual trigger of the capture/compare DMA request.
1956 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1957 * @param TIMx Timer instance
1958 * @retval Returned value can be one of the following values:
1959 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1960 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1961 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1962 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1963 {
1964 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1965 }
1966
1967 /**
1968 * @brief Set the lock level to freeze the
1969 * configuration of several capture/compare parameters.
1970 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1971 * the lock mechanism is supported by a timer instance.
1972 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1973 * @param TIMx Timer instance
1974 * @param LockLevel This parameter can be one of the following values:
1975 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1976 * @arg @ref LL_TIM_LOCKLEVEL_1
1977 * @arg @ref LL_TIM_LOCKLEVEL_2
1978 * @arg @ref LL_TIM_LOCKLEVEL_3
1979 * @retval None
1980 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1981 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1982 {
1983 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1984 }
1985
1986 /**
1987 * @brief Enable capture/compare channels.
1988 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1989 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1990 * CCER CC2E LL_TIM_CC_EnableChannel\n
1991 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1992 * CCER CC3E LL_TIM_CC_EnableChannel\n
1993 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1994 * CCER CC4E LL_TIM_CC_EnableChannel\n
1995 * CCER CC5E LL_TIM_CC_EnableChannel\n
1996 * CCER CC6E LL_TIM_CC_EnableChannel
1997 * @param TIMx Timer instance
1998 * @param Channels This parameter can be a combination of the following values:
1999 * @arg @ref LL_TIM_CHANNEL_CH1
2000 * @arg @ref LL_TIM_CHANNEL_CH1N
2001 * @arg @ref LL_TIM_CHANNEL_CH2
2002 * @arg @ref LL_TIM_CHANNEL_CH2N
2003 * @arg @ref LL_TIM_CHANNEL_CH3
2004 * @arg @ref LL_TIM_CHANNEL_CH3N
2005 * @arg @ref LL_TIM_CHANNEL_CH4
2006 * @arg @ref LL_TIM_CHANNEL_CH5
2007 * @arg @ref LL_TIM_CHANNEL_CH6
2008 * @retval None
2009 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2010 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2011 {
2012 SET_BIT(TIMx->CCER, Channels);
2013 }
2014
2015 /**
2016 * @brief Disable capture/compare channels.
2017 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
2018 * CCER CC1NE LL_TIM_CC_DisableChannel\n
2019 * CCER CC2E LL_TIM_CC_DisableChannel\n
2020 * CCER CC2NE LL_TIM_CC_DisableChannel\n
2021 * CCER CC3E LL_TIM_CC_DisableChannel\n
2022 * CCER CC3NE LL_TIM_CC_DisableChannel\n
2023 * CCER CC4E LL_TIM_CC_DisableChannel\n
2024 * CCER CC5E LL_TIM_CC_DisableChannel\n
2025 * CCER CC6E LL_TIM_CC_DisableChannel
2026 * @param TIMx Timer instance
2027 * @param Channels This parameter can be a combination of the following values:
2028 * @arg @ref LL_TIM_CHANNEL_CH1
2029 * @arg @ref LL_TIM_CHANNEL_CH1N
2030 * @arg @ref LL_TIM_CHANNEL_CH2
2031 * @arg @ref LL_TIM_CHANNEL_CH2N
2032 * @arg @ref LL_TIM_CHANNEL_CH3
2033 * @arg @ref LL_TIM_CHANNEL_CH3N
2034 * @arg @ref LL_TIM_CHANNEL_CH4
2035 * @arg @ref LL_TIM_CHANNEL_CH5
2036 * @arg @ref LL_TIM_CHANNEL_CH6
2037 * @retval None
2038 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2039 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2040 {
2041 CLEAR_BIT(TIMx->CCER, Channels);
2042 }
2043
2044 /**
2045 * @brief Indicate whether channel(s) is(are) enabled.
2046 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2047 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2048 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2049 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2050 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2051 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2052 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2053 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2054 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2055 * @param TIMx Timer instance
2056 * @param Channels This parameter can be a combination of the following values:
2057 * @arg @ref LL_TIM_CHANNEL_CH1
2058 * @arg @ref LL_TIM_CHANNEL_CH1N
2059 * @arg @ref LL_TIM_CHANNEL_CH2
2060 * @arg @ref LL_TIM_CHANNEL_CH2N
2061 * @arg @ref LL_TIM_CHANNEL_CH3
2062 * @arg @ref LL_TIM_CHANNEL_CH3N
2063 * @arg @ref LL_TIM_CHANNEL_CH4
2064 * @arg @ref LL_TIM_CHANNEL_CH5
2065 * @arg @ref LL_TIM_CHANNEL_CH6
2066 * @retval State of bit (1 or 0).
2067 */
LL_TIM_CC_IsEnabledChannel(TIM_TypeDef * TIMx,uint32_t Channels)2068 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2069 {
2070 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2071 }
2072
2073 /**
2074 * @}
2075 */
2076
2077 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2078 * @{
2079 */
2080 /**
2081 * @brief Configure an output channel.
2082 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2083 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2084 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2085 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2086 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2087 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2088 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2089 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2090 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2091 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2092 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2093 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2094 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2095 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2096 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2097 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2098 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2099 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2100 * @param TIMx Timer instance
2101 * @param Channel This parameter can be one of the following values:
2102 * @arg @ref LL_TIM_CHANNEL_CH1
2103 * @arg @ref LL_TIM_CHANNEL_CH2
2104 * @arg @ref LL_TIM_CHANNEL_CH3
2105 * @arg @ref LL_TIM_CHANNEL_CH4
2106 * @arg @ref LL_TIM_CHANNEL_CH5
2107 * @arg @ref LL_TIM_CHANNEL_CH6
2108 * @param Configuration This parameter must be a combination of all the following values:
2109 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2110 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2111 * @retval None
2112 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2113 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2114 {
2115 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2116 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2117 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2118 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2119 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2120 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2121 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2122 }
2123
2124 /**
2125 * @brief Define the behavior of the output reference signal OCxREF from which
2126 * OCx and OCxN (when relevant) are derived.
2127 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2128 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2129 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2130 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2131 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2132 * CCMR3 OC6M LL_TIM_OC_SetMode
2133 * @param TIMx Timer instance
2134 * @param Channel This parameter can be one of the following values:
2135 * @arg @ref LL_TIM_CHANNEL_CH1
2136 * @arg @ref LL_TIM_CHANNEL_CH2
2137 * @arg @ref LL_TIM_CHANNEL_CH3
2138 * @arg @ref LL_TIM_CHANNEL_CH4
2139 * @arg @ref LL_TIM_CHANNEL_CH5
2140 * @arg @ref LL_TIM_CHANNEL_CH6
2141 * @param Mode This parameter can be one of the following values:
2142 * @arg @ref LL_TIM_OCMODE_FROZEN
2143 * @arg @ref LL_TIM_OCMODE_ACTIVE
2144 * @arg @ref LL_TIM_OCMODE_INACTIVE
2145 * @arg @ref LL_TIM_OCMODE_TOGGLE
2146 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2147 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2148 * @arg @ref LL_TIM_OCMODE_PWM1
2149 * @arg @ref LL_TIM_OCMODE_PWM2
2150 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2151 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2152 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2153 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2154 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2155 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2156 * @retval None
2157 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2158 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2159 {
2160 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2161 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2162 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2163 }
2164
2165 /**
2166 * @brief Get the output compare mode of an output channel.
2167 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2168 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2169 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2170 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2171 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2172 * CCMR3 OC6M LL_TIM_OC_GetMode
2173 * @param TIMx Timer instance
2174 * @param Channel This parameter can be one of the following values:
2175 * @arg @ref LL_TIM_CHANNEL_CH1
2176 * @arg @ref LL_TIM_CHANNEL_CH2
2177 * @arg @ref LL_TIM_CHANNEL_CH3
2178 * @arg @ref LL_TIM_CHANNEL_CH4
2179 * @arg @ref LL_TIM_CHANNEL_CH5
2180 * @arg @ref LL_TIM_CHANNEL_CH6
2181 * @retval Returned value can be one of the following values:
2182 * @arg @ref LL_TIM_OCMODE_FROZEN
2183 * @arg @ref LL_TIM_OCMODE_ACTIVE
2184 * @arg @ref LL_TIM_OCMODE_INACTIVE
2185 * @arg @ref LL_TIM_OCMODE_TOGGLE
2186 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2187 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2188 * @arg @ref LL_TIM_OCMODE_PWM1
2189 * @arg @ref LL_TIM_OCMODE_PWM2
2190 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2191 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2192 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2193 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2194 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2195 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2196 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2197 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2198 {
2199 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2200 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2201 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2202 }
2203
2204 /**
2205 * @brief Set the polarity of an output channel.
2206 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2207 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2208 * CCER CC2P LL_TIM_OC_SetPolarity\n
2209 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2210 * CCER CC3P LL_TIM_OC_SetPolarity\n
2211 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2212 * CCER CC4P LL_TIM_OC_SetPolarity\n
2213 * CCER CC5P LL_TIM_OC_SetPolarity\n
2214 * CCER CC6P LL_TIM_OC_SetPolarity
2215 * @param TIMx Timer instance
2216 * @param Channel This parameter can be one of the following values:
2217 * @arg @ref LL_TIM_CHANNEL_CH1
2218 * @arg @ref LL_TIM_CHANNEL_CH1N
2219 * @arg @ref LL_TIM_CHANNEL_CH2
2220 * @arg @ref LL_TIM_CHANNEL_CH2N
2221 * @arg @ref LL_TIM_CHANNEL_CH3
2222 * @arg @ref LL_TIM_CHANNEL_CH3N
2223 * @arg @ref LL_TIM_CHANNEL_CH4
2224 * @arg @ref LL_TIM_CHANNEL_CH5
2225 * @arg @ref LL_TIM_CHANNEL_CH6
2226 * @param Polarity This parameter can be one of the following values:
2227 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2228 * @arg @ref LL_TIM_OCPOLARITY_LOW
2229 * @retval None
2230 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2231 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2232 {
2233 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2234 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2235 }
2236
2237 /**
2238 * @brief Get the polarity of an output channel.
2239 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2240 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2241 * CCER CC2P LL_TIM_OC_GetPolarity\n
2242 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2243 * CCER CC3P LL_TIM_OC_GetPolarity\n
2244 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2245 * CCER CC4P LL_TIM_OC_GetPolarity\n
2246 * CCER CC5P LL_TIM_OC_GetPolarity\n
2247 * CCER CC6P LL_TIM_OC_GetPolarity
2248 * @param TIMx Timer instance
2249 * @param Channel This parameter can be one of the following values:
2250 * @arg @ref LL_TIM_CHANNEL_CH1
2251 * @arg @ref LL_TIM_CHANNEL_CH1N
2252 * @arg @ref LL_TIM_CHANNEL_CH2
2253 * @arg @ref LL_TIM_CHANNEL_CH2N
2254 * @arg @ref LL_TIM_CHANNEL_CH3
2255 * @arg @ref LL_TIM_CHANNEL_CH3N
2256 * @arg @ref LL_TIM_CHANNEL_CH4
2257 * @arg @ref LL_TIM_CHANNEL_CH5
2258 * @arg @ref LL_TIM_CHANNEL_CH6
2259 * @retval Returned value can be one of the following values:
2260 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2261 * @arg @ref LL_TIM_OCPOLARITY_LOW
2262 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2263 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2264 {
2265 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2266 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2267 }
2268
2269 /**
2270 * @brief Set the IDLE state of an output channel
2271 * @note This function is significant only for the timer instances
2272 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2273 * can be used to check whether or not a timer instance provides
2274 * a break input.
2275 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2276 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2277 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2278 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2279 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2280 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2281 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2282 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2283 * CR2 OIS6 LL_TIM_OC_SetIdleState
2284 * @param TIMx Timer instance
2285 * @param Channel This parameter can be one of the following values:
2286 * @arg @ref LL_TIM_CHANNEL_CH1
2287 * @arg @ref LL_TIM_CHANNEL_CH1N
2288 * @arg @ref LL_TIM_CHANNEL_CH2
2289 * @arg @ref LL_TIM_CHANNEL_CH2N
2290 * @arg @ref LL_TIM_CHANNEL_CH3
2291 * @arg @ref LL_TIM_CHANNEL_CH3N
2292 * @arg @ref LL_TIM_CHANNEL_CH4
2293 * @arg @ref LL_TIM_CHANNEL_CH5
2294 * @arg @ref LL_TIM_CHANNEL_CH6
2295 * @param IdleState This parameter can be one of the following values:
2296 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2297 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2298 * @retval None
2299 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2300 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2301 {
2302 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2303 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2304 }
2305
2306 /**
2307 * @brief Get the IDLE state of an output channel
2308 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2309 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2310 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2311 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2312 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2313 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2314 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2315 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2316 * CR2 OIS6 LL_TIM_OC_GetIdleState
2317 * @param TIMx Timer instance
2318 * @param Channel This parameter can be one of the following values:
2319 * @arg @ref LL_TIM_CHANNEL_CH1
2320 * @arg @ref LL_TIM_CHANNEL_CH1N
2321 * @arg @ref LL_TIM_CHANNEL_CH2
2322 * @arg @ref LL_TIM_CHANNEL_CH2N
2323 * @arg @ref LL_TIM_CHANNEL_CH3
2324 * @arg @ref LL_TIM_CHANNEL_CH3N
2325 * @arg @ref LL_TIM_CHANNEL_CH4
2326 * @arg @ref LL_TIM_CHANNEL_CH5
2327 * @arg @ref LL_TIM_CHANNEL_CH6
2328 * @retval Returned value can be one of the following values:
2329 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2330 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2331 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2332 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2333 {
2334 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2335 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2336 }
2337
2338 /**
2339 * @brief Enable fast mode for the output channel.
2340 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2341 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2342 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2343 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2344 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2345 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2346 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2347 * @param TIMx Timer instance
2348 * @param Channel This parameter can be one of the following values:
2349 * @arg @ref LL_TIM_CHANNEL_CH1
2350 * @arg @ref LL_TIM_CHANNEL_CH2
2351 * @arg @ref LL_TIM_CHANNEL_CH3
2352 * @arg @ref LL_TIM_CHANNEL_CH4
2353 * @arg @ref LL_TIM_CHANNEL_CH5
2354 * @arg @ref LL_TIM_CHANNEL_CH6
2355 * @retval None
2356 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2357 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2358 {
2359 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2360 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2361 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2362
2363 }
2364
2365 /**
2366 * @brief Disable fast mode for the output channel.
2367 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2368 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2369 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2370 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2371 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2372 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2373 * @param TIMx Timer instance
2374 * @param Channel This parameter can be one of the following values:
2375 * @arg @ref LL_TIM_CHANNEL_CH1
2376 * @arg @ref LL_TIM_CHANNEL_CH2
2377 * @arg @ref LL_TIM_CHANNEL_CH3
2378 * @arg @ref LL_TIM_CHANNEL_CH4
2379 * @arg @ref LL_TIM_CHANNEL_CH5
2380 * @arg @ref LL_TIM_CHANNEL_CH6
2381 * @retval None
2382 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2383 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2384 {
2385 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2386 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2387 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2388
2389 }
2390
2391 /**
2392 * @brief Indicates whether fast mode is enabled for the output channel.
2393 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2394 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2395 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2396 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2397 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2398 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2399 * @param TIMx Timer instance
2400 * @param Channel This parameter can be one of the following values:
2401 * @arg @ref LL_TIM_CHANNEL_CH1
2402 * @arg @ref LL_TIM_CHANNEL_CH2
2403 * @arg @ref LL_TIM_CHANNEL_CH3
2404 * @arg @ref LL_TIM_CHANNEL_CH4
2405 * @arg @ref LL_TIM_CHANNEL_CH5
2406 * @arg @ref LL_TIM_CHANNEL_CH6
2407 * @retval State of bit (1 or 0).
2408 */
LL_TIM_OC_IsEnabledFast(TIM_TypeDef * TIMx,uint32_t Channel)2409 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
2410 {
2411 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2412 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2413 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2414 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2415 }
2416
2417 /**
2418 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2419 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2420 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2421 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2422 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2423 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2424 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2425 * @param TIMx Timer instance
2426 * @param Channel This parameter can be one of the following values:
2427 * @arg @ref LL_TIM_CHANNEL_CH1
2428 * @arg @ref LL_TIM_CHANNEL_CH2
2429 * @arg @ref LL_TIM_CHANNEL_CH3
2430 * @arg @ref LL_TIM_CHANNEL_CH4
2431 * @arg @ref LL_TIM_CHANNEL_CH5
2432 * @arg @ref LL_TIM_CHANNEL_CH6
2433 * @retval None
2434 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2435 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2436 {
2437 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2438 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2439 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2440 }
2441
2442 /**
2443 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2444 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2445 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2446 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2447 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2448 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2449 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2450 * @param TIMx Timer instance
2451 * @param Channel This parameter can be one of the following values:
2452 * @arg @ref LL_TIM_CHANNEL_CH1
2453 * @arg @ref LL_TIM_CHANNEL_CH2
2454 * @arg @ref LL_TIM_CHANNEL_CH3
2455 * @arg @ref LL_TIM_CHANNEL_CH4
2456 * @arg @ref LL_TIM_CHANNEL_CH5
2457 * @arg @ref LL_TIM_CHANNEL_CH6
2458 * @retval None
2459 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2460 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2461 {
2462 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2463 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2464 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2465 }
2466
2467 /**
2468 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2469 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2470 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2471 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2472 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2473 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2474 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2475 * @param TIMx Timer instance
2476 * @param Channel This parameter can be one of the following values:
2477 * @arg @ref LL_TIM_CHANNEL_CH1
2478 * @arg @ref LL_TIM_CHANNEL_CH2
2479 * @arg @ref LL_TIM_CHANNEL_CH3
2480 * @arg @ref LL_TIM_CHANNEL_CH4
2481 * @arg @ref LL_TIM_CHANNEL_CH5
2482 * @arg @ref LL_TIM_CHANNEL_CH6
2483 * @retval State of bit (1 or 0).
2484 */
LL_TIM_OC_IsEnabledPreload(TIM_TypeDef * TIMx,uint32_t Channel)2485 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
2486 {
2487 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2488 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2489 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2490 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2491 }
2492
2493 /**
2494 * @brief Enable clearing the output channel on an external event.
2495 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2496 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2497 * or not a timer instance can clear the OCxREF signal on an external event.
2498 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2499 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2500 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2501 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2502 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2503 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2504 * @param TIMx Timer instance
2505 * @param Channel This parameter can be one of the following values:
2506 * @arg @ref LL_TIM_CHANNEL_CH1
2507 * @arg @ref LL_TIM_CHANNEL_CH2
2508 * @arg @ref LL_TIM_CHANNEL_CH3
2509 * @arg @ref LL_TIM_CHANNEL_CH4
2510 * @arg @ref LL_TIM_CHANNEL_CH5
2511 * @arg @ref LL_TIM_CHANNEL_CH6
2512 * @retval None
2513 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2514 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2515 {
2516 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2517 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2518 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2519 }
2520
2521 /**
2522 * @brief Disable clearing the output channel on an external event.
2523 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2524 * or not a timer instance can clear the OCxREF signal on an external event.
2525 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2526 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2527 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2528 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2529 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2530 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2531 * @param TIMx Timer instance
2532 * @param Channel This parameter can be one of the following values:
2533 * @arg @ref LL_TIM_CHANNEL_CH1
2534 * @arg @ref LL_TIM_CHANNEL_CH2
2535 * @arg @ref LL_TIM_CHANNEL_CH3
2536 * @arg @ref LL_TIM_CHANNEL_CH4
2537 * @arg @ref LL_TIM_CHANNEL_CH5
2538 * @arg @ref LL_TIM_CHANNEL_CH6
2539 * @retval None
2540 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2541 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2542 {
2543 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2544 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2545 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2546 }
2547
2548 /**
2549 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2550 * @note This function enables clearing the output channel on an external event.
2551 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2552 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2553 * or not a timer instance can clear the OCxREF signal on an external event.
2554 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2555 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2556 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2557 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2558 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2559 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2560 * @param TIMx Timer instance
2561 * @param Channel This parameter can be one of the following values:
2562 * @arg @ref LL_TIM_CHANNEL_CH1
2563 * @arg @ref LL_TIM_CHANNEL_CH2
2564 * @arg @ref LL_TIM_CHANNEL_CH3
2565 * @arg @ref LL_TIM_CHANNEL_CH4
2566 * @arg @ref LL_TIM_CHANNEL_CH5
2567 * @arg @ref LL_TIM_CHANNEL_CH6
2568 * @retval State of bit (1 or 0).
2569 */
LL_TIM_OC_IsEnabledClear(TIM_TypeDef * TIMx,uint32_t Channel)2570 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
2571 {
2572 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2573 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2574 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2575 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2576 }
2577
2578 /**
2579 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2580 * the Ocx and OCxN signals).
2581 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2582 * dead-time insertion feature is supported by a timer instance.
2583 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2584 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2585 * @param TIMx Timer instance
2586 * @param DeadTime between Min_Data=0 and Max_Data=255
2587 * @retval None
2588 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2589 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2590 {
2591 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2592 }
2593
2594 /**
2595 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2596 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2597 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2598 * whether or not a timer instance supports a 32 bits counter.
2599 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2600 * output channel 1 is supported by a timer instance.
2601 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2602 * @param TIMx Timer instance
2603 * @param CompareValue between Min_Data=0 and Max_Data=65535
2604 * @retval None
2605 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2606 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2607 {
2608 WRITE_REG(TIMx->CCR1, CompareValue);
2609 }
2610
2611 /**
2612 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2613 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2614 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2615 * whether or not a timer instance supports a 32 bits counter.
2616 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2617 * output channel 2 is supported by a timer instance.
2618 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2619 * @param TIMx Timer instance
2620 * @param CompareValue between Min_Data=0 and Max_Data=65535
2621 * @retval None
2622 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2623 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2624 {
2625 WRITE_REG(TIMx->CCR2, CompareValue);
2626 }
2627
2628 /**
2629 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2630 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2631 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2632 * whether or not a timer instance supports a 32 bits counter.
2633 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2634 * output channel is supported by a timer instance.
2635 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2636 * @param TIMx Timer instance
2637 * @param CompareValue between Min_Data=0 and Max_Data=65535
2638 * @retval None
2639 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2640 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2641 {
2642 WRITE_REG(TIMx->CCR3, CompareValue);
2643 }
2644
2645 /**
2646 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2647 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2648 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2649 * whether or not a timer instance supports a 32 bits counter.
2650 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2651 * output channel 4 is supported by a timer instance.
2652 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2653 * @param TIMx Timer instance
2654 * @param CompareValue between Min_Data=0 and Max_Data=65535
2655 * @retval None
2656 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2657 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2658 {
2659 WRITE_REG(TIMx->CCR4, CompareValue);
2660 }
2661
2662 /**
2663 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2664 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2665 * output channel 5 is supported by a timer instance.
2666 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2667 * @param TIMx Timer instance
2668 * @param CompareValue between Min_Data=0 and Max_Data=65535
2669 * @retval None
2670 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2671 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2672 {
2673 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2674 }
2675
2676 /**
2677 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2678 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2679 * output channel 6 is supported by a timer instance.
2680 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2681 * @param TIMx Timer instance
2682 * @param CompareValue between Min_Data=0 and Max_Data=65535
2683 * @retval None
2684 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2685 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2686 {
2687 WRITE_REG(TIMx->CCR6, CompareValue);
2688 }
2689
2690 /**
2691 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2692 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2693 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2694 * whether or not a timer instance supports a 32 bits counter.
2695 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2696 * output channel 1 is supported by a timer instance.
2697 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2698 * @param TIMx Timer instance
2699 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2700 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2701 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2702 {
2703 return (uint32_t)(READ_REG(TIMx->CCR1));
2704 }
2705
2706 /**
2707 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2708 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2709 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2710 * whether or not a timer instance supports a 32 bits counter.
2711 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2712 * output channel 2 is supported by a timer instance.
2713 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2714 * @param TIMx Timer instance
2715 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2716 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2717 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2718 {
2719 return (uint32_t)(READ_REG(TIMx->CCR2));
2720 }
2721
2722 /**
2723 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2724 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2725 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2726 * whether or not a timer instance supports a 32 bits counter.
2727 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2728 * output channel 3 is supported by a timer instance.
2729 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2730 * @param TIMx Timer instance
2731 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2732 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2733 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2734 {
2735 return (uint32_t)(READ_REG(TIMx->CCR3));
2736 }
2737
2738 /**
2739 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2740 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2741 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2742 * whether or not a timer instance supports a 32 bits counter.
2743 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2744 * output channel 4 is supported by a timer instance.
2745 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2746 * @param TIMx Timer instance
2747 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2748 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2749 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2750 {
2751 return (uint32_t)(READ_REG(TIMx->CCR4));
2752 }
2753
2754 /**
2755 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2756 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2757 * output channel 5 is supported by a timer instance.
2758 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2759 * @param TIMx Timer instance
2760 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2761 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)2762 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
2763 {
2764 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2765 }
2766
2767 /**
2768 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2769 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2770 * output channel 6 is supported by a timer instance.
2771 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2772 * @param TIMx Timer instance
2773 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2774 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)2775 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
2776 {
2777 return (uint32_t)(READ_REG(TIMx->CCR6));
2778 }
2779
2780 /**
2781 * @brief Select on which reference signal the OC5REF is combined to.
2782 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2783 * whether or not a timer instance supports the combined 3-phase PWM mode.
2784 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2785 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2786 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2787 * @param TIMx Timer instance
2788 * @param GroupCH5 This parameter can be a combination of the following values:
2789 * @arg @ref LL_TIM_GROUPCH5_NONE
2790 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2791 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2792 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2793 * @retval None
2794 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2795 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2796 {
2797 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2798 }
2799
2800 /**
2801 * @}
2802 */
2803
2804 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2805 * @{
2806 */
2807 /**
2808 * @brief Configure input channel.
2809 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2810 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2811 * CCMR1 IC1F LL_TIM_IC_Config\n
2812 * CCMR1 CC2S LL_TIM_IC_Config\n
2813 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2814 * CCMR1 IC2F LL_TIM_IC_Config\n
2815 * CCMR2 CC3S LL_TIM_IC_Config\n
2816 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2817 * CCMR2 IC3F LL_TIM_IC_Config\n
2818 * CCMR2 CC4S LL_TIM_IC_Config\n
2819 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2820 * CCMR2 IC4F LL_TIM_IC_Config\n
2821 * CCER CC1P LL_TIM_IC_Config\n
2822 * CCER CC1NP LL_TIM_IC_Config\n
2823 * CCER CC2P LL_TIM_IC_Config\n
2824 * CCER CC2NP LL_TIM_IC_Config\n
2825 * CCER CC3P LL_TIM_IC_Config\n
2826 * CCER CC3NP LL_TIM_IC_Config\n
2827 * CCER CC4P LL_TIM_IC_Config\n
2828 * CCER CC4NP LL_TIM_IC_Config
2829 * @param TIMx Timer instance
2830 * @param Channel This parameter can be one of the following values:
2831 * @arg @ref LL_TIM_CHANNEL_CH1
2832 * @arg @ref LL_TIM_CHANNEL_CH2
2833 * @arg @ref LL_TIM_CHANNEL_CH3
2834 * @arg @ref LL_TIM_CHANNEL_CH4
2835 * @param Configuration This parameter must be a combination of all the following values:
2836 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2837 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2838 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2839 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2840 * @retval None
2841 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2842 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2843 {
2844 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2845 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2846 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2847 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2848 << SHIFT_TAB_ICxx[iChannel]);
2849 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2850 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2851 }
2852
2853 /**
2854 * @brief Set the active input.
2855 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2856 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2857 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2858 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2859 * @param TIMx Timer instance
2860 * @param Channel This parameter can be one of the following values:
2861 * @arg @ref LL_TIM_CHANNEL_CH1
2862 * @arg @ref LL_TIM_CHANNEL_CH2
2863 * @arg @ref LL_TIM_CHANNEL_CH3
2864 * @arg @ref LL_TIM_CHANNEL_CH4
2865 * @param ICActiveInput This parameter can be one of the following values:
2866 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2867 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2868 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2869 * @retval None
2870 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2871 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2872 {
2873 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2874 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2875 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2876 }
2877
2878 /**
2879 * @brief Get the current active input.
2880 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2881 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2882 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2883 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2884 * @param TIMx Timer instance
2885 * @param Channel This parameter can be one of the following values:
2886 * @arg @ref LL_TIM_CHANNEL_CH1
2887 * @arg @ref LL_TIM_CHANNEL_CH2
2888 * @arg @ref LL_TIM_CHANNEL_CH3
2889 * @arg @ref LL_TIM_CHANNEL_CH4
2890 * @retval Returned value can be one of the following values:
2891 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2892 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2893 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2894 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)2895 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
2896 {
2897 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2898 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2899 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2900 }
2901
2902 /**
2903 * @brief Set the prescaler of input channel.
2904 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2905 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2906 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2907 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2908 * @param TIMx Timer instance
2909 * @param Channel This parameter can be one of the following values:
2910 * @arg @ref LL_TIM_CHANNEL_CH1
2911 * @arg @ref LL_TIM_CHANNEL_CH2
2912 * @arg @ref LL_TIM_CHANNEL_CH3
2913 * @arg @ref LL_TIM_CHANNEL_CH4
2914 * @param ICPrescaler This parameter can be one of the following values:
2915 * @arg @ref LL_TIM_ICPSC_DIV1
2916 * @arg @ref LL_TIM_ICPSC_DIV2
2917 * @arg @ref LL_TIM_ICPSC_DIV4
2918 * @arg @ref LL_TIM_ICPSC_DIV8
2919 * @retval None
2920 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2921 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2922 {
2923 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2924 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2925 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2926 }
2927
2928 /**
2929 * @brief Get the current prescaler value acting on an input channel.
2930 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2931 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2932 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2933 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2934 * @param TIMx Timer instance
2935 * @param Channel This parameter can be one of the following values:
2936 * @arg @ref LL_TIM_CHANNEL_CH1
2937 * @arg @ref LL_TIM_CHANNEL_CH2
2938 * @arg @ref LL_TIM_CHANNEL_CH3
2939 * @arg @ref LL_TIM_CHANNEL_CH4
2940 * @retval Returned value can be one of the following values:
2941 * @arg @ref LL_TIM_ICPSC_DIV1
2942 * @arg @ref LL_TIM_ICPSC_DIV2
2943 * @arg @ref LL_TIM_ICPSC_DIV4
2944 * @arg @ref LL_TIM_ICPSC_DIV8
2945 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)2946 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
2947 {
2948 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2949 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2950 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2951 }
2952
2953 /**
2954 * @brief Set the input filter duration.
2955 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2956 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2957 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2958 * CCMR2 IC4F LL_TIM_IC_SetFilter
2959 * @param TIMx Timer instance
2960 * @param Channel This parameter can be one of the following values:
2961 * @arg @ref LL_TIM_CHANNEL_CH1
2962 * @arg @ref LL_TIM_CHANNEL_CH2
2963 * @arg @ref LL_TIM_CHANNEL_CH3
2964 * @arg @ref LL_TIM_CHANNEL_CH4
2965 * @param ICFilter This parameter can be one of the following values:
2966 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2967 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2968 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2969 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2970 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2971 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2972 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2973 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2974 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2975 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2976 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2977 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2978 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2979 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2980 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2981 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2982 * @retval None
2983 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2984 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2985 {
2986 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2987 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2988 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2989 }
2990
2991 /**
2992 * @brief Get the input filter duration.
2993 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2994 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2995 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2996 * CCMR2 IC4F LL_TIM_IC_GetFilter
2997 * @param TIMx Timer instance
2998 * @param Channel This parameter can be one of the following values:
2999 * @arg @ref LL_TIM_CHANNEL_CH1
3000 * @arg @ref LL_TIM_CHANNEL_CH2
3001 * @arg @ref LL_TIM_CHANNEL_CH3
3002 * @arg @ref LL_TIM_CHANNEL_CH4
3003 * @retval Returned value can be one of the following values:
3004 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3005 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3006 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3007 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3008 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3009 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3010 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3011 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3012 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3013 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3014 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3015 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3016 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3017 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3018 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3019 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3020 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)3021 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
3022 {
3023 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3024 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3025 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3026 }
3027
3028 /**
3029 * @brief Set the input channel polarity.
3030 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3031 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3032 * CCER CC2P LL_TIM_IC_SetPolarity\n
3033 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3034 * CCER CC3P LL_TIM_IC_SetPolarity\n
3035 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3036 * CCER CC4P LL_TIM_IC_SetPolarity\n
3037 * CCER CC4NP LL_TIM_IC_SetPolarity
3038 * @param TIMx Timer instance
3039 * @param Channel This parameter can be one of the following values:
3040 * @arg @ref LL_TIM_CHANNEL_CH1
3041 * @arg @ref LL_TIM_CHANNEL_CH2
3042 * @arg @ref LL_TIM_CHANNEL_CH3
3043 * @arg @ref LL_TIM_CHANNEL_CH4
3044 * @param ICPolarity This parameter can be one of the following values:
3045 * @arg @ref LL_TIM_IC_POLARITY_RISING
3046 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3047 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3048 * @retval None
3049 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3050 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3051 {
3052 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3053 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3054 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3055 }
3056
3057 /**
3058 * @brief Get the current input channel polarity.
3059 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3060 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3061 * CCER CC2P LL_TIM_IC_GetPolarity\n
3062 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3063 * CCER CC3P LL_TIM_IC_GetPolarity\n
3064 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3065 * CCER CC4P LL_TIM_IC_GetPolarity\n
3066 * CCER CC4NP LL_TIM_IC_GetPolarity
3067 * @param TIMx Timer instance
3068 * @param Channel This parameter can be one of the following values:
3069 * @arg @ref LL_TIM_CHANNEL_CH1
3070 * @arg @ref LL_TIM_CHANNEL_CH2
3071 * @arg @ref LL_TIM_CHANNEL_CH3
3072 * @arg @ref LL_TIM_CHANNEL_CH4
3073 * @retval Returned value can be one of the following values:
3074 * @arg @ref LL_TIM_IC_POLARITY_RISING
3075 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3076 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3077 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3078 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3079 {
3080 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3081 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3082 SHIFT_TAB_CCxP[iChannel]);
3083 }
3084
3085 /**
3086 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3087 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3088 * a timer instance provides an XOR input.
3089 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3090 * @param TIMx Timer instance
3091 * @retval None
3092 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3093 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3094 {
3095 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3096 }
3097
3098 /**
3099 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3100 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3101 * a timer instance provides an XOR input.
3102 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3103 * @param TIMx Timer instance
3104 * @retval None
3105 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3106 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3107 {
3108 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3109 }
3110
3111 /**
3112 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3113 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3114 * a timer instance provides an XOR input.
3115 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3116 * @param TIMx Timer instance
3117 * @retval State of bit (1 or 0).
3118 */
LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef * TIMx)3119 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
3120 {
3121 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3122 }
3123
3124 /**
3125 * @brief Get captured value for input channel 1.
3126 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3127 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3128 * whether or not a timer instance supports a 32 bits counter.
3129 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3130 * input channel 1 is supported by a timer instance.
3131 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3132 * @param TIMx Timer instance
3133 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3134 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3135 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3136 {
3137 return (uint32_t)(READ_REG(TIMx->CCR1));
3138 }
3139
3140 /**
3141 * @brief Get captured value for input channel 2.
3142 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3143 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3144 * whether or not a timer instance supports a 32 bits counter.
3145 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3146 * input channel 2 is supported by a timer instance.
3147 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3148 * @param TIMx Timer instance
3149 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3150 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3151 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3152 {
3153 return (uint32_t)(READ_REG(TIMx->CCR2));
3154 }
3155
3156 /**
3157 * @brief Get captured value for input channel 3.
3158 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3159 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3160 * whether or not a timer instance supports a 32 bits counter.
3161 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3162 * input channel 3 is supported by a timer instance.
3163 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3164 * @param TIMx Timer instance
3165 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3166 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3167 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3168 {
3169 return (uint32_t)(READ_REG(TIMx->CCR3));
3170 }
3171
3172 /**
3173 * @brief Get captured value for input channel 4.
3174 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3175 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3176 * whether or not a timer instance supports a 32 bits counter.
3177 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3178 * input channel 4 is supported by a timer instance.
3179 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3180 * @param TIMx Timer instance
3181 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3182 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3183 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3184 {
3185 return (uint32_t)(READ_REG(TIMx->CCR4));
3186 }
3187
3188 /**
3189 * @}
3190 */
3191
3192 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3193 * @{
3194 */
3195 /**
3196 * @brief Enable external clock mode 2.
3197 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3198 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3199 * whether or not a timer instance supports external clock mode2.
3200 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3201 * @param TIMx Timer instance
3202 * @retval None
3203 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3204 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3205 {
3206 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3207 }
3208
3209 /**
3210 * @brief Disable external clock mode 2.
3211 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3212 * whether or not a timer instance supports external clock mode2.
3213 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3214 * @param TIMx Timer instance
3215 * @retval None
3216 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3217 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3218 {
3219 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3220 }
3221
3222 /**
3223 * @brief Indicate whether external clock mode 2 is enabled.
3224 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3225 * whether or not a timer instance supports external clock mode2.
3226 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3227 * @param TIMx Timer instance
3228 * @retval State of bit (1 or 0).
3229 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3230 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3231 {
3232 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3233 }
3234
3235 /**
3236 * @brief Set the clock source of the counter clock.
3237 * @note when selected clock source is external clock mode 1, the timer input
3238 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3239 * function. This timer input must be configured by calling
3240 * the @ref LL_TIM_IC_Config() function.
3241 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3242 * whether or not a timer instance supports external clock mode1.
3243 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3244 * whether or not a timer instance supports external clock mode2.
3245 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3246 * SMCR ECE LL_TIM_SetClockSource
3247 * @param TIMx Timer instance
3248 * @param ClockSource This parameter can be one of the following values:
3249 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3250 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3251 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3252 * @retval None
3253 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3254 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3255 {
3256 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3257 }
3258
3259 /**
3260 * @brief Set the encoder interface mode.
3261 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3262 * whether or not a timer instance supports the encoder mode.
3263 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3264 * @param TIMx Timer instance
3265 * @param EncoderMode This parameter can be one of the following values:
3266 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3267 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3268 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3269 * @retval None
3270 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3271 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3272 {
3273 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3274 }
3275
3276 /**
3277 * @}
3278 */
3279
3280 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3281 * @{
3282 */
3283 /**
3284 * @brief Set the trigger output (TRGO) used for timer synchronization .
3285 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3286 * whether or not a timer instance can operate as a master timer.
3287 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3288 * @param TIMx Timer instance
3289 * @param TimerSynchronization This parameter can be one of the following values:
3290 * @arg @ref LL_TIM_TRGO_RESET
3291 * @arg @ref LL_TIM_TRGO_ENABLE
3292 * @arg @ref LL_TIM_TRGO_UPDATE
3293 * @arg @ref LL_TIM_TRGO_CC1IF
3294 * @arg @ref LL_TIM_TRGO_OC1REF
3295 * @arg @ref LL_TIM_TRGO_OC2REF
3296 * @arg @ref LL_TIM_TRGO_OC3REF
3297 * @arg @ref LL_TIM_TRGO_OC4REF
3298 * @retval None
3299 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3300 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3301 {
3302 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3303 }
3304
3305 /**
3306 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3307 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3308 * whether or not a timer instance can be used for ADC synchronization.
3309 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3310 * @param TIMx Timer Instance
3311 * @param ADCSynchronization This parameter can be one of the following values:
3312 * @arg @ref LL_TIM_TRGO2_RESET
3313 * @arg @ref LL_TIM_TRGO2_ENABLE
3314 * @arg @ref LL_TIM_TRGO2_UPDATE
3315 * @arg @ref LL_TIM_TRGO2_CC1F
3316 * @arg @ref LL_TIM_TRGO2_OC1
3317 * @arg @ref LL_TIM_TRGO2_OC2
3318 * @arg @ref LL_TIM_TRGO2_OC3
3319 * @arg @ref LL_TIM_TRGO2_OC4
3320 * @arg @ref LL_TIM_TRGO2_OC5
3321 * @arg @ref LL_TIM_TRGO2_OC6
3322 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3323 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3324 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3325 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3326 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3327 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3328 * @retval None
3329 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3330 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3331 {
3332 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3333 }
3334
3335 /**
3336 * @brief Set the synchronization mode of a slave timer.
3337 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3338 * a timer instance can operate as a slave timer.
3339 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3340 * @param TIMx Timer instance
3341 * @param SlaveMode This parameter can be one of the following values:
3342 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3343 * @arg @ref LL_TIM_SLAVEMODE_RESET
3344 * @arg @ref LL_TIM_SLAVEMODE_GATED
3345 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3346 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3347 * @retval None
3348 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3349 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3350 {
3351 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3352 }
3353
3354 /**
3355 * @brief Set the selects the trigger input to be used to synchronize the counter.
3356 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3357 * a timer instance can operate as a slave timer.
3358 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3359 * @param TIMx Timer instance
3360 * @param TriggerInput This parameter can be one of the following values:
3361 * @arg @ref LL_TIM_TS_ITR0
3362 * @arg @ref LL_TIM_TS_ITR1
3363 * @arg @ref LL_TIM_TS_ITR2
3364 * @arg @ref LL_TIM_TS_ITR3
3365 * @arg @ref LL_TIM_TS_TI1F_ED
3366 * @arg @ref LL_TIM_TS_TI1FP1
3367 * @arg @ref LL_TIM_TS_TI2FP2
3368 * @arg @ref LL_TIM_TS_ETRF
3369 * @retval None
3370 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3371 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3372 {
3373 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3374 }
3375
3376 /**
3377 * @brief Enable the Master/Slave mode.
3378 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3379 * a timer instance can operate as a slave timer.
3380 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3381 * @param TIMx Timer instance
3382 * @retval None
3383 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3384 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3385 {
3386 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3387 }
3388
3389 /**
3390 * @brief Disable the Master/Slave mode.
3391 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3392 * a timer instance can operate as a slave timer.
3393 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3394 * @param TIMx Timer instance
3395 * @retval None
3396 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3397 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3398 {
3399 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3400 }
3401
3402 /**
3403 * @brief Indicates whether the Master/Slave mode is enabled.
3404 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3405 * a timer instance can operate as a slave timer.
3406 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3407 * @param TIMx Timer instance
3408 * @retval State of bit (1 or 0).
3409 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3410 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3411 {
3412 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3413 }
3414
3415 /**
3416 * @brief Configure the external trigger (ETR) input.
3417 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3418 * a timer instance provides an external trigger input.
3419 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3420 * SMCR ETPS LL_TIM_ConfigETR\n
3421 * SMCR ETF LL_TIM_ConfigETR
3422 * @param TIMx Timer instance
3423 * @param ETRPolarity This parameter can be one of the following values:
3424 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3425 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3426 * @param ETRPrescaler This parameter can be one of the following values:
3427 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3428 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3429 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3430 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3431 * @param ETRFilter This parameter can be one of the following values:
3432 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3433 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3434 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3435 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3436 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3437 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3438 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3439 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3440 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3441 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3442 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3443 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3444 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3445 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3446 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3447 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3448 * @retval None
3449 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3450 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3451 uint32_t ETRFilter)
3452 {
3453 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3454 }
3455
3456 /**
3457 * @brief Select the external trigger (ETR) input source.
3458 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3459 * not a timer instance supports ETR source selection.
3460 * @rmtoll OR2 ETRSEL LL_TIM_SetETRSource
3461 * @param TIMx Timer instance
3462 * @param ETRSource This parameter can be one of the following values:
3463 * @arg @ref LL_TIM_ETRSOURCE_LEGACY
3464 * @arg @ref LL_TIM_ETRSOURCE_COMP1
3465 * @arg @ref LL_TIM_ETRSOURCE_COMP2
3466 * @retval None
3467 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3468 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3469 {
3470 MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource);
3471 }
3472
3473 /**
3474 * @}
3475 */
3476
3477 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3478 * @{
3479 */
3480 /**
3481 * @brief Enable the break function.
3482 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3483 * a timer instance provides a break input.
3484 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3485 * @param TIMx Timer instance
3486 * @retval None
3487 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3488 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3489 {
3490 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3491 }
3492
3493 /**
3494 * @brief Disable the break function.
3495 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3496 * @param TIMx Timer instance
3497 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3498 * a timer instance provides a break input.
3499 * @retval None
3500 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3501 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3502 {
3503 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3504 }
3505
3506 /**
3507 * @brief Configure the break input.
3508 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3509 * a timer instance provides a break input.
3510 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3511 * BDTR BKF LL_TIM_ConfigBRK
3512 * @param TIMx Timer instance
3513 * @param BreakPolarity This parameter can be one of the following values:
3514 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3515 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3516 * @param BreakFilter This parameter can be one of the following values:
3517 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3518 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3519 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3520 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3521 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3522 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3523 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3524 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3525 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3526 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3527 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3528 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3529 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3530 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3531 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3532 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3533 * @retval None
3534 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter)3535 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
3536 uint32_t BreakFilter)
3537 {
3538 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
3539 }
3540
3541 /**
3542 * @brief Enable the break 2 function.
3543 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3544 * a timer instance provides a second break input.
3545 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3546 * @param TIMx Timer instance
3547 * @retval None
3548 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3549 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3550 {
3551 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3552 }
3553
3554 /**
3555 * @brief Disable the break 2 function.
3556 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3557 * a timer instance provides a second break input.
3558 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3559 * @param TIMx Timer instance
3560 * @retval None
3561 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3562 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3563 {
3564 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3565 }
3566
3567 /**
3568 * @brief Configure the break 2 input.
3569 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3570 * a timer instance provides a second break input.
3571 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3572 * BDTR BK2F LL_TIM_ConfigBRK2
3573 * @param TIMx Timer instance
3574 * @param Break2Polarity This parameter can be one of the following values:
3575 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3576 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3577 * @param Break2Filter This parameter can be one of the following values:
3578 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3579 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3580 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3581 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3582 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3583 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3584 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3585 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3586 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3587 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3588 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3589 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3590 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3591 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3592 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3593 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3594 * @retval None
3595 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter)3596 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
3597 {
3598 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
3599 }
3600
3601 /**
3602 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3603 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3604 * a timer instance provides a break input.
3605 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3606 * BDTR OSSR LL_TIM_SetOffStates
3607 * @param TIMx Timer instance
3608 * @param OffStateIdle This parameter can be one of the following values:
3609 * @arg @ref LL_TIM_OSSI_DISABLE
3610 * @arg @ref LL_TIM_OSSI_ENABLE
3611 * @param OffStateRun This parameter can be one of the following values:
3612 * @arg @ref LL_TIM_OSSR_DISABLE
3613 * @arg @ref LL_TIM_OSSR_ENABLE
3614 * @retval None
3615 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3616 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3617 {
3618 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3619 }
3620
3621 /**
3622 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3623 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3624 * a timer instance provides a break input.
3625 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3626 * @param TIMx Timer instance
3627 * @retval None
3628 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3629 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3630 {
3631 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3632 }
3633
3634 /**
3635 * @brief Disable automatic output (MOE can be set only by software).
3636 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3637 * a timer instance provides a break input.
3638 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3639 * @param TIMx Timer instance
3640 * @retval None
3641 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3642 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3643 {
3644 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3645 }
3646
3647 /**
3648 * @brief Indicate whether automatic output is enabled.
3649 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3650 * a timer instance provides a break input.
3651 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3652 * @param TIMx Timer instance
3653 * @retval State of bit (1 or 0).
3654 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)3655 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
3656 {
3657 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3658 }
3659
3660 /**
3661 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3662 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3663 * software and is reset in case of break or break2 event
3664 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3665 * a timer instance provides a break input.
3666 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3667 * @param TIMx Timer instance
3668 * @retval None
3669 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3670 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3671 {
3672 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3673 }
3674
3675 /**
3676 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3677 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3678 * software and is reset in case of break or break2 event.
3679 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3680 * a timer instance provides a break input.
3681 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3682 * @param TIMx Timer instance
3683 * @retval None
3684 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3685 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3686 {
3687 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3688 }
3689
3690 /**
3691 * @brief Indicates whether outputs are enabled.
3692 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3693 * a timer instance provides a break input.
3694 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3695 * @param TIMx Timer instance
3696 * @retval State of bit (1 or 0).
3697 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)3698 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3699 {
3700 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3701 }
3702
3703 /**
3704 * @brief Enable the signals connected to the designated timer break input.
3705 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3706 * or not a timer instance allows for break input selection.
3707 * @rmtoll OR2 BKINE LL_TIM_EnableBreakInputSource\n
3708 * OR2 BKCMP1E LL_TIM_EnableBreakInputSource\n
3709 * OR2 BKCMP2E LL_TIM_EnableBreakInputSource\n
3710 * OR2 BKDF1BK0E LL_TIM_EnableBreakInputSource\n
3711 * OR3 BK2INE LL_TIM_EnableBreakInputSource\n
3712 * OR3 BK2CMP1E LL_TIM_EnableBreakInputSource\n
3713 * OR3 BK2CMP2E LL_TIM_EnableBreakInputSource\n
3714 * OR3 BK2DF1BK1E LL_TIM_EnableBreakInputSource
3715 * @param TIMx Timer instance
3716 * @param BreakInput This parameter can be one of the following values:
3717 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3718 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3719 * @param Source This parameter can be one of the following values:
3720 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3721 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3722 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3723 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3724 * @retval None
3725 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3726 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3727 {
3728 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
3729 SET_BIT(*pReg, Source);
3730 }
3731
3732 /**
3733 * @brief Disable the signals connected to the designated timer break input.
3734 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3735 * or not a timer instance allows for break input selection.
3736 * @rmtoll OR2 BKINE LL_TIM_DisableBreakInputSource\n
3737 * OR2 BKCMP1E LL_TIM_DisableBreakInputSource\n
3738 * OR2 BKCMP2E LL_TIM_DisableBreakInputSource\n
3739 * OR2 BKDF1BK0E LL_TIM_DisableBreakInputSource\n
3740 * OR3 BK2INE LL_TIM_DisableBreakInputSource\n
3741 * OR3 BK2CMP1E LL_TIM_DisableBreakInputSource\n
3742 * OR3 BK2CMP2E LL_TIM_DisableBreakInputSource\n
3743 * OR3 BK2DF1BK1E LL_TIM_DisableBreakInputSource
3744 * @param TIMx Timer instance
3745 * @param BreakInput This parameter can be one of the following values:
3746 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3747 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3748 * @param Source This parameter can be one of the following values:
3749 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3750 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3751 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3752 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3753 * @retval None
3754 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3755 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3756 {
3757 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
3758 CLEAR_BIT(*pReg, Source);
3759 }
3760
3761 /**
3762 * @brief Set the polarity of the break signal for the timer break input.
3763 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3764 * or not a timer instance allows for break input selection.
3765 * @rmtoll OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3766 * OR2 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
3767 * OR2 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
3768 * OR3 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3769 * OR3 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
3770 * OR3 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
3771 * @param TIMx Timer instance
3772 * @param BreakInput This parameter can be one of the following values:
3773 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3774 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3775 * @param Source This parameter can be one of the following values:
3776 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3777 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3778 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3779 * @param Polarity This parameter can be one of the following values:
3780 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
3781 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3782 * @retval None
3783 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)3784 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3785 uint32_t Polarity)
3786 {
3787 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
3788 MODIFY_REG(*pReg, (TIMx_OR2_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
3789 }
3790 /**
3791 * @}
3792 */
3793
3794 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3795 * @{
3796 */
3797 /**
3798 * @brief Configures the timer DMA burst feature.
3799 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3800 * not a timer instance supports the DMA burst mode.
3801 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3802 * DCR DBA LL_TIM_ConfigDMABurst
3803 * @param TIMx Timer instance
3804 * @param DMABurstBaseAddress This parameter can be one of the following values:
3805 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3806 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3807 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3808 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3809 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3810 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3811 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3812 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3813 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3814 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3815 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3816 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3817 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3818 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3819 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3820 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3821 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3822 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3823 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
3824 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3825 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3826 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3827 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR2
3828 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR3
3829 * @param DMABurstLength This parameter can be one of the following values:
3830 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3831 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3832 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3833 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3834 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3835 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3836 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3837 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3838 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3839 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3840 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3841 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3842 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3843 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3844 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3845 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3846 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3847 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3848 * @retval None
3849 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3850 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3851 {
3852 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3853 }
3854
3855 /**
3856 * @}
3857 */
3858
3859 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3860 * @{
3861 */
3862 /**
3863 * @brief Remap TIM inputs (input channel, internal/external triggers).
3864 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3865 * a some timer inputs can be remapped.
3866 @if STM32L486xx
3867 * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n
3868 * TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
3869 * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n
3870 * TIM8_OR1 ETR_ADC2_RMP LL_TIM_SetRemap\n
3871 * TIM8_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
3872 * TIM8_OR1 TI1_RMP LL_TIM_SetRemap\n
3873 * TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n
3874 * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n
3875 * TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n
3876 * TIM3_OR1 TI1_RMP LL_TIM_SetRemap\n
3877 * TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n
3878 * TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n
3879 * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n
3880 * TIM17_OR1 TI1_RMP LL_TIM_SetRemap
3881 @endif
3882 @if STM32L443xx
3883 * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n
3884 * TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
3885 * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n
3886 * TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n
3887 * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n
3888 * TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n
3889 * TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n
3890 * TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n
3891 * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n
3892 @endif
3893 * @param TIMx Timer instance
3894 * @param Remap Remap param depends on the TIMx. Description available only
3895 * in CHM version of the User Manual (not in .pdf).
3896 * Otherwise see Reference Manual description of OR registers.
3897 *
3898 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3899 *
3900 @if STM32L486xx
3901 * TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
3902 *
3903 * . . ADC1_RMP can be one of the following values
3904 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
3905 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
3906 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
3907 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
3908 *
3909 * . . ADC3_RMP can be one of the following values
3910 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC
3911 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1
3912 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2
3913 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3
3914 *
3915 * . . TI1_RMP can be one of the following values
3916 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
3917 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
3918 *
3919 * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
3920 *
3921 * ITR1_RMP can be one of the following values
3922 * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
3923 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
3924 *
3925 * . . ETR1_RMP can be one of the following values
3926 * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
3927 * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
3928 *
3929 * . . TI4_RMP can be one of the following values
3930 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
3931 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
3932 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
3933 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
3934 *
3935 * TIM3: one of the following values
3936 *
3937 * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
3938 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
3939 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
3940 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1_COMP2
3941 *
3942 * TIM8: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
3943 *
3944 * . . ADC1_RMP can be one of the following values
3945 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC
3946 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1
3947 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2
3948 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3
3949 *
3950 * . . ADC3_RMP can be one of the following values
3951 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC
3952 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1
3953 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2
3954 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3
3955 *
3956 * . . TI1_RMP can be one of the following values
3957 * @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
3958 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
3959 *
3960 * TIM15: any combination of TI1_RMP, ENCODER_MODE where
3961 *
3962 * . . TI1_RMP can be one of the following values
3963 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
3964 * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
3965 *
3966 * . . ENCODER_MODE can be one of the following values
3967 * @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
3968 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2
3969 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
3970 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
3971 *
3972 * TIM16: one of the following values
3973 *
3974 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
3975 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
3976 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
3977 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
3978 * @arg @ref LL_TIM_TIM16_TI1_RMP_MSI
3979 * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
3980 * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
3981 *
3982 * TIM17: one of the following values
3983 *
3984 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
3985 * @arg @ref LL_TIM_TIM17_TI1_RMP_MSI
3986 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
3987 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
3988 @endif
3989 @if STM32L443xx
3990 * TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
3991 *
3992 * . . ADC1_RMP can be one of the following values
3993 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
3994 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
3995 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
3996 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
3997 *
3998 * . . TI1_RMP can be one of the following values
3999 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
4000 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
4001 *
4002 * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
4003 *
4004 * ITR1_RMP can be one of the following values
4005 * @arg @ref LL_TIM_TIM2_ITR1_RMP_NONE
4006 * @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF
4007 *
4008 * . . ETR1_RMP can be one of the following values
4009 * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
4010 * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
4011 *
4012 * . . TI4_RMP can be one of the following values
4013 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
4014 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
4015 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
4016 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
4017 *
4018 * TIM15: any combination of TI1_RMP, ENCODER_MODE where
4019 *
4020 * . . TI1_RMP can be one of the following values
4021 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
4022 * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
4023 *
4024 * . . ENCODER_MODE can be one of the following values
4025 * @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
4026 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2
4027 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
4028 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
4029 *
4030 * TIM16: one of the following values
4031 *
4032 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
4033 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
4034 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
4035 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
4036 * @arg @ref LL_TIM_TIM16_TI1_RMP_MSI
4037 * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
4038 * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
4039 @endif
4040 * @retval None
4041 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)4042 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
4043 {
4044 MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK));
4045 }
4046
4047 /**
4048 * @}
4049 */
4050
4051 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
4052 * @{
4053 */
4054 /**
4055 * @brief Set the OCREF clear input source
4056 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
4057 * @note This function can only be used in Output compare and PWM modes.
4058 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
4059 * @param TIMx Timer instance
4060 * @param OCRefClearInputSource This parameter can be one of the following values:
4061 * @arg @ref LL_TIM_OCREF_CLR_INT_NC
4062 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
4063 * @retval None
4064 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)4065 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
4066 {
4067 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
4068 }
4069 /**
4070 * @}
4071 */
4072
4073 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4074 * @{
4075 */
4076 /**
4077 * @brief Clear the update interrupt flag (UIF).
4078 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
4079 * @param TIMx Timer instance
4080 * @retval None
4081 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)4082 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
4083 {
4084 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
4085 }
4086
4087 /**
4088 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
4089 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
4090 * @param TIMx Timer instance
4091 * @retval State of bit (1 or 0).
4092 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)4093 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
4094 {
4095 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
4096 }
4097
4098 /**
4099 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
4100 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
4101 * @param TIMx Timer instance
4102 * @retval None
4103 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)4104 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
4105 {
4106 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
4107 }
4108
4109 /**
4110 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
4111 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
4112 * @param TIMx Timer instance
4113 * @retval State of bit (1 or 0).
4114 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)4115 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
4116 {
4117 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
4118 }
4119
4120 /**
4121 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4122 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4123 * @param TIMx Timer instance
4124 * @retval None
4125 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)4126 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4127 {
4128 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4129 }
4130
4131 /**
4132 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4133 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4134 * @param TIMx Timer instance
4135 * @retval State of bit (1 or 0).
4136 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)4137 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
4138 {
4139 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
4140 }
4141
4142 /**
4143 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4144 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4145 * @param TIMx Timer instance
4146 * @retval None
4147 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)4148 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4149 {
4150 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4151 }
4152
4153 /**
4154 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4155 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4156 * @param TIMx Timer instance
4157 * @retval State of bit (1 or 0).
4158 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)4159 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
4160 {
4161 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4162 }
4163
4164 /**
4165 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4166 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4167 * @param TIMx Timer instance
4168 * @retval None
4169 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)4170 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4171 {
4172 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4173 }
4174
4175 /**
4176 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4177 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4178 * @param TIMx Timer instance
4179 * @retval State of bit (1 or 0).
4180 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)4181 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
4182 {
4183 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4184 }
4185
4186 /**
4187 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4188 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4189 * @param TIMx Timer instance
4190 * @retval None
4191 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4192 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4193 {
4194 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4195 }
4196
4197 /**
4198 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4199 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4200 * @param TIMx Timer instance
4201 * @retval State of bit (1 or 0).
4202 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)4203 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
4204 {
4205 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4206 }
4207
4208 /**
4209 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4210 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4211 * @param TIMx Timer instance
4212 * @retval None
4213 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4214 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4215 {
4216 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4217 }
4218
4219 /**
4220 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4221 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4222 * @param TIMx Timer instance
4223 * @retval State of bit (1 or 0).
4224 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)4225 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
4226 {
4227 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4228 }
4229
4230 /**
4231 * @brief Clear the commutation interrupt flag (COMIF).
4232 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4233 * @param TIMx Timer instance
4234 * @retval None
4235 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4236 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4237 {
4238 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4239 }
4240
4241 /**
4242 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4243 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4244 * @param TIMx Timer instance
4245 * @retval State of bit (1 or 0).
4246 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)4247 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
4248 {
4249 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4250 }
4251
4252 /**
4253 * @brief Clear the trigger interrupt flag (TIF).
4254 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4255 * @param TIMx Timer instance
4256 * @retval None
4257 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)4258 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4259 {
4260 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4261 }
4262
4263 /**
4264 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4265 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4266 * @param TIMx Timer instance
4267 * @retval State of bit (1 or 0).
4268 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)4269 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
4270 {
4271 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4272 }
4273
4274 /**
4275 * @brief Clear the break interrupt flag (BIF).
4276 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4277 * @param TIMx Timer instance
4278 * @retval None
4279 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)4280 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4281 {
4282 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4283 }
4284
4285 /**
4286 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4287 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4288 * @param TIMx Timer instance
4289 * @retval State of bit (1 or 0).
4290 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)4291 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
4292 {
4293 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4294 }
4295
4296 /**
4297 * @brief Clear the break 2 interrupt flag (B2IF).
4298 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4299 * @param TIMx Timer instance
4300 * @retval None
4301 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)4302 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4303 {
4304 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4305 }
4306
4307 /**
4308 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4309 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4310 * @param TIMx Timer instance
4311 * @retval State of bit (1 or 0).
4312 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)4313 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
4314 {
4315 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4316 }
4317
4318 /**
4319 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4320 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4321 * @param TIMx Timer instance
4322 * @retval None
4323 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)4324 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4325 {
4326 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4327 }
4328
4329 /**
4330 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
4331 * (Capture/Compare 1 interrupt is pending).
4332 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4333 * @param TIMx Timer instance
4334 * @retval State of bit (1 or 0).
4335 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)4336 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
4337 {
4338 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4339 }
4340
4341 /**
4342 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4343 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4344 * @param TIMx Timer instance
4345 * @retval None
4346 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)4347 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4348 {
4349 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4350 }
4351
4352 /**
4353 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
4354 * (Capture/Compare 2 over-capture interrupt is pending).
4355 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4356 * @param TIMx Timer instance
4357 * @retval State of bit (1 or 0).
4358 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)4359 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
4360 {
4361 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4362 }
4363
4364 /**
4365 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4366 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4367 * @param TIMx Timer instance
4368 * @retval None
4369 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)4370 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4371 {
4372 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4373 }
4374
4375 /**
4376 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
4377 * (Capture/Compare 3 over-capture interrupt is pending).
4378 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4379 * @param TIMx Timer instance
4380 * @retval State of bit (1 or 0).
4381 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)4382 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
4383 {
4384 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4385 }
4386
4387 /**
4388 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4389 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4390 * @param TIMx Timer instance
4391 * @retval None
4392 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)4393 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4394 {
4395 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4396 }
4397
4398 /**
4399 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
4400 * (Capture/Compare 4 over-capture interrupt is pending).
4401 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4402 * @param TIMx Timer instance
4403 * @retval State of bit (1 or 0).
4404 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)4405 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
4406 {
4407 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4408 }
4409
4410 /**
4411 * @brief Clear the system break interrupt flag (SBIF).
4412 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4413 * @param TIMx Timer instance
4414 * @retval None
4415 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)4416 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4417 {
4418 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4419 }
4420
4421 /**
4422 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4423 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4424 * @param TIMx Timer instance
4425 * @retval State of bit (1 or 0).
4426 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)4427 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
4428 {
4429 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4430 }
4431
4432 /**
4433 * @}
4434 */
4435
4436 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4437 * @{
4438 */
4439 /**
4440 * @brief Enable update interrupt (UIE).
4441 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4442 * @param TIMx Timer instance
4443 * @retval None
4444 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)4445 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4446 {
4447 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4448 }
4449
4450 /**
4451 * @brief Disable update interrupt (UIE).
4452 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4453 * @param TIMx Timer instance
4454 * @retval None
4455 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)4456 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4457 {
4458 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4459 }
4460
4461 /**
4462 * @brief Indicates whether the update interrupt (UIE) is enabled.
4463 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4464 * @param TIMx Timer instance
4465 * @retval State of bit (1 or 0).
4466 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)4467 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
4468 {
4469 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4470 }
4471
4472 /**
4473 * @brief Enable capture/compare 1 interrupt (CC1IE).
4474 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4475 * @param TIMx Timer instance
4476 * @retval None
4477 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4478 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4479 {
4480 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4481 }
4482
4483 /**
4484 * @brief Disable capture/compare 1 interrupt (CC1IE).
4485 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4486 * @param TIMx Timer instance
4487 * @retval None
4488 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4489 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4490 {
4491 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4492 }
4493
4494 /**
4495 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4496 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4497 * @param TIMx Timer instance
4498 * @retval State of bit (1 or 0).
4499 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)4500 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
4501 {
4502 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4503 }
4504
4505 /**
4506 * @brief Enable capture/compare 2 interrupt (CC2IE).
4507 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4508 * @param TIMx Timer instance
4509 * @retval None
4510 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4511 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4512 {
4513 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4514 }
4515
4516 /**
4517 * @brief Disable capture/compare 2 interrupt (CC2IE).
4518 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4519 * @param TIMx Timer instance
4520 * @retval None
4521 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4522 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4523 {
4524 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4525 }
4526
4527 /**
4528 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4529 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4530 * @param TIMx Timer instance
4531 * @retval State of bit (1 or 0).
4532 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)4533 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
4534 {
4535 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4536 }
4537
4538 /**
4539 * @brief Enable capture/compare 3 interrupt (CC3IE).
4540 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4541 * @param TIMx Timer instance
4542 * @retval None
4543 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4544 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4545 {
4546 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4547 }
4548
4549 /**
4550 * @brief Disable capture/compare 3 interrupt (CC3IE).
4551 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4552 * @param TIMx Timer instance
4553 * @retval None
4554 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4555 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4556 {
4557 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4558 }
4559
4560 /**
4561 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4562 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4563 * @param TIMx Timer instance
4564 * @retval State of bit (1 or 0).
4565 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)4566 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
4567 {
4568 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4569 }
4570
4571 /**
4572 * @brief Enable capture/compare 4 interrupt (CC4IE).
4573 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4574 * @param TIMx Timer instance
4575 * @retval None
4576 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4577 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4578 {
4579 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4580 }
4581
4582 /**
4583 * @brief Disable capture/compare 4 interrupt (CC4IE).
4584 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4585 * @param TIMx Timer instance
4586 * @retval None
4587 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4588 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4589 {
4590 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4591 }
4592
4593 /**
4594 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4595 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4596 * @param TIMx Timer instance
4597 * @retval State of bit (1 or 0).
4598 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)4599 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
4600 {
4601 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4602 }
4603
4604 /**
4605 * @brief Enable commutation interrupt (COMIE).
4606 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4607 * @param TIMx Timer instance
4608 * @retval None
4609 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4610 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4611 {
4612 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4613 }
4614
4615 /**
4616 * @brief Disable commutation interrupt (COMIE).
4617 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4618 * @param TIMx Timer instance
4619 * @retval None
4620 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4621 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4622 {
4623 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4624 }
4625
4626 /**
4627 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4628 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4629 * @param TIMx Timer instance
4630 * @retval State of bit (1 or 0).
4631 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)4632 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
4633 {
4634 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4635 }
4636
4637 /**
4638 * @brief Enable trigger interrupt (TIE).
4639 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4640 * @param TIMx Timer instance
4641 * @retval None
4642 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4643 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4644 {
4645 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4646 }
4647
4648 /**
4649 * @brief Disable trigger interrupt (TIE).
4650 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4651 * @param TIMx Timer instance
4652 * @retval None
4653 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4654 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4655 {
4656 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4657 }
4658
4659 /**
4660 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4661 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4662 * @param TIMx Timer instance
4663 * @retval State of bit (1 or 0).
4664 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)4665 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
4666 {
4667 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4668 }
4669
4670 /**
4671 * @brief Enable break interrupt (BIE).
4672 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4673 * @param TIMx Timer instance
4674 * @retval None
4675 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4676 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4677 {
4678 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4679 }
4680
4681 /**
4682 * @brief Disable break interrupt (BIE).
4683 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4684 * @param TIMx Timer instance
4685 * @retval None
4686 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4687 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4688 {
4689 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4690 }
4691
4692 /**
4693 * @brief Indicates whether the break interrupt (BIE) is enabled.
4694 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4695 * @param TIMx Timer instance
4696 * @retval State of bit (1 or 0).
4697 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)4698 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
4699 {
4700 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4701 }
4702
4703 /**
4704 * @}
4705 */
4706
4707 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
4708 * @{
4709 */
4710 /**
4711 * @brief Enable update DMA request (UDE).
4712 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4713 * @param TIMx Timer instance
4714 * @retval None
4715 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4716 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4717 {
4718 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4719 }
4720
4721 /**
4722 * @brief Disable update DMA request (UDE).
4723 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4724 * @param TIMx Timer instance
4725 * @retval None
4726 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4727 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4728 {
4729 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4730 }
4731
4732 /**
4733 * @brief Indicates whether the update DMA request (UDE) is enabled.
4734 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4735 * @param TIMx Timer instance
4736 * @retval State of bit (1 or 0).
4737 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)4738 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
4739 {
4740 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4741 }
4742
4743 /**
4744 * @brief Enable capture/compare 1 DMA request (CC1DE).
4745 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4746 * @param TIMx Timer instance
4747 * @retval None
4748 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4749 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4750 {
4751 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4752 }
4753
4754 /**
4755 * @brief Disable capture/compare 1 DMA request (CC1DE).
4756 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4757 * @param TIMx Timer instance
4758 * @retval None
4759 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4760 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4761 {
4762 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4763 }
4764
4765 /**
4766 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4767 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4768 * @param TIMx Timer instance
4769 * @retval State of bit (1 or 0).
4770 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)4771 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
4772 {
4773 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4774 }
4775
4776 /**
4777 * @brief Enable capture/compare 2 DMA request (CC2DE).
4778 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4779 * @param TIMx Timer instance
4780 * @retval None
4781 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4782 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4783 {
4784 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4785 }
4786
4787 /**
4788 * @brief Disable capture/compare 2 DMA request (CC2DE).
4789 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4790 * @param TIMx Timer instance
4791 * @retval None
4792 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4793 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4794 {
4795 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4796 }
4797
4798 /**
4799 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4800 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4801 * @param TIMx Timer instance
4802 * @retval State of bit (1 or 0).
4803 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)4804 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
4805 {
4806 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4807 }
4808
4809 /**
4810 * @brief Enable capture/compare 3 DMA request (CC3DE).
4811 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4812 * @param TIMx Timer instance
4813 * @retval None
4814 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4815 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4816 {
4817 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4818 }
4819
4820 /**
4821 * @brief Disable capture/compare 3 DMA request (CC3DE).
4822 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4823 * @param TIMx Timer instance
4824 * @retval None
4825 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)4826 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4827 {
4828 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4829 }
4830
4831 /**
4832 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4833 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4834 * @param TIMx Timer instance
4835 * @retval State of bit (1 or 0).
4836 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)4837 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
4838 {
4839 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4840 }
4841
4842 /**
4843 * @brief Enable capture/compare 4 DMA request (CC4DE).
4844 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4845 * @param TIMx Timer instance
4846 * @retval None
4847 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)4848 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4849 {
4850 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4851 }
4852
4853 /**
4854 * @brief Disable capture/compare 4 DMA request (CC4DE).
4855 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4856 * @param TIMx Timer instance
4857 * @retval None
4858 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)4859 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4860 {
4861 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4862 }
4863
4864 /**
4865 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4866 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4867 * @param TIMx Timer instance
4868 * @retval State of bit (1 or 0).
4869 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)4870 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
4871 {
4872 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4873 }
4874
4875 /**
4876 * @brief Enable commutation DMA request (COMDE).
4877 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4878 * @param TIMx Timer instance
4879 * @retval None
4880 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)4881 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4882 {
4883 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4884 }
4885
4886 /**
4887 * @brief Disable commutation DMA request (COMDE).
4888 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4889 * @param TIMx Timer instance
4890 * @retval None
4891 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)4892 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4893 {
4894 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4895 }
4896
4897 /**
4898 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4899 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4900 * @param TIMx Timer instance
4901 * @retval State of bit (1 or 0).
4902 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)4903 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
4904 {
4905 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4906 }
4907
4908 /**
4909 * @brief Enable trigger interrupt (TDE).
4910 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4911 * @param TIMx Timer instance
4912 * @retval None
4913 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)4914 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4915 {
4916 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4917 }
4918
4919 /**
4920 * @brief Disable trigger interrupt (TDE).
4921 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4922 * @param TIMx Timer instance
4923 * @retval None
4924 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)4925 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4926 {
4927 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4928 }
4929
4930 /**
4931 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4932 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4933 * @param TIMx Timer instance
4934 * @retval State of bit (1 or 0).
4935 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)4936 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
4937 {
4938 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4939 }
4940
4941 /**
4942 * @}
4943 */
4944
4945 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4946 * @{
4947 */
4948 /**
4949 * @brief Generate an update event.
4950 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4951 * @param TIMx Timer instance
4952 * @retval None
4953 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)4954 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4955 {
4956 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4957 }
4958
4959 /**
4960 * @brief Generate Capture/Compare 1 event.
4961 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4962 * @param TIMx Timer instance
4963 * @retval None
4964 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)4965 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4966 {
4967 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4968 }
4969
4970 /**
4971 * @brief Generate Capture/Compare 2 event.
4972 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4973 * @param TIMx Timer instance
4974 * @retval None
4975 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)4976 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4977 {
4978 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4979 }
4980
4981 /**
4982 * @brief Generate Capture/Compare 3 event.
4983 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4984 * @param TIMx Timer instance
4985 * @retval None
4986 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4987 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4988 {
4989 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4990 }
4991
4992 /**
4993 * @brief Generate Capture/Compare 4 event.
4994 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4995 * @param TIMx Timer instance
4996 * @retval None
4997 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4998 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4999 {
5000 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
5001 }
5002
5003 /**
5004 * @brief Generate commutation event.
5005 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
5006 * @param TIMx Timer instance
5007 * @retval None
5008 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)5009 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
5010 {
5011 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
5012 }
5013
5014 /**
5015 * @brief Generate trigger event.
5016 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
5017 * @param TIMx Timer instance
5018 * @retval None
5019 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)5020 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
5021 {
5022 SET_BIT(TIMx->EGR, TIM_EGR_TG);
5023 }
5024
5025 /**
5026 * @brief Generate break event.
5027 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
5028 * @param TIMx Timer instance
5029 * @retval None
5030 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)5031 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
5032 {
5033 SET_BIT(TIMx->EGR, TIM_EGR_BG);
5034 }
5035
5036 /**
5037 * @brief Generate break 2 event.
5038 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
5039 * @param TIMx Timer instance
5040 * @retval None
5041 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)5042 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
5043 {
5044 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
5045 }
5046
5047 /**
5048 * @}
5049 */
5050
5051 #if defined(USE_FULL_LL_DRIVER)
5052 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
5053 * @{
5054 */
5055
5056 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
5057 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
5058 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
5059 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
5060 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
5061 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
5062 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
5063 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5064 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5065 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5066 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5067 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5068 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5069 /**
5070 * @}
5071 */
5072 #endif /* USE_FULL_LL_DRIVER */
5073
5074 /**
5075 * @}
5076 */
5077
5078 /**
5079 * @}
5080 */
5081
5082 #endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
5083
5084 /**
5085 * @}
5086 */
5087
5088 #ifdef __cplusplus
5089 }
5090 #endif
5091
5092 #endif /* __STM32L4xx_LL_TIM_H */
5093
