1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 *
7 ******************************************************************************
8 * @attention
9 *
10 * Copyright (c) 2017 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file
14 * in the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 @verbatim
19 ==============================================================================
20 ##### How to use this driver #####
21 ==============================================================================
22 [..]
23 The LL SYSTEM driver contains a set of generic APIs that can be
24 used by user:
25 (+) Some of the FLASH features need to be handled in the SYSTEM file.
26 (+) Access to DBGCMU registers
27 (+) Access to SYSCFG registers
28 (+) Access to VREFBUF registers
29
30 @endverbatim
31 ******************************************************************************
32 */
33
34 /* Define to prevent recursive inclusion -------------------------------------*/
35 #ifndef STM32L4xx_LL_SYSTEM_H
36 #define STM32L4xx_LL_SYSTEM_H
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 /* Includes ------------------------------------------------------------------*/
43 #include "stm32l4xx.h"
44
45 /** @addtogroup STM32L4xx_LL_Driver
46 * @{
47 */
48
49 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
50
51 /** @defgroup SYSTEM_LL SYSTEM
52 * @{
53 */
54
55 /* Private types -------------------------------------------------------------*/
56 /* Private variables ---------------------------------------------------------*/
57
58 /* Private constants ---------------------------------------------------------*/
59 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
60 * @{
61 */
62
63 /**
64 * @brief Power-down in Run mode Flash key
65 */
66 #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */
67 #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1
68 to unlock the RUN_PD bit in FLASH_ACR */
69
70 /**
71 * @}
72 */
73
74 /* Private macros ------------------------------------------------------------*/
75
76 /* Exported types ------------------------------------------------------------*/
77 /* Exported constants --------------------------------------------------------*/
78 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
79 * @{
80 */
81
82 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
83 * @{
84 */
85 #define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */
86 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
87 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */
88 #if defined(FMC_Bank1_R)
89 #define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */
90 #endif /* FMC_Bank1_R */
91 #define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000 */
92 /**
93 * @}
94 */
95
96 #if defined(SYSCFG_MEMRMP_FB_MODE)
97 /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
98 * @{
99 */
100 #define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000)
101 and Flash Bank2 mapped at 0x08080000 (and aliased at 0x00080000) */
102 #define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
103 and Flash Bank1 mapped at 0x08080000 (and aliased at 0x00080000) */
104 /**
105 * @}
106 */
107
108 #endif /* SYSCFG_MEMRMP_FB_MODE */
109 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
110 * @{
111 */
112 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
113 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
114 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
115 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
116 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
117 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
118 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
119 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
120 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
121 #if defined(I2C2)
122 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
123 #endif /* I2C2 */
124 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
125 #if defined(I2C4)
126 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
127 #endif /* I2C4 */
128 /**
129 * @}
130 */
131
132 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
133 * @{
134 */
135 #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
136 #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
137 #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
138 #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
139 #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
140 #if defined(GPIOF)
141 #define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */
142 #endif /* GPIOF */
143 #if defined(GPIOG)
144 #define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */
145 #endif /* GPIOG */
146 #define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */
147 #if defined(GPIOI)
148 #define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */
149 #endif /* GPIOI */
150 /**
151 * @}
152 */
153
154 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
155 * @{
156 */
157 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */
158 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */
159 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */
160 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */
161 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */
162 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */
163 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */
164 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */
165 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */
166 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */
167 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */
168 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */
169 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */
170 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */
171 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */
172 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */
173 /**
174 * @}
175 */
176
177 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
178 * @{
179 */
180 #define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
181 with Break Input of TIM1/8/15/16/17 */
182 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
183 with TIM1/8/15/16/17 Break Input
184 and also the PVDE and PLS bits of the Power Control Interface */
185 #define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal
186 with Break Input of TIM1/8/15/16/17 */
187 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4
188 with Break Input of TIM1/15/16/17 */
189 /**
190 * @}
191 */
192
193 /** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRP
194 * @{
195 */
196 #define LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */
197 #define LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */
198 #define LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */
199 #define LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */
200 #define LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */
201 #define LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */
202 #define LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */
203 #define LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */
204 #define LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */
205 #define LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */
206 #define LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */
207 #define LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */
208 #define LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */
209 #define LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
210 #define LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
211 #define LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
212 #if defined(SYSCFG_SWPR_PAGE31)
213 #define LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
214 #define LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
215 #define LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
216 #define LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */
217 #define LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */
218 #define LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */
219 #define LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */
220 #define LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */
221 #define LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */
222 #define LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */
223 #define LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */
224 #define LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */
225 #define LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */
226 #define LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
227 #define LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
228 #define LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
229 #endif /* SYSCFG_SWPR_PAGE31 */
230 #if defined(SYSCFG_SWPR2_PAGE63)
231 #define LL_SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */
232 #define LL_SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */
233 #define LL_SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */
234 #define LL_SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */
235 #define LL_SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */
236 #define LL_SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */
237 #define LL_SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */
238 #define LL_SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */
239 #define LL_SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */
240 #define LL_SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */
241 #define LL_SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */
242 #define LL_SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */
243 #define LL_SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */
244 #define LL_SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */
245 #define LL_SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */
246 #define LL_SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */
247 #define LL_SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */
248 #define LL_SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */
249 #define LL_SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */
250 #define LL_SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */
251 #define LL_SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */
252 #define LL_SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */
253 #define LL_SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */
254 #define LL_SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */
255 #define LL_SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */
256 #define LL_SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */
257 #define LL_SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */
258 #define LL_SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */
259 #define LL_SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */
260 #define LL_SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */
261 #define LL_SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */
262 #define LL_SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */
263 #endif /* SYSCFG_SWPR2_PAGE63 */
264 /**
265 * @}
266 */
267
268 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
269 * @{
270 */
271 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
272 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
273 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
274 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
275 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
276 /**
277 * @}
278 */
279
280 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
281 * @{
282 */
283 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/
284 #if defined(TIM3)
285 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/
286 #endif /* TIM3 */
287 #if defined(TIM4)
288 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/
289 #endif /* TIM4 */
290 #if defined(TIM5)
291 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/
292 #endif /* TIM5 */
293 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/
294 #if defined(TIM7)
295 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/
296 #endif /* TIM7 */
297 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted*/
298 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/
299 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/
300 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/
301 #if defined(I2C2)
302 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/
303 #endif /* I2C2 */
304 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen*/
305 #define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP /*!< The bxCAN receive registers are frozen*/
306 #if defined(CAN2)
307 #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1FZR1_DBG_CAN2_STOP /*!< The bxCAN2 receive registers are frozen*/
308 #endif /* CAN2 */
309 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
310 /**
311 * @}
312 */
313
314 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
315 * @{
316 */
317 #if defined(I2C4)
318 #define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/
319 #endif /* I2C4 */
320 #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
321 /**
322 * @}
323 */
324
325 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
326 * @{
327 */
328 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/
329 #if defined(TIM8)
330 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/
331 #endif /* TIM8 */
332 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/
333 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/
334 #if defined(TIM17)
335 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/
336 #endif /* TIM17 */
337 /**
338 * @}
339 */
340
341 #if defined(VREFBUF)
342 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
343 * @{
344 */
345 #define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
346 #define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */
347 /**
348 * @}
349 */
350 #endif /* VREFBUF */
351
352 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
353 * @{
354 */
355 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
356 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
357 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
358 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
359 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
360 #if defined(FLASH_ACR_LATENCY_5WS)
361 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
362 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
363 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */
364 #define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */
365 #define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */
366 #define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */
367 #define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
368 #define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
369 #define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
370 #define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
371 #define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
372 #endif
373 /**
374 * @}
375 */
376
377 /**
378 * @}
379 */
380
381 /* Exported macro ------------------------------------------------------------*/
382
383 /* Exported functions --------------------------------------------------------*/
384 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
385 * @{
386 */
387
388 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
389 * @{
390 */
391
392 /**
393 * @brief Set memory mapping at address 0x00000000
394 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
395 * @param Memory This parameter can be one of the following values:
396 * @arg @ref LL_SYSCFG_REMAP_FLASH
397 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
398 * @arg @ref LL_SYSCFG_REMAP_SRAM
399 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
400 * @arg @ref LL_SYSCFG_REMAP_QUADSPI
401 *
402 * (*) value not defined in all devices
403 * @retval None
404 */
LL_SYSCFG_SetRemapMemory(uint32_t Memory)405 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
406 {
407 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
408 }
409
410 /**
411 * @brief Get memory mapping at address 0x00000000
412 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
413 * @retval Returned value can be one of the following values:
414 * @arg @ref LL_SYSCFG_REMAP_FLASH
415 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
416 * @arg @ref LL_SYSCFG_REMAP_SRAM
417 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
418 * @arg @ref LL_SYSCFG_REMAP_QUADSPI
419 *
420 * (*) value not defined in all devices
421 */
LL_SYSCFG_GetRemapMemory(void)422 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
423 {
424 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
425 }
426
427 #if defined(SYSCFG_MEMRMP_FB_MODE)
428 /**
429 * @brief Select Flash bank mode (Bank flashed at 0x08000000)
430 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode
431 * @param Bank This parameter can be one of the following values:
432 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
433 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
434 * @retval None
435 */
LL_SYSCFG_SetFlashBankMode(uint32_t Bank)436 __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
437 {
438 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);
439 }
440
441 /**
442 * @brief Get Flash bank mode (Bank flashed at 0x08000000)
443 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode
444 * @retval Returned value can be one of the following values:
445 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
446 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
447 */
LL_SYSCFG_GetFlashBankMode(void)448 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
449 {
450 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));
451 }
452 #endif /* SYSCFG_MEMRMP_FB_MODE */
453
454 /**
455 * @brief Firewall protection enabled
456 * @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_EnableFirewall
457 * @retval None
458 */
LL_SYSCFG_EnableFirewall(void)459 __STATIC_INLINE void LL_SYSCFG_EnableFirewall(void)
460 {
461 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS);
462 }
463
464 /**
465 * @brief Check if Firewall protection is enabled or not
466 * @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_IsEnabledFirewall
467 * @retval State of bit (1 or 0).
468 */
LL_SYSCFG_IsEnabledFirewall(void)469 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void)
470 {
471 return !(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS) == SYSCFG_CFGR1_FWDIS);
472 }
473
474 /**
475 * @brief Enable I/O analog switch voltage booster.
476 * @note When voltage booster is enabled, I/O analog switches are supplied
477 * by a dedicated voltage booster, from VDD power domain. This is
478 * the recommended configuration with low VDDA voltage operation.
479 * @note The I/O analog switch voltage booster is relevant for peripherals
480 * using I/O in analog input: ADC, COMP, OPAMP.
481 * However, COMP and OPAMP inputs have a high impedance and
482 * voltage booster do not impact performance significantly.
483 * Therefore, the voltage booster is mainly intended for
484 * usage with ADC.
485 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
486 * @retval None
487 */
LL_SYSCFG_EnableAnalogBooster(void)488 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
489 {
490 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
491 }
492
493 /**
494 * @brief Disable I/O analog switch voltage booster.
495 * @note When voltage booster is enabled, I/O analog switches are supplied
496 * by a dedicated voltage booster, from VDD power domain. This is
497 * the recommended configuration with low VDDA voltage operation.
498 * @note The I/O analog switch voltage booster is relevant for peripherals
499 * using I/O in analog input: ADC, COMP, OPAMP.
500 * However, COMP and OPAMP inputs have a high impedance and
501 * voltage booster do not impact performance significantly.
502 * Therefore, the voltage booster is mainly intended for
503 * usage with ADC.
504 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
505 * @retval None
506 */
LL_SYSCFG_DisableAnalogBooster(void)507 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
508 {
509 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
510 }
511
512 /**
513 * @brief Enable the I2C fast mode plus driving capability.
514 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
515 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
516 * @param ConfigFastModePlus This parameter can be a combination of the following values:
517 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
518 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
519 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
520 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
521 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
522 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
523 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
524 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
525 *
526 * (*) value not defined in all devices
527 * @retval None
528 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)529 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
530 {
531 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
532 }
533
534 /**
535 * @brief Disable the I2C fast mode plus driving capability.
536 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
537 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
538 * @param ConfigFastModePlus This parameter can be a combination of the following values:
539 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
540 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
541 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
542 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
543 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
544 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
545 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
546 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
547 *
548 * (*) value not defined in all devices
549 * @retval None
550 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)551 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
552 {
553 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
554 }
555
556 /**
557 * @brief Enable Floating Point Unit Invalid operation Interrupt
558 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
559 * @retval None
560 */
LL_SYSCFG_EnableIT_FPU_IOC(void)561 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
562 {
563 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
564 }
565
566 /**
567 * @brief Enable Floating Point Unit Divide-by-zero Interrupt
568 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
569 * @retval None
570 */
LL_SYSCFG_EnableIT_FPU_DZC(void)571 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
572 {
573 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
574 }
575
576 /**
577 * @brief Enable Floating Point Unit Underflow Interrupt
578 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
579 * @retval None
580 */
LL_SYSCFG_EnableIT_FPU_UFC(void)581 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
582 {
583 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
584 }
585
586 /**
587 * @brief Enable Floating Point Unit Overflow Interrupt
588 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
589 * @retval None
590 */
LL_SYSCFG_EnableIT_FPU_OFC(void)591 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
592 {
593 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
594 }
595
596 /**
597 * @brief Enable Floating Point Unit Input denormal Interrupt
598 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
599 * @retval None
600 */
LL_SYSCFG_EnableIT_FPU_IDC(void)601 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
602 {
603 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
604 }
605
606 /**
607 * @brief Enable Floating Point Unit Inexact Interrupt
608 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
609 * @retval None
610 */
LL_SYSCFG_EnableIT_FPU_IXC(void)611 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
612 {
613 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
614 }
615
616 /**
617 * @brief Disable Floating Point Unit Invalid operation Interrupt
618 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
619 * @retval None
620 */
LL_SYSCFG_DisableIT_FPU_IOC(void)621 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
622 {
623 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
624 }
625
626 /**
627 * @brief Disable Floating Point Unit Divide-by-zero Interrupt
628 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
629 * @retval None
630 */
LL_SYSCFG_DisableIT_FPU_DZC(void)631 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
632 {
633 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
634 }
635
636 /**
637 * @brief Disable Floating Point Unit Underflow Interrupt
638 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
639 * @retval None
640 */
LL_SYSCFG_DisableIT_FPU_UFC(void)641 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
642 {
643 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
644 }
645
646 /**
647 * @brief Disable Floating Point Unit Overflow Interrupt
648 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
649 * @retval None
650 */
LL_SYSCFG_DisableIT_FPU_OFC(void)651 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
652 {
653 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
654 }
655
656 /**
657 * @brief Disable Floating Point Unit Input denormal Interrupt
658 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
659 * @retval None
660 */
LL_SYSCFG_DisableIT_FPU_IDC(void)661 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
662 {
663 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
664 }
665
666 /**
667 * @brief Disable Floating Point Unit Inexact Interrupt
668 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
669 * @retval None
670 */
LL_SYSCFG_DisableIT_FPU_IXC(void)671 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
672 {
673 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
674 }
675
676 /**
677 * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
678 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
679 * @retval State of bit (1 or 0).
680 */
LL_SYSCFG_IsEnabledIT_FPU_IOC(void)681 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
682 {
683 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
684 }
685
686 /**
687 * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
688 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
689 * @retval State of bit (1 or 0).
690 */
LL_SYSCFG_IsEnabledIT_FPU_DZC(void)691 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
692 {
693 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
694 }
695
696 /**
697 * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
698 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
699 * @retval State of bit (1 or 0).
700 */
LL_SYSCFG_IsEnabledIT_FPU_UFC(void)701 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
702 {
703 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
704 }
705
706 /**
707 * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
708 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
709 * @retval State of bit (1 or 0).
710 */
LL_SYSCFG_IsEnabledIT_FPU_OFC(void)711 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
712 {
713 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
714 }
715
716 /**
717 * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
718 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
719 * @retval State of bit (1 or 0).
720 */
LL_SYSCFG_IsEnabledIT_FPU_IDC(void)721 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
722 {
723 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
724 }
725
726 /**
727 * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
728 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
729 * @retval State of bit (1 or 0).
730 */
LL_SYSCFG_IsEnabledIT_FPU_IXC(void)731 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
732 {
733 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
734 }
735
736 /**
737 * @brief Configure source input for the EXTI external interrupt.
738 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
739 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
740 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
741 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
742 * @param Port This parameter can be one of the following values:
743 * @arg @ref LL_SYSCFG_EXTI_PORTA
744 * @arg @ref LL_SYSCFG_EXTI_PORTB
745 * @arg @ref LL_SYSCFG_EXTI_PORTC
746 * @arg @ref LL_SYSCFG_EXTI_PORTD
747 * @arg @ref LL_SYSCFG_EXTI_PORTE
748 * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
749 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
750 * @arg @ref LL_SYSCFG_EXTI_PORTH
751 * @arg @ref LL_SYSCFG_EXTI_PORTI (*)
752 *
753 * (*) value not defined in all devices
754 * @param Line This parameter can be one of the following values:
755 * @arg @ref LL_SYSCFG_EXTI_LINE0
756 * @arg @ref LL_SYSCFG_EXTI_LINE1
757 * @arg @ref LL_SYSCFG_EXTI_LINE2
758 * @arg @ref LL_SYSCFG_EXTI_LINE3
759 * @arg @ref LL_SYSCFG_EXTI_LINE4
760 * @arg @ref LL_SYSCFG_EXTI_LINE5
761 * @arg @ref LL_SYSCFG_EXTI_LINE6
762 * @arg @ref LL_SYSCFG_EXTI_LINE7
763 * @arg @ref LL_SYSCFG_EXTI_LINE8
764 * @arg @ref LL_SYSCFG_EXTI_LINE9
765 * @arg @ref LL_SYSCFG_EXTI_LINE10
766 * @arg @ref LL_SYSCFG_EXTI_LINE11
767 * @arg @ref LL_SYSCFG_EXTI_LINE12
768 * @arg @ref LL_SYSCFG_EXTI_LINE13
769 * @arg @ref LL_SYSCFG_EXTI_LINE14
770 * @arg @ref LL_SYSCFG_EXTI_LINE15
771 * @retval None
772 */
LL_SYSCFG_SetEXTISource(uint32_t Port,uint32_t Line)773 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
774 {
775 MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
776 }
777
778 /**
779 * @brief Get the configured defined for specific EXTI Line
780 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
781 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
782 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
783 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
784 * @param Line This parameter can be one of the following values:
785 * @arg @ref LL_SYSCFG_EXTI_LINE0
786 * @arg @ref LL_SYSCFG_EXTI_LINE1
787 * @arg @ref LL_SYSCFG_EXTI_LINE2
788 * @arg @ref LL_SYSCFG_EXTI_LINE3
789 * @arg @ref LL_SYSCFG_EXTI_LINE4
790 * @arg @ref LL_SYSCFG_EXTI_LINE5
791 * @arg @ref LL_SYSCFG_EXTI_LINE6
792 * @arg @ref LL_SYSCFG_EXTI_LINE7
793 * @arg @ref LL_SYSCFG_EXTI_LINE8
794 * @arg @ref LL_SYSCFG_EXTI_LINE9
795 * @arg @ref LL_SYSCFG_EXTI_LINE10
796 * @arg @ref LL_SYSCFG_EXTI_LINE11
797 * @arg @ref LL_SYSCFG_EXTI_LINE12
798 * @arg @ref LL_SYSCFG_EXTI_LINE13
799 * @arg @ref LL_SYSCFG_EXTI_LINE14
800 * @arg @ref LL_SYSCFG_EXTI_LINE15
801 * @retval Returned value can be one of the following values:
802 * @arg @ref LL_SYSCFG_EXTI_PORTA
803 * @arg @ref LL_SYSCFG_EXTI_PORTB
804 * @arg @ref LL_SYSCFG_EXTI_PORTC
805 * @arg @ref LL_SYSCFG_EXTI_PORTD
806 * @arg @ref LL_SYSCFG_EXTI_PORTE
807 * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
808 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
809 * @arg @ref LL_SYSCFG_EXTI_PORTH
810 * @arg @ref LL_SYSCFG_EXTI_PORTI (*)
811 *
812 * (*) value not defined in all devices
813 */
LL_SYSCFG_GetEXTISource(uint32_t Line)814 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
815 {
816 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
817 }
818
819 /**
820 * @brief Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is
821 * automatically cleared at the end of the SRAM2 erase operation.)
822 * @note This bit is write-protected: setting this bit is possible only after the
823 * correct key sequence is written in the SYSCFG_SKR register as described in
824 * the Reference Manual.
825 * @rmtoll SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase
826 * @retval None
827 */
LL_SYSCFG_EnableSRAM2Erase(void)828 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void)
829 {
830 /* Starts a hardware SRAM2 erase operation*/
831 SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER);
832 }
833
834 /**
835 * @brief Check if SRAM2 erase operation is on going
836 * @rmtoll SYSCFG_SCSR SRAM2BSY LL_SYSCFG_IsSRAM2EraseOngoing
837 * @retval State of bit (1 or 0).
838 */
LL_SYSCFG_IsSRAM2EraseOngoing(void)839 __STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void)
840 {
841 return (READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY));
842 }
843
844 /**
845 * @brief Set connections to TIM1/8/15/16/17 Break inputs
846 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
847 * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
848 * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
849 * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
850 * @param Break This parameter can be a combination of the following values:
851 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
852 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
853 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
854 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
855 * @retval None
856 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)857 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
858 {
859 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
860 }
861
862 /**
863 * @brief Get connections to TIM1/8/15/16/17 Break inputs
864 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
865 * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
866 * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
867 * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
868 * @retval Returned value can be can be a combination of the following values:
869 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
870 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
871 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
872 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
873 */
LL_SYSCFG_GetTIMBreakInputs(void)874 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
875 {
876 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
877 }
878
879 /**
880 * @brief Check if SRAM2 parity error detected
881 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
882 * @retval State of bit (1 or 0).
883 */
LL_SYSCFG_IsActiveFlag_SP(void)884 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
885 {
886 return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF));
887 }
888
889 /**
890 * @brief Clear SRAM2 parity error flag
891 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
892 * @retval None
893 */
LL_SYSCFG_ClearFlag_SP(void)894 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
895 {
896 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
897 }
898
899 /**
900 * @brief Enable SRAM2 page write protection for Pages in range 0 to 31
901 * @note Write protection is cleared only by a system reset
902 * @rmtoll SYSCFG_SWPR PxWP LL_SYSCFG_EnableSRAM2PageWRP_0_31
903 * @param SRAM2WRP This parameter can be a combination of the following values:
904 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0
905 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1
906 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2
907 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3
908 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4
909 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5
910 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6
911 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7
912 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8
913 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9
914 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10
915 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11
916 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12
917 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13
918 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14
919 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15
920 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16 (*)
921 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17 (*)
922 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18 (*)
923 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19 (*)
924 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20 (*)
925 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21 (*)
926 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22 (*)
927 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23 (*)
928 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24 (*)
929 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25 (*)
930 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26 (*)
931 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27 (*)
932 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28 (*)
933 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29 (*)
934 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30 (*)
935 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31 (*)
936 *
937 * (*) value not defined in all devices
938 * @retval None
939 */
940 /* Legacy define */
941 #define LL_SYSCFG_EnableSRAM2PageWRP LL_SYSCFG_EnableSRAM2PageWRP_0_31
LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)942 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)
943 {
944 SET_BIT(SYSCFG->SWPR, SRAM2WRP);
945 }
946
947 #if defined(SYSCFG_SWPR2_PAGE63)
948 /**
949 * @brief Enable SRAM2 page write protection for Pages in range 32 to 63
950 * @note Write protection is cleared only by a system reset
951 * @rmtoll SYSCFG_SWPR2 PxWP LL_SYSCFG_EnableSRAM2PageWRP_32_63
952 * @param SRAM2WRP This parameter can be a combination of the following values:
953 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE32 (*)
954 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE33 (*)
955 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE34 (*)
956 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE35 (*)
957 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE36 (*)
958 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE37 (*)
959 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE38 (*)
960 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE39 (*)
961 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE40 (*)
962 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE41 (*)
963 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE42 (*)
964 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE43 (*)
965 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE44 (*)
966 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE45 (*)
967 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE46 (*)
968 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE47 (*)
969 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE48 (*)
970 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE49 (*)
971 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE50 (*)
972 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE51 (*)
973 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE52 (*)
974 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE53 (*)
975 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE54 (*)
976 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE55 (*)
977 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE56 (*)
978 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE57 (*)
979 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE58 (*)
980 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE59 (*)
981 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE60 (*)
982 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE61 (*)
983 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE62 (*)
984 * @arg @ref LL_SYSCFG_SRAM2WRP_PAGE63 (*)
985 *
986 * (*) value not defined in all devices
987 * @retval None
988 */
LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)989 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)
990 {
991 SET_BIT(SYSCFG->SWPR2, SRAM2WRP);
992 }
993 #endif /* SYSCFG_SWPR2_PAGE63 */
994
995 /**
996 * @brief SRAM2 page write protection lock prior to erase
997 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP
998 * @retval None
999 */
LL_SYSCFG_LockSRAM2WRP(void)1000 __STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void)
1001 {
1002 /* Writing a wrong key reactivates the write protection */
1003 WRITE_REG(SYSCFG->SKR, 0x00);
1004 }
1005
1006 /**
1007 * @brief SRAM2 page write protection unlock prior to erase
1008 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP
1009 * @retval None
1010 */
LL_SYSCFG_UnlockSRAM2WRP(void)1011 __STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void)
1012 {
1013 /* unlock the write protection of the SRAM2ER bit */
1014 WRITE_REG(SYSCFG->SKR, 0xCA);
1015 WRITE_REG(SYSCFG->SKR, 0x53);
1016 }
1017
1018 /**
1019 * @}
1020 */
1021
1022
1023 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1024 * @{
1025 */
1026
1027 /**
1028 * @brief Return the device identifier
1029 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1030 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
1031 */
LL_DBGMCU_GetDeviceID(void)1032 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1033 {
1034 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1035 }
1036
1037 /**
1038 * @brief Return the device revision identifier
1039 * @note This field indicates the revision of the device.
1040 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1041 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1042 */
LL_DBGMCU_GetRevisionID(void)1043 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1044 {
1045 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1046 }
1047
1048 /**
1049 * @brief Enable the Debug Module during SLEEP mode
1050 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
1051 * @retval None
1052 */
LL_DBGMCU_EnableDBGSleepMode(void)1053 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
1054 {
1055 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1056 }
1057
1058 /**
1059 * @brief Disable the Debug Module during SLEEP mode
1060 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
1061 * @retval None
1062 */
LL_DBGMCU_DisableDBGSleepMode(void)1063 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
1064 {
1065 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1066 }
1067
1068 /**
1069 * @brief Enable the Debug Module during STOP mode
1070 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
1071 * @retval None
1072 */
LL_DBGMCU_EnableDBGStopMode(void)1073 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1074 {
1075 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1076 }
1077
1078 /**
1079 * @brief Disable the Debug Module during STOP mode
1080 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
1081 * @retval None
1082 */
LL_DBGMCU_DisableDBGStopMode(void)1083 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1084 {
1085 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1086 }
1087
1088 /**
1089 * @brief Enable the Debug Module during STANDBY mode
1090 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
1091 * @retval None
1092 */
LL_DBGMCU_EnableDBGStandbyMode(void)1093 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1094 {
1095 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1096 }
1097
1098 /**
1099 * @brief Disable the Debug Module during STANDBY mode
1100 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
1101 * @retval None
1102 */
LL_DBGMCU_DisableDBGStandbyMode(void)1103 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1104 {
1105 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1106 }
1107
1108 /**
1109 * @brief Set Trace pin assignment control
1110 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
1111 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
1112 * @param PinAssignment This parameter can be one of the following values:
1113 * @arg @ref LL_DBGMCU_TRACE_NONE
1114 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1115 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1116 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1117 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1118 * @retval None
1119 */
LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)1120 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
1121 {
1122 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
1123 }
1124
1125 /**
1126 * @brief Get Trace pin assignment control
1127 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
1128 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
1129 * @retval Returned value can be one of the following values:
1130 * @arg @ref LL_DBGMCU_TRACE_NONE
1131 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1132 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1133 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1134 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1135 */
LL_DBGMCU_GetTracePinAssignment(void)1136 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
1137 {
1138 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
1139 }
1140
1141 /**
1142 * @brief Freeze APB1 peripherals (group1 peripherals)
1143 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
1144 * @param Periphs This parameter can be a combination of the following values:
1145 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1146 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1147 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1148 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
1149 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1150 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1151 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1152 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1153 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1154 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1155 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
1156 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1157 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
1158 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
1159 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1160 *
1161 * (*) value not defined in all devices.
1162 * @retval None
1163 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1164 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1165 {
1166 SET_BIT(DBGMCU->APB1FZR1, Periphs);
1167 }
1168
1169 /**
1170 * @brief Freeze APB1 peripherals (group2 peripherals)
1171 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
1172 * @param Periphs This parameter can be a combination of the following values:
1173 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
1174 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1175 *
1176 * (*) value not defined in all devices.
1177 * @retval None
1178 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1179 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1180 {
1181 SET_BIT(DBGMCU->APB1FZR2, Periphs);
1182 }
1183
1184 /**
1185 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1186 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1187 * @param Periphs This parameter can be a combination of the following values:
1188 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1189 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1190 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1191 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
1192 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1193 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1194 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1195 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1196 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1197 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1198 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
1199 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1200 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
1201 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
1202 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1203 *
1204 * (*) value not defined in all devices.
1205 * @retval None
1206 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1207 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1208 {
1209 CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
1210 }
1211
1212 /**
1213 * @brief Unfreeze APB1 peripherals (group2 peripherals)
1214 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
1215 * @param Periphs This parameter can be a combination of the following values:
1216 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
1217 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1218 *
1219 * (*) value not defined in all devices.
1220 * @retval None
1221 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1222 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1223 {
1224 CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
1225 }
1226
1227 /**
1228 * @brief Freeze APB2 peripherals
1229 * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1230 * @param Periphs This parameter can be a combination of the following values:
1231 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1232 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1233 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1234 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1235 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
1236 *
1237 * (*) value not defined in all devices.
1238 * @retval None
1239 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1240 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1241 {
1242 SET_BIT(DBGMCU->APB2FZ, Periphs);
1243 }
1244
1245 /**
1246 * @brief Unfreeze APB2 peripherals
1247 * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1248 * @param Periphs This parameter can be a combination of the following values:
1249 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1250 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1251 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1252 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1253 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
1254 *
1255 * (*) value not defined in all devices.
1256 * @retval None
1257 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1258 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1259 {
1260 CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
1261 }
1262
1263 /**
1264 * @}
1265 */
1266
1267 #if defined(VREFBUF)
1268 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
1269 * @{
1270 */
1271
1272 /**
1273 * @brief Enable Internal voltage reference
1274 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
1275 * @retval None
1276 */
LL_VREFBUF_Enable(void)1277 __STATIC_INLINE void LL_VREFBUF_Enable(void)
1278 {
1279 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1280 }
1281
1282 /**
1283 * @brief Disable Internal voltage reference
1284 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
1285 * @retval None
1286 */
LL_VREFBUF_Disable(void)1287 __STATIC_INLINE void LL_VREFBUF_Disable(void)
1288 {
1289 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1290 }
1291
1292 /**
1293 * @brief Enable high impedance (VREF+pin is high impedance)
1294 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
1295 * @retval None
1296 */
LL_VREFBUF_EnableHIZ(void)1297 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
1298 {
1299 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1300 }
1301
1302 /**
1303 * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
1304 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
1305 * @retval None
1306 */
LL_VREFBUF_DisableHIZ(void)1307 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
1308 {
1309 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1310 }
1311
1312 /**
1313 * @brief Set the Voltage reference scale
1314 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
1315 * @param Scale This parameter can be one of the following values:
1316 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1317 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1318 * @retval None
1319 */
LL_VREFBUF_SetVoltageScaling(uint32_t Scale)1320 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
1321 {
1322 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
1323 }
1324
1325 /**
1326 * @brief Get the Voltage reference scale
1327 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
1328 * @retval Returned value can be one of the following values:
1329 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1330 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1331 */
LL_VREFBUF_GetVoltageScaling(void)1332 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
1333 {
1334 return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
1335 }
1336
1337 /**
1338 * @brief Check if Voltage reference buffer is ready
1339 * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
1340 * @retval State of bit (1 or 0).
1341 */
LL_VREFBUF_IsVREFReady(void)1342 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
1343 {
1344 return (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR));
1345 }
1346
1347 /**
1348 * @brief Get the trimming code for VREFBUF calibration
1349 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
1350 * @retval Between 0 and 0x3F
1351 */
LL_VREFBUF_GetTrimming(void)1352 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
1353 {
1354 return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
1355 }
1356
1357 /**
1358 * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
1359 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
1360 * @param Value Between 0 and 0x3F
1361 * @retval None
1362 */
LL_VREFBUF_SetTrimming(uint32_t Value)1363 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
1364 {
1365 WRITE_REG(VREFBUF->CCR, Value);
1366 }
1367
1368 /**
1369 * @}
1370 */
1371 #endif /* VREFBUF */
1372
1373 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1374 * @{
1375 */
1376
1377 /**
1378 * @brief Set FLASH Latency
1379 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1380 * @param Latency This parameter can be one of the following values:
1381 * @arg @ref LL_FLASH_LATENCY_0
1382 * @arg @ref LL_FLASH_LATENCY_1
1383 * @arg @ref LL_FLASH_LATENCY_2
1384 * @arg @ref LL_FLASH_LATENCY_3
1385 * @arg @ref LL_FLASH_LATENCY_4
1386 * @arg @ref LL_FLASH_LATENCY_5 (*)
1387 * @arg @ref LL_FLASH_LATENCY_6 (*)
1388 * @arg @ref LL_FLASH_LATENCY_7 (*)
1389 * @arg @ref LL_FLASH_LATENCY_8 (*)
1390 * @arg @ref LL_FLASH_LATENCY_9 (*)
1391 * @arg @ref LL_FLASH_LATENCY_10 (*)
1392 * @arg @ref LL_FLASH_LATENCY_11 (*)
1393 * @arg @ref LL_FLASH_LATENCY_12 (*)
1394 * @arg @ref LL_FLASH_LATENCY_13 (*)
1395 * @arg @ref LL_FLASH_LATENCY_14 (*)
1396 * @arg @ref LL_FLASH_LATENCY_15 (*)
1397 *
1398 * (*) value not defined in all devices.
1399 * @retval None
1400 */
LL_FLASH_SetLatency(uint32_t Latency)1401 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1402 {
1403 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1404 }
1405
1406 /**
1407 * @brief Get FLASH Latency
1408 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1409 * @retval Returned value can be one of the following values:
1410 * @arg @ref LL_FLASH_LATENCY_0
1411 * @arg @ref LL_FLASH_LATENCY_1
1412 * @arg @ref LL_FLASH_LATENCY_2
1413 * @arg @ref LL_FLASH_LATENCY_3
1414 * @arg @ref LL_FLASH_LATENCY_4
1415 * @arg @ref LL_FLASH_LATENCY_5 (*)
1416 * @arg @ref LL_FLASH_LATENCY_6 (*)
1417 * @arg @ref LL_FLASH_LATENCY_7 (*)
1418 * @arg @ref LL_FLASH_LATENCY_8 (*)
1419 * @arg @ref LL_FLASH_LATENCY_9 (*)
1420 * @arg @ref LL_FLASH_LATENCY_10 (*)
1421 * @arg @ref LL_FLASH_LATENCY_11 (*)
1422 * @arg @ref LL_FLASH_LATENCY_12 (*)
1423 * @arg @ref LL_FLASH_LATENCY_13 (*)
1424 * @arg @ref LL_FLASH_LATENCY_14 (*)
1425 * @arg @ref LL_FLASH_LATENCY_15 (*)
1426 *
1427 * (*) value not defined in all devices.
1428 */
LL_FLASH_GetLatency(void)1429 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1430 {
1431 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1432 }
1433
1434 /**
1435 * @brief Enable Prefetch
1436 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
1437 * @retval None
1438 */
LL_FLASH_EnablePrefetch(void)1439 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1440 {
1441 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1442 }
1443
1444 /**
1445 * @brief Disable Prefetch
1446 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
1447 * @retval None
1448 */
LL_FLASH_DisablePrefetch(void)1449 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1450 {
1451 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1452 }
1453
1454 /**
1455 * @brief Check if Prefetch buffer is enabled
1456 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
1457 * @retval State of bit (1 or 0).
1458 */
LL_FLASH_IsPrefetchEnabled(void)1459 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1460 {
1461 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
1462 }
1463
1464 /**
1465 * @brief Enable Instruction cache
1466 * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
1467 * @retval None
1468 */
LL_FLASH_EnableInstCache(void)1469 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
1470 {
1471 SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1472 }
1473
1474 /**
1475 * @brief Disable Instruction cache
1476 * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
1477 * @retval None
1478 */
LL_FLASH_DisableInstCache(void)1479 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
1480 {
1481 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1482 }
1483
1484 /**
1485 * @brief Enable Data cache
1486 * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
1487 * @retval None
1488 */
LL_FLASH_EnableDataCache(void)1489 __STATIC_INLINE void LL_FLASH_EnableDataCache(void)
1490 {
1491 SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1492 }
1493
1494 /**
1495 * @brief Disable Data cache
1496 * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
1497 * @retval None
1498 */
LL_FLASH_DisableDataCache(void)1499 __STATIC_INLINE void LL_FLASH_DisableDataCache(void)
1500 {
1501 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1502 }
1503
1504 /**
1505 * @brief Enable Instruction cache reset
1506 * @note bit can be written only when the instruction cache is disabled
1507 * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
1508 * @retval None
1509 */
LL_FLASH_EnableInstCacheReset(void)1510 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
1511 {
1512 SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1513 }
1514
1515 /**
1516 * @brief Disable Instruction cache reset
1517 * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
1518 * @retval None
1519 */
LL_FLASH_DisableInstCacheReset(void)1520 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
1521 {
1522 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1523 }
1524
1525 /**
1526 * @brief Enable Data cache reset
1527 * @note bit can be written only when the data cache is disabled
1528 * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
1529 * @retval None
1530 */
LL_FLASH_EnableDataCacheReset(void)1531 __STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
1532 {
1533 SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1534 }
1535
1536 /**
1537 * @brief Disable Data cache reset
1538 * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
1539 * @retval None
1540 */
LL_FLASH_DisableDataCacheReset(void)1541 __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
1542 {
1543 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1544 }
1545
1546 /**
1547 * @brief Enable Flash Power-down mode during run mode or Low-power run mode
1548 * @note Flash memory can be put in power-down mode only when the code is executed
1549 * from RAM
1550 * @note Flash must not be accessed when power down is enabled
1551 * @note Flash must not be put in power-down while a program or an erase operation
1552 * is on-going
1553 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
1554 * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n
1555 * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown
1556 * @retval None
1557 */
LL_FLASH_EnableRunPowerDown(void)1558 __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
1559 {
1560 /* Following values must be written consecutively to unlock the RUN_PD bit in
1561 FLASH_ACR */
1562 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
1563 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
1564 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
1565 }
1566
1567 /**
1568 * @brief Disable Flash Power-down mode during run mode or Low-power run mode
1569 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n
1570 * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n
1571 * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown
1572 * @retval None
1573 */
LL_FLASH_DisableRunPowerDown(void)1574 __STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
1575 {
1576 /* Following values must be written consecutively to unlock the RUN_PD bit in
1577 FLASH_ACR */
1578 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
1579 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
1580 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
1581 }
1582
1583 /**
1584 * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
1585 * @note Flash must not be put in power-down while a program or an erase operation
1586 * is on-going
1587 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
1588 * @retval None
1589 */
LL_FLASH_EnableSleepPowerDown(void)1590 __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
1591 {
1592 SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1593 }
1594
1595 /**
1596 * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
1597 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
1598 * @retval None
1599 */
LL_FLASH_DisableSleepPowerDown(void)1600 __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
1601 {
1602 CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1603 }
1604
1605 /**
1606 * @}
1607 */
1608
1609 /**
1610 * @}
1611 */
1612
1613 /**
1614 * @}
1615 */
1616
1617 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
1618
1619 /**
1620 * @}
1621 */
1622
1623 #ifdef __cplusplus
1624 }
1625 #endif
1626
1627 #endif /* STM32L4xx_LL_SYSTEM_H */
1628
